PERMANENT STORAGE EXPRESS TRANSPORT PROTOCOL MESSAGE EXCHANGE FOR PARITY GENERATING

Abstract

Methods, devices, and systems for transmitting a parity generation command from a host processor (110) to an acceleration engine (120) via a permanent storage transport protocol, for generating parities from source data by the acceleration engine based on the command, and for storing the generated parities. Methods, devices, and systems for generating parities by an acceleration engine based on source data from a central processing unit using a permanent storage transport protocol for transmitting a parity generation command.

Description

CLAIM TO PRIORITY

[0001] The present application claims priority over Indian patent application No. 202311056027, which was filed on 21 August 2023, the entire disclosure of which is incorporated herein by reference. TECHNICAL AREA

[0002] This disclosure relates to the offloading of computational operations from a host processor, in particular the generation of parities by an acceleration engine based on source data from a central processing unit using an NVMe transport protocol to transmit a parity generation instruction and Direct Memory Access (DMA) to transmit parities from the acceleration engine to the host processor or other peer PCIe devices. BACKGROUND

[0003] Traditionally, a hardware-redundant array of independent disks (RAID) stack runs on an embedded controller and has local access to a parity engine for calculating RAID parity. Conventional stacks running on hosts use the host's central processing unit (CPU) instructions for parity generation, which is a CPU- and memory-intensive operation, even on powerful x86_64 servers. CPU instructions can require up to two inputs and may be inefficient with larger amounts of data. Some server CPUs use Advanced Vector Extension (AVX) instructions, which place an additional load on the host CPU and dynamic random-access memory (DRAM) for all parity calculations.

[0004] Exclusive OR (XOR) parity generation is a fundamental building block of RAID algorithms. XOR parity generation is also used in various other operations, such as error detection, encryption, and pseudorandom number generation, without limitation. Software stacks running on host servers typically use either regular processor instructions or extended vector instructions like AVX-256 or AVX-512 for XOR operations. Data streams that XOR across multiple strips of scattered data buffers consume a significant amount of bandwidth from the host processor and storage controller to perform this XOR operation. Traditional hardware RAID architecture can become a performance bottleneck when scaled with high-performance NVMe (Nonvolatile Memory Express) drives.

[0005] Peripheral Component Interconnect Express (PCIe) is a standard for high-speed serial computer expansion buses, replacing the older bus standards PCI, PCI-X, and AGP. PCIe connects the host processor and PCIe peripheral devices, such as NVMe devices, graphics cards, and RAID controllers, without limitations. PCIe uses a point-to-point topology, enabling faster communication between devices. Motherboards and systems that support PCIe use PCIe devices of various sizes, such as x1, x4, x8, or x16, which refers to the number of paths used. PCIe devices are connected to the motherboard or system via a PCIe slot so that the device can be recognized by the motherboard or system.

[0006] Non-Volatile Memory Express (NVMe) is an open, logical device interface specification for accessing a computer's non-volatile storage media, typically connected via the PCIe bus. NVMe can be used with flash memory contained in PCIe add-in cards.

[0007] There is a need for methods and systems to accelerate the generation of parities without burdening a central processing unit. SUMMARY

[0008] Aspekte provides methods and systems for generating parities through an acceleration engine connected to a host processor via a Peripheral Component Interconnect Express (PCIe) endpoint and using a non-volatile NVMe transport protocol to transmit a parity generation instruction, with the generated parities being stored in the acceleration engine or transferred to the central processing unit's memory or the memory of a peer device via direct memory access (DMA).

[0009] According to one aspect, a procedure is provided which includes: providing a host processor; providing an acceleration engine; transmitting a command to generate parities from the host processor to the acceleration engine via a permanent storage transport protocol; generating parities from source data by the acceleration engine based on the command; and storing the generated parities.

[0010] One aspect provides a method as in the preceding paragraph, wherein the provisioning of the acceleration engine features the provisioning of the acceleration engine which is connected to the host processor via a Peripheral Component Interconnect Express (PCIe) bus, and wherein the acceleration engine is implemented as a PCIe endpoint.

[0011] One aspect provides a procedure like that described in one of the two preceding paragraphs, in which a direct memory access (DMA) is initiated by the acceleration engine to retrieve source data from a host memory.

[0012] One aspect provides a procedure as in one of the previous three paragraphs, which includes the provision of a peer NVMe device, wherein the instruction is transmitted by the peer NVMe device, and wherein the storage of the generated parities includes storing the generated parities in a memory of the peer NVMe device.

[0013] One aspect provides a procedure as in one of the previous four paragraphs, wherein generating parities involves generating RAID parities of a Redundant Array of Independent Disks (RAID) by XOR operations, and wherein the generated parities are RAID parities.

[0014] One aspect provides a procedure as in one of the previous five paragraphs, wherein storing the generated parities involves storing the generated parities in a memory selected from: Central processing unit memory, peer device memory, and acceleration engine memory.

[0015] One aspect provides a procedure like that described in one of the previous six paragraphs, which involves allocating buffers in memory for source data from the host processor based on the instruction.

[0016] Aspekte provides a device comprising: a parity generation engine for generating parities based on source data from a host processor; a permanent storage transport protocol controller for receiving a command from a host processor, the command being to initiate parity generation by the parity generation engine; and a direct storage access engine for transmitting source data from a host processor to the parity generation engine.

[0017] One aspect envisages a device as described in the previous paragraph, which includes a DRAM controller for controlling a dynamic random access memory (DRAM) for storing source data from a host processor and parities generated by the parity generation engine.

[0018] One aspect provides a device as in one of the two preceding paragraphs, wherein the transport protocol controller receives an NVMe instruction from a host processor containing a list of source and destination buffer pointers to storage locations for the source data.

[0019] One aspect provides a device as in one of the previous three paragraphs, wherein the parity generation engine has a RAID parity generation routine to generate RAID parities of a Redundant Array of Independent Disks (RAID) by XOR operations.

[0020] One aspect provides a device as in one of the previous four paragraphs, wherein the direct memory access engine serves to transmit generated parities to a memory selected from: memory of the central processing unit, and memory of a counterpart.

[0021] According to one aspect, a system is provided that includes: a host processor having a Peripheral Component Interconnect Express (PCIe) endpoint, a permanent storage transport protocol controller, and a DMA engine; an acceleration engine for generating parities, wherein the acceleration engine is connected to the host processor via a Peripheral Component Interconnect Express (PCIe) bus and the acceleration engine includes: dynamic random access memory (DRAM) with buffers for storing source data from the host processor and for storing generated parities; and an integrated circuit with: a Peripheral Component Interconnect Express (PCIe) endpoint that connects the acceleration engine to the host processor via the PCIe bus;a permanent storage transport protocol controller to receive an instruction from the host processor, the instruction being to initiate parity generation by the parity generation engine; a buffer manager to allocate buffers in DRAM for source data from the host processor and parities based on the instruction; a parity generation engine to generate parities based on source data from the host processor and to store the parities in allocated buffers in DRAM; and a direct memory access engine to transfer source data from a host processor to allocated buffers in DRAM.

[0022] One aspect provides a system as described in the previous paragraph, where the transport protocol controller receives an NVMe instruction containing a list of source and destination buffer pointers to memory locations for the source data in the DRAM.

[0023] One aspect provides a system as in one of the two preceding paragraphs, where the parity generation engine includes a RAID parity generation routine for performing XOR operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The figures show examples of systems and methods for offloading parity generation from a central processing unit to an acceleration engine with a PCIe endpoint using NVMe transport protocol commands and DMA communication of source data and parities. Fig. Figure 1 shows a block diagram of a system for offloading parity generation from a central processing unit to acceleration engines and storage devices via a PCIe bus and using the NVMe transport protocol for command communication. Fig. Figure 2 shows a block diagram of a host processor and an acceleration engine, as shown in Fig. Figure 1 shows the acceleration engine having an ASIC and DRAM. Fig. Figure 3 shows a command context flow that is implemented in the ASIC of Fig. 2 expires. Fig. Figure 4 shows a block diagram of an acceleration circuit containing one or more processors coupled to one or more data storage devices, wherein the Fig. The ASIC shown in the second example can be one aspect of the processor and is located in... Fig. The dynamic random access memory (DRAM) shown in Figure 2 can be one aspect of data storage devices. Fig. Figure 5 is a flowchart illustrating the process for generating parities outside of a central processing unit. It uses an NVMe transport protocol to transmit a parity generation command and direct memory access (DMA) to transfer the generated parities to the central processing unit. Fig. Figure 6 shows a Redundant Array of Independent Disks (RAID).

[0025] The reference sign for a depicted element that appears in several different figures has the same meaning in all figures, and the mention or discussion of a depicted element in connection with a particular figure also applies to any other figure in which the same depicted element is shown. DESCRIPTION

[0026] Aspekte provides systems and methods for offloading computational operations for parity generation from a central processing unit to a PCIe endpoint using NVMe transport protocol command transfers and Direct Memory Access (DMA) data transfers.

[0027] In one aspect, a hardware engine PCIe endpoint offloads parity generation processes from a host processor. A host processor can set up a single NVMe command and send it to an acceleration engine, allowing the acceleration engine to generate parities through a parity generation routine within the engine. Commands for a parity generation operation can be sent to the acceleration engine, which is an endpoint device, as vendor-defined NVMe commands. This vendor-defined NVMe command can include a set of either a Scatter / Gather List (SGL) or a Physical Region Page (PRP) as the source buffer and a Scatter / Gather List (SGL) or a Physical Region Page (PRP) as the destination buffer.

[0028] Aspekte provides a system and method for generating XOR parity for a number of data strips using an XOR offloading engine in an acceleration engine deployed as a PCIe endpoint. This is achieved using the NVMe transport protocol and a defined NVMe instruction for applications running on a processor, such as a host processor or central processing unit (CPU). A dedicated XOR parity generator in the acceleration engine can offload this task from the host processor or CPU and the host DRAM controllers.

[0029] Parity calculations can encompass both RAID and non-RAID applications. Parity calculations may be required for either RAID or non-RAID applications. From some perspectives, an acceleration engine operating over standard transport protocols can provide efficient operation for many applications and use cases. A swapping procedure can be extended to calculate non-XOR parities. Integrated support can be added to move data from an acceleration engine to another device, such as a graphics processing unit (GPU) or an NVMe drive, and can provide versatility in some applications.

[0030] Systems and methods for offloading computational operations from a processor, such as a host processor or central processing unit, to a PCIe endpoint using an NVMe transport protocol can achieve lower overhead for parity calculations. These systems and methods can free up processor cycles and DRAM for use by other applications and processes.

[0031] The power consumption of a PCIe Gen-5 x8 ASIC for offloading parity calculations from a processor to a PCIe endpoint using an NVMe transport protocol can be low. With certain integrated circuits, a system can achieve up to approximately 4 GBps of data transfer from the host to the accelerator per data lane (28 GBps with 8 lanes).

[0032] Fig. Figure 1 shows a block diagram of a system for offloading computational parity generation operations from a processor, such as a host processor, to an acceleration engine, which may be an NVMe accelerator. The NVMe accelerator may be a PCIe endpoint using an NVMe transport protocol. The System 100 has a host processor 110 and random access memory 112 connected and coupled to the host processor 110. The random access memory 112 can therefore be referred to as "host memory." The random access memory 112 can be double-rate (DDR) or double-rate dynamic random access memory (DDR SDRAM), without restriction. The System 100 may also have one or more NVMe accelerators 120 and one or more NVMe solid-state devices (SSDs) 130. NVMe accelerators can be examples of the acceleration engines described here.The NVMe solid-state devices (SSDs) 130 can use open logical device interface specifications for accessing a computer's non-volatile storage media, where the specifications may include Non-Volatile Memory Express (NVMe) or a Non-Volatile Memory Host Controller Interface (NVMHCIS) specification. The NVMe accelerator 120 and the NVMe solid-state devices (SSDs) 130 can be connected to the host processor 110 via a PCI Express bus 140.

[0033] Fig. Figure 2 shows a block diagram of a host processor 210, where the host processor 210 is an example of the host processor 110. Fig. It can be 1, and an acceleration engine 221. The NVMe accelerator 120 from Fig. 1 can be an example of an acceleration engine 221, which is in Fig. Figure 1 shows the host processor 210, which has a host memory 213. The host processor 210 has a PCIe root complex 212 and is connected to the acceleration engine 221 via a PCIe bus 240.

[0034] The acceleration engine 221 comprises an integrated circuit (IC) 222 and a dynamic random-access memory (DRAM) 228, which are interconnected via a data bus or other connection, without restriction. The IC 222 can be an application-specific integrated circuit (ASIC). Alternatively, the IC 222 can also be an FPGA (field-programmable gate array) or any other device, without restriction. The IC 222 includes a PCIe endpoint (EP) 223, a direct memory access (DMA) engine 224, an NVMe controller 225, a parity-generating engine 226, and a DRAM controller 227. Alternatively, a different random-access memory can be used instead of the combination of DRAM 228 and DRAM controller 227.

[0035] The PCIe endpoint (EP) 223 provides an endpoint for the PCIe bus 240, which is connected to the host 210. The Direct Memory Access (DMA) engine 224 controls the DMA communication of data from the host Random Access Memory 112 (see Fig. 1) to the acceleration engine 221 and from the acceleration engine 221 to the host random access memory 112. A buffer manager 229 can allocate buffers in the DRAM 228 for source data from the host and parity generated by the parity generation engine 226. The NVMe controller 225 manages the communication of messages to and from the acceleration engine 221. The parity generation engine 226 can be implemented by an XOR engine 226 and can include a RAID parity generation routine.

[0036] The DRAM controller 227 can control the dynamic random access memory (DRAM) 228 and the reading / writing of data in it.

[0037] Alternatively, a peer NVMe device can be provided, in which the generated parities can be stored in the peer NVMe device's memory. Alternatively, a target memory buffer address can belong to a peer PCIe device, and if the target belongs to a peer PCIe device, the address accelerator can transfer DMA results to the peer device's memory. The generated parities can be stored in memory selected from: host processor memory (210), a peer device's memory, and the accelerator engine's DRAM (228).

[0038] Fig. Figure 3 shows a command context flow that is used in the IC 222 by Fig. 2. The IC 222 can be an implementation of an NVMe controller to release an NVMe namespace with an NVMe input / output (I / O) instruction (e.g., an XOR instruction). The NVMe I / O instruction can contain a list of source and destination buffer pointers in Scatter / Gather List (SGL) or Physical Region Page (PRP) format, which the NVMe SSD 130 (see Fig. 1) Specify the memory locations in DRAM 228 for the source data. A software stack can run on the host processor 110 (see Fig. 1) run to send the NVMe I / O command to the DMA engine 224 (see Fig. 2) with source and destination buffers in Host Random Access Memory 112 (see Fig. 1) to send. Upon receiving this NVMe I / O command, the internal operation of IC 222 starts, initiates direct memory access (DMA) by the acceleration engine 221 to retrieve source data from the host processor 110 via direct memory access to source buffers from the host random access memory 112, perform XOR operations, and transfer the results back to the host random access memory 112 via direct memory access. Specifically, the internal operation of IC 222 can decode the NVMe I / O command using a submission queue manager 310. A buffer manager 322 can use the decoded NVMe I / O command to allocate 320 DRAM memory pools in the acceleration engine (e.g., buffers) according to a list of the physical region page (PRP) for source data and generated parity. Alternatively, the buffers can also be assigned according to a Scatter / Gather list (SGL).A DMA engine 332 can retrieve the Physical Region Page (PRP) list for data and parity information from the host processor 110 via an Ingress Direct Memory Access (IDMA) 330. The Buffer Manager 322 can allocate buffers for the source data and the generated parity 340. The DMA engine 332 can then access source data from the host random access memory 112 via an Ingress Direct Memory Access (IDMA) 350 (see . Fig. 1) retrieve directly. An XOR engine 362, which may be an example of the parity generation engine 226, can then perform XOR operations on the source data 360 and send the results to the buffers designated for parities 370. Instead of XOR operations, the parity generation engine can perform any parity calculation, or it can be a parity generation engine that includes a RAID parity generation routine for generating RAID parities of a Redundant Array of Independent Disks (RAID). The DMA engine 332 can send parities by direct memory access to the host random access memory 112 380 (see Fig. 1) A Completion Queue Manager 392 can then send a Nonvolatile Memory Express (NVMe) Completion Command (CMD) to the host 390. The Buffer Manager 322 can release the source data buffers, the parity buffers, and the buffers for the Physical Region Page (PRP) list 395. The generated parities can be RAID parities.

[0039] The DRAM controller 227 can provide control over the storage of source data from a host processor in the dynamic random access memory (DRAM) 228, which includes buffers, to the acceleration engine 221. Parities generated by the parity generation engine 226 can also be stored in the DRAM 228 of the acceleration engine 221, which includes buffers. The DRAM 228 can be located outside the chip; that is, the DRAM 228 can be separate from the IC 222 and cannot be DRAM that communicates with the acceleration engine 221.

[0040] The workflow can also support peer-to-peer direct memory access (DMA), meaning that DMA to and from an acceleration engine can be performed by peer PCIe devices instead of DMA performed by the acceleration engine for operations involving other peer PCIe devices. Sources for source data can be any host DRAM and any peer PCIe device, without restriction. Destinations for the generated results can be any host DRAM, any peer PCIe device, and any acceleration engine, without restriction.The data and message flows can include: (1) the acceleration engine receives source data from host storage and returns generated results to the host storage; (2) the acceleration engine receives source data from a peer PCIe device and outputs generated results to a host processor memory or a peer PCIe device memory; or (3) a first peer PCIe device transfers data to the acceleration engine, and the acceleration engine retains the results in its memory, and a second peer PCIe device (e.g., an NVMe device) retrieves the results from the acceleration engine.

[0041] An NVMe I / O command (e.g., an XOR command) to release an NVMe namespace might look like this.

[0042] Fig. Figure 4 is a block diagram of the accelerator circuit 400, which in some aspects can be used to implement various functions, operations, actions, processes, and / or procedures disclosed herein. The accelerator circuit 400 comprises one or more processors 402 (here sometimes referred to as "processors 402") connected to one or more data storage devices (here sometimes referred to as "memory 404"). The Fig. The integrated circuit (IC) 222 shown in section 2 may be an aspect of the 402 processor. The one in Fig. The dynamic random access memory (DRAM) 228 shown can be part of the memory 404. The memory 404 contains machine-executable code 406 stored on it, and the processors 402 contain a logic circuit 408. The machine-executable code 406 contains information describing functional elements that can be implemented (e.g., executed) by the logic circuit 408. The logic circuit 408 is designed to implement (e.g., execute) the functional elements described in the machine-executable code 406. When executing the functional elements described by the machine-executable code 406, the acceleration circuit 400 can be considered dedicated hardware configured to execute the functional elements disclosed here. In some aspects, the processors 402 can execute the functional elements described by the machine-executable code 402 sequentially, concurrently (e.g.,on one or more different hardware platforms) or in one or more parallel process streams.

[0043] When implemented by the logic circuit 408 of the processors 402, the machine-executable code 406 modifies the processors 402 to perform operations of the aspects disclosed herein. For example, the machine-executable code 406 can modify the processors 402 to execute at least part or all of the instruction context of Fig. 3. As another example, the machine-executable code 506 can adapt the processors 402 to perform at least some or all of the operations specified for the IC 222 in Fig. 2 are described. As a specific, non-restrictive example, the machine-executable code 406 can adapt the processors 402 so that they perform at least some of the parity generation operations discussed here.

[0044] The processors 402 may be a general-purpose processor, a special-purpose processor, a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof, designed to perform the functions disclosed herein. A general-purpose computer with one processor is considered a dedicated computer, while the general-purpose computer is configured to execute functional elements corresponding to the machine-executable code 406 (e.g., software code, firmware code, hardware descriptions) relating to aspects of the present disclosure.It should be noted that a general-purpose processor (also referred to here as a host processor or simply a host) can be a microprocessor, but alternatively, the 402 processors can encompass any conventional processor, controller, microcontroller, or state machine. The 402 processors can also be implemented as a combination of computing units, such as a combination of a DSP and a microprocessor, a multitude of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0045] In some aspects, Memory 404 encompasses volatile data storage (e.g., random access memory (RAM)) and non-volatile data storage (e.g., flash memory, a hard disk drive, a solid-state drive, erasable programmable read-only memory (EPROM), without limitation). In some aspects, the Processors 402 and Memory 402 can be implemented in a single device (e.g., a semiconductor device product, a system-on-a-chip (SoC), without limitation). In some aspects, the Processors 402 and Memory 404 can be implemented in separate devices.

[0046] In some aspects, the machine-executable code 406 can contain computer-readable instructions (e.g., software code, firmware code). As a non-restrictive example, the computer-readable instructions can be stored in memory 404, which the processors 402 access directly and execute using at least logic circuit 408. Alternatively, as a non-restrictive example, the computer-readable instructions can be stored in memory 404, transferred to a storage device (not shown) for execution, and executed by the processors 402 using at least logic circuit 408. Accordingly, logic circuit 408 includes, in some aspects, electrically configurable logic circuits 408.

[0047] In some aspects, machine-executable code 406 can describe hardware (e.g., circuits) that is implemented in logic circuit 408 to execute the functional elements. This hardware can be described at a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high abstraction level, a hardware description language (HDL) such as an IEEE Standard Hardware Description Language (HDL) can be used. Non-restrictive examples include Verilog™, SystemVerilog™, or the hardware description language VHDLT (Very Large Scale Integration).

[0048] HDL descriptions can be converted into descriptions at one of numerous other levels of abstraction. As a non-restrictive example, a high-level description can be converted into a logic-level description such as a register-transfer language (RTL), a gate-level description (GL), a layout-level description, or a mask-level description. As another non-restrictive example, micro-operations to be performed by hardware logic circuits (e.g., gates, flip-flops, registers, without restriction) of the 408 logic circuit can be described in an RTL and then converted into a GL description by a synthesis tool.The GL description can be transformed by a placement and routing tool into a layout-level description that corresponds to the physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, the machine-executable code 406 may, in some aspects, contain an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0049] In cases where the machine-executable code 406 contains a hardware description (at any level of abstraction), a system (not shown, but including the memory 404) can be configured to implement the hardware description provided by the machine-executable code 406. As a non-restrictive example, the processors 402 can contain a programmable logic unit (e.g., an FPGA or a PLC), and the logic circuit 408 can be electrically controlled to implement circuits according to the hardware description within the logic circuit 408.

[0050] As a non-restrictive example, the logic circuit 408 may also contain hard-wired logic produced by a manufacturing system (not shown, but including memory 404) according to the hardware description of the machine-executable code 406.

[0051] Regardless of whether the machine-executable code 406 contains computer-readable instructions or a hardware description, the logic circuit 408 is designed to execute the functional elements described by the machine-executable code 406 when it implements the functional elements of the machine-executable code 406. It should be noted that while a hardware description does not directly describe functional elements, it indirectly describes functional elements that can execute the hardware elements described by the hardware description.

[0052] Fig. Figure 5 is a flowchart showing the procedures for generating parities outside of a central processing unit (CPU). It uses a permanent storage transport protocol to transmit a parity generation instruction and direct memory access (DMA) to transmit the generated parities to the CPU. A host processor is present (Figure 502). An acceleration engine is present (Figure 504). A parity generation instruction is transmitted from the host processor to the acceleration engine via a permanent storage transport protocol (Figure 506). Parities are generated by the acceleration engine from source data based on the instruction (Figure 508).

[0053] The generated parities can be transferred from the acceleration engine to the host's memory via Direct Memory Access (DMA) communication. Alternatively, the generated parities can be transferred to a peer NVMe device and stored there in memory, or they can be stored in the acceleration engine's own memory. The generated parities can be RAID parities.

[0054] Fig. Figure 6 shows a Redundant Array of Independent Disks (RAID). Parities can be generated for the source data stored on the hard drives. These parities can be RAID parities of the Redundant Array of Independent Disks (RAID). The RAID parities can be generated using XOR operations.

[0055] Although examples have been described above, other variations and examples can be made from this revelation without deviating from the spirit and scope of these disclosed examples. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] IN 202311056027

[0001]

Claims

[1] Method which features: Providing a host processor; Providing an acceleration engine; Transmitting a command to generate parities from the host processor to the acceleration engine via a permanent storage transport protocol; Generating parities from source data using the acceleration engine based on the command; and Saving the generated parities. [2] Method according to claim 1, wherein providing the acceleration engine comprises providing the acceleration engine connected to the host processor via a Peripheral Component Interconnect Express (PCIe) bus, and wherein the acceleration engine is implemented as a PCIe endpoint. [3] Method according to one of claims 1 to 2, comprising initiating a direct memory access (DMA) by the acceleration engine to retrieve source data from a host memory. [4] Method according to any one of claims 1 to 3, comprising providing a peer NVMe device, wherein the transmission of the command is carried out by the peer NVMe device and wherein storing the generated parities comprises storing the generated parities in a memory of the peer NVMe device. [5] Method according to any one of claims 1 to 4, wherein the generation of parities comprises the generation of RAID parities of a Redundant Array of Independent Disks (RAID) by XOR operations, and wherein the generated parities are RAID parities. [6] Method according to any one of claims 1 to 5, wherein storing the generated parities comprises storing the generated parities in a memory selected from: the memory of the central processing unit, the memory of a peer device and the memory of the acceleration engine. [7] Method according to any one of claims 1 to 6, comprising the allocation of buffers in memory for source data from the host processor based on the instruction. [8] Device comprising: a parity generation engine for generating parities based on source data from a host processor; a permanent storage transport protocol controller to receive a command from a host processor, the command being to initiate parity generation by the parity generation engine; and a direct memory access engine to transfer source data from a host processor to the parity generation engine. [9] Device according to claim 8, comprising a DRAM controller for controlling a dynamic random access memory (DRAM) for storing source data from a host processor and parities generated by the parity generation engine. [10] Device according to one of claims 8 to 9, wherein the transport protocol controller serves to receive an NVMe instruction from a host processor which includes a list of source and destination buffer pointers to storage locations for the source data. [11] Device according to one of claims 8 to 10, wherein the parity generation engine comprises a RAID parity generation routine to generate RAID parities of a Redundant Array of Independent Disks (RAID) by XOR operations. [12] Device according to any one of claims 8 to 11, wherein the direct memory access engine transmits the generated parities to a memory selected from: the memory of the central processing unit and the memory of a peer device. [13] System that features: a host processor that includes a Peripheral Component Interconnect express (PCIe) endpoint, a permanent storage transport protocol controller, and a DMA engine; an acceleration engine for generating parities, wherein the acceleration engine is connected to the host processor via a Peripheral Component Interconnect express (PCIe) bus, and wherein the acceleration engine comprises: a dynamic direct access memory (DRAM) with buffers for storing source data from the host processor and for storing generated parities; a Peripheral Component Interconnect express (PCIe) endpoint that connects the acceleration engine to the host processor via the PCIe bus; a permanent storage transport protocol controller to receive a command from the host processor, the command being used to initiate parity generation by the parity generation engine; a buffer manager for allocating buffers in DRAM for source data from the host processor and parities based on the instruction; a parity generation engine for generating parities based on source data from the host processor and for storing the parities in allocated buffers in DRAM; and A direct memory access engine for transferring source data from the host processor to allocated buffers in DRAM. [14] System according to claim 13, wherein the transport protocol controller receives an NVMe instruction containing a list of source and destination buffer pointers to memory locations for the source data in the DRAM. [15] System according to claim 13, wherein the parity generation engine comprises a RAID parity generation routine for performing XOR operations.

Images