User-defined adaptive health indication

Abstract

This application relates to user-defined adaptive health indications. A host device can be configured to dynamically indicate an adaptive health flag for monitoring health and wear information of a memory device. The host device can indicate a first index to the memory device. The first index can correspond to a first wear level of a set of multiple indexed wear levels of the memory device. The memory device can determine that a metric of the memory device satisfies the first wear level and indicate to the host device that the first wear level is satisfied. The host device can receive the indication that the first wear level is satisfied and indicate to the memory device a second wear level of the set of indexed wear levels that is different from the first wear level.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. patent application No. 17 / 500,751 filed by Boehm et al. on October 13, 2021, entitled “ADAPTIVE USER DEFINED HEALTH INDICATION,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to user-defined adaptive health indicators. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, consumer devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often represented by a logic 1 or a logic 0. In some instances, a single memory cell can support more than two states, either of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state in the memory device.

[0005] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Non-volatile memory devices such as FeRAM can maintain a stored logic state for a long time even in the absence of an external power source. Volatile memory devices such as DRAM may lose their stored state when disconnected from an external power source. Summary of the Invention

[0006] A method is described. The method can include receiving, from a host device, an indication of a first index corresponding to a first wear level of a plurality of indexed wear levels of a memory device; after receiving the indication of the first index, determining that a metric of the memory device satisfies the first wear level; based on determining that the metric of the memory device satisfies the first wear level, indicating to the host device that the first wear level is satisfied; and in response to the indication, receiving, from the host device, an indication of a second index corresponding to a second wear level of the plurality of indexed wear levels different from the first wear level.

[0007] A method is described. The method can include indicating, to a memory device, a first index corresponding to a first wear level of a plurality of indexed wear levels of the memory device; receiving, from the memory device based on indicating the first index, an indication that a metric of the memory device satisfies the first wear level; and in response to the indication, indicating, to the memory device, a second index corresponding to a second wear level of the plurality of indexed wear levels different from the first wear level.

[0008] An apparatus is described. The apparatus can include an array of memory cells, a first register, and a second register. The second register can be configured to indicate whether a wear level of the apparatus is satisfied. The apparatus can also include circuitry. The circuitry can be configured to receive, from a host device via the first register, an indication of a first index corresponding to a first wear level of a plurality of indexed wear levels of the apparatus; after receiving the indication of the first index, determine that a metric of the apparatus satisfies the first wear level; based on determining that the metric of the apparatus satisfies the first wear level, indicate to the host device via the second register that the first wear level is satisfied; and in response to the indication, receive, from the host device via the first register, an indication of a second index corresponding to a second wear level of the plurality of indexed wear levels different from the first wear level.

[0009] An apparatus is described. The apparatus can include circuitry that can be configured to indicate, to a memory device coupled with the apparatus, a first index corresponding to a first wear level of a plurality of indexed wear levels of the memory device; receive, from the memory device based on indicating the first index, an indication that a metric of the memory device satisfies the first wear level; and in response to the indication, indicate, to the memory device, a second index corresponding to a second wear level of the plurality of indexed wear levels different from the first wear level. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 An example of a system that supports user-defined adaptive health indications is shown in accordance with the examples disclosed herein.

[0011] Figure 2 An example of a memory die that supports user-defined adaptive health indications is shown in accordance with the examples disclosed herein.

[0012] Figure 3 An example of a wear curve that supports user-defined adaptive health indications is shown in accordance with the examples disclosed herein.

[0013] Figure 4 An example of a memory device architecture that supports user-defined adaptive health indications is shown in accordance with the examples disclosed herein.

[0014] Figure 5 An example of a process flow that supports user-defined adaptive health indications is shown in accordance with the examples disclosed herein.

[0015] Figure 6 A block diagram of a memory device that supports user-defined adaptive health indications is shown in accordance with the examples disclosed herein.

[0016] Figure 7 A block diagram of a host device that supports user-defined adaptive health indications is shown in accordance with the examples disclosed herein.

[0017] Figure 8 And 9 A flow diagram showing one or more methods that support user-defined adaptive health indications is shown in accordance with the examples disclosed herein. DETAILED DESCRIPTION

[0018] The health or reliability of a memory device may be affected by one or more factors, such as normal use of the device, heavy use of the device, or an "aggressor" attack on the memory device. Reliability degradation may include circuit degradation (e.g., degradation of one or more transistors or other components) or compromise of data integrity through repeated access operations (e.g., row hammering). In some systems, the memory device may be configured to alert a source external to the memory device (e.g., a host device) of performance issues, such as possible wear or performance degradation of one or more components within the memory device. For example, when a metric of the memory device reaches a threshold percentage of wear, the memory device may flag the host device. However, different components and metrics in the memory device may wear at different rates (e.g., each component may follow a different wear curve with a different slope). A host device that receives a flag or health monitoring indication at a single wear point may not support identifying different degradation rates for different use cases. For example, when components have different degradation rates, the host device may not accurately estimate the end of life of each component.

[0019] The present disclosure provides techniques for dynamically indicating adaptive health indicators for monitoring health information of a memory device. A host device can configure a set of multiple indexed wear levels for a memory device. The host device can dynamically indicate to the memory device an index corresponding to a corresponding threshold wear level in the set of indexed wear levels. The memory device can monitor one or more metrics of the memory device and indicate to the host device when at least one of the one or more metrics meets the indicated wear level. The metric can correspond to a component type (e.g., a transistor, diode, resistor, metal line, or any other component), a type of measurement performed on the component, a type of stress applied to the component, a component degradation rate, or any combination thereof. The host device can dynamically indicate one or more additional wear levels of the memory device for monitoring throughout the life of the memory device (e.g., in response to an indication that a previous wear level has been met). Such adaptive health monitoring techniques can enable the host device to track the degradation rate of one or more metrics of the memory device. For example, by obtaining dynamic health monitoring information, the host device can improve the reliability and accuracy of end-of-life estimates compared to a system in which the host device obtains health monitoring information at a pass / fail point near the end of component life.

[0020] The features of this disclosure are first Figure 1 and 2 The features of the present disclosure are described in the context of the systems and dies described. Figure 3-5 These and other features of the present disclosure are further described in the context of the wear curve diagrams, memory device architectures, and process flows described herein. Figure 6-9The device diagrams and flow diagrams described herein involving user-defined adaptive health indicators are shown and described with reference to the device diagrams and flow diagrams.

[0021] Figure 1 An example of a system 100 supporting user-defined adaptive health indicators according to examples disclosed herein is shown. The system 100 can include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 and the memory device 110. The system 100 can include one or more memory devices 110, but aspects of the one or more memory devices 110 can be described in the context of a single memory device (e.g., memory device 110).

[0022] System 100 may comprise part of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop, a tablet, a smartphone, a mobile phone, a wearable device, an Internet-connected device, a vehicle controller, and the like. Memory device 110 may be a component of the system that may be used to store data for one or more other components of system 100.

[0023] At least a portion of system 100 may be an instance of a host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet, a smartphone, a mobile phone, a wearable device, an internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105. Host device 105 may be external to memory device 110 and may communicate with memory device 110. For example, host device 105 may transmit an indication of a health status reporting configuration to memory device 110 and may receive health status information from memory device 110.

[0024] For example, the memory device 110 may include one or more monitoring components (e.g., monitoring circuitry) that may be configured to monitor the health and wear information of the memory device 110 (e.g., among other parameters). A source external to the memory device (e.g., the host device 105) may write to a dedicated register (e.g., a configuration register, such as a mode register) of the memory device 110 to configure the memory device with dynamic health status information reporting parameters. The memory device 110 may monitor and report the health status information of the memory device 110 based on the received dynamic health status information reporting parameters, which may be referred to as an adaptive threshold wear level. The memory device 110 may write one or more values ​​indicating the health status of the memory device 110 relative to a first indicated threshold wear level to a dedicated register (e.g., a readout register, such as a mode register) so that the host device 105 can access the information. The host device 105 may write a second threshold wear level to the configuration register, and the memory device may indicate when the second threshold wear level is met via the readout register. Such dynamic health monitoring may continue until host device 105 obtains health monitoring information of sufficient granularity to accurately estimate the end of life of one or more components within memory device 110 .

[0025] Memory device 110 may be a standalone device or component that can be used to provide a physical memory address / space that can be used or referenced by system 100. In some examples, memory device 110 can be configured to function with one or more different types of host devices. Signaling between host device 105 and memory device 110 can be used to support one or more of the following: a modulation scheme for modulating signals, various pin configurations for transmitting signals, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 may be used to store data for components of host device 105. In some examples, memory device 110 may act as a slave or dependent device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0027] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of host device 105 may be coupled to each other using a bus 135.

[0028] The processor 125 may be used to provide control or other functionality to at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such instances, the processor 125 may be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a SoC, among other instances. In some instances, the external memory controller 120 may be implemented by or be part of the processor 125.

[0029] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and the various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0030] In some examples, system 100 or host device 105 may include various peripheral components. A peripheral component can be any input device or output device, or an interface for such a device (e.g., a bus, a set of one or more pins, etc.), that can be integrated into or with system 100 or host device 105. Examples can include one or more of the following: a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a Universal Serial Bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a Peripheral Component Interconnect (PCI) or a dedicated graphics port. Peripheral components can be other components that one of ordinary skill in the art would understand to be peripheral devices.

[0031] In some examples, system 100 or host device 105 may include an I / O controller. The I / O controller may manage data communications between processor 125 and peripheral components, input devices, or output devices. The I / O controller may manage peripheral devices that are not integrated into or with system 100 or host device 105. In some examples, the I / O controller may represent a physical connection or port to an external peripheral component.

[0032] In some examples, system 100 or host device 105 may include input components, output components, or both. An input component may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. In some examples, an input component may include a user interface or interface with or between other devices. In some examples, an input component may be a peripheral device that interfaces with system 100 via one or more peripheral components, or may be managed by an I / O controller. An output component may represent a device or signal external to system 100 that can be used to receive output from system 100 or any of its components. Examples of output components may include a display, an audio speaker, a printing device, another processor on a printed circuit board, and the like. In some examples, an output may be a peripheral device that interfaces with system 100 via one or more peripheral components, or may be managed by an I / O controller.

[0033] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support the required or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more sectors), where each memory cell can be used to store at least one data bit. A memory device 110 that includes two or more memory dies 160 may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0034] The device memory controller 155 may include circuitry, logic, or components that may be used to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0035] In some examples, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0036] A local memory controller 165 (e.g., local to the memory die 160) may include circuitry, logic, or components for controlling the operation of the memory die 160. In some examples, the local memory controller 165 may be used to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some examples, the memory device 110 may not include a device memory controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be used to communicate with the device memory controller 155, other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers that may be used to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0037] The external memory controller 120 may be used to enable one or more of information, data, or commands to be transferred between components of the system 100 or host device 105 (e.g., processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or the functionality described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or the functionality described herein may be implemented by one or more components of the memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0038] Components of host device 105 can use one or more channels 115 to exchange information with memory device 110. Channels 115 can be used to support communication between external memory controller 120 and memory device 110. Each channel 115 can be an example of a transmission medium that carries information between host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path can be an example of a conductive path that can be used to carry a signal. For example, channel 115 can include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin can be an example of a conductive input or output point of a device of system 100, and a pin can be used to serve as part of a channel. For example, a pin, register, channel, side channel, or any combination thereof can be used by host device 105 and memory device 110 to transmit information about a health monitoring configuration and / or health status information of memory device 110.

[0039] Channels 115 (and associated signal paths and terminals) can be dedicated to transmitting one or more types of information. For example, channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling can be transmitted over channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal can be registered for each clock cycle (e.g., on either the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0040] In some examples, CA channel 186 may be used to communicate commands between host device 105 and memory device 110, including control information associated with the commands (e.g., address information). For example, a command carried by CA channel 186 may include a read command with the address of desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) for decoding one or more of the address or command data.

[0041] In some examples, clock signal channel 188 may be used to transmit one or more clock signals between host device 105 and memory device 110. Each clock signal may be used to oscillate between a high state and a low state and may support coordination (e.g., in time) between the actions of host device 105 and memory device 110. In some examples, the clock signal may be single-ended. In some examples, the clock signal may provide a timing reference for command and addressing operations of memory device 110 or other system-level operations of memory device 110. Thus, the clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., an oscillator, a crystal, logic gates, transistors).

[0042] In some examples, data channel 190 may be used to transfer one or more of data or control information between host device 105 and memory device 110. For example, data channel 190 may transfer information to be written to memory device 110 or information to be read from memory device 110 (e.g., bidirectionally).

[0043] Channel 115 may include any number of signal paths (including a single signal path). In some examples, channel 115 may include multiple separate signal paths. For example, a channel may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), and so on.

[0044] In some cases, the health or reliability of the memory device 110 may be affected by normal use of the device, heavy use of the device, or attacks on the memory device, among other examples. According to various aspects described herein, the memory device 110 may include a monitor or sensor for detecting memory device health issues, such as issues caused by device access and / or wear. The memory device 110 may be configured to alert the host device 105 (e.g., a source external to the memory device) of performance issues (e.g., possible wear or performance degradation) or possible attacks (e.g., operation beyond the intended use or specifications in order to cause the device to malfunction or operate outside of an expected mode), and the host device 105 or the memory device 110 may be configured to implement corrective actions to counteract or prevent the detected problem or attack. For example, the host device 105 may set a dynamic threshold wear level for the memory device 110 to be monitored so that the host device can accurately estimate the wear profile and corresponding end of life of one or more components of the memory device 110.

[0045] Figure 2 An example of a memory die 200 supporting user-defined adaptive health indicators according to examples disclosed herein is shown. The memory die 200 may be a reference Figure 11 . An example of a memory die 160 is described. In some examples, the memory die 200 can be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 can include one or more memory cells 205, each of which can be programmed to store a different logic state (e.g., programmed to one of a set of two or more possible states). For example, a memory cell 205 can be used to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell) can be used to store more than one bit of information at a time (e.g., a logic 00, a logic 01, a logic 10, a logic 11). In some examples, the memory cells 205 can be arranged in an array, such as with reference to FIG. Figure 1 Memory array 170 is depicted.

[0046] Memory cell 205 may store a charge representing a programmable state in a capacitor. DRAM architectures may include capacitors comprising a dielectric material for storing a charge representing a programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed. Memory cell 205 may include a logic storage component, such as capacitor 230, and a switch component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage, such as Vpl, or a ground, such as Vss.

[0047] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digit lines 215) arranged in a pattern, such as a grid pattern. The access lines may be conductive lines coupled to the memory cells 205 and may be used to perform access operations on the memory cells 205. In some examples, the word lines 210 may be referred to as row lines. In some examples, the digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, are interchangeable and do not affect understanding or operation. The memory cells 205 may be positioned at the intersection of the word lines 210 and the digit lines 215.

[0048] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting an access line, such as one or more of word line 210 or digit line 215. By biasing word line 210 and digit line 215 (e.g., applying a voltage to word line 210 or digit line 215), a single memory cell 205 can be accessed at their intersection. The intersection of word line 210 and digit line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205.

[0049] Access to memory cell 205 may be controlled by row decoder 220 or column decoder 225. For example, row decoder 220 may receive a row address from local memory controller 260 and activate word line 210 based on the received row address. Column decoder 225 may receive a column address from local memory controller 260 and activate digit line 215 based on the received column address.

[0050] Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switch component 235 using word line 210. Capacitor 230 may be coupled to digit line 215 using switch component 235. For example, capacitor 230 may be isolated from digit line 215 when switch component 235 is deactivated, and capacitor 230 may be coupled to digit line 215 when switch component 235 is activated.

[0051] The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 may be coupled to the gate of the switching component 235 of the memory cell 205 and may be used to control the switching component 235 of the memory cell. In some architectures, the word line 210 may be coupled to a node of a capacitor of the memory cell 205, and the memory cell 205 may not include a switching component.

[0052] The digit line 215 can be a conductive line connecting the memory cell 205 with the sensing element 245. In some architectures, the memory cell 205 can be selectively coupled to the digit line 215 during portions of an access operation. For example, the word line 210 and the switching element 235 of the memory cell 205 can be used to couple and / or isolate the capacitor 230 of the memory cell 205 from the digit line 215. In some architectures, the memory cell 205 can be coupled to the digit line 215.

[0053] The sensing component 245 can be used to detect the state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine the logic state of the memory cell 205 based on the stored state. The sensing component 245 can include one or more sense amplifiers for amplifying or otherwise converting the signal generated by accessing the memory cell 205. The sensing component 245 can compare the signal detected from the memory cell 205 with a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 can be provided as an output of the sensing component 245 (e.g., to the input / output 255), and the detected logic state can be indicated to another component of the memory device including the memory die 200.

[0054] The local memory controller 260 can control access to the memory cell 205 through various components (eg, row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 can be a reference Figure 1 1. In some examples, one or more of the row decoder 220, column decoder 225, and sense component 245 can be co-located with the local memory controller 260. The local memory controller 260 can be configured to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the host device 105 based on the execution of the one or more operations. The local memory controller 260 can generate row signals and column address signals to activate the target word lines 210 and the target digit lines 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the magnitude, shape, or duration of the applied voltages or currents discussed herein may vary and may be different for the various operations discussed in operating memory die 200 .

[0055] The local memory controller 260 may be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 may be used to perform other access operations not listed here or other operations related to the operation of the memory die 200 (not directly related to accessing the memory cells 205).

[0056] The local memory controller 260 can be used to perform a write operation (e.g., a program operation) on one or more memory cells 205 of the memory die 200. During a write operation, a memory cell 205 of the memory die 200 can be programmed to store a desired logic state. The local memory controller 260 can identify a target memory cell 205 on which to perform the write operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 can apply a particular signal (e.g., a write pulse) to the digit line 215 during the write operation to store a particular state (e.g., a charge) in the capacitor 230 of the memory cell 205. The pulse used as part of the write operation can include one or more voltage levels for a duration of time.

[0057] The local memory controller 260 can be used to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, a logic state stored in a memory cell 205 of the memory die 200 can be determined. The local memory controller 260 can identify a target memory cell 205 on which to perform the read operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 coupled with the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 can transfer a signal to the sense component 245 in response to biasing the access lines. The sense component 245 can amplify the signal. The local memory controller 260 can activate the sense component 245 (e.g., a latched sense component) and thereby compare the signal received from the memory cell 205 to the reference 250. Based on the comparison, the sense component 245 can determine the logic state stored on the memory cell 205.

[0058] Some components of a memory device may be affected by normal use of the device, heavy use of the device, or an attack on the memory device. For example, row decoder 220, column decoder 225, switch component 235, or capacitor 230, as well as other instances (e.g., one or more transistors of memory die 200, one or more transistors within a component of memory die 200) may experience repeated or high duty cycle use, resulting in component wear. According to various aspects, a memory device may include a monitor or sensor for detecting memory device health issues, such as issues caused by device access and / or wear. The memory device may be configured to warn a source external to the memory device (e.g., a host device) of performance issues (e.g., possible wear or performance degradation) or a possible attack, and the source external to the memory device or the memory device may be configured to implement corrective actions to counteract or prevent the detected problem or attack.

[0059] In some cases, a memory device may be configured to indicate to a source external to the memory device when one or more defined threshold wear levels (e.g., predefined trip or failure points) have been reached (e.g., by setting a bit high or low or by raising a flag). In such cases, a source external to the memory device (e.g., a host device) may receive an indication that a component of the memory device has reached a threshold percentage of its expected lifespan (e.g., 94% of the component's expected lifespan, or some other threshold). The host device may estimate the amount of time remaining in the component's lifespan based on a nominal wear curve (e.g., a linear curve). However, the wear curve for one or more components within the memory device may not be nominal. For example, the wear curve may be an exponential or power curve. In such cases, the component may have more or less time before the end of its lifespan than the host device estimated based on the nominal wear curve, which may reduce the reliability of the memory system.

[0060] To improve health monitoring performance, the techniques described herein provide adaptive health feedback. A host device or a user operating a memory system may set one or more adaptive health flags, which may be referred to as threshold wear levels. For example, a host device may set a first threshold wear level to 10% (e.g., or some other threshold), and the memory device may indicate to the host device when 10% of the expected lifespan of a component within the memory device has been reached by use. The host device may then set a second threshold (e.g., 20% or some other percentage or threshold), and the memory device may indicate when the second threshold is met. By dynamically setting the threshold wear level of the memory device to be monitored, the host device (e.g., or a user controlling the host device) may adjust the granularity of the wear curve of one or more components within the memory device.

[0061] Figure 3An example of a wear curve graph 300 supporting user-defined adaptive health indicators according to examples disclosed herein is shown. The wear curve graph 300 shows three example wear curves, including a first wear curve 305, a second wear curve 310 (e.g., a nominal or linear wear line), and a third wear curve 315. Each wear curve can correspond to a degradation rate or wear level of a corresponding component of a memory device over time, which can be associated with or referred to as a metric of the memory device.

[0062] Each wear curve can thus correspond to a corresponding metric from a set of metrics for the memory device. The set of metrics can include metrics associated with transistor wear or other wear measured for different types of devices or components. Metrics associated with transistor wear can include threshold voltage drift, current drive, hot carrier stress degradation, negative bias temperature instability (NBTI) stress degradation, and the like for the corresponding transistor type (e.g., N-type metal oxide semiconductor (N-MOS) or P-type metal oxide semiconductor (P-MOS) transistors). In some cases, different metrics can be measured for different types of components, which can include different metrics measured for different transistors, different diodes, different resistors, different metal lines (e.g., to measure electromigration in the lines), and the like within the memory device.

[0063] exist Figure 3 In the example of FIG, a first wear curve 305 may correspond to a first metric, such as threshold voltage degradation of a first transistor (e.g., a P-MOS transistor) over time. A third wear curve 315 may correspond to a second metric, such as threshold voltage degradation of a second transistor (e.g., an N-MOS transistor) over time. A second wear curve 310 may correspond to a third metric. Alternatively, the second wear curve 310 may represent a linear or normalized wear line of a metric, such as the first metric or the second metric. Although three example wear curves are shown, it should be understood that a memory device may include any number of components and any number of metrics associated with the respective components (e.g., and associated wear curves) may be monitored, including the metrics listed here or other metrics not explicitly described herein.

[0064] In some cases, the memory device may notify a source external to the memory device (e.g., a host device) when a metric meets a threshold, which may indicate that a threshold wear level for an associated component (e.g., 90% of expected life or some other threshold level) is met. For example, referring to Figure 3, (e.g., approximately 9 years into the life of the memory device) the host device may be notified that the first metric associated with the first wear curve 305 has reached a threshold of 90% of the expected life, which may be referred to as a 90% threshold wear level. The host device may determine or indicate device operating information, such as health status or warning information, based on the indication that the 90% threshold wear level has been met.

[0065] In some cases, the host device may not be aware of or programmed with the general shape of the first wear curve 305 associated with the first metric or the third wear curve 315 associated with the second metric. Therefore, the host device may assume that the first metric follows the nominal wear curve 310, and the host device may estimate that the associated component of the memory device will reach 100% of the estimated life expectancy at a first time (e.g., around year 11), as predicted by the nominal wear curve 310. However, the actual time at which the component may reach 100% of the estimated life expectancy, as predicted by the corresponding wear curve 305, may be later than the estimated time (e.g., after year 12).

[0066] Similarly, the host device may estimate based on the nominal wear curve 310 that a second metric associated with the third wear curve 315 will reach 100% of the expected lifespan at a first time (e.g., around the 11th year), but the second metric may actually reach 100% before the first time (e.g., before the 11th year), as predicted by the third wear curve 315. Figure 3 The vertical dashed line in shows the difference 320 between the actual end of life of the metric associated with the wear curve 315 and the estimated end of life of the metric based on the nominal wear curve 310. The difference 320 between the actual end of life and the estimated end of life may lead to inaccurate wear estimates and reduce the safety and reliability of the memory device or host device.

[0067] To improve health monitoring techniques, the host device can dynamically set and / or send one or more intermediate threshold wear levels (e.g., associated with values ​​of corresponding metrics) to the memory device so that the host device can obtain health monitoring data of sufficient granularity to estimate the wear curve of the corresponding component. The host device can use the identified wear curve to predict when the component is likely to reach 100% of its expected life, which can be more accurate than using the nominal curve 310. The host device can configure a set of threshold wear levels for the memory device and can dynamically indicate a corresponding threshold wear level from the set of threshold wear levels to the memory device (e.g., by indicating an index corresponding to the corresponding threshold wear level). The memory device can report when one or more metrics meet the indicated threshold wear level. For example, the memory device can indicate that one or more of the first wear curve 305, the second wear curve 310, or the third wear curve 315 has reached the indicated threshold wear level. In response to the indication that the metric has met the threshold, the host device can indicate a subsequent wear level to the memory device.

[0068] By dynamically sending threshold wear levels (which may be referred to as performing a user-defined adaptive health indication), the host device may receive more granular health monitoring information. The host device may thereby identify a wear profile for the corresponding component, which the host device may use to improve estimates of the end of life of the component, the memory device, or both. Methods for configuring and sending such dynamic threshold wear levels are described in further detail elsewhere herein, including with reference to Figure 4 and 5 To describe.

[0069] Figure 4 An example of a memory device architecture 400 supporting user-defined adaptive health indicators according to examples disclosed herein is shown. The memory device architecture 400 may include a memory device 405, which may be a reference Figure 1 The memory device 110 described or referenced Figure 2 Examples of memory die 200 are described or may include aspects thereof.In some examples, memory device 405 may be an example of a silicon memory device.

[0070] The memory device 405 may include a memory array 410, which may be a reference Figure 1 The memory array 170 described or referenced Figure 2 Examples of aspects of the described arrays. Memory array 410 can be a collection (eg, one or more gates, one or more groups, one or more tiles, one or more sectors) of memory cells, where each memory cell can be used to store at least one bit of data.

[0071] Memory device 405 may also include circuitry 415 coupled to memory array 410. Circuitry 415 may include circuitry for monitoring the health or degradation level of one or more components of or associated with memory array 410 (e.g., monitoring circuitry). Additionally or alternatively, circuitry 415 may include a controller and / or circuitry for operating or accessing memory array 410. The controller may be a reference Figure 1 The device memory controller 155 or local memory controller 165 described or reference Figure 2 Examples of various aspects of the local memory controller 265 are described. Circuitry 415, the controller, or both may be used to control the operation of the memory array 410. For example, circuitry 415 may be used to respond to a request from a source external to the memory device 405 (e.g., a memory device 405 ( Figure 4 The circuit system 415 may also include or be coupled to a decoding circuit system, such as a host device coupled to the memory device (not depicted in FIG. 1 ). Figure 2 One or more row decoders 220 or column decoders 225 are depicted, or command decoders for decoding commands received from a source external to the memory device 405 .

[0072] The circuitry 415 may be coupled to one or more pins 420 or communication pads (e.g., CA pads and / or DQ pads) via which the circuitry 415 may receive and transmit data from and to a host device or some other source external to the memory device 405. The circuitry 415 may be configured to store data received via the communication pads and pins 420 in a subset of the memory array 410 (e.g., a subset of memory cells within the memory array 410). The communication pads and / or pins 420 may be coupled to any number of conductive materials that may be coupled to a reference Figure 1 The depicted communication channels 115 are associated and include a data channel 190 and a CA channel 186, among other examples.

[0073] In some examples, circuitry 415 may include monitoring circuitry or some other subset of circuitry configured to monitor one or more health parameters of one or more corresponding systems or subsystems of memory device 405 (e.g., one or more systems or subsystems of or associated with memory array 410). Circuitry 415 may include a set of sensors configured to monitor the one or more health parameters of memory device 405, which may include one or more traffic patterns associated with access operations of memory device 405, wear levels of components of memory device 405 (e.g., resistors, capacitors, transistors, diodes, drivers, latches, registers, etc.), temperatures of components of memory device 405, operating frequencies of components of memory device 405, or any combination thereof (e.g., among other examples).

[0074] Memory device 405 may also include one or more registers 425 (e.g., register 425-a, register 425-b, and / or one or more other registers 425) that can be used to write information from a source external to memory device 405 (e.g., a host device) to memory device 405 or read information from memory device 405 to the host device. For example, register 425-a may be configured to be written to (e.g., receive information from) the host device, and register 425-b may be configured to be read by the host device after being written to by memory device 405 (e.g., in response to a read command, such as a mode register read command), or vice versa. Registers 425 may be coupled to pins 420, communication pads, a channel, or a side channel, or any combination thereof, such that registers 425 can be accessed by the host device. Registers 425 may also be coupled to circuitry 415. Register 425-a may represent or be referred to as a configuration register (e.g., a health monitoring sensitivity configuration register) or an adaptation flag register, and register 425-b may represent or be referred to as a read register. Memory device 405 may include more than two registers 425, and in some cases, registers 425 may be configured to be written to and read by a host device or other source external to memory device 405 (eg, may perform the functions of both configuring and reading registers).

[0075] The one or more registers 425 may include or represent respective instances of mode registers or programmable registers (e.g., programmable by a host device). In some examples, the host device may write to one or more dedicated registers 425 (e.g., configuration registers, such as a mode register) of the memory device 405 to configure the memory device 405. The one or more registers 425 may serve as dedicated access points for monitoring status or information associated with the health of the memory device 405 and may be enabled or disabled based on the device. In some cases, one or more aspects of the one or more registers 425 may be performed by one or more other components of the memory device 405 (e.g., may be performed by part of the circuitry 415 or controller).

[0076] Circuitry 415 may monitor one or more health parameters of memory device 405, for example, according to a reporting configuration or a monitoring configuration received via register 425 (e.g., register 425-a), or according to a default or predefined configuration. As described herein, memory device 405 may be configured with a set of one or more indexed wear levels for memory device 405, and a host device may indicate a corresponding index to memory device 405 via register 425-a, which may be a mode register that can be used to store a number of bits configured to indicate a corresponding wear level to memory device 405 (e.g., an available mode register can be used to store three bits or another number of bits). The host device may thereby dynamically indicate a corresponding wear level or other health information to circuitry 415 of memory device 405 to be monitored. For example, a first value (e.g., '000') of register 425-a may correspond to a first index indicating a wear level of 10%, a second value (e.g., '001') of register 425-a may correspond to a second index indicating a wear level of 20%, and so on.

[0077] The circuitry 415 of the memory device 405 may be configured to monitor or read values ​​from register 425-a. For example, after a host device writes a value to register 425-a (e.g., indicating a corresponding index and wear level), the circuitry 415 may read the value of register 425-a and identify the index represented by or corresponding to the value. The circuitry 415 may determine a corresponding wear level in the set of indexed wear levels based on the index. The circuitry 415 may monitor one or more health parameters or health metrics of the memory array 410 based on the indicated wear level. In some examples, the host device may indicate the indexed wear level and other health monitoring information, such as a metric corresponding to the indexed wear level (e.g., a metric to be monitored and reported when the indexed wear level is reached), via register 425-a.

[0078] After identifying the wear level indicated by register 425-a, circuitry 415 may also be used to read data or access health monitoring information stored in memory array 410, access health monitoring information written to second register 425, or both. Circuitry 415 may determine whether the health metric of memory device 405 satisfies the wear level based on accessing the health monitoring information.

[0079] Circuitry 415 may be configured to send an indication to a host device of whether the health metric of memory device 405 meets an indicated wear level. Circuitry 415 may write a value to register 425-b indicating that the wear level is met. In some examples, writing the value to register 425-b may include setting a bit in register 425-b. For example, register 425-b may be a mode register (e.g., an available register that can be used to store one or more bits) configured to include a bit indicating whether the wear level is met. Circuitry 415 may be configured to set a bit high (e.g., to a value of '1') to indicate that a previously indicated wear level (e.g., a threshold wear level) is met. The host device may read register 425-b (e.g., one or more bit values ​​of register 425-b), which may indicate to the host device whether the indicated wear level has been met.

[0080] For example, the host device may poll (e.g., read from, monitor) register 425-b periodically (e.g., at set time intervals), may randomly poll register 425-b, or may poll register 425-b in response to an instruction from memory device 405. For example, the host device may read a bit value from register 425-b using a read command (e.g., a mode register read command). For example, the host device may transmit the read command to memory device 405, and memory device 405 may read the bit value in response to the read command and send the bit value to the host device.

[0081] In some instances, the circuit system 415 may indicate that the wear level is satisfied when any metric of the memory device 405 satisfies a threshold wear level. In such cases, the host device may not know which metric satisfies the wear level. Therefore, the host device may request an indication from the memory device 405 as to which metric satisfies the wear level. In some other instances, the circuit system 415 may be used to store measured values ​​of one or more metrics of the memory device 405 in corresponding registers 425, where each register 425 may be associated with a corresponding metric of the memory device 405. In such instances, the host device may read register 425-b, indicating that the first metric satisfies the threshold wear level, and the host device may additionally or alternatively read one or more other registers 425 of the memory device 405 to obtain health monitoring information for one or more other corresponding metrics. The host device may use the health monitoring information for each metric to analyze the corresponding wear curve for each metric, such as reference Figure 3 described.

[0082] In some other examples, the circuitry 415 may be used to adjust one or more of the threshold wear levels to normalize a wear curve (e.g., a nonlinear wear curve) to a linear wear curve. For example, the circuitry 415 may adjust one or more threshold wear levels such that Figure 3 The exponential wear curve 305 or 315 shown in (eg, or some other non-linear wear curve) can be normalized to a linear wear curve, e.g. Figure 3 . In some cases, a general model for the wear curve 305 or 315 of the corresponding metric (e.g., a typical model for the transistor type associated with the metric) may be known (e.g., circuitry 415 may be configured with one or more general wear curves for one or more corresponding metrics of memory device 405), and circuitry 415 may be configured to scale the threshold wear level based on the corresponding general model to reduce or increase the degradation rate of wear curve 305 or 315, respectively.

[0083] Each metric (e.g., each transistor type or other metric) can be associated with a corresponding function or process for normalizing the associated health measurement, and the circuit system 415 can be configured to use the corresponding function or process to normalize the measurement. By sending the normalized value of the wear curve 315, the circuit system 415 can indicate to the host device that although the wear level associated with the corresponding metric may be less than the nominal curve, the wear level may be increasing faster than expected. Additionally or alternatively, the circuit system 415 can indicate to the host device that although the wear level associated with the corresponding metric may exceed the nominal curve, the wear level may be increasing slower than expected.

[0084] In some cases, the host device can be configured to adjust one or more of the threshold wear levels to normalize a wear curve (e.g., a nonlinear wear curve) to a linear wear curve, as described herein. For example, the host device can use a model (e.g., a general model, a known model) of wear curve 305 or 315 to normalize a corresponding metric (e.g., a typical model for the transistor type associated with the metric), and the host device can be configured to scale the threshold wear levels based on the corresponding model to reduce or amplify the degradation rate of wear curve 305 or 315, respectively. As described herein, each metric (e.g., each transistor type or other metric) can be associated with a corresponding function or process for normalizing the metric, and the host device can be configured to use the corresponding function or process to normalize the metric.

[0085] To reduce overhead and power consumption of the host device (e.g., associated with polling register 425-b), in some examples, circuitry 415 may set pin 420 (e.g., a special function select (DSF) pin) to a first value in response to determining that the wear level is met. Pin 420 may flag the host device to indicate that the host device will poll or monitor register 425-b. The host device may poll register 425-b to identify whether the wear level is met based on the value of pin 420. Thus, pin 420 may prevent the host device from continuously polling register 425-b, which may reduce latency and power consumption.

[0086] Based on the techniques described herein, the host device can indicate one or more threshold wear levels with adjustable granularity, and the circuitry 415 of the memory device 405 can indicate when one or more metrics meet the indicated threshold wear levels. Thus, the host device can obtain health monitoring information with sufficient granularity to identify or determine the wear profile of one or more components of the memory device 405, such as Figure 3 The host device can utilize the identified wear profile to improve the accuracy of predicting the expiration timeline (e.g., predicting the lifetime or end of life) of the memory device 405 or one or more components thereof, which can improve the reliability and security of the memory device 405, the host device, or both. Additionally, by setting a dynamic threshold wear level and marking each time a metric meets the threshold, the host device can avoid continuously performing read operations, which can reduce power consumption.

[0087] Figure 5 An example of a process flow 500 for supporting user-defined adaptive health indicators according to examples disclosed herein is shown. The process flow 500 may illustrate the operation of a memory device 505 and a host device 510. In some examples, the host device 510 and the memory device 505 may represent a reference Figure 1-4The process flow 500 may illustrate the process of setting an adaptive flag register for health monitoring, as described with reference to FIG. Figure 1-4 Alternative examples of process flow 500 may be implemented in which some operations are performed in an order different from that described or not performed at all. In some cases, the operations may include features not mentioned below, or additional operations may be added.

[0088] At 515, the host device 510 may indicate the first index to the memory device 505. The host device 510 may configure a set of multiple indexed wear levels for the memory device 505, or the memory device may be otherwise configured with the set of multiple indexed wear levels (e.g., which may be preconfigured or predefined for the memory device 505). The first index may correspond to a first wear level in the set of multiple indexed wear levels for the memory device 505, as described with reference to FIG. Figure 3 and 4 The host device 510 may indicate the first index by writing a first value to a set of bits in a first register of the memory device 505. For example, the first register may be a reference Figure 4 An example of register 425 - a is described (eg, an adaptive flag register). The first value may indicate a first index, which may correspond to a first wear level (eg, a certain percentage of the expected life of a component of the memory device 505 or some other threshold).

[0089] Host device 510 may select the first index based on the first value being the first value in a configured list of values ​​corresponding to the set of wear levels (e.g., the first wear level may be the lowest wear level). Alternatively, host device 510 may dynamically determine or confirm the first wear level based on one or more parameters associated with host device 510 and memory device 505. For example, the first wear level may not be the lowest wear level, and host device 510 may select the first index (e.g., and the corresponding first wear level) from the set of multiple indexed wear levels. Memory device 505 may access the set of bits in the first register to identify the first index (e.g., in response to the host device writing the first value to the first register).

[0090] At 520, the memory device 505 may determine whether a metric of the memory device 505 satisfies a first wear level. For example, after accessing the first register, the memory device 505 may exit a monitoring mode (e.g., stress mode) to read health information and then return to the monitoring mode. The memory device 505 may, based on an indication of receiving the first index (e.g., based on accessing the first register), perform a read to obtain health monitoring information stored within an array of the memory device 505 or within a register of the memory device 505. The health monitoring information may include the metric and one or more other metrics, each of which indicates a wear level of a corresponding component of the memory device 505. The memory device 505 may determine whether the metric satisfies the first wear level based on the health monitoring information.

[0091] The memory device 505 may perform one or more measurements to obtain a health level associated with the metric, the one or more other metrics, or both (e.g., in addition to or as an alternative to obtaining stored health monitoring information, or in order to determine and store health monitoring information). For example, the memory device 505 may perform threshold voltage measurements of one or more types of transistors that are experiencing one or more types of degradation (e.g., hot carrier type stress or NBTI stress, which may include gate oxide stress on transistors), or the memory device 505 may measure timing parameters (e.g., incremental timing offset), operating frequency parameters, or temperature parameters of one or more components of the memory device 505. The one or more types of transistors or the one or more components may be configured for measurement and may be subjected to the same type of stress as similar functional components of the memory device 505. Thus, the measured parameters (e.g., metrics, degradation levels) may correspond to similar parameters or corresponding degradation levels of functional components of the same type of the memory device 505. Each metric may correspond to a different wear performance, wear level, or degradation rate, such as Figure 3 Three examples of wear curves are shown in Figure 2.

[0092] The memory device 505 or the circuitry within the memory device 505 may include one or more sensors for performing measurements, and the metric may be based on a function of one or more of the measurements. In some examples, the memory device 505 may include a single sensor for each type of measurement. Additionally or alternatively, to improve the accuracy of the measurements, the memory device 505 may include multiple sensors for each type of measurement, such as multiple sensors for measuring the threshold voltage of one or more components. The memory device 505 may average measurements obtained by multiple sensors of the same type to improve the accuracy of the data (e.g., to remove peripheral measurements and improve safety and reliability). In some examples, the memory device 505 may include multiple sensors that can be used to perform one or more types of measurements on the same component.

[0093] At 525, the memory device 505 may indicate to the host device 510 that the first wear level is met (e.g., based on determining that the metric meets the first wear level). The memory device 505 may indicate that the first wear level is met by writing a value to a second register (e.g., reading a register) or setting a bit in the second register to indicate that the first wear level is met, as described with reference to FIG. Figure 4 In some examples, the memory device 505 may set a pin (e.g., a DSF pin) to a first value (e.g., raise a flag, set the pin high) to instruct the host device 510 to poll or monitor the second register. In some examples, the host device 510 may perform an OR operation on the pin with one or more other safety mechanisms on the memory device 505 to determine whether the pin is set to the first value. The host device 510 may avoid polling the second register until the pin or some other safety mechanism is set, which may reduce power consumption and complexity. The pin may be a reference Figure 4 An example of pin 420 is depicted. Host device 510 may poll or read from the second register by transmitting a register read command to memory device 505 , upon which memory device 505 may access information in the second register and send the information to host device 510 .

[0094] In some examples, host device 510 may send a request to memory device 505 for information regarding a degradation type (e.g., threshold voltage degradation, host carrier stress degradation, or NBTI degradation), which may correspond to a first metric. Additionally or alternatively, host device 510 may configure memory device 505 to indicate a degradation type associated with the first metric (e.g., a degradation type that satisfies a first wear level) or any other metric. In such cases, as well as in other cases, the memory device may indicate the degradation type to host device 510 (e.g., when indicating that the first wear level is satisfied, or via another indication). Thus, host device 510 may identify which metric or degradation type satisfies the first wear level.

[0095] Additionally or alternatively, memory device 505 may store health monitoring information for each metric in a corresponding register (e.g., where each register is associated with a particular metric), and host device 510 may poll one or more registers to identify a corresponding wear level for the associated metric, e.g., in response to receiving an indication that a first wear level is met. For example, if memory device 505 indicates that Figure 3 If the first metric associated with the wear curve 305 in FIG. 1 satisfies a first wear level (e.g., a 10% wear level, a 20% wear level, or some other wear level) after the first year, the host device 510 may read or poll the data associated with the data generated by Figure 3A second register associated with the metric represented by the wear curve 315 in is used to identify a wear level of the metric associated with the wear curve 315 (eg, to identify that the metric has achieved less than 5% wear in the first year).

[0096] In some examples, the memory device 505 may normalize one or more measurements associated with a metric (e.g., a metric associated with a transistor type, a component type, a measurement type) to obtain a normalized wear level associated with the metric. For example, the memory device 505 may normalize a nonlinear wear curve based on a function associated with the corresponding metric, such as reference numerals. Figure 4 In such examples, the memory device 505 can determine that the metric satisfies the first wear level based on a comparison of the normalized measurement to the first wear level.

[0097] At 530, host device 510 may indicate a second index to memory device 505 in response to the indication that the first wear level is met. The second index may correspond to a second wear level in the set of indexed wear levels that is different from the first wear level. Host device 510 may indicate the second index by writing a second value to the first register, the second value corresponding to the second wear level. Alternatively, memory device 505 may automatically increment the index to the second index based on providing the indication that the first wear level is met.

[0098] In some examples, the second value may be adjacent or proximate to the first value in a list of values ​​corresponding to the set of indexed wear levels. For example, the host device 510 may iteratively indicate the indexes in the list in sequence. The host device 510 may indicate the first index and the first wear level based on the first value being the initial value in the list. The host device 510 may also indicate the second value based on the second value being a neighboring value of the first value (e.g., in the list). Additionally or alternatively, the host device 510 may determine to indicate the second index and the second wear level to the memory device 505 based on one or more parameters associated with the memory device 505, the host device 510, or both (e.g., based on the granularity of the data, the wear profile of one or more components within the memory device 505, the required reliability of the memory device 505, or any combination thereof). In such cases, the second value may be different from the values ​​adjacent to the first value in the list (e.g., the second value may not be adjacent to the first value). In other words, the host device 510 may skip one or more values ​​in the list to reduce power consumption and complexity or provide higher reliability (e.g., among other examples).

[0099] At 535, the memory device 505 can determine that the metric or some other metric of the memory device 505 satisfies a second wear level. For example, as described herein, the memory device 505 can obtain health monitoring information in response to an indication of the second index, and the memory device 505 can determine that a wear level is satisfied based on the health monitoring information. Additionally or alternatively, the memory device 505 can perform one or more measurements of the metric using one or more sensors, as described herein. The metric can satisfy the second wear level before another metric of the memory device 505, or a second metric different from the metric can satisfy the second wear level before the metric. That is, each wear level can be satisfied by the same metric or a different metric of the memory device 505.

[0100] At 540, the memory device 505 can indicate to the host device 510 that the second wear level is satisfied in response to the determination. The memory device 505 can set a second register to a second value indicating that the second wear level is satisfied (e.g., and can set a pin to indicate to the host device 510 to poll the value of the second register). The host device 510 can issue a read command (e.g., a mode register read command) to the memory device 505, and in response to the read command, the memory device 505 can access information in the second register and transmit the information to the host device 510.

[0101] In some examples, the host device 510 can not know which metric satisfies the second wear level. The host device 510 can send a request for information regarding which metric satisfies the second wear level, and in response, the memory device 505 can indicate the metric to the host device 510. In some other examples, the memory device 505 can include multiple registers, and each register can correspond to a respective metric, such that the host device 510 can identify which metric satisfies the second wear level based on which register the memory device 505 writes to (e.g., and which register the host device 510 reads from or polls).

[0102] Although Figure 5Two iterations of the health monitoring technique are shown, but it should be understood that the host device 510 can indicate any number of threshold wear levels to the memory device 505 at any time and at any granularity. For example, the host device 510 can indicate three or more wear levels consecutively by indicating consecutive indices in an index list (e.g., when each previous wear level is met), or the host device 510 can dynamically select indices from the list. The host device 510 can indicate a threshold wear level that is a maximum of the total wear point (e.g., 80%, 90%, or some other total wear point). For example, the total wear point can be determined by the host device 510 based on a use case and one or more parameters associated with the memory device 505. Once the memory device 505 indicates that the metric meets the total wear point, the host device 510 can estimate the end of life of the component based on previously obtained health monitoring information for the corresponding component. Using the obtained data, the host device 510 can more accurately estimate the end of life than if the host device 510 assumed that the component followed a linear wear curve.

[0103] The host device 510 can thereby obtain health monitoring information about one or more metrics of the memory device 505 consistent with an adjustable granularity. The host device 510 can dynamically adjust the threshold wear level to monitor the estimated life expectancy of the one or more metrics without continuously reading or polling registers, which can reduce complexity and power consumption. In some examples, the host device 510 can be configured with a general shape or wear curve associated with each metric, and the host device 510 can assign a risk level to the corresponding metric based on the general wear curve. Alternatively, the host device 510 can generate a wear curve for each metric based on the received health monitoring information (for example, the host device 510 can construct the wear curve as a usage model of the host device 510).

[0104] Figure 6 A block diagram 600 illustrates a memory device 620 that supports user-defined adaptive health indicators according to examples disclosed herein. The memory device 620 may be a reference Figures 1 to 5 Memory device 620 or its various components may be examples of means for performing various aspects of the user-defined adaptive health indicators described herein. For example, memory device 620 may include an index component 625, a wear level component 630, a metric component 635, a health monitoring information component 640, a degradation type component 645, a measurement component 650, a measurement normalization component 655, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0105] Index component 625 may be configured to or otherwise support means for receiving, from a host device, an indication of a first index corresponding to a first wear level in a set of indexed wear levels for a memory device. Metric component 635 may be configured to or otherwise support means for determining, upon receiving the indication of the first index, that a metric of the memory device satisfies the first wear level. Wear level component 630 may be configured to or otherwise support means for indicating to the host device that the first wear level is satisfied based, at least in part, on determining that the metric of the memory device satisfies the first wear level. In some examples, index component 625 may be configured to or otherwise support means for receiving, from the host device, an indication of a second index corresponding to a second wear level in the set of indexed wear levels that is different from the first wear level, in response to the indication.

[0106] In some examples, index component 625 may be configured as or otherwise support means for accessing a set of bits of a first register, the set of bits representing an indication of a first index, wherein each value in the set of bits of the first register corresponds to a respective band-indexed wear level in the set, and wherein receiving the indication of the first index is based on accessing the set of bits representing the indication of the first index. In some examples, index component 625 may be configured as or otherwise support means for accessing the set of bits of the first register, the set of bits representing an indication of a second index, wherein receiving the indication of the second index is based on accessing the set of bits representing the indication of the second index.

[0107] In some examples, the health monitoring information component 640 may be configured as or otherwise support means for determining, based on receiving an indication of a first wear level, health monitoring information comprising one or more metrics, each metric indicating a level of wear of a corresponding component of the memory device, the one or more metrics including the metric, wherein determining that the metric satisfies the first wear level is based on determining the health monitoring information.

[0108] In some examples, the degradation type component 645 can be configured as or otherwise support means for transmitting an indication of a degradation type corresponding to the metric to a host device, the degradation type including threshold voltage degradation, hot carrier stress degradation, NBTI stress degradation, or any combination thereof. In some examples, the degradation type component 645 can be configured as or otherwise support means for receiving a request from the host device for the degradation type corresponding to the metric, wherein transmitting the indication is based on the request.

[0109] In some examples, to support indicating that the first wear level is met, wear level component 630 can be configured or otherwise support means for setting a bit in a second register to indicate that the first wear level is met. In some examples, wear level component 630 can be configured or otherwise support means for setting a pin to a first value in response to determining that the first wear level is met, wherein the pin instructs the host device to monitor the second register.

[0110] In some examples, the metric corresponds to a degradation level of one or more transistors of the memory device, the one or more transistors being of a first transistor type from a set of transistor types of the memory device. In some examples, each transistor type in the set corresponds to a respective degradation rate during operation of the memory device.

[0111] In some examples, the measurement normalization component 655 can be configured to or otherwise support means for normalizing one or more measurements associated with a transistor type in the set of transistor types to obtain a corresponding wear level associated with the metric, wherein each transistor type in the set is associated with a corresponding function for normalizing the one or more associated measurements. In some examples, the wear level component 630 can be configured to or otherwise support means for comparing the corresponding wear level associated with the metric to a first wear level, wherein determining that the metric satisfies the first wear level is based on the comparison.

[0112] In some examples, metric component 635 may be configured or otherwise support means for determining, upon receiving an indication of a second index, that the metric of the memory device satisfies a second wear level. In some examples, wear level component 630 may be configured or otherwise support means for indicating to a host device that the second wear level is satisfied based on determining that the metric satisfies the second wear level. In some examples, index component 625 may be configured or otherwise support means for receiving, from the host device, an indication of a third index in response to the indication, the third index corresponding to a third wear level in the set of indexed wear levels that is different from the first wear level and the second wear level.

[0113] In some examples, metric component 635 may be configured or otherwise support means for determining, upon receiving an indication of a second index, that a second metric of the memory device satisfies a second wear level, the second metric being different from the first metric. In some examples, wear level component 630 may be configured or otherwise support means for indicating to a host device that the second wear level is satisfied based on determining that the second metric of the memory device satisfies the second wear level. In some examples, index component 625 may be configured or otherwise support means for receiving, from the host device, an indication of a third index in response to the indication, the third index corresponding to a third wear level in the set of indexed wear levels that is different from the first wear level and the second wear level.

[0114] In some examples, measurement component 650 can be configured as or otherwise support means for measuring a timing parameter or threshold voltage associated with a transistor of a memory device. In some examples, metric component 635 can be configured as or otherwise support means for determining the metric based on the timing parameter or threshold voltage.

[0115] In some examples, measurement component 650 can be configured as or otherwise support means for obtaining a set of measurements associated with the transistor via one or more sensors, wherein the metric is based on a function of the set of measurements.

[0116] In some examples, a memory device includes a set of registers, each register in the set corresponding to a respective metric in a set of metrics each associated with a wear level of the memory device.

[0117] Figure 7 A block diagram 700 illustrates a host device 720 that supports user-defined adaptive health indicators according to examples disclosed herein. The host device 720 may be a reference Figures 1 to 5 7. The host device 720 or its various components may be examples of means for performing various aspects of the user-defined adaptive health indicators described herein. For example, the host device 720 may include an index component 725, a wear level component 730, a degradation type component 735, a read command component 740, a degradation rate component 745, a measurement normalization component 750, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0118] Index component 725 can be configured to or otherwise support means for indicating a first index to a memory device, the first index corresponding to a first wear level in a set of indexed wear levels for the memory device. Wear level component 730 can be configured to or otherwise support means for receiving an indication from the memory device that a metric of the memory device satisfies the first wear level based on indicating the first index. In some examples, index component 725 can be configured to or otherwise support means for indicating a second index to the memory device in response to the indication, the second index corresponding to a second wear level in the set of indexed wear levels that is different from the first wear level.

[0119] In some examples, index component 725 can be configured to or otherwise support means for writing a first value to a set of bits of a first register to indicate a first index, each value in the set of bits corresponding to a respective band-indexed wear level in the set, wherein the first value corresponds to a first wear level. In some examples, index component 725 can be configured to or otherwise support means for writing a second value to the set of bits of the first register to indicate a second index, wherein the second value corresponds to a second wear level.

[0120] In some examples, the second value is a value adjacent to the first value in the list of values ​​corresponding to the set of indexed wear levels. In some examples, the first index is indicated based on the second value being a value adjacent to the first value. In some examples, the index component 725 can be configured to or otherwise support means for selecting the second index based on one or more parameters associated with the memory device, wherein the second value is different from the values ​​adjacent to the first value in the list of values ​​corresponding to the set of indexed wear levels.

[0121] In some examples, the degradation type component 735 can be configured as or otherwise support means for receiving an indication of a degradation type corresponding to the metric from the memory device, the degradation type including threshold voltage degradation, hot carrier stress degradation, NBTI stress degradation, or any combination thereof. In some examples, the degradation type component 735 can be configured as or otherwise support means for transmitting a request for the degradation type corresponding to the metric to the memory device, wherein receiving the indication is based on transmitting the request.

[0122] In some examples, to support receiving the indication, the read command component 740 can be configured as or otherwise support means for transmitting a read command of a second register of the memory device upon which receiving the indication from the memory device is based.

[0123] In some examples, the wear level component 730 can be configured as or otherwise support means for identifying that a pin of the memory device is set to a first value, wherein the pin indication is stored at the second register.

[0124] In some examples, the metric corresponds to a degradation level of one or more transistors of a memory device, the one or more transistors having a first transistor type from a set of transistor types of the memory device. In some examples, the degradation rate component 745 can be configured to or otherwise support means for determining a respective degradation rate for each of the one or more transistors based on the metric satisfying the first wear level, wherein each transistor type in the set of transistor types corresponds to a respective degradation rate during operation of the memory device.

[0125] In some examples, the measurement normalization component 750 can be configured to or otherwise support means for normalizing one or more measurements associated with a transistor type in the set of transistor types to obtain a corresponding wear level associated with the metric, wherein each transistor type in the set is associated with a corresponding process for normalizing the one or more associated measurements. In some examples, the wear level component 730 can be configured to or otherwise support means for comparing the corresponding wear level associated with the metric to a first wear level.

[0126] In some examples, wear level component 730 can be configured to or otherwise support means for receiving, from the memory device, a second indication that the metric of the memory device satisfies a second wear level based on indicating a second index. In some examples, index component 725 can be configured to or otherwise support means for indicating, to the memory device, a third index based on the second indication, the third index corresponding to a third wear level in the set of indexed wear levels that is different from the first wear level and the second wear level.

[0127] In some examples, the wear level component 730 can be configured to or otherwise support means for receiving, from the memory device, a second indication that a second metric of the memory device satisfies a second wear level based on indicating a second index, the second metric being different from the metric. In some examples, the index component 725 can be configured to or otherwise support means for indicating, to the memory device, a third index based on the second indication, the third index corresponding to a third wear level in the set of indexed wear levels that is different from the first wear level and the second wear level.

[0128] Figure 8A flowchart illustrating a method 800 for supporting user-defined adaptive health indicators according to an example disclosed herein is shown. The operations of the method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 800 may be implemented by a memory device or components thereof as described herein. Figures 1 to 6 The memory device described herein performs. In some examples, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform various aspects of the described functions.

[0129] At 805, the method may include receiving an indication of a first index from a host device, the first index corresponding to a first wear level in a set of indexed wear levels of a memory device. Operation 805 may be performed according to a reference Figure 4 and 5 In some examples, aspects of operation 805 may be performed by reference to Figure 6 The described indexing component 625 performs.

[0130] At 810, the method may include, after receiving an indication of the first index, determining that a metric of the memory device satisfies a first wear level. Operation 810 may be performed based on a reference Figure 4 and 5 In some examples, aspects of operation 810 may be performed by reference to Figure 6 The described metrics component 635 performs.

[0131] At 815, the method may include indicating to the host device that the first wear level is satisfied based on determining that the metric of the memory device satisfies the first wear level. Operation 815 may be performed according to a reference Figure 4 and 5 In some examples, aspects of operation 815 may be performed by reference to Figure 6 The wear level component 630 performs as described.

[0132] At 820, the method may include receiving an indication of a second index from the host device in response to the indication, the second index corresponding to a second wear level in the set of indexed wear levels that is different from the first wear level. Operation 820 may be performed according to a reference Figure 4 and 5 In some examples, aspects of operation 820 may be performed by reference to Figure 6 The described indexing component 625 performs.

[0133] In some examples, the apparatus described herein may perform one or more methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0134] Aspect 1: The apparatus comprising features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving an indication of a first index from a host device, the first index corresponding to a first wear level in a set of indexed wear levels for a memory device; after receiving the indication of the first index, determining that a metric of the memory device satisfies the first wear level; indicating to the host device that the first wear level is satisfied based on determining that the metric of the memory device satisfies the first wear level; and receiving an indication of a second index from the host device in response to the indication, the second index corresponding to a second wear level in the set of indexed wear levels that is different from the first wear level.

[0135] Aspect 2: The apparatus according to Aspect 1, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: accessing a set of bits of a first register, the set of bits representing the indication of the first index, wherein each value in the set of bits of the first register corresponds to a corresponding band index wear level in the set, and wherein receiving the indication of the first index is based on accessing the set of bits representing the indication of the first index; and accessing the set of bits of the first register, the set of bits representing the indication of the second index, wherein receiving the indication of the second index is based on accessing the set of bits representing the indication of the second index.

[0136] Aspect 3: An apparatus according to any one of Aspects 1 to 2, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: determining health monitoring information comprising one or more metrics based on receiving the indication of the first wear level, each metric indicating a wear level of a corresponding component of the memory device, the one or more metrics including the metric, wherein determining that the metric satisfies the first wear level is based on determining the health monitoring information.

[0137] Aspect 4: The apparatus of any one of aspects 1 to 3, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for transmitting to the host device an indication of a degradation type corresponding to the metric, the degradation type comprising threshold voltage degradation, hot carrier stress degradation, NBTI stress degradation, or any combination thereof.

[0138] Aspect 5: The apparatus of aspect 4, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for receiving a request from the host device for the degradation type corresponding to the metric, wherein transmitting the indication is based on the request.

[0139] Aspect 6: The apparatus of any one of Aspects 1 to 5, wherein indicating that the first wear level is met further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for setting a bit in a second register to indicate that the first wear level is met.

[0140] Aspect 7: The apparatus of aspect 6, further comprising operations, features, circuit systems, logic, means or instructions, or any combination thereof, for: in response to determining that the first wear level is met, setting a pin to a first value, wherein the pin instructs the host device to monitor the second register.

[0141] Aspect 8: The apparatus of any of aspects 1 to 7, wherein the metric corresponds to a degradation level of one or more transistors of the memory device, the one or more transistors being of a first transistor type from a set of transistor types of the memory device.

[0142] Aspect 9: The apparatus of aspect 8, wherein each transistor type in the set corresponds to a respective degradation rate during operation of the memory device.

[0143] Aspect 10: An apparatus according to any one of Aspects 8 to 9, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: normalizing one or more measurements associated with a transistor type in the group of transistor types to obtain a corresponding wear level associated with the metric, wherein each transistor type in the group is associated with a corresponding function for normalizing the one or more associated measurements; and comparing the corresponding wear level associated with the metric with the first wear level, wherein determining that the metric satisfies the first wear level is based on the comparison.

[0144] Aspect 11: An apparatus according to any one of Aspects 1 to 10, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: after receiving the indication of the second index, determining that the metric of the memory device satisfies the second wear level; based on determining that the metric satisfies the second wear level, indicating to the host device that the second wear level is satisfied; and in response to the indication, receiving an indication of a third index from the host device, the third index corresponding to a third wear level in the set of indexed wear levels that is different from the first wear level and the second wear level.

[0145] Aspect 12: An apparatus according to any one of Aspects 1 to 10, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: after receiving the indication of the second index, determining that a second metric of the memory device satisfies the second wear level, the second metric being different from the metric; indicating to the host device that the second wear level is satisfied based on determining that the second metric of the memory device satisfies the second wear level; and in response to the indication, receiving an indication of a third index from the host device, the third index corresponding to a third wear level in the set of indexed wear levels that is different from the first wear level and the second wear level.

[0146] Aspect 13: The apparatus of any one of Aspects 1 to 12, further comprising operations, features, circuit systems, logic, means or instructions, or any combination thereof, for: measuring a timing parameter or a threshold voltage associated with a transistor of the memory device; and determining the metric based on the timing parameter or the threshold voltage.

[0147] Aspect 14: The apparatus of aspect 13, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for obtaining a set of measurements associated with the transistor via one or more sensors, wherein the metric is based on a function of the set of measurements.

[0148] Aspect 15: The apparatus of any of aspects 1 to 14, wherein the memory device comprises a set of registers, each register in the set corresponding to a respective metric in a set of metrics each associated with a wear level of the memory device.

[0149] Figure 9 A flowchart illustrating a method 900 for supporting user-defined adaptive health indicators according to an example disclosed herein is shown. The operations of the method 900 may be implemented by a host device or a component thereof as described herein. For example, the operations of the method 900 may be implemented by a host device or a component thereof as described herein. Figures 1 to 5and 7. In some examples, the host device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host device may use dedicated hardware to perform various aspects of the described functions.

[0150] At 905, the method may include indicating a first index to a memory device, the first index corresponding to a first wear level in a set of indexed wear levels of the memory device. Operation 905 may be performed according to a reference Figure 4 and 5 In some examples, aspects of operation 905 may be performed by reference to Figure 7 The described indexing component 725 performs.

[0151] At 910, the method may include receiving an indication from a memory device that a metric of the memory device satisfies a first wear level based on indicating a first index. Operation 910 may be performed according to a reference Figure 4 and 5 In some examples, aspects of operation 910 may be performed by reference to Figure 7 The wear level component 730 performs as described.

[0152] At 915, the method may include, in response to the indication, indicating a second index to the memory device, the second index corresponding to a second wear level in the set of indexed wear levels that is different from the first wear level. Operation 915 may be performed according to a reference Figure 4 and 5 In some examples, aspects of operation 915 may be performed by reference to Figure 7 The described indexing component 725 performs.

[0153] In some examples, the apparatus described herein may perform one or more methods, such as method 900. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0154] Aspect 16: The apparatus comprising features, circuit systems, logic, components, or instructions, or any combination thereof, for: indicating a first index to a memory device, the first index corresponding to a first wear level in a set of indexed wear levels for the memory device; receiving an indication from the memory device that a metric of the memory device satisfies the first wear level based on indicating the first index; and responsive to the indication, indicating a second index to the memory device, the second index corresponding to a second wear level in the set of indexed wear levels that is different from the first wear level.

[0155] Aspect 17: The apparatus of Aspect 16, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: writing a first value to a set of bits of a first register to indicate the first index, each value in the set of bits corresponding to a corresponding indexed wear level in the set, wherein the first value corresponds to the first wear level; and writing a second value to the set of bits of the first register to indicate the second index, wherein the second value corresponds to the second wear level.

[0156] Aspect 18: The apparatus of aspect 17, wherein the second value is a value adjacent to the first value in a list of values ​​corresponding to the set of indexed wear levels, and the first index is indicated based on the second value being a value adjacent to the first value.

[0157] Aspect 19: An apparatus according to Aspect 17, further comprising operations, features, circuit systems, logic, components or instructions or any combination thereof for: selecting the second index based on one or more parameters associated with the memory device, wherein the second value is different from the value adjacent to the first value in the list of values ​​corresponding to the set of indexed wear levels.

[0158] Aspect 20: The apparatus of any one of aspects 16 to 19, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for receiving an indication of a degradation type corresponding to the metric from the memory device, the degradation type comprising threshold voltage degradation, hot carrier stress degradation, NBTI stress degradation, or any combination thereof.

[0159] Aspect 21: The apparatus of aspect 20, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for transmitting, to the memory device, a request for the degradation type corresponding to the metric, wherein receiving the indication is based on transmitting the request.

[0160] Aspect 22: An apparatus according to any one of aspects 16 to 21, wherein receiving the indication further includes the following operations, features, circuit systems, logic, components or instructions, or any combination thereof: transmitting a read command of a second register of the memory device, wherein receiving the indication from the memory device is based on transmitting the read command.

[0161] Aspect 23: The apparatus of aspect 22, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: identifying a pin of the memory device to be set to a first value, wherein the pin indicates that the indication is stored at the second register.

[0162] Aspect 24: The apparatus of any of aspects 16 to 23, wherein the metric corresponds to a degradation level of one or more transistors of the memory device, the one or more transistors being of a first transistor type from a set of transistor types of the memory device.

[0163] Aspect 25: The apparatus of Aspect 24, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining a respective degradation rate for each of the one or more transistors based on the metric satisfying the first wear level, wherein each transistor type in the set of transistor types corresponds to a respective degradation rate during operation of the memory device.

[0164] Aspect 26: An apparatus according to any one of Aspects 24 to 25, wherein receiving the indication further comprises operations, features, circuit systems, logic, components or instructions or any combination thereof for: normalizing one or more measurements associated with a transistor type in the group of transistor types to obtain a corresponding wear level associated with the metric, wherein each transistor type in the group is associated with a corresponding process for normalizing the one or more associated measurements; and comparing the corresponding wear level associated with the metric with the first wear level.

[0165] Aspect 27: An apparatus according to any one of Aspects 16 to 26, wherein receiving the indication further includes the following operations, features, circuit systems, logic, components or instructions or any combination thereof: based on indicating the second index, receiving a second indication from the memory device that the metric of the memory device meets the second wear level; and based on the second indication, indicating a third index to the memory device, the third index corresponding to a third wear level in the set of indexed wear levels that is different from the first wear level and the second wear level.

[0166] Aspect 28: An apparatus according to any one of Aspects 16 to 26, wherein receiving the indication further includes the following operations, features, circuit systems, logic, components or instructions or any combination thereof: based on indicating the second index, receiving a second indication from the memory device that a second metric of the memory device satisfies the second wear level, the second metric being different from the metric; and based on the second indication, indicating a third index to the memory device, the third index corresponding to a third wear level in the set of indexed wear levels being different from the first wear level and the second wear level.

[0167] It should be noted that the methods described herein describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Further, portions from two or more methods can be combined.

[0168] An apparatus is described. Summaries of aspects of the apparatus described herein are provided below:

[0169] Aspect 29: An apparatus, comprising: an array of memory cells; a first register; a second register configured to indicate whether a wear level of the apparatus is satisfied; and circuitry configured to: receive, from a host device via the first register, an indication of a first index, the first index corresponding to a first wear level of a set of indexed wear levels of the apparatus; after receiving the indication of the first index, determine that a metric of the apparatus satisfies the first wear level; based on determining that the metric of the apparatus satisfies the first wear level, indicate to the host device, via the second register, that the first wear level is satisfied; and in response to the indication, receive, from the host device via the first register, an indication of a second index, the second index corresponding to a second wear level of the set of indexed wear levels different from the first wear level.

[0170] Aspect 30: The apparatus of Aspect 29, wherein the circuitry is configured to: access a set of bits of the first register, the set of bits representing the first index, wherein each value in the set of bits of the first register corresponds to a respective indexed wear level in the set, and wherein receiving the indication of the first index is based on accessing the set of bits representing the first index; and access the set of bits of the first register, the set of bits representing the indication of the second index, wherein receiving the indication of the second index is based on accessing the set of bits representing the indication of the second index.

[0171] Aspect 31 : The apparatus of any of Aspects 29-30, wherein the circuitry is configured to: based on receiving the indication of the first wear level, determine health monitoring information comprising one or more metrics, each metric indicating a wear level of a respective component of the apparatus, the one or more metrics including the metric, wherein determining that the metric satisfies the first wear level is based on determining the health monitoring information.

[0172] Aspect 32: The apparatus of any of Aspects 29-31, wherein the circuitry is configured to: set a bit in the second register to indicate that the first wear level is satisfied.

[0173] Aspect 33: The apparatus of Aspect 32, further including a pin configured to instruct the host device to monitor the second register, wherein the circuitry is configured to set the pin to high in response to determining that the first wear level is satisfied.

[0174] Another apparatus is described. Summaries of aspects of the apparatus described herein are provided below:

[0175] Aspect 34: An apparatus comprising: circuitry configured to: instruct a memory device coupled with the apparatus of a first index, the first index corresponding to a first wear level in a set of indexed wear levels for the memory device; receive, from the memory device based on instructing the first index, an indication that a metric for the memory device satisfies the first wear level; and in response to the indication, instruct the memory device of a second index, the second index corresponding to a second wear level in the set of indexed wear levels different from the first wear level.

[0176] Aspect 35: The apparatus of Aspect 34, wherein the circuitry is further configured to: write a first value to a set of bits of a first register to instruct the first index, each value in the set of bits corresponding to a respective indexed wear level in the set, wherein the first value corresponds to the first wear level; and write a second value to the set of bits of the first register to instruct the second index, wherein the second value corresponds to the second wear level.

[0177] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, such signals can represent multiple signals, where the bus can have multiple bit widths.

[0178] The terms "electronic communication," "conductive contact," "connect," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed circuits based on the operation of the device that includes the connected components. The conductive paths between the connected components may be direct conductive paths between the components, or the conductive paths between the connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some instances, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0179] The term "coupling" refers to the condition of moving from an open-circuit relationship between components, in which signals are currently unable to pass between the components via the conductive paths, to a closed-circuit relationship between the components, in which signals are able to pass between the components via the conductive paths. When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via the conductive paths that previously did not allow signal flow.

[0180] The term "isolation" refers to a relationship between components where signals are currently unable to flow between them. Components are isolated from each other if a break in the circuit exists between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it implements a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0181] As used herein, the term "substantially" means that the modified characteristic (such as a verb or adjective modified by the term substantially) is not necessarily absolute but is close enough to obtain the advantage of the characteristic.

[0182] The devices including memory arrays discussed herein can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial extension of a semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0183] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via a conductive material (e.g., metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "switched on" or "activated." When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "off" or "deactivated."

[0184] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration" and is not "preferred" or "advantageous" over other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0185] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with an em dash and a second label that distinguishes the similar component. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0186] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0187] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0188] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted similarly to the phrase "based at least in part on."

[0189] Computer-readable media includes both non-transitory computer storage media and communication media, and communication media includes any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disc storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. In addition, any connection is appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs. Disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0190] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present invention is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: receiving, from a host device, an indication of a first index corresponding to a first wear level of a plurality of indexed wear levels of a memory device; after receiving the indication of the first index, determining that a metric of the memory device satisfies the first wear level; indicating to the host device that the first wear level is satisfied based at least in part on determining that the metric of the memory device satisfies the first wear level; as well as In response to the indication, an indication of a second index is received from the host device, the second index corresponding to a second wear level of the plurality of indexed wear levels different from the first wear level.

2. The method according to claim 1, further comprising: accessing a plurality of bits of a first register, the plurality of bits representing the indication of the first index, wherein each value of the plurality of bits of the first register corresponds to a respective band index wear level in the plurality, and wherein receiving the indication of the first index is based at least in part on accessing the plurality of bits representing the indication of the first index; and The plurality of bits of the first register are accessed, the plurality of bits representing the indication of the second index, wherein receiving the indication of the second index is based at least in part on accessing the plurality of bits representing the indication of the second index.

3. The method according to claim 1, further comprising: Based at least in part on receiving the indication of the first wear level, determining health monitoring information comprising one or more metrics, each metric indicating a level of wear of a corresponding component of the memory device, the one or more metrics including the metric, wherein determining that the metric satisfies the first wear level is based at least in part on determining the health monitoring information.

4. The method according to claim 1, further comprising: An indication of a degradation type corresponding to the metric is transmitted to the host device, the degradation type comprising threshold voltage degradation, hot carrier stress degradation, negative bias temperature instability stress degradation, or any combination thereof.

5. The method according to claim 4, further comprising: A request is received from the host device for the degradation type corresponding to the metric, wherein transmitting the indication is based at least in part on the request.

6. The method of claim 1 , wherein indicating that the first wear level is met further comprises: A bit in a second register is set to indicate that the first wear level is met.

7. The method according to claim 6, further comprising: In response to determining that the first wear level is met, a pin is set to a first value, wherein the pin instructs the host device to monitor the second register.

8. The method of claim 1, wherein the metric corresponds to a degradation level of one or more transistors of the memory device, the one or more transistors being of a first transistor type among a plurality of transistor types of the memory device.

9. The method of claim 8, wherein each transistor type in the plurality corresponds to a respective degradation rate during operation of the memory device.

10. The method according to claim 8, further comprising: normalizing one or more measurements associated with a transistor type in the plurality of transistor types to obtain a respective wear level associated with the metric, wherein each transistor type in the plurality is associated with a respective function for normalizing the one or more associated measurements; and The corresponding wear level associated with the metric is compared to the first wear level, wherein determining that the metric satisfies the first wear level is based at least in part on the comparison.

11. The method according to claim 1 , further comprising: after receiving the indication of the second index, determining that the metric of the memory device satisfies the second wear level; indicating to the host device that the second wear level is satisfied based at least in part on determining that the metric satisfies the second wear level; as well as In response to the indication, an indication of a third index is received from the host device, the third index corresponding to a third wear level of the plurality of indexed wear levels that is different from the first wear level and the second wear level.

12. The method of claim 1, further comprising: after receiving the indication of the second index, determining that a second metric of the memory device satisfies the second wear level, the second metric being different from the metric; indicating to the host device that the second wear level is satisfied based at least in part on determining that the second metric of the memory device satisfies the second wear level; as well as In response to the indication, an indication of a third index is received from the host device, the third index corresponding to a third wear level of the plurality of indexed wear levels that is different from the first wear level and the second wear level.

13. The method of claim 1, further comprising: measuring a timing parameter or a threshold voltage associated with a transistor of the memory device; and The metric is determined based at least in part on the timing parameter or the threshold voltage.

14. The method according to claim 13, further comprising: A plurality of measurements associated with the transistor are obtained via one or more sensors, wherein the metric is a function based at least in part on the plurality of measurements.

15. The method of claim 1, wherein the memory device comprises a plurality of registers, each register in the plurality corresponding to a respective metric in a plurality of metrics each associated with a wear level of the memory device.

16. A method comprising: indicating a first index to a memory device, the first index corresponding to a first wear level of a plurality of indexed wear levels of the memory device; receiving, from the memory device, an indication that a metric of the memory device satisfies the first wear level based at least in part on indicating the first index; as well as In response to the indication, a second index is indicated to the memory device, the second index corresponding to a second wear level of the plurality of indexed wear levels that is different from the first wear level.

17. The method according to claim 16, further comprising: writing a first value to a plurality of bits of a first register to indicate the first index, each value in the plurality of bits corresponding to a respective band-indexed wear level in the plurality, wherein the first value corresponds to the first wear level; and A second value is written to the plurality of bits of the first register to indicate the second index, wherein the second value corresponds to the second wear level.

18. The method according to claim 17, wherein: the second value is a value adjacent to the first value in a list of values ​​corresponding to the plurality of indexed wear levels; and The first index is indicated based at least in part on the second value being a neighboring value to the first value.

19. The method of claim 17, further comprising: The second index is selected based at least in part on one or more parameters associated with the memory device, wherein the second value is different from a value adjacent to the first value in a list of values ​​corresponding to the plurality of indexed wear levels.

20. The method of claim 16, further comprising: An indication of a degradation type corresponding to the metric is received from the memory device, the degradation type comprising threshold voltage degradation, hot carrier stress degradation, negative bias temperature instability stress degradation, or any combination thereof.

21. The method of claim 20, further comprising: A request for the degradation type corresponding to the metric is transmitted to the memory device, wherein receiving the indication is based at least in part on transmitting the request.

22. The method of claim 16, wherein receiving the indication comprises: A read command of a second register of the memory device is transmitted, wherein receiving the indication from the memory device is based at least in part on transmitting the read command.

23. The method of claim 22, further comprising: A pin identifying the memory device is set to a first value, wherein the pin indicates that the indication is stored at the second register.

24. The method of claim 16, wherein the metric corresponds to a degradation level of one or more transistors of the memory device, the one or more transistors being of a first transistor type among a plurality of transistor types of the memory device.

25. The method of claim 24, further comprising: Based at least in part on the metric satisfying the first wear level, a respective degradation rate of each of the one or more transistors is determined, wherein each transistor type of the plurality of transistor types corresponds to a respective degradation rate during operation of the memory device.

26. The method of claim 24, further comprising: normalizing one or more measurements associated with a transistor type in the plurality of transistor types to obtain a respective wear level associated with the metric, wherein each transistor type in the plurality is associated with a respective process for normalizing the one or more associated measurements; and The corresponding wear level associated with the metric is compared to the first wear level.

27. The method of claim 16, further comprising: receiving, from the memory device, a second indication that the metric of the memory device satisfies the second wear level based at least in part on indicating the second index; as well as Based at least in part on the second indication, a third index is indicated to the memory device, the third index corresponding to a third wear level of the plurality of indexed wear levels that is different from the first wear level and the second wear level.

28. The method of claim 16, further comprising: receiving, from the memory device, a second indication that a second metric of the memory device satisfies the second wear level based at least in part on indicating the second index, the second metric being different from the metric; as well as Based at least in part on the second indication, a third index is indicated to the memory device, the third index corresponding to a third wear level of the plurality of indexed wear levels that is different from the first wear level and the second wear level.

29. An apparatus comprising: memory cell array; First register; a second register configured to indicate whether a wear level of the device is met; as well as A circuit system configured to: receiving, from a host device via the first register, an indication of a first index corresponding to a first wear level of a plurality of indexed wear levels of the apparatus; upon receiving the indication of the first index, determining that a metric of the device satisfies the first wear level; indicating to the host device via the second register that the first wear level is satisfied based at least in part on determining that the metric of the device satisfies the first wear level; as well as In response to the indication, an indication of a second index is received from the host device via the first register, the second index corresponding to a second wear level of the plurality of indexed wear levels different from the first wear level.

30. The apparatus of claim 29, wherein the circuitry is configured to: accessing a plurality of bits of the first register, the plurality of bits representing the first index, wherein each value of the plurality of bits of the first register corresponds to a respective band-indexed wear level in the plurality, and wherein receiving the indication of the first index is based at least in part on accessing the plurality of bits representing the first index; and The plurality of bits of the first register are accessed, the plurality of bits representing the indication of the second index, wherein receiving the indication of the second index is based at least in part on accessing the plurality of bits representing the indication of the second index.

31. The apparatus of claim 29, wherein the circuitry is configured to: Based at least in part on receiving the indication of the first wear level, determining health monitoring information comprising one or more metrics, each metric indicating a level of wear of a corresponding component of the device, the one or more metrics including the metric, wherein determining that the metric satisfies the first wear level is based at least in part on determining the health monitoring information.

32. The apparatus of claim 29, wherein the circuitry is configured to: A bit in the second register is set to indicate that the first wear level is met.

33. The apparatus of claim 32, further comprising: a pin configured to instruct the host device to monitor the second register, wherein the circuit system is configured to: In response to determining that the first wear level is met, the pin is set high.

34. An apparatus comprising: A circuit system configured to: indicating a first index to a memory device coupled to the apparatus, the first index corresponding to a first wear level of a plurality of indexed wear levels of the memory device; receiving, from the memory device, an indication that a metric of the memory device satisfies the first wear level based at least in part on indicating the first index; as well as In response to the indication, a second index is indicated to the memory device, the second index corresponding to a second wear level of the plurality of indexed wear levels that is different from the first wear level.

35. The apparatus of claim 34, wherein the circuit system is further configured to: writing a first value to a plurality of bits of a first register to indicate the first index, each value in the plurality of bits corresponding to a respective band-indexed wear level in the plurality, wherein the first value corresponds to the first wear level; and A second value is written to the plurality of bits of the first register to indicate the second index, wherein the second value corresponds to the second wear level.

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