Array substrate and display device

Abstract

An array substrate includes a planarization layer; an anode material layer on the planarization layer and in a peripheral region of the array substrate; and a plurality of gas release vias extending through the anode material layer configured to release gas in the planarization layer during a manufacturing process. An opening size of a first respective gas release via in a first region is smaller than an opening size of a second respective gas release via in a second region.

Description

TECHNICAL FIELD

[0001] The present application relates to display technology, and in particular, to an array substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) displays are one of the hotspots in the field of flat panel display research today. Unlike thin film transistor liquid crystal displays (TFT-LCDs) that use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control luminance. An OLED display panel includes a plurality of pixel units configured with pixel driving circuits arranged in a plurality of rows and a plurality of columns. Each pixel driving circuit includes a driving transistor having a gate terminal and a drain terminal, each row of gate terminals is connected to a gate line, and each column of drain terminals is connected to a data line. When a row in which a pixel unit is selected is turned on, a switch transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line to the driving transistor via the switch transistor, so that the driving transistor outputs a current corresponding to the data voltage to an OLED device. The OLED device is driven to emit light of a corresponding brightness. SUMMARY

[0003] In one aspect, the present disclosure provides an array substrate, comprising: a planarization layer; an anode material layer on the planarization layer and in a peripheral region of the array substrate; and a plurality of gas release vias extending through the anode material layer configured to release a gas in the planarization layer during a manufacturing process; wherein an opening size of a first respective gas release via in a first region is smaller than an opening size of a second respective gas release via in a second region.

[0004] Optionally, the array substrate further comprises a pixel defining material layer including a plurality of via blocks spaced apart from each other on the anode material layer, a respective via block covering and filling a respective gas release via; wherein a width of a portion of the respective via block outside the respective gas release via is greater than an opening width of the respective gas release via.

[0005] Optionally, a first ratio of a first width of a first respective via block in the first region to a first opening width of a first respective gas release via is greater than a second ratio of a second width of a second respective via block in the second region to a second opening width of a second respective gas release via.

[0006] Optionally, the first width and the second width are substantially the same; and the first opening width is smaller than the second opening width.

[0007] Optionally, the plurality of via blocks are on a first portion of the anode material layer in a first sub-region of the peripheral region; the pixel defining material layer further comprises a pixel defining layer defining a sub-pixel opening of a light emitting element; and the pixel defining layer extends into a second sub-region of the peripheral region, covering and filling a second portion of the anode material layer in the gas release via.

[0008] Optionally, the pixel defining layer extends continuously in the entire second sub-region of the peripheral region.

[0009] Optionally, in at least one corner region of the array substrate, an opening size of at least one gas release via in the first sub-region is smaller than an opening size of at least one gas release via in the second sub-region.

[0010] Optionally, in at least one non-corner region of the array substrate, an opening size of at least one gas release via in the first sub-region is substantially the same as an opening size of at least one gas release via in the second sub-region.

[0011] Optionally, an opening size of at least one gas release via underneath an edge portion of the pixel defining layer bordering the first sub-region is smaller than an opening size of at least one gas release via in the first sub-region, and smaller than an opening size of at least one gas release via underneath a non-edge portion of the pixel defining layer.

[0012] Optionally, an opening size of at least one gas release via in the first sub-region bordering an edge portion of the pixel defining layer is smaller than an opening size of at least another gas release via in the first sub-region, the at least another gas release via being spaced apart from the edge portion by the at least one gas release via.

[0013] Optionally, an opening size of at least one gas release via in the first sub-region of the array substrate and in a corner region is smaller than an opening size of at least one gas release via in the first sub-region of the array substrate and in a non-corner region.

[0014] Optionally, the peripheral region includes a first side area located at a first side of the display region, a second side area located at a second side of the display region, a third side area located at a third side of the display region, and a fourth side area located at a fourth side of the display region; the first side is opposite to the fourth side; the second side is opposite to the third side; the first side area is configured as an integrated circuit; an opening size of at least one gas release via in the first sub-region and in a corner area connecting the second side area and the fourth side area or in a corner area connecting the third side area and the fourth side area is smaller than an opening size of at least one gas release via in the first sub-region and in a corner area connecting the first side area and the second side area or in a corner area connecting the first side area and the third side area.

[0015] Optionally, an opening size of the at least one gas release via in the first sub-region and in a corner area connecting the first side area and the second side area or in a corner area connecting the first side area and the third side area is smaller than an opening size of at least one gas release via in the first sub-region and in a non-corner area of the array substrate.

[0016] Optionally, the array substrate includes a peripheral voltage supply line in the peripheral region; wherein the anode material layer is a layer where the peripheral voltage supply line is located.

[0017] Optionally, the peripheral voltage supply line is a signal line configured to provide a voltage signal to a cathode of a light emitting element in a display region of the array substrate.

[0018] Optionally, the array substrate further includes a pixel defining material layer on the anode material layer; wherein the peripheral voltage supply line further includes a cathode material layer in the peripheral region, the cathode material layer is located on a side of the pixel defining material layer and the anode material layer away from the planarization layer; and the cathode material layer is connected with the anode material layer.

[0019] Optionally, the pixel defining material layer includes: a plurality of via blocks spaced apart from each other on the anode material layer, each via block covers and fills each gas release via; and a pixel defining layer respectively defines a sub-pixel opening of a light emitting element; wherein the plurality of via blocks are located in a first sub-region of the peripheral region; the pixel defining layer extends into a second sub-region of the peripheral region; and the cathode material layer at least partially exists in the first sub-region and at least partially does not exist in the second sub-region.

[0020] Optionally, the peripheral voltage supply line further comprises a signal line material layer on a side of the planarization layer distal from the anode material layer; and the anode material layer is connected to the signal line material layer through one or more peripheral vias in the peripheral region and extending through the planarization layer.

[0021] Optionally, the array substrate further comprises a plurality of second gas release vias extending through the signal line material layer for releasing gas in an insulating layer underneath the signal line material layer during a manufacturing process; and a normal projection of the second gas release vias in the signal line material layer onto the base substrate at least partially overlaps a normal projection of the gas release vias in the anode material layer onto the base substrate.

[0022] Optionally, a ratio of an opening size of the first respective gas release via in the first region to an opening size of the second respective gas release via in the second region is in a range of 1:1.5 to 1:5.0.

[0023] Optionally, the first ratio is 25% to 250% larger than the second ratio.

[0024] Optionally, a first thickness of a first respective via block in the first region is greater than a second thickness of a second respective via block in the second region.

[0025] Optionally, an opening size of a gas release via covered and filled by the first respective via block and the second respective via block, respectively, is substantially the same.

[0026] In another aspect, the disclosure provides a display device comprising an array substrate described herein or manufactured by a method described herein, and one or more integrated circuits connected to the array substrate in an integrated circuit bonding region. BRIEF DESCRIPTION OF DRAWINGS

[0027] According to various disclosed embodiments, the following drawings are merely examples for illustrative purposes and are not intended to limit the scope of the present invention.

[0028] FIG. 1 Optical microscope and focused ion beam images showing damage caused by electrostatic discharge between a fine metal mask and a substrate.

[0029] FIG. 2 Mechanism showing electrostatic discharge occurring during manufacturing of an array substrate.

[0030] FIG. 3A is a schematic diagram showing structures of selected layers in a peripheral region of an array substrate according to some embodiments of the present disclosure.

[0031] FIG. 3B is a schematic diagram showing the structure of the planarization layer in FIG. 3A

[0032] FIG. 3C is a schematic diagram showing the structure of the anode material layer in FIG. 3A

[0033] FIG. 3D is a schematic diagram showing the structure of the pixel definition material layer in FIG. 3A

[0034] FIG. 3E is a cross-sectional view along the line A-A' in FIG. 3A

[0035] FIG. 4 shows the structure of selected layers in a first region and a second region of a peripheral region of an array substrate in some embodiments according to the present disclosure.

[0036] FIG. 5 is a schematic diagram showing a display region and a peripheral region in an array substrate in some embodiments according to the present disclosure.

[0037] FIG. 6 is a schematic diagram showing the structure of selected layers in a first corner region in an array substrate in some embodiments according to the present disclosure.

[0038] FIG. 7 is a schematic diagram showing the structure of selected layers in a third side region of a peripheral region and a portion of a display region of an array substrate in some embodiments according to the present disclosure.

[0039] FIG. 8 is a schematic diagram showing the structure of selected layers in a portion of a display region and a third corner region in an array substrate in some embodiments according to the present disclosure.

[0040] FIG. 9A shows a first sub-region and a second sub-region of a peripheral region shown in FIG. 6

[0041] FIG. 9B shows a first sub-region and a second sub-region of a peripheral region shown in FIG. 7

[0042] FIG. 9C shows a first sub-region and a second sub-region of a peripheral region shown in FIG. 8

[0043] FIG. 10A shows a first portion and a second portion of an anode material layer shown in FIG. 6 ​​​​​​​​

[0044] FIG. 10B shows FIG. 7 a first portion and a second portion of the anode material layer shown in

[0045] FIG. 10C shows FIG. 8 a first portion and a second portion of the anode material layer shown in

[0046] FIG. 11A shows FIG. 6 an edge portion and a non-edge portion of the pixel defining layer shown in

[0047] FIG. 11B shows FIG. 7 an edge portion and a non-edge portion of the pixel defining layer shown in

[0048] FIG. 11C shows FIG. 8 an edge portion and a non-edge portion of the pixel defining layer shown in

[0049] FIG. 12A is a schematic diagram showing structures of selected layers in a peripheral region of an array substrate in some embodiments according to the present disclosure.

[0050] FIG. 12B is a schematic diagram showing FIG. 12A structures of signal line material layers of

[0051] FIG. 12C is a schematic diagram showing FIG. 12A structures of planarization layers in

[0052] FIG. 12D is a schematic diagram showing FIG. 12A structures of anode material layers in

[0053] FIG. 12E is a schematic diagram showing FIG. 12A structures of pixel defining material layers of

[0054] FIG. 12F is a schematic diagram showing FIG. 12A structures of cathode material layers in

[0055] FIG. 12G is a cross-sectional view along line B-B' in FIG. 12A

[0056] FIG. 13A is a schematic diagram showing structures of selected layers in a peripheral region of an array substrate in some embodiments according to the present disclosure.

[0057] FIG. 13B is a schematic diagram showing FIG. 13A ​A schematic diagram of the gate-on-array structure.

[0058] FIG. 13C It is shown FIG. 13A A schematic diagram of the structure of the signal line material layer.

[0059] FIG. 13D It is shown FIG. 13A A schematic diagram of the planarization layer structure.

[0060] FIG. 13E To show FIG. 13A A schematic diagram of the structure of the anode material layer.

[0061] FIG. 13F It is shown FIG. 13A A schematic diagram of the structure of the pixel-defined material layer.

[0062] FIG. 13G It is shown FIG. 13A A schematic diagram of the structure of the cathode material layer.

[0063] FIG. 13H It is along FIG. 13A A cross-sectional view of line C-C' in the diagram.

[0064] FIG. 13I This is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0065] FIG. 14 The structure of selected layers in a first and second region of the peripheral region of an array substrate is shown in some embodiments of the present disclosure.

[0066] FIG. 15 The structure of selected layers in a first and second region of the peripheral region of an array substrate is shown in some embodiments of the present disclosure.

[0067] FIG. 16 This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure.

[0068] FIG. 17 The detailed structure of a display area in a display device is shown according to some embodiments of the present disclosure.

[0069] FIG. 18 The detailed structure of a display area in a display device is shown according to some embodiments of the present disclosure.

[0070] FIG. 19 This is a schematic diagram illustrating the layout of certain signal lines in a display device according to some embodiments of the present disclosure. Detailed Implementation

[0071] The present disclosure will now be described in greater particularity by reference to the following examples. It should be noted that the following description of some examples presented herein is merely illustrative and is in no way limiting. It is not exhaustive or limited to the precise forms presented.

[0072] In manufacturing an organic light emitting diode array substrate, an organic light emitting material layer is typically deposited onto a substrate by evaporation using a fine metal mask. One of the problems of the fine metal mask is that the fine metal mask can come into contact with the substrate. When the fine metal mask is in close contact with the substrate, electrostatic discharge often occurs between the fine metal mask and portions of the substrate. In some cases, the electrostatic discharge can damage the encapsulation structure on the substrate, resulting in encapsulation failure. Therefore, the manufactured display panel can have a gradually increasing dark spot problem, adversely affecting display quality.

[0073] FIG. 1 Optical microscope and focused ion beam images showing damage caused by electrostatic discharge between a fine metal mask and a substrate are shown. Referring to FIG. 1 , the upper left image is an optical microscope image revealing a damaged spot (dark spot in the circle) in the substrate caused by electrostatic discharge. The upper right image is a magnified view of the damaged spot in the upper left image. The lower left image is a focused ion beam image of the damaged spot. The lower right image is another focused ion beam image showing a damaged layer in the damaged spot.

[0074] FIG. 2 A mechanism in which electrostatic discharge occurs during the manufacturing of an array substrate is shown. Referring to FIG. 2 , a fine metal mask ("FMM mask") is placed on top of a substrate having a plurality of manufactured layers including a planarization layer PLN, an anode material layer AML in a peripheral area PA of the substrate and on the planarization layer PLN, and a plurality of gas release vias grv extending through the anode material layer AML, the gas release vias grv being configured to release gas in the planarization layer PLN during the manufacturing process. The anode material layer AML is in the same layer as anodes AD of light emitting elements in a display area DA of the substrate. The plurality of via blocks VB are in the same layer as a pixel defining layer PDL in the display area DA. The substrate further includes a plurality of via blocks VB spaced apart from each other on the anode material layer AML. Each via block is in each gas release via.

[0075] As FIG. 2As shown, when the fine metal mask is placed on the substrate, the fine metal mask is partially supported by the first barrier layer DAM1 and the spacer layer PS on the pixel defining layer PDL. The second barrier layer DAM2 is shorter than the first barrier layer DAM1, so it does not support the fine metal mask. Due to the magnetic attraction effect between the fine metal mask and the substrate, the fine metal mask undergoes deformation, moving towards the substrate. When the anode material layer AML is not completely wrapped or coated by the plurality of via blocks VB along the edges of the gas release vias grv, the edges of the anode material layer AML are exposed. An electrostatic discharge occurs between the fine metal mask and the edges of the anode material layer AML, damaging the substrate during the deposition process.

[0076] Accordingly, the present disclosure provides, among other things, an array substrate and a display apparatus that substantially obviate one or more problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a planarization layer; an anode material layer on the planarization layer and in a peripheral region of the array substrate; and a plurality of gas release vias extending through the anode material layer configured to release a gas in the planarization layer during a manufacturing process. Optionally, an opening size of a first respective gas release via in a first region is smaller than an opening size of a second respective gas release via in a second region. As used herein, the term opening size refers to an opening area or an opening width. In one example, the term opening size refers to a maximum opening width of the opening, e.g., a maximum width at both ends of the opening. In another example, the term opening size refers to an average opening width of the opening. In another example, the term opening size refers to a minimum opening width of the opening.

[0077] FIG. 3A FIG. 1 is a schematic diagram illustrating a structure of selected layers in a peripheral region of an array substrate according to some embodiments of the present disclosure. FIG. 3B FIG. 2 is a schematic diagram illustrating a structure of a planarization layer in the array substrate of FIG. 1. FIG. 3A FIG. 3 is a schematic diagram illustrating a structure of the planarization layer in the array substrate of FIG. 1. FIG. 3C FIG. 4 is a schematic diagram illustrating a structure of an anode material layer in the array substrate of FIG. 1. FIG. 3A FIG. 5 is a schematic diagram illustrating a structure of the anode material layer in the array substrate of FIG. 1. FIG. 3D FIG. 6 is a schematic diagram illustrating a structure of a pixel defining material layer in the array substrate of FIG. 1. Referring to FIG. 6, the pixel defining material layer PDL is disposed on the anode material layer AML and in the peripheral region of the array substrate. The pixel defining material layer PDL includes a plurality of pixel defining material blocks PDB, each of which defines a pixel PXL of the array substrate. The pixel defining material layer PDL also includes a plurality of via blocks VB, each of which defines a gas release via grv of the array substrate. FIG. 3A FIG. 7 is a schematic diagram illustrating a structure of the pixel defining material layer in the array substrate of FIG. 1. FIG. 3A to FIG. 3C In some embodiments, the array substrate includes a planarization layer PLN; an anode material layer AML on the planarization layer PLN and in a peripheral region of the array substrate; and a plurality of gas release vias grv extending through the anode material layer AML and configured to release a gas in the planarization layer PLN during a manufacturing process. Referring to FIG. 8, the array substrate includes a plurality of pixel defining material blocks PDB, each of which defines a pixel PXL of the array substrate. The array substrate also includes a plurality of via blocks VB, each of which defines a gas release via grv of the array substrate. FIG. 3A FIG. 9 is a schematic diagram illustrating a structure of the array substrate of FIG. 1. FIG. 3DIn some embodiments, the array substrate further comprises a pixel-defining material layer comprising a plurality of via blocks VB located on the anode material layer AML and spaced apart from each other.

[0078] FIG. 3E is a cross-sectional view along line A-A' in FIG. 3A . As shown in FIG. 3E , the respective via block RVB covers and fills the respective gas release via rgrv. The portion of the respective via block RVB outside the respective gas release via rgrv has a width W, which is greater than the opening width AP of the respective gas release via rgrv.

[0079] In some embodiments, the gas release vias grv have different opening sizes in different regions, respectively. Optionally, the opening size of a first respective gas release via in a first region is smaller than the opening size of a second respective gas release via in a second region. In some embodiments, the ratio of the opening size of the first respective gas release via in the first region to the opening size of the second respective gas release via in the second region is in the range of 1:1.5 to 1:5.0, for example, 1:1.5 to 1:2.0, 1:2.0 to 1:2.5, 1:2.5 to 1:3.0, 1:3.0 to 1:3.5, 1:3.5 to 1:4.0, 1:4.0 to 1:4.5, or 1:4.5 to 1:5.0. In some embodiments, the opening size of the first respective gas release via in the first region is at least 5% smaller than the opening size of the second respective gas release via in the second region, for example, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85%.

[0080] In some embodiments, the gas release vias grv have different opening widths in different regions, respectively. Optionally, the opening width of a first respective gas release via in the first region is smaller than the opening width of a second respective gas release via in the second region. In some embodiments, the ratio of the opening width of a first respective gas release via in the first region to the opening width of a second respective gas release via in the second region is in the range of 1 : 1.5 to 1 : 5.0, for example, 1 : 1.5 to 1 : 2.0, 1 : 2.0 to 1 : 2.5, 1 : 2.5 to 1 : 3.0, 1 : 3.0 to 1 : 3.5, 1 : 3.5 to 1 : 4.0, 1 : 4.0 to 1 : 4.5, or 1 : 4.5 to 1 : 5.0. In some embodiments, the opening width of a first respective gas release via in the first region is at least 5% smaller than the opening width of a second respective gas release via in the second region, for example, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85%. In one example, the term opening width refers to the maximum opening width. In another example, the term opening width refers to the maximum opening width of the opening, for example, the maximum width at both ends of the opening. In another example, the term opening width refers to the average opening width of the opening. In another example, the term opening width refers to the minimum opening width of the opening.

[0081] FIG. 4 The structure of selected layers in the first and second regions of the peripheral region of the array substrate in some embodiments according to the present disclosure is shown. Referring to FIG. 4 , the peripheral region of the array substrate includes a first region R1 and a second region R2. In the first region R1, a first respective gas release via rgrv1 has a first opening width AP1. In the second region R2, a second respective gas release via rgrv2 has a second opening width AP2. Optionally, the first opening width AP1 is smaller than the second opening width AP2.

[0082] As above, the electrostatic discharge problem is related to the exposed edge of the anode material layer that is not sufficiently coated by the plurality of via blocks or pixel defining layers. Therefore, in some embodiments, a problematic region of the array substrate in which the edge of the anode material layer is prone to be exposed can be identified. In the identified region (“first region”), the structure of the array substrate can be different from that in a region in which the edge of the anode material layer is not exposed (“second region”).

[0083] FIG. 5 A schematic diagram showing the display region and the peripheral region in the array substrate in some embodiments according to the present disclosure is shown. Referring to FIG. 5In some embodiments, the array substrate includes a display area DA and a peripheral area PA. In some embodiments, the peripheral area PA includes a first side area PA1 located at a first side S1 of the display area DA, a second side area PA2 located at a second side S2 of the display area DA, a third side area PA3 located at a third side S3 of the display area DA, and a fourth side area PA4 located at a fourth side S4 of the display area DA. Optionally, the first side S1 and the fourth side S4 are opposite to each other. Optionally, the second side S2 and the third side S3 are opposite to each other. Optionally, the first side area PA1 includes an integrated circuit bonding area on which an integrated circuit, such as a display control integrated circuit and / or a touch control integrated circuit, is bonded. In some embodiments, the peripheral area PA further includes a first corner area CR1 connecting the third side area PA3 and the fourth side area PA4, a second corner area CR2 connecting the second side area PA2 and the fourth side area PA4, a third corner area CR3 connecting the first side area PA1 and the third side area PA3, and a fourth corner area CR4 connecting the first side area PA1 and the second side area PA2.

[0084] Reference is made to FIG. 5 The inventors of the present disclosure found that the first corner area CR1 and / or the second corner area CR2 are areas in which edges of the anode material layer along the openings of the gas release vias are prone to be exposed. This problem becomes particularly serious when the corner areas are rounded corner areas, and particularly when the rounded corner areas have a relatively large curvature. The inventors of the present disclosure found that in these corner areas, the alignment between the pixel defining material layer (including the plurality of via blocks and the pixel defining layer) and the anode material layer cannot be maintained with high precision compared to other areas of the peripheral area. Due to the misalignment, the edges of the anode material layer along the openings of the gas release vias are prone to be exposed.

[0085] Therefore, in some embodiments, the peripheral area of the array substrate includes a first region R1 and a second region R2. In the first region R1, a first respective gas release via rgrv1 has a first opening width AP1. In the second region R2, a second respective gas release via rgrv2 has a second opening width AP2. Optionally, the first opening width AP1 is smaller than the second opening width AP2. Optionally, the first region R1 is in the first corner area CR1. Optionally, the first region R1 is in the second corner area CR2. Optionally, the second region R2 is a region outside the corner areas of the array substrate, wherein the array substrate includes a plurality of via blocks on the anode material layer and spaced apart from each other, each via block covering and filling each gas release via. Optionally, the second region R2 is in the first side area PA1. Optionally, the second region R2 is in the second side area PA2. Optionally, the second region R2 is in the third side area PA3. Optionally, the second region R2 is in the fourth side area PA4.

[0086] FIG. 6is a schematic diagram showing the structure of selected layers in a first corner region in an array substrate according to some embodiments of the present disclosure. FIG. 7 is a schematic diagram showing the structure of selected layers in a third side region of a peripheral region and a portion of a display region of an array substrate according to some embodiments of the present disclosure. FIG. 8 is a schematic diagram showing the structure of selected layers in a portion of a display region and a third corner region in an array substrate according to some embodiments of the present disclosure. FIG. 9A shows FIG. 6 the first and second sub-regions of the peripheral region shown in FIG. 9B shows FIG. 7 the first and second sub-regions of the peripheral region shown in FIG. 9C shows FIG. 8 the first and second sub-regions of the peripheral region shown in FIG. 10A shows FIG. 6 the first and second portions of the anode material layer shown in FIG. 10B shows FIG. 7 the first and second portions of the anode material layer shown in FIG. 10C shows FIG. 8 the first and second portions of the anode material layer shown in. Referring to FIG. 6 to FIG. 8 , FIG. 9A to FIG. 9C and FIG. 10A to FIG. 10C , the array substrate further comprises a plurality of anodes AD of the plurality of light emitting elements, respectively. Optionally, the anode material layer AML and the plurality of anodes AD are in the same layer. Optionally, the anode material layer AML comprises a first portion P1 in the first sub-region Sa1 of the peripheral region and a second portion P2 in the second sub-region Sa2 of the peripheral region.

[0087] In some embodiments, the array substrate further comprises a pixel defining material layer. In some embodiments, the pixel defining material layer comprises a plurality of via blocks VB and a pixel defining layer PDL. The plurality of via blocks VB is on the first portion P1 of the anode material layer AML in the first sub-region Sa1 of the peripheral region. The pixel defining layer PDL is mainly in the display region DA, defining sub-pixel openings SA for the plurality of light emitting elements (e.g., see FIG. 7 ). The pixel defining layer PDL extends from the display region DA into the second sub-region Sa2 of the peripheral region, covering and filling the gas release via in the second portion P2 of the anode material layer AML. Optionally, the pixel defining layer PDL continuously extends throughout the second sub-region Sa2 of the peripheral region.

[0088] In some embodiments, in at least one corner region of the array substrate, the opening size (e.g., opening width) of the at least one gas release via in the first sub-region is smaller than the opening size (e.g., opening width) of the at least one gas release via in the second sub-region. Referring to FIG. 6 In the first corner region CR1, the opening size of the at least one gas release via grva in the first sub-region Sa1 is smaller than the opening size of the at least one gas release via grvr in the second sub-region Sa2. Optionally, the corner region CR2 in FIG. 5 has a layout similar to that of the first corner region CR1, mirror-symmetric with respect to each other. Optionally, in the second corner region CR2, the opening size of the at least one gas release via in the first sub-region Sa1 is smaller than the opening size of the at least one gas release via in the second sub-region Sa2.

[0089] In some embodiments, in at least one corner region of the array substrate, the ratio of the opening size (e.g., opening width) of the at least one gas release via in the first sub-region to the opening size (e.g., opening width) of the at least one gas release via in the second sub-region is in the range of 1:1.5 to 1:5.0, e.g., 1:1.5 to 1:2.0, 1:2.0 to 1:2.5, 1:2.5 to 1:3.0, 1:3.0 to 1:3.5, 1:3.5 to 1:4.0, 1:4.0 to 1:4.5, or 1:4.5 to 1:5.0. In some embodiments, in at least one corner region of the array substrate, the opening size (e.g., opening width) of the at least one gas release via in the first sub-region is at least 5% smaller, e.g., at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85% smaller than the opening size (e.g., opening width) of the at least one gas release via in the second sub-region.

[0090] Referring to FIG. 8 In the third corner region CR3, the opening size (e.g., opening width) of the at least one gas release via grvc in the first sub-region Sa1 is smaller than the opening size (e.g., opening width) of the at least one gas release via grvr in the second sub-region Sa2. Optionally, the corner region CR4 in FIG. 5 has a layout similar to that of the third corner region CR3, optionally, mirror-symmetric with respect to each other. Optionally, in the fourth corner region CR4, the at least one gas release via in the first sub-region Sa1 has the opening size of the at least one gas release via in the second sub-region Sa2.

[0091] In some embodiments, in at least one non-corner region of the array substrate, an opening size (e.g., an opening width) of the at least one gas release via in the first sub-region is substantially the same as an opening size (e.g., an opening width) of the at least one gas release via in the second sub-region. Referring to FIG. 7 In the third side region PA3 (non-corner region), an opening size of the at least one gas release via grvb in the first sub-region Sa1 is substantially the same as an opening size of the gas release via grvr in the second sub-region Sa2. Optionally, the first side region PA1, the second side region PA2, and the fourth side region PA4 are non-corner regions, and have a layout similar to the third side region PA3. Optionally, in the first side region PA1, an opening size of the at least one gas release via in the first sub-region Sa1 is substantially the same as an opening size of the at least one gas release via in the second sub-region Sa2. Optionally, in the second side region PA2, an opening size of the at least one gas release via in the first sub-region Sa1 is substantially the same as an opening size of the at least one gas release via in the second sub-region Sa2. Optionally, in the fourth side region PA4, an opening size of the at least one gas release via in the first sub-region Sa1 is substantially the same as an opening size of the at least one gas release via in the second sub-region Sa2. FIG. 5 FIG. 5 FIG. 5

[0092] In some embodiments, an opening size (e.g., an opening width) of the at least one gas release via in the first sub-region and in a corner region of the array substrate is smaller than an opening size (e.g., an opening width) of the at least one gas release via in the first sub-region and in a non-corner region of the array substrate. Referring to FIG. 6 FIG. 7 In the first sub-region Sa1 of the array substrate and in a corner region (e.g., the first corner region CR1), an opening size of the gas release via grva is smaller than an opening size of the gas release via grvb in the first sub-region Sa1 of the array substrate and in a non-corner region (e.g., the first side region PA1, the second side region PA2, the third side region PA3, or the fourth side region PA4). Referring to FIG. 8 FIG. 7 In the first sub-region Sa1 of the array substrate and in a corner region (e.g., the third corner region CR3), an opening size of the gas release via grvc is smaller than an opening size of the gas release via grvb in the first sub-region Sa1 of the array substrate and in a non-corner region (e.g., the first side region PA1, the second side region PA2, the third side region PA3, or the fourth side region PA4).

[0093] ​​​​​In some embodiments, a ratio of an opening size (e.g., an opening width) of the at least one gas release via in the first sub-region of the array substrate and in the corner region to an opening size (e.g., an opening width) of the at least one gas release via in the first sub-region of the array substrate and in the non-corner region is in a range from 1 : 1.5 to 1 : 5.0, for example, 1 : 1.5 to 1 : 2.0, 1 : 2.0 to 1 : 2.5, 1 : 2.5 to 1 : 3.0, 1 : 3.0 to 1 : 3.5, 1 : 3.5 to 1 : 4.0, 1 : 4.0 to 1 : 4.5, or 1 : 4.5 to 1 : 5.0. In some embodiments, the opening size (e.g., the opening width) of the at least one gas release via in the first sub-region of the array substrate and in the corner region is at least 5% smaller, for example, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85% smaller than the opening size (e.g., the opening width) of the at least one gas release via in the first sub-region of the array substrate and in the non-corner region.

[0094] In some embodiments, the opening size (e.g., the opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the second side region and the fourth side region or the corner region connecting the third side region and the fourth side region is smaller than the opening size (e.g., the opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the first side region and the second side region or the corner region connecting the first side region and the third side region. Referring to FIG. 1, the opening size (e.g., the opening width) of the gas release via grva in the first sub-region Sa1 and in the first corner region CR1 (e.g., the corner region connecting the third side region PA3 and the fourth side region PA4) is smaller than the opening size (e.g., the opening width) of the gas release via grvc in the first sub-region Sa1 and in the third corner region CR3 (e.g., the corner region connecting the first side region PA1 and the third side region PA3). FIG. 6 FIG. 8 In some embodiments, the opening size (e.g., the opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the second side region and the fourth side region or the corner region connecting the third side region and the fourth side region is smaller than the opening size (e.g., the opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the first side region and the second side region or the corner region connecting the first side region and the third side region. Referring to FIG. 1, the opening size (e.g., the opening width) of the gas release via grva in the first sub-region Sa1 and in the first corner region CR1 (e.g., the corner region connecting the third side region PA3 and the fourth side region PA4) is smaller than the opening size (e.g., the opening width) of the gas release via grvc in the first sub-region Sa1 and in the third corner region CR3 (e.g., the corner region connecting the first side region PA1 and the third side region PA3).

[0095] ​In some embodiments, the ratio of the opening size (e.g., opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the second side region and the fourth side region or the corner region connecting the third side region and the fourth side region to the opening size (e.g., opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the first side region and the second side region or the corner region connecting the first side region and the third side region is in the range of 1 : 1.5 to 1 : 5.0, such as 1 : 1.5 to 1 : 2.0, 1 : 2.0 to 1 : 2.5, 1 : 2.5 to 1 : 3.0, 1 : 3.0 to 1 : 3.5, 1 : 3.5 to 1 : 4.0, 1 : 4.0 to 1 : 4.5, or 1 : 4.5 to 1 : 5.0. In some embodiments, the opening size (e.g., opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the second side region and the fourth side region or the corner region connecting the third side region and the fourth side region is at least 5% smaller, such as at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85% smaller than the opening size (e.g., opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the first side region and the second side region or the corner region connecting the first side region and the third side region.

[0096] In some embodiments, the opening size (e.g., opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the first side region and the second side region or in the corner region connecting the first side region and the third side region is smaller than the opening size (e.g., opening width) of the at least one gas release via in the first sub-region of the array substrate and in a non-corner region. See FIG. 7 and FIG. 8 In the first sub-region Sa1 and in the third corner region CR3 (e.g., the corner region connecting the first side region PA1 and the third side region PA3), the opening size of the gas release via is smaller than the opening size of the gas release via grvb in the first sub-region Sa1 and the third side region PA3 (e.g., a non-corner region of the array substrate).

[0097] In some embodiments, a ratio of an opening size (e.g., opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the first side region and the second side region or in the corner region connecting the first side region and the third side region to an opening size (e.g., opening width) of the at least one gas release via in the first sub-region of the array substrate and in the non-corner region is in a range from 1:1.5 to 1:5.0, for example, 1:1.5 to 1:2.0, 1:2.0 to 1:2.5, 1:2.5 to 1:3.0, 1:3.0 to 1:3.5, 1:3.5 to 1:4.0, 1:4.0 to 1:4.5, or 1:4.5 to 1:5.0. In some embodiments, the opening size (e.g., opening width) of the at least one gas release via in the first sub-region and in the corner region connecting the first side region and the second side region or in the corner region connecting the first side region and the third side region is at least 5% smaller, for example, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85% smaller than the opening size (e.g., opening width) of the at least one gas release via in the first sub-region of the array substrate and in the non-corner region.

[0098] FIG. 6 An edge portion and a non-edge portion of the pixel-defining layer shown in FIG. 8 An edge portion and a non-edge portion of the pixel-defining layer shown in FIG. 8 An edge portion and a non-edge portion of the pixel-defining layer shown in FIG. 6 to FIG. 8 An edge portion and a non-edge portion of the pixel-defining layer shown in FIG. 6 to FIG. 8 An edge portion and a non-edge portion of the pixel-defining layer shown in FIG. 6 An edge portion and a non-edge portion of the pixel-defining layer shown in FIG. 7 , FIG. 7 and FIG. 7 The pixel-defining layer PDL includes an edge portion EP that borders the first sub-region Sa1 and a non-edge portion NEP that is located on a side of the edge portion EP away from the first sub-region Sa1. The edge portion EP spaces the non-edge portion NEP from the first sub-region Sa1.

[0099] The inventors of the present disclosure also found that regions close to the edge portion of the pixel-defining layer are regions in which edges of the anode material layer along openings of the gas release vias are prone to be exposed. The inventors of the present disclosure found that in these regions, the alignment between the pixel-defining material layer (including the plurality of via blocks and the pixel-defining layer) and the anode material layer cannot be maintained with high precision compared to other regions of the peripheral region. Due to the misalignment, the edges of the anode material layer along the openings of the gas release vias are prone to be exposed.

[0100] Accordingly, in some embodiments, the opening size (e.g., opening width) of the at least one gas release via under the edge portion of the pixel defining layer bordering the first sub-region is smaller than the opening size (e.g., opening width) of the at least one gas release via in the first sub-region, and is smaller than the opening size (e.g., opening width) of the at least one gas release via under the non-edge portion of the pixel defining layer. Referring to FIG. 6 to FIG. 8 In the first corner region CR1, the opening size of the at least one gas release via grvs1 under the edge portion EP of the pixel defining layer PDL bordering the first sub-region Sa1 is smaller than the opening size of the at least one gas release via grva in the first sub-region Sa1, and is smaller than the opening size of the at least one gas release via grvr under the non-edge portion NEP of the pixel defining layer PDL. Optionally, the second corner region CR2) has a layout similar to that of the first corner region CR1, optionally, mirror-symmetrical with respect to each other. Optionally, in the second corner region CR2, the opening size of the at least one gas release via under the edge portion EP of the pixel defining layer PDL bordering the first sub-region Sa1 is smaller than the opening size of the at least one gas release via in the first sub-region Sa1, and is smaller than the opening size of the at least one gas release via grvr under the non-edge portion NEP of the pixel defining layer PDL. FIG. 6 to FIG. 8 In the first corner region CR1, the opening size of the at least one gas release via grvs1 under the edge portion EP of the pixel defining layer PDL bordering the first sub-region Sa1 is smaller than the opening size of the at least one gas release via grva in the first sub-region Sa1, and is smaller than the opening size of the at least one gas release via grvr under the non-edge portion NEP of the pixel defining layer PDL. Optionally, the second corner region CR2) has a layout similar to that of the first corner region CR1, optionally, mirror-symmetrical with respect to each other. Optionally, in the second corner region CR2, the opening size of the at least one gas release via under the edge portion EP of the pixel defining layer PDL bordering the first sub-region Sa1 is smaller than the opening size of the at least one gas release via in the first sub-region Sa1, and is smaller than the opening size of the at least one gas release via grvr under the non-edge portion NEP of the pixel defining layer PDL.

[0101] In some embodiments, the ratio of the opening size (e.g., opening width) of the at least one gas release via under the edge portion of the pixel defining layer bordering the first sub-region to the opening size (e.g., opening width) of the at least one gas release via in the first sub-region is in the range of 1:1.5 to 1:5.0, e.g., 1:1.5 to 1:2.0, 1:2.0 to 1:2.5, 1:2.5 to 1:3.0, 1:3.0 to 1:3.5, 1:3.5 to 1:4.0, 1:4.0 to 1:4.5, or 1:4.5 to 1:5.0. In some embodiments, the opening size (e.g., opening width) of the at least one gas release via under the edge portion of the pixel defining layer bordering the first sub-region is at least 5% smaller, e.g., at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85% smaller than the opening size (e.g., opening width) of the at least one gas release via in the first sub-region.

[0102] In some embodiments, a ratio of an opening size (e.g., opening width) of the at least one gas release via under an edge portion of the pixel-defining layer bordering the first sub-region to an opening size (e.g., opening width) of the at least one gas release via under a non-edge portion of the pixel-defining layer is in a range from 1:1.5 to 1:5.0, such as 1:1.5 to 1:2.0, 1:2.0 to 1:2.5, 1:2.5 to 1:3.0, 1:3.0 to 1:3.5, 1:3.5 to 1:4.0, 1:4.0 to 1:4.5, or 1:4.5 to 1:5.0. In some embodiments, the opening size (e.g., opening width) of the at least one gas release via under an edge portion of the pixel-defining layer bordering the first sub-region is at least 5% smaller, such as at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85% smaller than the opening size (e.g., opening width) of the at least one gas release via under a non-edge portion of the pixel-defining layer.

[0103] Referring to FIG. 8 In the third side area PA3, an opening size (e.g., opening width) of the at least one gas release via grvs1 under an edge portion EP of the pixel-defining layer PDL bordering the first sub-region Sa1 is smaller than an opening size (e.g., opening width) of the at least one gas release via grvb in the first sub-region Sa1, and is smaller than an opening size of the at least one gas release via grvr under a non-edge portion NEP of the pixel-defining layer PDL. Optionally, the first side area PA1, the second side area PA2, and the fourth side area PA4 in the first sub-region Sa1 have the same or similar configuration as the third side area PA3. FIG. 8 FIG. 12A FIG. 12B ​​The first corner region CR1 and the fourth corner region CR4 in the pixel array PA4 are both non-corner regions and have a layout similar to the third side region PA3. Optionally, in the first side region PA1, the opening size of the at least one gas release via underneath the edge portion EP of the pixel defining layer PDL bordering the first sub-region S al is smaller than the opening size of the at least one gas release via in the first sub-region S al, and smaller than the opening size of the at least one gas release via underneath the non-edge portion NEP of the pixel defining layer PDL. Optionally, in the second side region PA2, the opening size of the at least one gas release via underneath the edge portion EP of the pixel defining layer PDL bordering the first sub-region S al is smaller than the opening size of the at least one gas release via in the first sub-region S al, and smaller than the opening size of the at least one gas release via underneath the non-edge portion NEP of the pixel defining layer PDL. Optionally, in the fourth side region PA4, the opening size of the at least one gas release via underneath the edge portion EP of the pixel defining layer PDL bordering the first sub-region S al is smaller than the opening size of the at least one gas release via in the first sub-region S al, and smaller than the opening size of the at least one gas release via underneath the non-edge portion NEP of the pixel defining layer PDL.

[0104] Referring to FIG. 12A In the third corner region CR3, the opening size (e.g., opening width) of the at least one gas release via grvs1 underneath the edge portion EP of the pixel defining layer PDL bordering the first sub-region S al is smaller than the opening size (e.g., opening width) of the at least one gas release via grvc in the first sub-region S al, and smaller than the opening size of the at least one gas release via grvr underneath the non-edge portion NEP of the pixel defining layer PDL. Optionally, the fourth corner region CR4 has a similar layout as the third corner region CR3, optionally, mirror-symmetrical with respect to each other. Optionally, in the fourth corner region CR4, the opening size of the at least one gas release via underneath the edge portion EP of the pixel defining layer PDL bordering the first sub-region S al is smaller than the opening size of the at least one gas release via in the first sub-region S al, and smaller than the opening size of the at least one gas release via underneath the non-edge portion NEP of the pixel defining layer PDL. FIG. 12C

[0105] In some embodiments, the opening size (e.g., opening width) of the at least one gas release via in the first sub-region bordering the edge portion of the pixel defining layer is smaller than the opening size (e.g., opening width) of at least another gas release via in the first sub-region spaced apart from the edge portion by the at least one gas release via. Referring to FIG. 12A ​In the third corner region CR3, the opening size of the at least one gas release via grvs2 in the first sub-region bordering the edge portion EP of the pixel-defining layer PDL is smaller than the opening size of the at least one gas release via grvc in the first sub-region Sa1. The gas release via grvc is spaced apart from the edge portion EP by the gas release via grvs2.

[0106] In some embodiments, a ratio of an opening size (e.g., opening width) of the at least one gas release via in the first sub-region bordering the edge portion of the pixel-defining layer to an opening size (e.g., opening width) of at least one other gas release via in the first sub-region spaced apart from the edge portion by the at least one gas release via is in a range of 1 : 1.5 to 1 : 5.0, e.g., 1 : 1.5 to 1 : 2.0, 1 : 2.0 to 1 : 2.5, 1 : 2.5 to 1 : 3.0, 1 : 3.0 to 1 : 3.5, 1 : 3.5 to 1 : 4.0, 1 : 4.0 to 1 : 4.5, or 1 : 4.5 to 1 : 5.0. In some embodiments, the opening size (e.g., opening width) of the at least one gas release via in the first sub-region bordering the edge portion of the pixel-defining layer is at least 5% smaller, e.g., at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, or at least 85% smaller than the opening size (e.g., opening width) of at least one other gas release via in the first sub-region spaced apart from the edge portion by the at least one gas release via.

[0107] In some embodiments, a first ratio of a first width of a first respective via block in the first region to a first opening width of a first respective gas release via is greater than a second ratio of a second width of a second respective via block in the second region to a second opening width of a second respective gas release via. Referring to FIG. 12D In some embodiments, a first ratio of a first width of a first respective via block in the first region to a first opening width of a first respective gas release via is greater than a second ratio of a second width of a second respective via block in the second region to a second opening width of a second respective gas release via. Referring to

[0108] In some embodiments, the first width W1 and the second width W2 are substantially the same. As used herein, the term "substantially the same" means that the difference between the two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as not exceeding 8%, 6%, 4%, 2%, 1%, 0.5%, 0.1%, 0.05%, and 0.01% of the base value. Optionally, the first opening width AP1 is smaller than the second opening width AP2.

[0109] Reference FIG. 12A In some embodiments, FIG. 12E , FIG. 12A and FIG. 12F Multiple through-hole blocks in the structure have essentially the same width. In one example, the corner area (e.g.) FIG. 12A The first corner region CR1 or FIG. 12G The first ratio of the first width of the first corresponding through-hole block in the third corner region (CR3) to the first opening width of the first corresponding gas release through-hole is greater than that in the non-corner region (e.g., the third corner region CR3). FIG. 12A The second ratio of the second width of the second corresponding through-hole block in the third side region PA3) to the second opening width of the second corresponding gas release through-hole.

[0110] In another example, in the corner area connecting the second side area and the fourth side area, or in the corner area connecting the third side area and the fourth side area (e.g., FIG. 12A to FIG. 12G The first corner region CR1 or FIG. 12A to FIG. 12G In the third corner region CR3), the first ratio of the first width of the first corresponding through-hole block to the first opening width of the first corresponding gas release through-hole is greater than that in the corner region connecting the first side region and the second side region or the corner region connecting the first side region and the third side region (e.g., FIG. 12F The second ratio of the second width of the second corresponding through-hole block in the third corner region CR3 to the second opening width of the second corresponding gas release through-hole.

[0111] Optionally, the first ratio is 25% to 250% larger than the second ratio, for example, 25% to 35%, 35% to 45%, 45% to 55%, 55% to 65%, 65% to 75%, 75% to 85%, 85% to 95%, 95% to 105%, 105% to 115%, 115% to 125%, 125% to 135%, 135% to 145%, 145% to 155%, 155% to 165%, 165% to 175%, 175% to 185%, 185% to 195%, 195% to 205%, 205% to 215%, 215% to 225%, 225% to 235%, 235% to 245%, or 245% to 250%.

[0112] In some embodiments, a ratio of an opening size (e.g., opening width) of a first respective gas release via in the first region to an opening size (e.g., opening width) of a second respective gas release via in the second region is in a range of 1 : 1.5 to 1 : 5.0, for example, 1 : 1.5 to 1 : 2.0, 1 : 2.0 to 1 : 2.5, 1 : 2.5 to 1 : 3.0, 1 : 3.0 to 1 : 3.5, 1 : 3.5 to 1 : 4.0, 1 : 4.0 to 1 : 4.5, or 1 : 4.5 to 1 : 5.0.

[0113] Optionally, FIG. 9A to FIG. 9C The gas release vias grvr in the region have an opening width in a range of 10.5 pm to 18.5 pm, for example, 10.5 pm to 11.5 pm, 11.5 pm to 12.5 pm, 12.5 pm to 13.5 pm, 13.5 pm to 14.5 pm, 14.5 pm to 15.5 pm, 15.5 pm to 16.5 pm, 16.5 pm to 17.5 pm, or 17.5 pm to 18.5 pm. In one example, FIG. 13A The gas release vias grvr in the region have an opening width of 14.5 pm.

[0114] Optionally, FIG. 13B The gas release vias grva in the region have an opening width in a range of 3.5 pm to 10.5 pm, for example, 3.5 pm to 4.5 pm, 4.5 pm to 5.5 pm, 5.5 pm to 6.5 pm, 6.5 pm to 7.5 pm, 7.5 pm to 8.5 pm, 8.5 pm to 9.5 pm, or 9.5 pm to 10.5 pm. In one example, FIG. 13A The gas release vias grva in the region have an opening width of 7.5 pm.

[0115] Optionally, FIG. 13C The gas release vias grvb in the region have an opening width in a range of 10.5 pm to 18.5 pm, for example, 10.5 pm to 11.5 pm, 11.5 pm to 12.5 pm, 12.5 pm to 13.5 pm, 13.5 pm to 14.5 pm, 14.5 pm to 15.5 pm, 15.5 pm to 16.5 pm, 16.5 pm to 17.5 pm, or 17.5 pm to 18.5 pm. In one example, FIG. 13A The gas release vias grvb in the region have an opening width of 14.5 pm.

[0116] Optionally, FIG. 13DThe gas release via-hole grvs1 in the gas release layer 130 has an opening width in a range from 3.5 μm to 10.5 μm, such as 3.5 μm to 4.5 μm, 4.5 μm to 5.5 μm, 5.5 μm to 6.5 μm, 6.5 μm to 7.5 μm, 7.5 μm to 8.5 μm, 8.5 μm to 9.5 μm, or 9.5 μm to 10.5 μm. In one example, FIG. 13A The gas release via-hole grvs in the gas release layer 130 has an opening width of 7.5 μm.

[0117] Optionally, FIG. 13E The gas release via-hole grvs2 in the gas release layer 130 has an opening width in a range from 3.5 μm to 10.5 μm, such as 3.5 μm to 4.5 μm, 4.5 μm to 5.5 μm, 5.5 μm to 6.5 μm, 6.5 μm to 7.5 μm, 7.5 μm to 8.5 μm, 8.5 μm to 9.5 μm, or 9.5 μm to 10.5 μm. In one example, FIG. 13A The gas release via-hole grvs2 in the gas release layer 130 has an opening width of 7.5 μm.

[0118] In some embodiments, the array substrate includes a peripheral voltage supply line in the peripheral region. The anode material layer is the layer where the peripheral voltage supply line is located. In one example, the peripheral voltage supply line is a signal line (e.g., a low voltage signal line) configured to provide a voltage signal (e.g., a Vss signal) to the cathode of a light emitting element in the display region of the array substrate.

[0119] FIG. 13F is a schematic diagram showing the structure of selected layers in the peripheral region of the array substrate in some embodiments according to the present disclosure. FIG. 13A is a schematic diagram showing the structure of the signal line material layer of FIG. 13G . FIG. 13A is a schematic diagram showing the structure of the planarization layer of FIG. 13H . FIG. 13A is a schematic diagram showing the structure of the anode material layer of FIG. 13A to FIG. 13H . FIG. 13A to FIG. 13H is a schematic diagram showing the structure of the pixel defining material layer of FIG. 13B . FIG. 13H is a schematic diagram showing the structure of the cathode material layer of FIG. 13I . FIG. 13I is a cross-sectional view along the line B-B' of FIG. 4 . FIG. 6 to FIG. 7 shows the structure of layers in the peripheral region of the array substrate where there is no gate on array. Refer to FIG. 14In some embodiments, the peripheral voltage supply line further includes a cathode material layer CML located in the peripheral region and on a side of the pixel-defining material layer (e.g., the plurality of via blocks VB) and the anode material layer AML distal from the planarization layer PLN. The cathode material layer CML is connected to the anode material layer AML.

[0120] In some embodiments, as shown in FIG. 14 and FIG. 15 , the cathode material layer CML is at least partially present in the first sub-region Sa1 and at least partially absent in the second sub-region Sa2. Optionally, the cathode material layer CML is at least partially present in the first sub-region Sa1 and completely absent in the second sub-region Sa2.

[0121] In some embodiments, the peripheral voltage supply line further includes a signal line material layer pvss located on a side of the planarization layer PLN distal from the anode material layer AML. For example, the planarization layer PLN is located between the signal line material layer pvss and the anode material layer AML. The anode material layer AML is connected to the signal line material layer pvss by one or more peripheral vias pv in the peripheral region and extending through the planarization layer PLN.

[0122] FIG. 15 is a schematic diagram showing the structure of selected layers in the peripheral region of an array substrate in some embodiments according to the present disclosure. FIG. 16 is a schematic diagram showing the structure of an array-on-gate in FIG. 16 . FIG. 17 is a schematic diagram showing the structure of a signal line material layer in FIG. 17 . FIG. 18 is a schematic diagram showing the structure of a planarization layer in FIG. 18 . FIG. 17 is a schematic diagram showing the structure of an anode material layer in FIG. 18 . FIG. 4 is a schematic diagram showing the structure of a pixel-defining material layer in FIG. 4 . FIG. 6 to FIG. 8 is a schematic diagram showing the structure of a cathode material layer in FIG. 12F . FIG. 12G is a cross-sectional view along line C-C' in FIG. 17 . FIG. 12F shows the structure of layers in the peripheral region of an array substrate in which an array-on-gate is present.

[0123] Referring to FIG. 12G , the array substrate includes one or more array-on-gate circuits on the base substrate BS in the peripheral region (e.g., as shown in FIG. 18The gate GOA and the EM GOA shown), a signal line material layer pvss on a side of the one or more array-on-gate circuits that is distal to the base substrate BS, a planarization layer PLN on a side of the signal line material layer pvss that is distal to the one or more array-on-gate circuits, an anode material layer AML on a side of the planarization layer PLN that is distal to the signal line material layer pvss, a plurality of via blocks VB on a side of the anode material layer AML that is distal to the planarization layer PLN, and a cathode material layer CML on a side of the plurality of via blocks VB that is distal to the anode material layer AML. The anode material layer AML is connected to the signal line material layer pvss through one or more peripheral vias pv in the peripheral region and extending through the planarization layer PLN.

[0124] In some embodiments, the array substrate further comprises a plurality of second gas release vias 2grv extending through the signal line material layer pvss for releasing gas in the insulating layer underneath the signal line material layer pvss during the manufacturing process. As FIG. 12F In some embodiments, the second gas release vias 2grv in the signal line material layer pvss have a footprint on the base substrate BS that at least partially overlaps with a footprint of the gas release vias grv in the anode material layer AML on the base substrate BS.

[0125] FIG. 12G is a cross-sectional view of an array substrate in some embodiments according to the present disclosure. Reference is made to FIG. 19 In some embodiments, the second gas release vias 2grv in the signal line material layer pvss have a footprint on the base substrate BS that at least partially does not overlap with a footprint of the gas release vias grv in the anode material layer AML on the base substrate BS.

[0126] In FIG. 19 , FIG. 19 In the embodiments shown, the gas release vias in the anode material layer AML have a non-uniform opening size in different regions of the peripheral region PA. The inventors of the present disclosure found that, as an alternative solution to the electrostatic discharge damage problem, the gas release vias in the anode material layer AML can have a uniform opening size throughout the peripheral region PA. In this alternative, the plurality of via blocks VB on the anode material layer AML can be made to have a non-uniform width in different regions of the peripheral region PA. In problematic regions such as the first corner region CR1 and / or the second corner region CR2, and in regions proximate to the edge portions of the pixel defining layer, the via blocks can be made to have a greater width. In non-corner regions, the via blocks can be made to have a smaller width.

[0127] ​ shows structures of selected layers in a first region and a second region of a peripheral region of an array substrate in some embodiments according to the present disclosure. Reference is made to​ The peripheral region of the array substrate includes a first region R1 and a second region R2. In the first region R1, a first corresponding gas release via rgrv1 has a first opening width AP1. In the second region R2, a second corresponding gas release via rgrv2 has a second opening width AP2. Optionally, the first opening width AP1 and the second opening width AP2 are substantially the same. In the first region R1, a first corresponding via block RVB1 has a first width W1. In the second region R2, a second corresponding via block RVB2 has a second width W2. Optionally, the first width W1 is greater than the second width W1. Optionally, the first ratio of the first width W1 of the first corresponding via block RVB1 in the first region R1 to the first opening width AP1 of the first corresponding gas release via rgrv1 is greater than the second ratio of the second width W2 of the second corresponding via block RVB2 in the second region R2 to the second opening width AP2 of the second corresponding gas release via rgrv2.

[0128] The inventors of this disclosure have discovered that, as an alternative solution to the electrostatic discharge damage problem, gas release vias in the anolyte layer AML can have a uniform opening size throughout the peripheral region PA. In another alternative solution, multiple via blocks VB on the anolyte layer AML can have non-uniform thicknesses in different regions of the peripheral region PA. In problematic regions such as the first corner region CR1 and / or the second corner region CR2, and in regions near the edge portions of the pixel-defining layer, the via blocks can have a greater thickness. In non-corner regions, the via blocks can have a smaller thickness.

[0129] ​ The diagram illustrates the structure of selected layers in a first and second region of the peripheral region of an array substrate according to some embodiments of the present disclosure. (Refer to...) ​The peripheral area of the array substrate includes a first region R1 and a second region R2. In the first region R1, the first corresponding gas release via rgrv1 has a first opening width AP1. In the second region R2, the second corresponding gas release via rgrv2 has a second opening width AP2. Optionally, the first opening width AP1 is substantially the same as the second opening width AP2. In the first region R1, the first corresponding via block RVB1 has a first thickness T1. In the second region R2, the second corresponding via block RVB2 has a second thickness T2. Optionally, the first thickness T1 is greater than the second thickness T2. The first width W1 can be substantially the same as the second width W2. Optionally, a first ratio of the first thickness T1 of the first corresponding via block RVB1 in the first region R1 to the first opening width AP1 of the first corresponding gas release via rgrv1 in the first region R1 is greater than a second ratio of the second thickness T2 of the second corresponding via block RVB2 in the second region R2 to the second opening width AP2 of the second corresponding gas release via rgrv2 in the second region R2.

[0130] In another aspect, the present disclosure provides a display device including the array substrate herein and one or more integrated circuits connected to the array substrate in an integrated circuit bonding area. ​ is a schematic diagram showing a structure of a display device in some embodiments according to the present disclosure. Refer to ​ The display device includes the array substrate herein and one or more integrated circuits IC connected to the array substrate in an integrated circuit bonding area.

[0131] In some embodiments, the display device includes a display area DA and a peripheral area PA. In some embodiments, the peripheral area PA includes a first side region PA1 located at a first side S1 of the display area DA, a second side region PA2 located at a second side S2 of the display area DA, a third side region PA3 located at a third side S3 of the display area DA, and a fourth side region PA4 located at a fourth side S4 of the display area DA. Optionally, the first side S1 and the fourth side S4 are opposite to each other. Optionally, the second side S2 and the third side S3 are opposite to each other. Optionally, the first side region PA1 includes an integrated circuit bonding area onto which one or more integrated circuits IC, such as display control integrated circuits and / or touch control integrated circuits, are bonded. In some embodiments, the peripheral area PA further includes a first corner region CR1 connecting the third side region PA3 and the fourth side region PA4, a second corner region CR2 connecting the second side region PA2 and the fourth side region PA4, a third corner region CR3 connecting the first side region PA1 and the third side region PA3, and a fourth corner region CR4 connecting the first side region PA1 and the second side region PA2.

[0132] ​ is a schematic diagram showing a detailed structure in a display area in a display device in some embodiments according to the present disclosure. Refer to​ In some embodiments, the display device includes, in the display area: a base substrate BS (e.g., a flexible base substrate); an active layer ACT of a respective one of a plurality of thin film transistors TFT on the base substrate BS; a gate insulating layer GI on a side of the active layer ACT distal from the base substrate BS; a gate G and a first capacitor electrode Cel (both part of a first gate metal layer) on a side of the gate insulating layer GI distal from the base substrate BS; an insulating layer IN on a side of the gate G and the first capacitor electrode Cel distal from the gate insulating layer GI; a second capacitor electrode Ce2 (part of a second gate metal layer) on a side of the insulating layer IN distal from the gate insulating layer GI; an interlayer dielectric layer ILD on a side of the second capacitor electrode Ce2 distal from the gate insulating layer GI; a source S and a drain D (part of a first SD metal layer) on a side of the interlayer dielectric layer ILD distal from the gate insulating layer GI; a planarization layer PLN on a side of the source S and the drain D distal from the interlayer dielectric layer ILD; a pixel definition layer PDL defining a sub-pixel opening and on a side of the planarization layer PLN distal from the base substrate BS; and a light-emitting element LE in the sub-pixel opening. The light-emitting element LE includes: an anode AD on a side of the planarization layer PLN distal from the interlayer dielectric layer ILD; a light-emitting layer EL on a side of the anode AD distal from the planarization layer PLN; and a cathode layer CD on a side of the light-emitting layer EL distal from the anode AD. The display device further includes, in the display area: an encapsulation layer EN encapsulating a dummy light-emitting element DLE and on a side of the cathode layer CD distal from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sub-layer CVD1 on a side of the cathode layer CD distal from the base substrate BS, an organic encapsulation sub-layer IJP on a side of the first inorganic encapsulation sub-layer CVD1 distal from the base substrate BS, and a second inorganic encapsulation sub-layer CVD2 on a side of the organic encapsulation sub-layer IJP distal from the first inorganic encapsulation sub-layer CVD1. The display device further includes, in the display area: a buffer layer BUF on a side of the encapsulation layer EN distal from the base substrate BS; a plurality of second electrode bridges BR2 on a side of the buffer layer BUF distal from the encapsulation layer EN; a touch insulating layer TI on a side of the plurality of second electrode bridges BR2 distal from the buffer layer BUF; a plurality of first touch electrodes TE1 on a side of the touch insulating layer TI distal from the buffer layer BUF; and an overcoat layer OC on a side of the plurality of first touch electrodes TE1 distal from the touch insulating layer TI.

[0133] ​ Detailed structures in a display area in a display device according to some embodiments of the present disclosure are shown. Referring to ​In some embodiments, the display device includes, in the display area: a base substrate BS (e.g., a flexible base substrate); an active layer ACT of a respective one of a plurality of thin film transistors TFT on the base substrate BS; a gate insulating layer GI on a side of the active layer ACT distal from the base substrate BS; a gate G and a first capacitor electrode Cel (both part of a first gate metal layer) on a side of the gate insulating layer GI distal from the base substrate BS; an insulating layer IN on a side of the gate G and the first capacitor electrode Cel distal from the gate insulating layer GI; a second capacitor electrode Ce2 (part of a second gate metal layer) on a side of the insulating layer IN distal from the gate insulating layer GI; an interlayer dielectric layer ILD on a side of the second capacitor electrode Ce2 distal from the gate insulating layer GI; a source S and a drain D (part of a first SD metal layer) on a side of the interlayer dielectric layer ILD distal from the gate insulating layer GI; a passivation layer PVX on a side of the source S and the drain D distal from the interlayer dielectric layer ILD; a first planarization layer PLN' on a side of the passivation layer PVX distal from the interlayer dielectric layer ILD; a planarization layer PLN on a side of the first planarization layer PLN' distal from the passivation layer PVX; a relay electrode RE (part of a second SD metal layer) on a side of the planarization layer PLN distal from the first planarization layer PLN'; a pixel definition layer PDL defining a sub-pixel opening and on a side of the planarization layer PLN distal from the base substrate BS; and a light-emitting element LE in the sub-pixel opening. The light-emitting element LE includes: an anode AD on a side of the planarization layer PLN distal from the first planarization layer PLN'; a light-emitting layer EL on a side of the anode AD distal from the planarization layer PLN; and a cathode layer CD on a side of the light-emitting layer EL distal from the anode AD. The display device further includes, in the display area: an encapsulation layer EN encapsulating a dummy light-emitting element DLE and on a side of the cathode layer CD distal from the base substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sub-layer CVD1 on a side of the cathode layer CD distal from the base substrate BS, an organic encapsulation sub-layer IJP on a side of the first inorganic encapsulation sub-layer CVD1 distal from the base substrate BS, and a second inorganic encapsulation sub-layer CVD2 on a side of the organic encapsulation sub-layer IJP distal from the first inorganic encapsulation sub-layer CVD1. The display device further includes, in the display area: a buffer layer BUF on a side of the encapsulation layer EN distal from the base substrate BS; a plurality of second electrode bridges BR2 on a side of the buffer layer BUF distal from the encapsulation layer EN; a touch insulating layer TI on a side of the plurality of second electrode bridges BR2 distal from the buffer layer BUF; a plurality of first touch electrodes TE1 on a side of the touch insulating layer TI distal from the buffer layer BUF; and an overcoat layer OC on a side of the plurality of first touch electrodes TE1 distal from the touch insulating layer TI.Optionally, the display device does not include a passivation layer PVX in the display area, e.g., the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN’.

[0134] Referring to ​ and ​ , the planarization layer PLN in the display area of the display device is in the same layer as the planarization layer PLN in the peripheral area as shown in ​ . The anode AD in the display area of the display device is in the same layer as the anode material layer AML in the peripheral area as shown in ​ . The pixel definition layer PDL in the display area of the display device is a portion of the pixel definition material layer, and is in the same layer as the plurality of via blocks VB in the peripheral area as shown in ​ . The cathode layer CD in the display area of the display device is in the same layer as the cathode material layer CML in the peripheral area as shown in ​ and ​ . Referring to ​ , the source S and the drain D in the display area of the display device are in the same layer as the signal line material layer pvss in the peripheral area as shown in ​ and ​ . Referring to ​ , the relay electrode RE in the display area of the display device is in the same layer as the signal line material layer pvss in the peripheral area as shown in ​ and ​ .

[0135] As used herein, the term “same layer” refers to a relationship between layers that are formed at the same time in the same step. In one example, the anode AD and the anode material layer AML are in the same layer when they are formed as a result of one or more steps of the same patterning process performed in the material deposited in the same deposition process. In another example, the anode AD and the anode material layer AML can be formed in the same layer by performing the step of forming the anode AD and the step of forming the anode material layer AML at the same time. The term “same layer” does not always mean that the thickness of the layer or the height of the layer is the same in a cross-sectional view.

[0136] ​ is a schematic diagram showing the layout of certain signal lines in a display device in some embodiments according to the present disclosure. Referring to ​In some embodiments, the display device includes a peripheral voltage supply line PVSS in the peripheral area PA configured to provide a low voltage signal to cathodes of the plurality of light emitting elements in the display area DA. The display device also includes one or more integrated circuits IC, one or more high voltage signal lines VDD configured to provide a high voltage signal to pixel driving circuits of the display device, one or more reset signal lines VIN configured to provide an initialization signal to reset transistors in the pixel driving circuits, and one or more array gate circuits GOA in the peripheral area PA. As shown in FIG. 8, at least a portion of the peripheral voltage supply line PVSS is located on a side of the one or more array gate circuits GOA away from the base substrate. ​

[0137] In another aspect, the present disclosure also provides a method of manufacturing an array substrate. In some embodiments, the method includes forming a planarization layer on a base substrate; forming an anode material layer on the planarization layer and in a peripheral area of the array substrate; and forming a plurality of gas release vias extending through the anode material layer, the gas release vias configured to release gas in the planarization layer during a manufacturing process. Optionally, an opening size of a first respective gas release via in a first region is smaller than an opening size of a second respective gas release via in a second region.

[0138] ​The foregoing description of embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. The description was presented as illustrative of the broadest aspects of the application that are and can be claimed as it is and only limited by the appended claims. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to explain the principles of the application and its best mode of practical application to thereby enable others skilled in the art to understand the application for various embodiments and with various modifications that are suited to the particular use or implementation. The scope of the application is to be defined by the claims and their equivalents, where all terms are meant to be construed in their broadest reasonable sense, unless otherwise indicated. Thus, the terms "the invention," "the present invention," or similar referents used in the context of the detailed description are not intended to be limiting of the claimed subject matter, and will be included in the scope of the claims along with the equivalents thereof. The present invention is only limited by the claims appended hereto and encompasses all variations falling within the scope of the claims, which are to be interpreted in accordance with the principles of patent law. Furthermore, these claims can refer to "a," "an" or "the" article, which is intended to be interpreted to mean "at least one" or "one or more." Also, any application recitations of "first," "second," or "third" or similar language are not intended to be construed as limiting the number or order of elements. Any advantages and benefits provided by the described embodiments can not apply in all instances. It should be understood that various changes can be made by those skilled in the art which would be apparent to one skilled in the art. Such changes are not to be considered limiting of the scope of the application as defined by the appended claims and their equivalents. Furthermore, elements and components of the disclosure can be arranged and designed in a wide variety of different configurations, all of which are intended to fall within the scope of the present disclosure. Also, the elements and components of the disclosure can be interchanged with other elements and components that serve the same function or are otherwise suitable for use in the same or similar manner.

Claims

1. An array substrate, comprising a display area and a peripheral area; the peripheral area comprises a first side area located at a first side of the display area, a second side area located at a second side of the display area, a third side area located at a third side of the display area, and a fourth side area located at a fourth side of the display area; wherein, The first side and the fourth side are opposite to each other, and the second side and the third side are opposite to each other; the peripheral region further includes a first corner region connecting the third side region and the fourth side region, a second corner region connecting the second side region and the fourth side region, a third corner region connecting the first side region and the third side region, and a fourth corner region connecting the first side region and the second side region; The peripheral region includes a first region and a second region; the first region is in the first corner region or in the second corner region; the second region is outside the first corner region, the second corner region, the third corner region, and the fourth corner region; The array substrate includes: a planarization layer; an anode material layer on the planarization layer and in a peripheral region of the array substrate; and a plurality of gas release vias extending through the anode material layer configured to release gas in the planarization layer during a manufacturing process; wherein an opening size of a first respective gas release via in the first region is smaller than an opening size of a second respective gas release via in the second region.

2. The array substrate of claim 1, further comprising a pixel defining material layer including a plurality of via blocks spaced apart from each other on the anode material layer, a respective via block covering and filling a respective gas release via; wherein a portion of the respective via block outside the respective gas release via has a width greater than an opening width of the respective gas release via.

3. The array substrate according to claim 2, wherein, a first ratio of a first width of a first respective via block in the first region to a first opening width of a first respective gas release via is greater than a second ratio of a second width of a second respective via block in the second region to a second opening width of a second respective gas release via.

4. The array substrate according to claim 3, wherein, the first width and the second width are substantially the same; and the first opening width is smaller than the second opening width.

5. The array substrate of claim 2, wherein, the plurality of via blocks are on a first portion of the anode material layer in a first sub-region of the peripheral region; the pixel defining material layer further includes a pixel defining layer defining a sub-pixel opening of a light emitting element; and the pixel defining layer extends into a second sub-region of the peripheral region, covering and filling gas release vias in a second portion of the anode material layer.

6. The array substrate according to claim 5, wherein, the pixel defining layer extends continuously throughout the second sub-region of the peripheral region.

7. The array substrate according to claim 5 or 6, wherein, In at least one corner region of the array substrate, an opening size of at least one gas release via in the first sub-region is smaller than an opening size of at least one gas release via in the second sub-region.

8. The array substrate of claim 5, wherein, In at least one non-corner region of the array substrate, an opening size of at least one gas release via in the first sub-region is substantially the same as an opening size of at least one gas release via in the second sub-region.

9. The array substrate of claim 5, wherein, An opening size of the at least one gas release via under an edge portion of the pixel defining layer bordering the first sub-region is smaller than an opening size of the at least one gas release via in the first sub-region and smaller than an opening size of the at least one gas release via under a non-edge portion of the pixel defining layer.

10. The array substrate of claim 5, wherein, An opening size of the at least one gas release via in the first sub-region bordering an edge portion of the pixel defining layer is smaller than an opening size of the at least one other gas release via in the first sub-region, the at least one other gas release via being spaced apart from the edge portion by the at least one gas release via.

11. The array substrate of claim 5, wherein, An opening size of the at least one gas release via in the first sub-region of the array substrate and in a corner region is smaller than an opening size of the at least one gas release via in the first sub-region of the array substrate and in a non-corner region.

12. The array substrate of claim 5, wherein, The first side region is configured to bond an integrated circuit; An opening size of the at least one gas release via in the first sub-region and in a corner region connecting the second side region and the fourth side region or in a corner region connecting the third side region and the fourth side region is smaller than an opening size of the at least one gas release via in the first sub-region and in a corner region connecting the first side region and the second side region or in a corner region connecting the first side region and the third side region.

13. The array substrate of claim 12, wherein, An opening size of the at least one gas release via in the first sub-region and in a corner region connecting the first side region and the second side region or in a corner region connecting the first side region and the third side region is smaller than an opening size of the at least one gas release via in the first sub-region of the array substrate and in a non-corner region.

14. The array substrate of claim 1, comprising a peripheral voltage supply line in the peripheral region; wherein, The anode material layer is a layer in which the peripheral voltage supply line is located.

15. The array substrate of claim 14, wherein, The peripheral voltage supply line is a signal line configured to supply a voltage signal to a cathode of a light emitting element in a display region of the array substrate.

16. The array substrate of claim 14, further comprising a pixel defining material layer on the anode material layer; wherein The peripheral voltage supply line further comprises a cathode material layer in the peripheral region, the cathode material layer being located on a side of the pixel defining material layer and the anode material layer distal to the planarization layer; and The cathode material layer is connected to the anode material layer.

17. The array substrate of claim 16, wherein, The pixel defining material layer comprises: a plurality of via blocks on the anode material layer spaced apart from each other, each via block covering and filling each gas release via; and a pixel defining layer defining a sub-pixel opening of a light emitting element, respectively; wherein the plurality of via blocks are located in a first sub-region of the peripheral region; the pixel defining layer extends into a second sub-region of the peripheral region; and the cathode material layer is at least partially present in the first sub-region and at least partially absent in the second sub-region.

18. The array substrate of claim 14, wherein, The peripheral voltage supply line further includes a signal line material layer on a side of the planarization layer distal from the anode material layer; and The anode material layer is connected to the signal line material layer through one or more peripheral vias in the peripheral region and extending through the planarization layer.

19. The array substrate of claim 18, wherein, The array substrate further includes a plurality of second gas release vias extending through the signal line material layer for releasing gas in an insulating layer underneath the signal line material layer during a manufacturing process; and A normal projection on a base substrate of a second gas release via in the signal line material layer at least partially overlaps a normal projection on the base substrate of a gas release via in the anode material layer.

20. The array substrate of claim 1, wherein, A ratio of an opening size of the first respective gas release via in the first region to an opening size of the second respective gas release via in the second region is in a range of 1:1.5 to 1:5.

0.

21. The array substrate of claim 3, wherein, The first ratio is 25% to 250% larger than the second ratio.

22. The array substrate of claim 2, wherein, A first thickness of a first respective via block in the first region is greater than a second thickness of a second respective via block in the second region.

23. The array substrate of claim 22, wherein, An opening size of a gas release via covered and filled by the first respective via block and the second respective via block, respectively, is substantially the same.

24. A display device comprising the array substrate of any one of claims 1 to 23, and one or more integrated circuits connected to the array substrate in an integrated circuit bonding region.

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