Memory structure with read-write assist based on self-regulating capacitive coupling

Abstract

This invention relates to a memory structure with read / write assistance based on self-regulating capacitive coupling, disclosing a memory structure including word lines (WL) and cell supply lines (CSL) located between and parallel to boost lines (VBL). Depending on whether read or write assistance is needed, the VBL initiates a capacitively coupled boost to adjacent WL and / or CSL. During a read operation, all VBLs of a selected row can be charged to form coupling capacitance with the WL and CSL, thereby boosting the word line voltage (Vwl) and cell supply voltage (Vcs) for read assistance. During a write operation, one VBL adjacent to the WL of the selected row can be charged to form coupling capacitance only with the WL, thereby boosting Vwl for write assistance. The coupling capacitance formed by charging the VBLs in the structure is self-regulating because the potential coupling capacitance increases with the row length.

Description

Technical Field

[0001] This invention relates to memory circuits, and more particularly to embodiments of memory structures with capacitively coupled read / write assistance. Background Technology

[0002] Key factors considered in current integrated circuit design include, but are not limited to, performance, power scaling, and size scaling. However, improvements in one of these factors often result in an undesirable trade-off with one or more of the others. For example, in a single-track memory architecture (such as a single-track static random access memory (SRAM) architecture), a positive power supply (Vdd) can be used to power the entire memory structure. That is, the same Vdd can be used to power memory cells within the memory array, charging word lines connected to those cells during read and write operations. Lowering this Vdd level results in a corresponding reduction in power consumption and leakage power. Unfortunately, lowering this Vdd level also negatively impacts performance; more specifically, it makes the memory structure more prone to read and write failures. Summary of the Invention

[0003] In view of the above, this document discloses an embodiment of a memory structure with a boost voltage based on self-adjusting capacitive coupling for read / write assistance. In various embodiments, the word line (WL) and cell supply line (CSL) for a row of memory cells in the array are located between and parallel to the voltage boost line (VBL). Depending on whether read assistance or write assistance is required, these VBLs initiate a capacitively coupled boost voltage to adjacent WLs and / or CSLs. For example, during a read operation, all VBLs of a selected row can be charged to form a coupling capacitance with the WL and the CSL, thereby boosting the word line voltage (Vwl) and the cell supply voltage (Vcs) for read assistance. During a write operation, one VBL adjacent to the WL of the selected row can be charged to form a coupling capacitance only with that WL, thereby boosting the word line voltage (Vwl) for write assistance. In some embodiments, each row may have a corresponding CSL and boost circuitry. In other embodiments, adjacent rows may share the same CSL and boost circuitry to minimize arbitrary size increases. In any case, the coupling capacitance formed by charging the VBL adjacent to the WL or CSL is not fixed. Instead, it is self-adjusting. That is, as the number of memory cells in each row increases (i.e., as the number of columns increases), the length of the VBL, the WL, and the CSL also increases, and therefore, the arbitrary coupling capacitance formed by charging the VBL also increases.

[0004] This document discloses various embodiments of memory structures. Each embodiment may include multiple parallel conductors within the same backend of the line (BEOL) metal layer. These parallel conductors may include a first boost line (VBL), a word line (WL), a second VBL, a cell power supply line (CSL), and a third VBL. The WL and CSL may be connected to all memory cells in a row of memory cells within the memory array. The WL may be located between and parallel to the first VBL and the second VBL. The CSL may be located between and parallel to the second VBL and the third VBL. Each embodiment may also include a boost circuit connected to the first VBL, the WL, the second VBL, and the third VBL.

[0005] In some embodiments, each row may have a corresponding CSL and boost circuit. However, in other embodiments, the CSL and boost circuit may be shared between a pair of adjacent rows. For example, some embodiments of the memory structure may include multiple parallel conductive lines within the same back-end process (BEOL) metal layer. These parallel conductors may include a first VBL, a first WL, a second VBL, a shared CSL, a third VBL, a second WL, and a fourth VBL. The first WL and the shared CSL may be connected to all memory cells in the first row of memory cells within the memory array. The second WL and the shared CSL may be connected to all memory cells in the second row of memory cells adjacent to the first row within the memory array. Furthermore, the first WL may be located between and parallel to the first VBL and the second VBL. The cell power supply line may be located between and parallel to the second VBL and the third VBL. The second WL may be located between and parallel to the third VBL and the fourth VBL. Each embodiment may further include a boost circuit connected to the first VBL, the first WL, the second VBL, the third VBL, the second WL, and the fourth VBL.

[0006] In some embodiments, the boost circuit may be specifically a digital boost circuit. The configuration of the digital boost circuit (especially the logic gates included therein) may vary, for example, depending on whether the CSL and the boost circuit are shared between adjacent rows. Attached Figure Description

[0007] The invention will be better understood from the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0008] Figure 1A A schematic diagram showing an embodiment of a memory structure having a boost converter based on self-adjusting capacitive coupling for read / write assistance;

[0009] Figure 1B Displayed Figure 1AA schematic diagram of an example memory cell in a column of memory cells in a memory structure;

[0010] Figure 1C Display and Figure 1A A schematic diagram of the boost circuit associated with a row of memory cells in the memory structure;

[0011] Figure 2A A schematic diagram showing another embodiment of a memory structure having a boost converter based on self-adjusting capacitive coupling for read / write assistance;

[0012] Figure 2B Displayed Figure 2A A schematic diagram of a pair of adjacent memory cells in a column of memory cells in a memory structure;

[0013] Figure 2C Display and Figure 2A A schematic diagram of a boost circuit connecting adjacent rows of memory cells in a memory structure;

[0014] Figure 3A and 3B The diagram shows voltage levels on the word line (WL), on the cell power supply line (CSL), and on the three boost lines (VBL) during read and write operations in the disclosed memory structure with a small number of columns; and

[0015] Figure 4A and 4B The diagram shows the voltage levels on the word line (WL), the cell power supply line (CSL), and the three boost lines (VBL) during read and write operations in the disclosed memory structure with a large number of columns. Detailed Implementation

[0016] As mentioned above, key factors considered in current integrated circuit design include, but are not limited to, performance, power scaling, and size scaling. However, improvements in one of these factors often result in unfavorable trade-offs with one or more of the others. For example, in a single-track memory architecture (such as a single-track static random access memory (SRAM) architecture), a positive power supply (Vdd) can be used to power the entire memory architecture. That is, the same Vdd can be used to power memory cells within the memory array, for charging word lines connected to those memory cells during read and write operations, etc. Lowering this Vdd level results in a corresponding reduction in power consumption and leakage power. Unfortunately, lowering this Vdd level also negatively impacts performance, more specifically, making the memory architecture more prone to read and write failures.

[0017] When using low or ultra-low Vdd to power the memory structure, techniques for minimizing read and write failures include boosting the word line and / or cell power supply lines according to the operation. For example, during read and / or write operations, the word line voltage on the word line connected to the selected memory cell can be charged to Vdd, and then boosted from Vdd to Vdd+ to increase the speed of the operation. Alternatively, during a read operation, the cell supply voltage on the cell power supply line (CSL) connected to the selected memory cell can be boosted from Vdd to Vdd+. These techniques typically employ boost devices (e.g., P-type field-effect transistor-based devices) connected to the word lines (WL) and, where applicable, to the cell power supply lines (CSL) in the array, configured to provide a fixed coupling capacitance to these lines in response to control signals. However, if too many memory cells are included in each row (i.e., if there are too many columns in the array), making the lines long, the fixed coupling capacitance may be insufficient to achieve the required boost over the entire length of the lines (especially at the ends of the lines located far from the boost device). One proposed solution is to use a programmable boost device to set the coupling capacitance to one of a finite number of different fixed coupling capacitance settings based on the final number of columns included in the memory array. However, this solution is still coarse-grained and has the disadvantage of increasing the complexity of the Tiler code.

[0018] In view of the foregoing, this document discloses an embodiment of a memory architecture with a boost converter based on self-adjusting capacitive coupling for read / write assistance. In various embodiments, the word line (WL) and cell supply line (CSL) for a row of memory cells in the array are located between and parallel to the boost line (VBL). Depending on whether read assistance or write assistance is required, these VBLs initiate a capacitively coupled boost to adjacent WLs and / or CSLs. For example, during a read operation, all VBLs of a selected row can be charged to form a coupling capacitance with the WL and the CSL, thereby boosting the word line voltage (Vwl) and the cell supply voltage (Vcs) for read assistance. During a write operation, one VBL adjacent to the WL of the selected row can be charged to form a coupling capacitance only with that WL, thereby boosting Vwl for write assistance. In some embodiments, each row may have a corresponding CSL and boost circuitry. In other embodiments, adjacent rows may share the same CSL and boost circuitry to minimize arbitrary size increases. In any case, the coupling capacitance formed by charging the VBL adjacent to the WL or CSL is not fixed. Instead, it is self-adjusting. That is, as the number of memory cells in each row increases (i.e., as the number of columns increases), the length of the VBL, the WL, and the CSL also increases, and therefore, the arbitrary coupling capacitance formed by charging the VBL also increases.

[0019] Generally, this document discloses various embodiments of memory structures with boost converters based on self-adjusting capacitive coupling for read / write assistance (see, for example, see...). Figure 1A-1C Memory structure 100; see also Figure 2A-2C Memory structure 200).

[0020] Memory structures 100 and 200 may include arrays of memory cells 101 and 201 arranged in rows (see row an) and columns (see column AN). For example, the memory cells 101 and 201 may be arranged in substantially parallel rows oriented along a first direction and in substantially parallel columns oriented along a second direction perpendicular to the first direction. The first direction may be the X direction and the second direction may be the Y direction (as shown in the figures), or vice versa.

[0021] Memory cells 101 and 201 can be any suitable type of memory cell powered by a cell supply voltage (Vcs) (e.g., at a positive supply voltage (Vdd) level). During read and write operations, the memory cell is accessed by switching the word line voltage (Vwl) from ground to Vdd. During a read operation, this can be assisted by increasing both Vwl and Vcs to Vdd+, and during a write operation, it can be assisted by increasing only Vwl to Vdd+. Such memory cells 101 and 201 can be, for example, static random access memory (SRAM) cells.

[0022] Figure 1B and 2B This diagram shows an example six-transistor (6T) SRAM cell that can be included in memory structures 100 and 200.

[0023] Each 6T-SRAM cell 101, 201 may include a first inverter, which includes a first pull-up transistor 102, 202 (e.g., a p-type field-effect transistor (PFET)) and a first pull-down transistor 103, 203 (e.g., an n-type field-effect transistor (NFET)) connected in series between the cell power supply lines (CSLs) 125, 225 and ground. Each 6T-SRAM cell may also include a second inverter, which is cross-coupled to the first inverter and includes a second pull-up transistor 112, 212 (e.g., a PFET) and a second pull-down transistor 113, 213 (e.g., an NFET) connected in series between the same CSL 125, 225 and ground. Those skilled in the art will recognize that, through the cross-coupled first and second inverters, the junction between the first pull-up transistors 102, 202 and the first pull-down transistors 103, 203 (also referred to herein as the first data storage node 105, 205 or the true node) will connect to (i.e. control) the gates of the second pull-up transistors 112, 212 and the second pull-down transistors 113, 213. Furthermore, the junction between the second pull-up transistors 112, 212 and the second pull-down transistors 113, 213 (also referred herein as the second data storage node 215 or the complement node) will connect to (i.e. control) the gates of the first pull-up transistors 102, 202 and the first pull-down transistors 103, 203.

[0024] Each 6T-SRAM cell 101, 201 may further include: a first access transistor 104, 204 (also referred to herein as a first pass-gate transistor) (e.g., NFET), connected in series between the first bit line (also referred to herein as a true bit line (BLT)) 131, 231 for the column containing the SRAM cell and the first data storage node 105, 205, and having a gate connected to the word line (WL) 121, 221 for the row containing the SRAM cell; and a second access transistor 114, 214 (also referred to herein as a second pass-gate transistor), connected in series between the second bit line (also referred to herein as a filler bit line (BLC)) 132, 232 for the column containing the SRAM cell and the second data storage node 115, 215, and also having a gate connected to the WL 121, 221 for the row containing the SRAM cell.

[0025] Therefore, the memory structures 100 and 200 including the 6T-SRAM cell array will also include: WL121 and 221 for each row an, wherein each WL of each row is connected to the gate of the first access transistor 104 and 204 and the second access transistor 114 and 214 of all SRAM cells in that row; paired bit lines (BLT 131 and 231 and BLC 132 and 232) for each column AN, wherein the BLT and BLC of each column are connected to the drain regions of the first access transistor 104 and 204 and the drain regions of the second access transistor 114 and 214, respectively; and CSL125 and 225 for each row an. It should be noted that in some embodiments, each CSL 125 may be associated with a corresponding row of those rows, and all memory cells in that row and only that row are connected to the CSL 125 (e.g., see...). Figure 1A-1C (Memory structure 100). However, in other embodiments, each CSL 225 may be shared between two adjacent rows, with all memory cells in both rows connected to the CSL (e.g., see memory structure 100). Figure 2A-2C The memory structure 200 is described in more detail below.

[0026] It should be noted that these figures are not intended to be limiting. Although 6T-SRAM cells are described above and shown in the figures, any other suitable type of memory cells may be included in the arrays of memory structures 100 and 200. Such memory cells include, but are not limited to, 8T-SRAM cells, 10T-SRAM cells, etc.

[0027] In any of these embodiments, memory structures 100, 200 may further include controllers 195, 295 and peripheral circuitry connected to the array and configured to facilitate various memory functions (e.g., read and write operations for selected memory cells in the array) in response to control signals from controllers 195, 295. Similar to conventional memory structures (e.g., conventional SRAM structures), the peripheral circuitry may include peripheral circuitry 191, 291 for the rows. The peripheral circuitry 191, 291 for the rows may be connected to WLs 121, 221 for row an and may include, for example, a row decoder configured to facilitate WL activation (i.e., charging selected WLs to a positive supply voltage (Vdd) level) to provide memory cell access during memory functions (e.g., read or write operations). The peripheral circuitry may also include peripheral circuitry 192, 292 for the columns. Peripheral circuitry 192, 292 for these columns may be connected to BLT / BLC pairs 131-132, 231-232 for column AN, and may include a column decoder configured to facilitate BL bias during memory functions. Finally, the peripheral circuitry may include additional peripheral circuitry 193, 293, also electrically connected to BLT / BLC pairs 131-132, 231-232 for column AN, and includes sensing circuitry configured to sense changes in BL electrical properties (e.g., voltage or current) during read operations to determine the stored data value within a selected memory cell.

[0028] Such peripheral circuitry is well known in the art; therefore, its details are omitted from this specification to allow the reader to focus on the salient forms of the disclosed embodiments. However, as described in more detail below, embodiments of memory structures 100, 200 also include VBLs for those rows, with each WL and CSL located between and parallel to the two boost lines. Therefore, in addition to known features, peripheral circuitry 191, 291 for those rows also includes novel boost circuits 170, 270 (described in more detail below and for example in…) Figure 1C and 2C (as shown in the image) to selectively charge these VBLs, thereby initiating capacitively coupled WL and / or CSL boost based on whether read assistance or write assistance is required.

[0029] More specifically, please refer to Figure 1A-1CThe memory structure 100 may also include multiple parallel conductors (i.e., metal wires or threads) within the same back-end process (BEOL) metal layer. For each row an of memory cells 101 in the array, these parallel conductors may include three boost lines (VBLs) 181-183, a word line (WL) 121, and a cell power line (CSL) 125. Specifically, these parallel conductors may include: a first VBL 181, a WL 121, a second VBL 182, a CSL 125, and a third VBL 183. The WL 121 and CSL 125 for that row may be connected to all memory cells 101 in that row (as described above). The WL 121 may be located between and parallel to the first VBL 181 and the second VBL 182. The CSL 125 may be located between and parallel to the second VBL 182 and the third VBL 183. As described above, these parallel conductors may be located within the same BEOL metal layer. Each conductor can be separated from its adjacent conductor by a thin layer of interlayer dielectric (ILD) material, thus forming a capacitor for each pair of adjacent conductors.

[0030] The memory structure 100 may also include boost circuits 170 for each row an. Each boost circuit 170 may include a first node connected to the WL 121 of that row and a second input node for receiving a mode selection signal 171 (e.g., from controller 195), which indicates a read mode (e.g., with a low logic OR "0" value) or a write mode (e.g., with a high logic OR "1" value). Each boost circuit 170 may also include a first output node connected to a first VBL 181 and a second output node connected to a second VBL 182 and a third VBL 183.

[0031] Each boost circuit 170 for each row can be configured such that when Vwl on WL 121 for that row switches to the Vdd level (detected at the first input node) when a read or write operation is initiated and when the mode selection signal (detected at the second input node) indicates the read mode, the first VBL 181 is charged through the first output node (e.g., from ground to a high positive voltage level), and the second VBL 182 and the third VBL 183 are similarly charged through the second output node (e.g., from ground to the high positive voltage level). The three VBLs 181-183 of this row are charged, forming coupling capacitors (CC1 and CC2) between WL 121 and the first VBL 181 and the second VBL 182, to increase Vwl on WL 121 above the VDD level (i.e., to a certain Vdd+). Additional coupling capacitors (CC3 and CC4) are also formed between CSL 125 and the second VBL 182 and the third VBL 183, to increase Vcs on CSL 125 above the Vdd level (i.e., to a certain Vdd+). In other words, during a read operation, both sets of CCs affect the WL, and both sets of CCs affect the CSL.

[0032] Each boost circuit 170 for each row can also be configured such that when Vwl on WL 121 switches to the Vdd level (detected at the first input node) during a read or write operation, but the mode selection signal (detected at the second input node) indicates write mode, only the first VBL 181 is charged through the first output node (e.g., from ground to a high positive voltage level). Charging the first VBL 181 forms a coupling capacitance (CC1) only between WL and the first VBL 181, thereby increasing Vwl on WL 121 above the Vdd level only, without increasing Vcs on CSL 125. That is, during a read operation, only one set of CCs affects WL, and no CC set affects CSL.

[0033] Each boost circuit 170 for each row can also be configured such that when Vwl on WL 121 is not charged (e.g., when WL is discharged to ground) (detected at the first input node), and therefore no read or write operation is performed on any memory cell in that row, none of the three VBLs 181-183 will be charged by the boost circuit 170. By keeping the three VBLs 181-183 uncharged, no coupling capacitance is formed with WL and CSL. Therefore, WL 121 will remain ground, and CSL 125 will not be boosted above the Vdd level.

[0034] Figure 1CA schematic diagram of an example boost circuit 170 that may be included in memory structure 100 is shown. Boost circuit 170 may be a digital boost circuit. This example boost circuit 170 includes a first input node 301 connected to WL 121 and a first output node 311 connected to a first VBL 181. This example boost circuit 170 may also include a pair of inverters 172 and 173 connected in series between the first input node 301 and the first output node 311. This example boost circuit 170 may also include a second input node 302 that receives a mode selection signal 171, and a second output node 312 connected to a second VBL 182 and a third VBL 183. This example boost circuit 170 may also include an inverter 174 that receives the mode selection signal 171 as an input signal through the second input node 302. This example boost circuit 170 may also include an AND gate that receives the Vwl signal from the first input node 301 and the output signal from the inverter 174 as input signals.

[0035] Those skilled in the art will recognize that the output signal from the two series-connected inverters 172-173 at the first output node 311 corresponds to the input signal (i.e., Vwl) at the first input node 301. That is, if Vwl is low, the output signal at the first output node will be low, and vice versa. Those skilled in the art will also recognize that the output signal from the NAND gate 175 at the second output node will be low unless both input signals of the NAND gate 175 are high. Therefore, in such a digital boost circuit, if Vwl at the first input node 301 is low, the output signals at both the first output node 311 and the second output node 312 will be low, no VBL 181-183 will be charged, and no boost coupling capacitor will be formed. If Vwl at the first input node 301 is high and the mode selection signal 171 at the second input node 302 is low (indicating read mode), then: (a) the output signal at the first output node 311 will be high; and (b) given inverter 174, the input signal of NAND gate 175 will be high, and the output signal at the second output node 312 will also be high. Therefore, all three VBLs 181-183 will be charged, forming the aforementioned coupling capacitors CC1-CC4, and boosting Vwl on WL 121 and Vcs on CSL 125. If Vwl at the first input node 301 is high and the mode selection signal 171 at the second input node 302 is also high (indicating write mode), then: (a) the output signal at the first output node 311 will be high; but (b) given inverter 174, the input signal of NAND gate 175 will be both high and low, and the output signal at the second output node 312 will be low. Therefore, only the first VBL 181 will be charged, thus forming only the coupling capacitor CC1 and boosting Vwl on WL121.

[0036] In the memory structure 100 described above, each row has a corresponding CSL 125 and boost circuit 170. In other embodiments, particularly in memory structure 200, the CSL and boost circuit may be shared between a pair of adjacent rows (e.g., between row a and row b, ..., between row n-1 and row n).

[0037] More specifically, please refer to Figure 2A-2CThe memory structure 200 may also include multiple parallel conductors (i.e., metal lines or wires) located within the same back-end process (BEOL) metal layer. For each pair of adjacent rows of memory cells 101 in the array (e.g., for adjacent rows a and b, c and d, e and f, ..., n-1 and n), these parallel conductors may include four boost lines (VBLs) 281-284, two word lines (WLs) (one word line for each row of the pair of adjacent rows), and a common cell power supply line (CSL) 225. Specifically, the parallel conductors may include: a first VBL 281, a first WL 221 for the first row of the pair of adjacent rows, a second VBL 282, a common CSL 225, a third VBL 283, a second WL 221' for the second row of the pair of adjacent rows, and a fourth VBL 284. The first WL 221 for the first row of the pair of adjacent rows and the CSL 225 shared between the first and second rows of the pair of adjacent rows can be connected to all memory cells 201 (as described above). Furthermore, the second WL 221' for the second row of the pair of adjacent rows and the CSL 225 shared between the first and second rows of the pair of adjacent rows can be connected to all memory cells 201 (as described above). The first WL 221 can be located between and parallel to the first VBL 281 and the second VBL 282. The CSL 225 can be located between and parallel to the second VBL 282 and the third VBL 283. The second WL 221' can be located between and parallel to the third VBL 283 and the fourth VBL 284. As described above, these parallel conductors can be located in the same BEOL metal layer. Each conductor can be separated from adjacent conductors by a thin layer of interlayer dielectric (ILD) material, thereby forming a capacitor for each pair of adjacent conductors.

[0038] The memory structure 200 may further include boost circuits 270 for pairs of adjacent rows (e.g., rows a and b, c and d, ... n-1 and n). Each boost circuit 270 may include a first node connected to a first WL 221 for the first row of the pair of adjacent rows, a second input node connected to a second WL 221' for the second row of the pair of adjacent rows, and a third input node for receiving a mode selection signal 271 (e.g., from controller 295) indicating a read mode (e.g., a low logic or "0" value) or a write mode (e.g., a high logic or "1" value). Each boost circuit 270 may further include a first output node connected to a first VBL 281, a second output node connected to a fourth VBL 284, and a third output node connected to a second VBL 282 and a third VBL 283.

[0039] Each boost circuit 270 for each pair of adjacent rows (e.g., rows a and b, c and d, ..., n-1 and n) can be configured such that when the first Vwl on the first WL 221 for the first row switches to the Vdd level (detected at the first input node) when a read or write operation is initiated on the memory cell in the first row, and when the mode selection signal (detected at the third input node) indicates the read mode, the first VBL 281 is charged through the first output node (e.g., from ground to a high positive voltage level), and the second VBL 282 and the third VBL 283 are similarly charged through the third output node (e.g., from ground to the high positive voltage level). Charging three VBLs 281-283 creates coupling capacitors (CC1 and CC2) between the first WL 221 and the first VBL 281 and the second VBL 282 to increase the first Vwl on the first WL 221 above the VDD level (i.e., to a certain Vdd+). Additional coupling capacitors (CC3 and CC4) are also created between CSL 225 and the second VBL 282 and the third VBL 283 to increase the Vcs on CSL 225 above the Vdd level (i.e., to a certain Vdd+). Since only one WL in the array is typically selected at a given time, if the first Vwl on the first WL 221 is high, the second Vwl on the second WL 221' will be low.

[0040] Each boost circuit 270 for each pair of adjacent rows (e.g., rows a and b, c and d, ..., n-1 and n) can also be configured such that when the second Vwl on the second WL 221' for the second row switches to the Vdd level (detected at the second input node) when a read or write operation is initiated on the memory cell in the second row, and when the mode selection signal (detected at the third input node) indicates the read mode, the fourth VBL 284 is charged through the second output node (e.g., from ground to a high positive voltage level), and the second VBL 282 and the third VBL 283 are similarly charged through the third output node (e.g., from ground to the high positive voltage level). Charging three VBLs 282-284 creates coupling capacitors (CC5 and CC6) between the second WL 221' and the third and fourth VBLs 283 and 284, increasing the second Vwl on the second WL 221' above the VDD level (i.e., to a certain Vdd+). Additional coupling capacitors (CC3 and CC4) are also created between CSL 225 and the second and third VBLs 282 and 283, increasing the Vcs on CSL 225 above the Vdd level (i.e., to a certain Vdd+). Similarly, typically only one WL within the array is selected at a given time; therefore, if the second Vwl on the second WL 221' is high, the first Vwl on the first WL 221 will be low. Thus, for a read operation, both sets of CCs affect one of the selected WLs, and both sets of CCs also affect the shared CSL.

[0041] Each boost circuit 270 for each pair of adjacent rows (e.g., rows a and b, c and d, ..., n-1 and n) can also be configured such that when the first Vwl on the first WL 221 switches to the Vdd level (detected at the first input node) when a read or write operation is initiated, but the mode selection signal (detected at the third input node) indicates write mode, only the first VBL 281 is charged through the first output node (e.g., from ground to a high positive voltage level). Charging the first VBL 281 only forms a coupling capacitor (CC1) between the first WL and the first VBL 281, thereby increasing only the first Vwl on the first WL 221 above the Vdd level, without increasing Vcs on CSL 225. Similarly, typically only one WL in the array is selected at a given time, so if the first Vwl on the first WL 221 is high, the second Vwl on the second WL 221' will be low. Each boost circuit 270 for each pair of adjacent rows (e.g., rows a and b, c and d, ..., n-1 and n) can also be configured such that when the second Vwl on the second WL 221' switches to the Vdd level (detected at the fourth input node) when a read or write operation is initiated, but the mode selection signal (detected at the third input node) indicates write mode, only the fourth VBL 284 is charged through the second output node (e.g., from ground to a high positive voltage level). Charging the fourth VBL 284 only forms a coupling capacitor (CC6) between the second WL and the fourth VBL 284, thereby increasing the second Vwl on the second WL 221' above the Vdd level, without increasing Vcs on CSL 225. Similarly, typically only one WL in the array is selected at a given time, so if the second Vwl on the second WL 221' is high, the first Vwl on the first WL 221 will be low. Therefore, for write operations, one set of CCs affects one of the selected WLs, and no CCs affect the shared CSL.

[0042] For each pair of adjacent rows (e.g., rows a and b, c and d, ..., n-1 and n), the boost circuit 270 can be configured such that when the first Vwl on the first WL 221 and the second Vwl on the second WL 221' are not charged (e.g., discharged to ground) (detected at the first input node and the second input node), and thus no read or write operation is performed on any memory cell in the first or second row of that pair, none of the four VBLs 281-284 will be charged through the boost circuit 270. By keeping the four VBLs 281-284 uncharged, no coupling capacitance is formed with the two WLs and the shared CSL. Therefore, the two WLs will remain grounded, and the shared CSL 225 will not be boosted above the Vdd level.

[0043] Figure 2CA schematic diagram of an example boost circuit 270 that may be included in memory structure 200 is shown. The boost circuit 270 may be a digital boost circuit. This example boost circuit 270 includes a first input node 401 connected to a first WL 221 and a first output node 411 connected to a first VBL 281. The example boost circuit 270 includes a second input node 402 connected to a second WL 221' and a second output node 412 connected to a fourth VBL 284. This example boost circuit 270 may also include a first pair of inverters 472 and 473 connected in series between the first input node 401 and the first output node 411. This example boost circuit 270 may also include a second pair of inverters 476 and 477 connected in series between the second input node 402 and the second output node 412. This example boost circuit 270 may further include a third input node 403 that receives the mode selection signal 271, and a third output node 413 connected to the second VBL 282 and the third VBL 283. This example boost circuit 270 may also include a NOR gate 474 that receives a first Vwl from the first WL 221 of the first input node 401 and a second Vwl from the second WL 221' of the second input node 402 as input signals. This example boost circuit 270 may also include an additional NOR gate 475 that receives the output signal from the NOR gate 474 and the mode selection signal 271 as input signals.

[0044] Those skilled in the art will recognize that the output signal from the two series-connected inverters 472-473 at the first output node 411 corresponds to the input signal at the first input node 401 (i.e., the first Vwl). That is, if the first Vwl is low, the output signal at the first output node 411 will be low, and vice versa. Similarly, the output signal from the two series-connected inverters 476-477 at the second output node 412 corresponds to the input signal at the second input node 402 (i.e., the second Vwl). That is, if the second Vwl is low, the output signal at the second output node 412 will be low, and vice versa. Those skilled in the art will also recognize that the output signal of a NOR gate will be low unless both input signals of the NOR gate are low, in which case the output signal will be high.

[0045] In this type of digital boost circuit 270, if the first Vwl of the first input node 401 and the second Vwl of the second input node 402 are both low, the output signal of the NOR gate 474 will be high. Therefore, the output signal of the additional NOR gate 475 will be low (regardless of the logic value of the mode selection signal 271), no VBL 281-284 will be charged, and no boost coupling capacitor will be formed.

[0046] If the first Vwl at the first input node 401 is high, the second Vwl at the second input node 402 is low, and the mode selection signal 271 at the third input node 403 is low (indicating read mode), then: (a) the output signal at the first output node 411 will be high; (b) the input signal of the NOR gate 474 will be both high and low, therefore, the output signal of the NOR gate 474 will be low; and (c) the input signals of the additional NOR gate 475 will both be low, therefore, the output signal of the additional NOR gate 475 will be high. Therefore, the first, second, and third boost lines 281-283 will be charged, thereby forming the aforementioned coupling capacitors CC1-CC4 and boosting the first Vwl on the first WL 221 and the Vcs on the common CSL 225. Furthermore, the output signals of the pair of inverters 476-477 at the second output node 412 will be low, therefore, the fourth VBL 283 will not be charged. Similarly, if the second Vwl at the second input node 402 is high, the first Vwl at the first input node 401 is low, and the mode selection signal 271 at the third input node 403 is low (indicating read mode), then: (a) the output signal at the second output node 412 will be high; (b) the input signals of the NOR gate 474 are both low and high, therefore, the output signal of the NOR gate 474 will be low; and (c) the input signals of the additional NOR gate 475 are both low, therefore, the output signal of the additional NOR gate 475 will be high. Therefore, the second, third, and fourth boost lines 282-284 will be charged, thereby forming the aforementioned coupling capacitors CC3-CC6 and boosting the second Vwl on the second WL 221' and the Vcs on the common CSL 225. Furthermore, the output signals of the pair of inverters 472-473 at the first output node 411 will be low, therefore, the first VBL 281 will not be charged.

[0047] If the first Vwl at the first input node 401 is high, the second Vwl at the second input node 402 is low, and the mode selection signal 271 at the third input node 403 is high (indicating write mode), then: (a) the output signal at the first output node 411 will be high; (b) the output signal at the second output node 412 will be low; (c) the input signal of the NOR gate 474 will be both high and low, therefore, the output signal will be low; and (d) the input signal of the additional NOR gate 475 will be both low and high, therefore, the output signal at the third output node 413 will be low. Therefore, only the first VBL 281 will be charged, thus forming only the coupling capacitor CC1 and boosting the first Vwl on the first WL 221. Similarly, if the first Vwl at the first input node 401 is low, the second Vwl at the second input node 402 is high, and the mode selection signal 271 at the third input node 403 is high (indicating write mode), then: (a) the output signal at the first output node 411 will be low; (b) the output signal at the second output node 412 will be high; (c) the input signal of the NOR gate 474 will be both low and high, therefore, the output signal will be low; and (d) the input signal of the additional NOR gate 475 will also be both low and high, therefore, the output signal at the third output node 413 will be low. Therefore, only the fourth VBL 284 will be charged, thus forming only the coupling capacitor CC6 and boosting the second Vwl on the second WL 221'.

[0048] It should be noted that in memory structures 100 and 200, boost circuits 170 and 270 may be integrated into peripheral circuits 191 and 291 for row an located at one end (e.g., at the same end as the word line driver, etc.), as shown. Alternatively, boost circuits 170 and 270 may be integrated into peripheral circuits 191 and 291 for row an located at other locations (e.g., at the end of the rows opposite the word line driver, along the middle of the rows, etc.).

[0049] The design of such memory structures can be performed using, for example, a process design kit (PDK). For the purposes of this disclosure, a PDK refers to a set of electronic documents (including data and script documents) that are developed (e.g., by a semiconductor foundry) for its customers to facilitate the design of integrated circuit (IC) chips at specific technology nodes supported by that foundry. These electronic documents can be accessed at different stages of the design flow through one or more electronic design automation (EDA) tools executed on a computer network (e.g., on a computer-aided design (CAD) system). Example PDK electronic documents may include, but are not limited to, simulation models, symbols and technical documents for that specific technology node, libraries (e.g., standard cell libraries, parametric cell (Pcell) libraries, etc.), and sets of design rules, etc., for different stages of the chip design flow (e.g., for planarization, power planning, input / output pin placement, library component placement, clock planning, routing, layout versus schematic (LVS) checking, 3D simulation, simulation, etc.). The design of this memory structure may include, for example: the selection of library elements corresponding to the desired memory cell structure and other memory circuitry (e.g., drivers, boost circuits, etc.); the arrangement of these library elements; and the subsequent wiring of parallel wires for each row or pair of rows in one of the BEOL metal layers, and the connections to the memory cells, boost circuits, etc. Alternatively, the design of this memory structure may include, for example: the selection of library elements corresponding to the desired memory cell structure (which already includes the wiring of the parallel wires) and other memory circuitry (e.g., drivers, boost circuits, etc.); the arrangement of these library elements; and the subsequent wiring of any remaining lines required. In any case, in various embodiments of this memory structure, the coupling capacitance formed by charging the VBL is not fixed due to the selection and / or programming of specific devices. Instead, it is self-adjusting. That is, during design, as the number of memory cells in each row increases (i.e., as the number of columns increases), the coupling capacitance used for read / write assistance also increases, and vice versa.

[0050] More specifically, a significant advantage of the disclosed embodiments is that when the number of bit cell columns in the array changes during design, the coupling capacitance formed by charging the first, second, and third VBLs 181-183, 281-283 during read operations and by charging only the first VBLs 181, 281 during write operations will automatically change proportionally, while the ratio of added coupling capacitance remains the same. That is, during read operations, both sets of coupling capacitors boost the voltage on WL (e.g., one from the charged first VBL and one from the charged second VBL), and both sets of coupling capacitors boost the voltage on CSL (e.g., one from the charged second VBL and one from the charged third VBL), regardless of the number of columns; however, during write operations, one set of coupling capacitors boosts the voltage on WL (e.g., only one from the charged first VBL), while zero sets of coupling capacitors boost the voltage on CSL (i.e., CSL remains at Vdd), regardless of the number of columns. It should be noted that when the number of columns is small, the grounding capacitance on WL and CSL will be small, and the coupling capacitance caused by the second and third boost lines will also be small; however, when the number of columns is large, the grounding capacitance on WL and CSL will be large, and the coupling capacitance caused by the second and third lines will also be large.

[0051] Figure 3A and 3B Example diagrams are shown showing the voltage levels on WL 121, 221, CSL 125, 225, the first VBL 181, 281, and the second and third VBL 182, 282 and 183, 283 during read and write operations in an array with a small number of columns (e.g., 16 columns). During the read operation, charging the VBL to, for example, a Vdd of 450mV results in a coupling capacitor-assisted boost of the voltage level on the WL from 450mV to 532mV, and a coupling capacitor-assisted boost of the voltage level on the CSL from 450mV to 558mV; however, during the write operation, charging only the first VBL to 450mV results in a coupling capacitor-assisted boost of approximately half the amount visible in the read operation (e.g., from 450mV to 491mV), while the CSL and the second and third VBLs remain unchanged at Vdd.

[0052] Figure 4A and 4BExample diagrams are shown showing the voltage levels on WL 121, 221, CSL 125, 225, the first VBL 181, 281, and the second and third VBLs 182, 282 and 183, 283 during read / write operations in an array with a large number of columns (e.g., 128 columns). The boost voltage seen during this read / write operation is slightly smaller, but the coupling capacitance ratio remains essentially the same. During the read operation, charging the VBL to, for example, 450mV Vdd can cause a coupling capacitor-assisted boost of the voltage level on the WL from 450mV to 525mV, and a coupling capacitor-assisted boost of the voltage level on the CSL from 450mV to 542mV; however, during the write operation, charging only the first VBL to 450mV can cause a coupling capacitor-assisted boost of the WL to be about half of the amount visible during the read operation (e.g., from 450mV to 488mV), while the CSL and the second and third VBLs remain unchanged at Vdd.

[0053] Therefore, the revealed memory structure allows for fine-grained fixed boost voltage that varies with the number of columns during design.

[0054] The method described above is used for the manufacture of integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in package form. In the latter case, the chip is housed in a single-chip package (e.g., a plastic carrier with pins attached to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with single-sided or double-sided interconnects or embedded interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product, such as a motherboard, or as part of (b) a final product. The final product can be any product including the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0055] It should be understood that the terminology used herein is for illustrative purposes of the disclosed structures and methods and is not intended to be limiting. For example, unless the context clearly indicates otherwise, the singular forms “a” and “the” as used herein are also intended to include the plural forms. Furthermore, the term “comprising” as used herein indicates the presence of the stated feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Moreover, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “parallel,” and “vertical” as used herein are intended to describe their relative positions when oriented and shown in the accompanying drawings (unless otherwise indicated), and terms such as “touching,” “direct contact,” “adjacent,” “directly adjacent,” and “closely adjacent” are intended to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term “lateral” as used herein describes the relative positions of the elements when oriented and shown in the accompanying drawings, particularly indicating that one element is located to the side of another element rather than above or below it. For example, an element laterally adjacent to another element will be next to that other element; an element laterally close to another element will be directly next to that other element; and an element laterally surrounding another element will be adjacent to and encircle the outer wall of that other element. All the manner or steps in the following claims, along with the corresponding structure, material, action, and equivalent diagram of the functional element, include any structure, material, or action that performs the function in combination with other claimed elements specifically claimed.

[0056] The descriptions of various embodiments of the invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements upon technical techniques known in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A memory structure, characterized in that, include: First boost line; Word lines; The second boost line, wherein the word line is located between the first boost line and the second boost line and is parallel to the first boost line and the second boost line; Unit power supply line; The third boost line, wherein the unit power supply line is located between the second boost line and the third boost line and is parallel to the second boost line and the third boost line; and The boost circuit is connected to the first boost line, the word line, the second boost line, and the third boost line.

2. The memory structure as described in claim 1, characterized in that, Also includes: A row of memory cells, wherein each memory cell in the row is connected to the word line and the cell power supply line, and wherein the first boost line, the second boost line, and the third boost line extend the length of the row.

3. The memory structure as described in claim 2, characterized in that, This memory unit includes a static random access memory unit.

4. The memory structure as described in claim 1, characterized in that, It also includes: wherein the boost circuit is configured to receive a mode selection signal indicating one of the read mode and the write mode.

5. The memory structure as described in claim 4, characterized in that, The boost circuit is configured such that when the word line voltage on the word line switches to the positive supply voltage level and the mode selection signal indicates the read mode, the first boost line, the second boost line, and the third boost line are charged to form a coupling capacitor between the word line and the first boost line and the second boost line, thereby increasing the word line voltage on the word line to above the positive supply voltage level, and forming a coupling capacitor between the cell power supply line and the second boost line and the third boost line, thereby increasing the cell supply voltage on the cell power supply line to above the positive supply voltage level.

6. The memory structure as described in claim 4, characterized in that, The boost circuit is configured such that when the word line voltage on the word line switches to the positive supply voltage level and the mode selection signal indicates the write mode, the first boost line is charged to form a coupling capacitance between the word line and the first boost line, thereby increasing the word line voltage on the word line above the positive supply voltage level without increasing the cell supply voltage on the cell power supply line.

7. The memory structure as described in claim 4, characterized in that, The boost circuit is configured such that when the word line voltage on the word line is lower than the positive supply voltage level, the boost circuit does not charge the first boost line, the second boost line, and the third boost line.

8. A memory structure, characterized in that, include: First boost line; First letter line; The second boost line, wherein the first letter line is located between the first boost line and the second boost line and is parallel to the first boost line and the second boost line; Unit power supply line; The third boost line, wherein the unit power supply line is located between the second boost line and the third boost line and is parallel to the second boost line and the third boost line; Second letter line; The fourth boost line, wherein the second letter is located between the third and fourth boost lines and is parallel to both the third and fourth boost lines; and The boost circuit is connected to the first boost line, the first word line, the second boost line, the third boost line, the second word line, and the fourth boost line.

9. The memory structure as described in claim 8, characterized in that, It also includes multiple rows of memory cells, wherein the multiple rows include: The memory cells in the first row, wherein each memory cell in the first row is connected to the first word line and the power supply line of the cell; and The memory cells in the second row are adjacent to the first row, and each memory cell in the second row is connected to the second word line and the power supply line of the cell. The first boost line, the second boost line, the third boost line, and the fourth boost line extend the length of these lines.

10. The memory structure as described in claim 9, characterized in that, This memory unit includes a static random access memory unit.

11. The memory structure as described in claim 8, characterized in that, in, The boost circuit is configured to receive a mode selection signal that indicates either the read mode or the write mode.

12. The memory structure as described in claim 11, characterized in that, The boost circuit is configured such that when the voltage of the first word line on the word line switches to the positive supply voltage level and the mode selection signal indicates the read mode, the first boost line, the second boost line, and the third boost line are charged to form a coupling capacitor between the first word line and the first and second boost lines, thereby increasing the voltage of the first word line on the first word line above the positive supply voltage level. Similarly, a coupling capacitor is formed between the cell power supply line and the second and third boost lines, thereby increasing the cell supply voltage on the cell power supply line above the positive supply voltage level. The boost circuit is configured such that when the voltage of the first word line on the word line switches to the positive supply voltage level and the mode selection signal indicates the write mode, the first boost line is charged to form a coupling capacitor between the first word line and the first boost line, thereby increasing the voltage of the first word line on the first word line to above the positive supply voltage level without increasing the unit supply voltage on the unit power supply line.

13. The memory structure as described in claim 11, characterized in that, The boost circuit is configured such that when the voltage of the second word line on the second word line switches to the positive supply voltage level and the mode selection signal indicates the read mode, the fourth boost line, the second boost line, and the third boost line are charged to form a coupling capacitor between the second word line and the fourth and third boost lines, thereby increasing the voltage of the second word line on the second word line to above the positive supply voltage level, and forming a coupling capacitor between the unit power supply line and the second and third boost lines, thereby increasing the unit supply voltage on the unit power supply line to above the positive supply voltage level; as well as The boost circuit is configured such that when the voltage of the second word line on the second word line switches to the positive supply voltage level and the mode selection signal indicates the write mode, the fourth boost line is charged to form a coupling capacitor between the second word line and the fourth boost line, thereby increasing the voltage of the second word line on the first word line to above the positive supply voltage level without increasing the cell supply voltage.

14. The memory structure as described in claim 11, characterized in that, The boost circuit is configured such that when the voltage of the first word line on the first word line and the voltage of the second word line on the second word line are lower than the positive supply voltage level, the boost circuit does not charge the first boost line, the second boost line, the third boost line, and the fourth boost line.

15. The memory structure as described in claim 11, characterized in that, The boost circuit also includes: The first input node is connected to the first word line; The second input node is connected to the second word line; The third input node receives the mode selection signal; The first output node is connected to the first boost line; The second output node is connected to the fourth boost line; The third output node is connected to the second boost line and the third boost line; The first pair of inverters is connected in series between the first input node and the first output node; The second pair of inverters is connected in series between the second input node and the second output node; A NOR gate that receives input signals from the first input node and the second input node; and An additional NOR gate receives input signals from the NOR gate and the third input node and outputs an output signal to the third output node.

16. A memory structure, characterized in that, include: First boost line; First letter line; The second boost line, wherein the first letter line is located between the first boost line and the second boost line and is parallel to the first boost line and the second boost line; Unit power supply line; The third boost line, wherein the unit power supply line is located between the second boost line and the third boost line and is parallel to the second boost line and the third boost line; Second letter line; The fourth boost line, wherein the second letter is located between the third and fourth boost lines and is parallel to both the third and fourth boost lines; and A digital boost circuit is connected to the first boost line, the first word line, the second boost line, the third boost line, the second word line, and the fourth boost line.

17. The memory structure as described in claim 16, characterized in that, It also includes multiple rows of memory cells, wherein the multiple rows include: The memory cells in the first row, wherein each memory cell in the first row is connected to the first word line and the power supply line of the cell; and The memory cells in the second row are adjacent to the first row, and each memory cell in the second row is connected to the second word line and the power supply line of the cell. The first boost line, the second boost line, the third boost line, and the fourth boost line extend the length of these lines.

18. The memory structure as described in claim 17, characterized in that, This memory unit includes a static random access memory unit.

19. The memory structure as described in claim 16, characterized in that, The digital boost circuit also includes: The first input node is connected to the first word line; The second input node is connected to the second word line; The third input node receives a mode selection signal that indicates either the read mode or the write mode; The first output node is connected to the first boost line; The second output node is connected to the fourth boost line; The third output node is connected to the second boost line and the third boost line; The first pair of inverters is connected in series between the first input node and the first output node; The second pair of inverters is connected in series between the second input node and the second output node; A NOR gate that receives input signals from the first input node and the second input node; and An additional NOR gate receives input signals from the NOR gate and the third input node and outputs an output signal to the third output node.

20. The memory structure as described in claim 19, characterized in that, When the first word line voltage on the word line switches to the positive supply voltage level and the mode selection signal indicates the read mode, the output signals at the first and third output nodes are high and the output signal at the second output node is low. Therefore, the first boost line, the second boost line, and the third boost line are charged to form a coupling capacitor between the first word line and the first and second boost lines, thereby increasing the first word line voltage on the first word line to above the positive supply voltage level. A coupling capacitor is also formed between the unit power supply line and the second and third boost lines, thereby increasing the unit supply voltage on the unit power supply line to above the positive supply voltage level. Specifically, when the voltage of the first word line on the word line switches to the positive supply voltage level and the mode selection signal indicates the write mode, the output signal at the first output node is high and the output signals at the second and third output nodes are low. Therefore, the first boost line is charged to form a coupling capacitor between the first word line and the first boost line, thereby increasing the voltage of the first word line on the first word line to above the positive supply voltage level without increasing the unit supply voltage on the unit power supply line. Specifically, when the voltage of the second word line on the second word line switches to the positive supply voltage level and the mode selection signal indicates the read mode, the output signals at the second and third output nodes are high and the output signal at the first output node is low. Therefore, the fourth boost line, the second boost line, and the third boost line are charged to form a coupling capacitor between the second word line and the fourth and third boost lines, thereby increasing the voltage of the second word line on the second word line to above the positive supply voltage level. Furthermore, a coupling capacitor is formed between the unit power supply line and the second and third boost lines, thereby increasing the unit supply voltage on the unit power supply line to above the positive supply voltage level. Specifically, when the voltage of the second word line switches to the positive supply voltage level and the mode selection signal indicates the write mode, the output signal at the second output node is high and the output signals at the first and third output nodes are low. Therefore, the fourth boost line is charged to form a coupling capacitor between the second word line and the fourth boost line, thereby increasing the voltage of the second word line on the first word line to above the positive supply voltage level without increasing the cell supply voltage. Specifically, when the voltage of the first word line on the first word line and the voltage of the second word line on the second word line are lower than the positive supply voltage level, the output signals at the first output node, the second output node and the third output node are low, so the boost circuit does not charge the first boost line, the second boost line, the third boost line and the fourth boost line.

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