Output buffer circuit with adaptive adjustment of driving characteristics

Abstract

The present invention provides an output buffer circuit for various high-voltage integrated circuits. The circuit includes: a P-terminal inverter chain, an N-terminal inverter chain, n P-terminal output inverters, n N-terminal output inverters, n P-terminal output PMOS transistors, n N-terminal output NMOS transistors, n P-terminal output inverter control switches, n N-terminal output inverter control switches, a sampling switch SW, a working timing generation circuit, a load comparison quantization circuit, and a drive current selection circuit. The output buffer circuit proposed by the present invention does not require interrupting the normal working state of the drive chip, can adaptively adjust the drive current in real time by adaptively identifying the load size and the frequency of the input control pulse, maximally improve the efficiency of the drive circuit, reduce the design complexity of the peripheral circuit, and facilitate user use.

Description

Technical Field

[0001] The present invention relates to an output buffer circuit with adaptive adjustment of driving characteristics, belonging to the technical field of high-voltage integrated circuits. Background Art

[0002] There are various types of high-voltage integrated circuits required for various power electronics systems. The most commonly used ones are high-voltage gate driver chips, motor driver chips, AC-DC and DC-DC controller chips. New generation power electronics systems have put forward higher requirements for the performance of the high-voltage integrated circuits used therein, thereby further improving the reliability of the whole system. Usually, an output buffer circuit is integrated inside a high-voltage integrated circuit chip. In order to ensure that the gate capacitance of a high-voltage power device can be quickly charged and discharged, so that the device can be quickly saturated and turned on and reliably turned off, it is required that the output impedance of the output buffer circuit is small and the output current is large (several amperes).

[0003] Figure 1 The figure shows a structure diagram of a conventional output buffer circuit. In the figure, the NOR gate NOR1, the inverter INV1-INV3 chain, and the NAND gate NAND1, the inverter INV4-INV6 chain are cross-coupled. The input signal IN is divided into two paths. After passing through the NOR gate NOR1 and the inverter chain INV1-INV3, the signal VA at point A has a rising-edge delay td11 and a falling-edge delay td12 relative to the input signal IN. Subsequently, the signal VA at point A and the input signal IN perform a logic operation through the NAND gate NAND1, and after passing through the inverter chain INV4-INV6, the signal VB at point B has a rising-edge delay td21 and a falling-edge delay td22 relative to the input signal IN. The signal VA at point A is used to drive the MOS transistor M1, and the signal VB at point B is used to drive the MOS transistor M2. In this way, there is a dead time TD between VA and VB to avoid shoot-through of the MOS transistors M1 and M2.

[0004] After the chip is designed and finalized, the output driving ability of the above output buffer circuit will be fixed. In practical applications, in order to prevent the output current of VO from damaging the gate terminal of the external power switch MOSFET to be driven, a resistor is usually connected in series at the VO output terminal to suppress the overshoot of the gate terminal voltage. When the equivalent capacitance of the MOSFET gate terminal is large, the series protection resistor needs to be relatively small, and vice versa, a larger series protection resistor is required. However, a relatively large series protection resistor will bring two problems: one is that the switching power consumption on the resistor becomes larger, reducing the efficiency of the driving circuit; the other is that the driving delay is increased, ultimately reducing the system switching frequency. In addition, using a series protection resistor will also increase the design workload of design engineers and reduce the reliability of the whole system.

[0005] The Chinese invention patent with the application number 202010319722.9 proposes an output buffer circuit with an adaptively adjustable driving ability and its control method for the above problems. The output buffer circuit adaptively adjusts the driving current size by adaptively identifying the load size and the frequency of the input control pulse. However, the working state of the output buffer circuit proposed in this invention patent includes two modes: adaptive adjustment of driving ability and normal operation. After the power supply voltage is powered on, the adaptive adjustment mode of the driving ability needs to be started first, and then the normal operation mode is entered. In the normal operation mode, the change of the load characteristics cannot be adjusted, and the power-on reset must be performed again to adjust the change of the load characteristics, which brings the problem of discontinuous working time. Summary of the Invention

[0006] The object of the present invention is to overcome the deficiencies existing in the prior art, and provide an output buffer circuit with an adaptively adjustable driving characteristic, which does not require interrupting the normal operation mode, can respond to the change of the load characteristics in real time, and at the same time adjusts the output driving ability in real time.

[0007] The output buffer circuit with self - adaptive adjustment of driving characteristics provided by the present invention includes: a P - end inverter chain, an N - end inverter chain, n P - end output inverters, n N - end output inverters, n P - end output PMOS transistors, n N - end output NMOS transistors, n P - end output inverter control switches, and n N - end output inverter control switches; the internal structures of the P - end inverter chain and the N - end inverter chain are the same, both being cascaded inverters, and the driving capabilities of the inverters gradually increase from the front stage to the rear stage; the input ends of the P - end inverter chain and the N - end inverter chain are both connected to the input data Din, the outputs of the P - end inverter chain are respectively connected to the input ends of the n P - end output inverters through the n P - end output inverter control switches, and the output ends of the n P - end output inverters are respectively connected to the gate ends of the n P - end output PMOS transistors; the outputs of the N - end inverter chain are respectively connected to the input ends of the n N - end output inverters through the n N - end output inverter control switches, and the output ends of the n N - end output inverters are respectively connected to the gate ends of the n N - end output NMOS transistors; the source ends of the n P - end output PMOS transistors are all connected to the power supply voltage VCC, the source ends of the n N - end output NMOS transistors are all connected to the ground, and the drain ends of the n P - end output PMOS transistors and the drain ends of the n N - end output NMOS transistors are connected together to generate the driving signal VO; its feature is that the driving signal VO is sampled by a sampling switch and then connected to a load comparison and quantization circuit, the load comparison and quantization circuit is also connected to the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin output by the working timing generation circuit, the load comparison and quantization circuit obtains the load quantization code Dlot under the control of the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin, and is connected to the driving current selection circuit; the input end of the working timing generation circuit is connected to the input data Din, tracks and discriminates the frequency of the input data Din to obtain the frequency discrimination code Dfin of Din, and generates non - overlapping high - level control clocks Ck1 and control clock Ck2; the control clock Ck1, the control clock Ck2, and the load quantization code Dlot output by the load comparison and quantization circuit simultaneously enter the driving current selection circuit to generate the switching control signals Kp1 - Kpn of the n P - end output inverter control switches and the switching control signals Kn1 - Knn of the n N - end output inverter control switches; where n is any positive integer.

[0008] After the power supply voltage is powered on, the working timing generation circuit tracks and discriminates the frequency of the input data Din to obtain the frequency discrimination code Dfin, and generates the control clock Ck1 and the control clock Ck2; when the Ck1 clock is valid, the load comparison and quantization circuit generates a set of default load quantization codes Dlot_pre according to the driving signal VO sampled by the sampling switch, the reference voltage Vr, and the state of the frequency discrimination code Dfin, and enters the drive current selection circuit. The drive current selection circuit will output a set of default switch control signals Kp1_pre~Kpn_pre and switch control signals Kn1_pre~Knn_pre to control the n P-terminal output inverter control switches and the n N-terminal output inverter control switches respectively; the driving signal VO will drive the external load under the action of the default drive current and gradually increase the voltage of the driving signal VO; when the Ck1 clock ends, the load quantization code Dlot_pre will be adjusted according to the magnitude of the driving signal VO at this time to obtain the adjusted load quantization code Dlot_lock and remain unchanged; when the Ck2 clock is valid, the drive current selection circuit will output a new set of switch control signals Kp1_lock~Kpn_lock and switch control signals Kn1_lock~Knn_lock according to the load quantization code Dlot_lock to control the n P-terminal output inverter control switches and the n N-terminal output inverter control switches respectively; the driving signal VO will drive the external load under the action of the new drive current and quickly increase the voltage of the driving signal VO to the power supply voltage VCC; when the Ck2 clock ends, the load quantization code Dlot will be cleared, and the output switch control signals Kp1~Kpn of the drive current selection circuit will be cleared synchronously, turning off the n P-terminal output inverter control switches, and at the same time turning on the switch control signals Kn1~Knn to turn on the n N-terminal output inverter control switches. The driving signal VO will quickly pull down from the power supply voltage VCC to the ground voltage GND, thereby turning off the external load power device.

[0009] Specifically, the working timing generation circuit includes: an oscillator, a pulse width counter, a counting period selection circuit, a comprehensive counter, a first clock waveform generation circuit, and a second clock waveform generation circuit; the OSC signal generated by the oscillator is connected to the pulse width counter and the comprehensive counter, and the input data Din is simultaneously connected to the pulse width counter and the comprehensive counter; the pulse width counter counts the pulse time width of the input data Din according to the OSC signal, and performs tracking discrimination and comparison quantization on the counted pulse time width size to output a frequency discrimination code Dfin; the frequency discrimination code Dfin is connected to the counting period selection circuit to generate a comprehensive counter mode selection signal sel0; the comprehensive counter generates a clock control signal ct1 and a clock control signal ct2 according to the mode selection signal sel0, the OSC signal, and the input data Din; finally, the clock control signal ct1 and the clock control signal ct2 are respectively connected to the first clock waveform generation circuit and the second clock waveform generation circuit, and the first clock waveform generation circuit and the second clock waveform generation circuit respectively output the final control clocks Ck1 and Ck2.

[0010] After the chip is powered on, the OSC signal starts to be valid; when the input data Din starts to appear a rising edge from low level to high level, both the pulse width counter and the comprehensive counter start counting, and at the same time, the frequency discrimination code Dfin outputs a default initial intermediate value. Immediately afterwards, the counting period selection circuit outputs a default initial comprehensive counter mode selection signal sel0; the comprehensive counter first starts counting the clock control signal ct1 according to the comprehensive counter mode selection signal sel0, the OSC signal, and the input data Din, and changes the clock control signal ct1 from low level to high level. Then, after J OSC time periods of counting delay, the counting of the clock control signal ct1 ends, and the clock control signal ct1 is changed from high level to low level; immediately afterwards, after K OSC time periods of counting delay, the comprehensive counter starts counting the clock control signal ct2 and changes the clock control signal ct2 from low level to high level; then, after L OSC time periods of counting delay, and when the input data Din starts to appear a falling edge from high level to low level, the comprehensive counter ends the counting of the clock control signal ct2 and changes the clock control signal ct2 from high level to low level; the waveforms generated by the clock control signal ct1 and the clock control signal ct2 in the above process are respectively buffered by the first clock waveform generation circuit and the second clock waveform generation circuit to obtain the final control clocks Ck1 and Ck2;

[0011] During the above waveform generation process, if the pulse width counter tracks and discriminates the pulse time width of the input data Din and the obtained frequency discrimination code Dfin is not equal to the default value, the comprehensive counter mode selection signal sel0 output by the counting period selection circuit will change, thereby adjusting the sizes of J, K, and L in proportion, and finally adjusting the output clock frequencies of the control clock Ck1 and the control clock Ck2; where J, K, and L are all positive integers, J is a positive integer greater than K, and L is a positive integer more than 3 times larger than J.

[0012] Specifically, the load comparison quantization circuit includes: a quantization voltage generation circuit, a high / low speed mode selection circuit, N comparators, an error filtering circuit, a path selection circuit, a serial shift register, a serial-to-parallel conversion circuit, and an M-bit buffer output circuit; the input end of the quantization voltage generation circuit is connected to the reference voltage Vr, the control clock Ck1, and the mode control signal mod output by the high / low speed mode selection circuit. The quantization voltage generation circuit converts the reference voltage Vr into N quantization reference voltages Vr1 to VrN under the control of the control clock Ck1, and respectively connects them to the reference voltage input ends of the N comparators; the detection voltage input ends of the N comparators are all connected to the drive signal VO, and the N comparators respectively compare the drive signal VO with the N quantization reference voltages Vr1 to VrN and output N-bit quantization values D1 to DN; then the N-bit quantization values D1 to DN enter the error filtering circuit and output N-bit quantization codes Dlo; the high / low speed mode selection circuit outputs the mode control signal mod according to the magnitude of the frequency discrimination code Dfin, thereby changing the mode of the load comparison quantization circuit, and finally changing the speed and power consumption of the load comparison quantization circuit. The mode control signal mod is respectively connected to the quantization voltage generation circuit, the N comparators, the error filtering circuit, and the path selection circuit; the path selection circuit selects the signal path of the N-bit quantization code Dlo under the control of the mode control signal mod; the high-speed path output port of the path selection circuit is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit. The low-speed path output port of the path selection circuit is 1-bit serial data, which is first connected to the serial shift register, and then enters the serial-to-parallel conversion circuit after output to obtain M-bit parallel quantization codes Dlp, which are connected to the second data input port of the M-bit buffer output circuit; the M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1; where M and N are both integers greater than 1.

[0013] The load comparison quantization circuit includes two modes: high-speed mode and low-speed mode. When in the high-speed mode, the quantization voltage generation circuit outputs N quantization reference voltages Vr1 to VrN simultaneously under the control of the control clock Ck1. N comparators respectively compare the drive signal VO with the N quantization reference voltages Vr1 to VrN simultaneously and output the quantization values D1 to DN in parallel. Then, through the error filtering circuit, the N-bit quantization code Dlo is obtained. At this time, the N-bit quantization code Dlo is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit through the high-speed path output port of the path selection circuit. The M-bit buffer output circuit outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1.

[0014] When in the low-speed mode, only the first comparator in the N comparators works, and the remaining N - 1 comparators are in the sleep state. The quantization voltage generation circuit outputs N quantization reference voltages in sequence according to the time order from the Vr1 output port under the control of the control clock Ck1. The first comparator compares the drive signal VO with the N quantization reference voltages output from Vr1 in sequence according to the time order, and outputs the quantization values D1 to DN in serial at the output port of the first comparator. Then, through the error filtering circuit, the N-bit quantization code Dlo is obtained. At this time, the N-bit quantization code Dlo is 1-bit serial data, which enters the serial shift register in sequence through the low-speed path output port of the path selection circuit. The output of the serial shift register enters the serial-to-parallel conversion circuit to obtain the M-bit parallel quantization code Dlp, which is output to the second data input port of the M-bit buffer output circuit. The M-bit buffer output circuit obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

[0015] The advantages of the present invention are as follows: The provided output buffer circuit does not need to interrupt the normal working state of the drive chip. It can adaptively identify the load size and the frequency of the input control pulse, and adjust the drive current in real time and adaptively, which can reduce the design complexity of the peripheral circuit to the greatest extent and is convenient for users to use. Description of the Drawings

[0016] Figure 1 It is a schematic diagram of the existing output buffer circuit.

[0017] Figure 2 It is a block diagram of the circuit structure of the present invention.

[0018] Figure 3 It is a schematic diagram of the working waveform of the present invention.

[0019] Figure 4 It is a block diagram of the working timing generation circuit of the present invention.

[0020] Figure 5This is the working timing diagram generated by the working timing generation circuit of the present invention.

[0021] Figure 6 This is the block diagram of the load comparison quantization circuit of the present invention.

[0022] Figure 7 This is the application schematic diagram of the present invention in an AC-DC controller.

[0023] Figure 8 This is the application schematic diagram of the present invention in a DC-DC controller.

[0024] Figure 9 This is the application schematic diagram of the present invention in a motor controller.

[0025] Figure 10 This is the application schematic diagram of the present invention in a PWM controller. Detailed implementation manners

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and examples.

[0027] As Figure 2 shown, the output buffer circuit with self-adaptive adjustment of driving characteristics according to the present invention includes: a P-terminal inverter chain 1, an N-terminal inverter chain 2, n P-terminal output inverters Invpk_1 to Invpk_n, n N-terminal output inverters Invnk_1 to Invnk_n, n P-terminal output PMOS transistors Mp1 to Mpn, n N-terminal output NMOS transistors Mn1 to Mnn, n P-terminal output inverter control switches Kp1 to Kpn, n N-terminal output inverter control switches Kn1 to Knn, a sampling switch SW, a working timing generation circuit 3, a load comparison quantization circuit 4, and a drive current selection circuit 5. The internal structures of the P-terminal inverter chain 1 and the N-terminal inverter chain 2 are the same, and both are cascaded inverters inside, and the driving capabilities of the inverters gradually increase from the front stage to the rear stage. n is any positive integer.

[0028] The input terminal of the P-terminal inverter chain 1 and the input terminal of the N-terminal inverter chain 2 are connected to the input data Din. The output of the P-terminal inverter chain 1 is simultaneously connected to one side of n P-terminal output inverter control switches Kp1 to Kpn, and the output of the N-terminal inverter chain 2 is simultaneously connected to one side of n N-terminal output inverter control switches Kn1 to Knn; the other sides of the n P-terminal output inverter control switches Kp1 to Kpn are respectively connected to the gate terminals of n P-terminal output PMOS transistors Mp1 to Mpn through n P-terminal output inverters Invpk_1 to Invpk_n, and the other sides of the n N-terminal output inverter control switches Kn1 to Knn are respectively connected to the gate terminals of n N-terminal output NMOS transistors Mn1 to Mnn through n N-terminal output inverters Invnk_1 to Invnk_n; the source terminals of the n P-terminal output PMOS transistors Mp1 to Mpn are simultaneously connected to the power supply voltage VCC, the source terminals of the n N-terminal output NMOS transistors Mn1 to Mnn are simultaneously connected to the ground, and the drain terminals of the n P-terminal output PMOS transistors Mp1 to Mpn are simultaneously connected to the drain terminals of the n N-terminal output NMOS transistors Mn1 to Mnn and the output terminal of the driving signal VO.

[0029] The input terminal of the load comparison quantization circuit 4 is connected to the driving signal VO through the sampling switch SW. The load comparison quantization circuit 4 is also connected to the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin output by the working timing generation circuit 3. The driving signal VO enters the load comparison quantization circuit 4 after being sampled by the sampling switch SW, and obtains the load quantization code Dlot under the control of the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin, and then enters the driving current selection circuit 5. The input terminal of the working timing generation circuit 3 is connected to the input data Din. The working timing generation circuit 3 tracks and discriminates the frequency of the input data Din, obtains the Din frequency discrimination code Dfin, and generates non-overlapping high-level control clocks Ck1 and Ck2; the load quantization code Dlot, the control clock Ck1, and the control clock Ck2 simultaneously enter the driving current selection circuit 5 to generate the switching control signals Kp1 to Kpn of the n P-terminal output inverter control switches and the switching control signals Kn1 to Knn of the n N-terminal output inverter control switches.

[0030] After the power supply voltage is powered on, the working timing generation circuit 3 tracks and discriminates the frequency of the input data Din and obtains the frequency discrimination code Dfin of Din, and generates the control clocks Ck1 and Ck2. Figure 3 It is a schematic diagram of the working waveform of the driving signal VO of the present invention.

[0031] When the Ck1 clock is valid, the load comparison quantization circuit 4 will, according to the driving signal VO sampled by the sampling switch SW, the reference voltage Vr, and the state of the frequency discrimination code Dfin, first generate a set of default load quantization codes Dlot_pre (the intermediate state of Dlot) and send them to the drive current selection circuit 5. The drive current selection circuit 5 will output a set of default switch control signals Kp1_pre to Kpn_pre and switch control signals Kn1_pre to Knn_pre. The driving signal VO will drive the external load under the action of the default drive current Iout_pre, causing the voltage of the driving signal VO to gradually increase.

[0032] When the Ck1 clock ends, the load quantization code Dlot_pre will be adjusted according to the magnitude of the driving signal VO at this time to obtain the adjusted load quantization code Dlot_lock (another intermediate state of Dlot), and it will remain unchanged.

[0033] When the Ck2 clock is valid, the drive current selection circuit 5 will output a new set of switch control signals Kp1_lock to Kpn_lock and switch control signals Kn1_lock to Knn_lock according to the load quantization code Dlot_lock. The driving signal VO will drive the external load under the action of the new drive current Iout_lock, causing the voltage of the driving signal VO to quickly rise to the power supply voltage VCC.

[0034] When the Ck2 clock ends, the load quantization code Dlot will be cleared, and the output switch control signals Kp1 to Kpn of the drive current selection circuit 5 will be cleared synchronously, turning off the control switches of the n P-terminal output inverters, and at the same time turning on the switch control signals Kn1 to Knn, turning on the control switches of the n N-terminal output inverters. The driving signal VO will be quickly pulled from the power supply voltage VCC to the ground voltage GND, thereby turning off the external load power device.

[0035] During the above working process, when the Ck1 clock is valid, the driving signal VO will drive the external load under the action of the default driving current Iout_pre and gradually increase the voltage of the driving signal VO. For different external loads, the driving signal VO will generate different dv / dt changes. For a fixed output driving current Iout_pre, obviously, the larger the load capacitance driven, the lower the rising slope of the driving signal VO. At the end of the Ck1 clock, the voltage magnitude of the driving signal VO is inversely proportional to the load capacitance. That is, the voltage of the driving signal VO when the load is 0.5nF should be 3 times the voltage of the driving signal VO when the load is 1.5nF. Therefore, under the condition of a fixed driving current, according to the magnitude of the voltage of the driving signal VO at the end of the Ck1 clock, the size of the output driving load can be determined, and the size of the output driving load is quantified by the load comparison quantization circuit 4 to obtain the load quantization code Dlot_lock.

[0036] When the Ck2 clock is valid, the driving current selection circuit 5 will output a new set of switch control signals Kp1_lock~Kpn_lock and switch control signals Kn1_lock~Knn_lock according to the load quantization code Dlot_lock. The driving signal VO will drive the external load under the action of the new driving current Iout_lock and quickly increase the voltage of the driving signal VO to the power supply voltage VCC.

[0037] When the load quantization code Dlot_lock indicates that the external load is large, the driving current selection circuit 5 will output a set of larger switch control signals Kp1_lock~Kpn_lock and switch control signals Kn1_lock~Knn_lock, so that the driving signal VO outputs a larger output driving current Iout_lock. When the load quantization code Dlot_lock indicates that the external load is small, the driving current selection circuit 5 will output a set of smaller switch control signals Kp1_lock~Kpn_lock and switch control signals Kn1_lock~Knn_lock, so that the driving signal VO outputs a smaller output driving current Iout_lock.

[0038] Figure 4 This is the structural block diagram of the working timing generation circuit 3 of the present invention. The working timing generation circuit 3 includes: an oscillator 31, a pulse width counter 32, a counting period selection circuit 33, a comprehensive counter 34, a first clock waveform generation circuit 35, and a second clock waveform generation circuit 36.

[0039] The oscillator 31 generates an OSC signal and connects it to the pulse width counter 32 and the comprehensive counter 34. The input data Din is simultaneously connected to the pulse width counter 32 and the comprehensive counter 34.

[0040] The pulse width counter 32 counts the pulse time width of the input data Din according to the OSC signal, tracks and discriminates the magnitude of the counted pulse time width, and performs comparison and quantization to obtain a frequency discrimination code Dfin; the frequency discrimination code Dfin then enters the counting cycle selection circuit 33 to generate a comprehensive counter mode selection signal sel0.

[0041] The comprehensive counter 34 generates a clock control signal ct1 and a clock control signal ct2 respectively according to the comprehensive counter mode selection signal sel0, the OSC signal, and the input data Din.

[0042] Finally, the clock control signal ct1 and the clock control signal ct2 enter the first clock waveform generation circuit 35 and the second clock waveform generation circuit 36 respectively to obtain the final control clocks Ck1 and Ck2.

[0043] Figure 5 The figure shows the working timing diagram generated by the above working timing generation circuit 3. After the chip is powered on, the OSC signal becomes valid; when the input data Din starts to appear a rising edge from low level to high level, both the pulse width counter 32 and the comprehensive counter 34 start counting, and at the same time the frequency discrimination code Dfin outputs a default initial intermediate value. Assuming the frequency discrimination code Dfin is a 2-digit digital code, the default initial value of the frequency discrimination code Dfin is "10". Immediately afterwards, the counting cycle selection circuit 33 outputs a default initial comprehensive counter mode selection signal sel0. The comprehensive counter 34 first starts counting the clock control signal ct1 according to the comprehensive counter mode selection signal sel0, the OSC signal, and the input data Din, changes the clock control signal ct1 from low level to high level, and after a counting delay of J OSC time periods, ends the counting of the clock control signal ct1, and changes the clock control signal ct1 from high level to low level. Immediately afterwards, after a counting delay of K OSC time periods, the comprehensive counter 34 starts counting the clock control signal ct2, and changes the clock control signal ct2 from low level to high level. After a counting delay of L OSC time periods, and when the input data Din starts to appear a falling edge from high level to low level, the comprehensive counter 34 ends the counting of the clock control signal ct2, and changes the clock control signal ct2 from high level to low level. The waveforms generated by the clock control signal ct1 and the clock control signal ct2 in the above process are buffered by the first clock waveform generation circuit 35 and the second clock waveform generation circuit 36 respectively, and the final control clocks Ck1 and Ck2 can be obtained. The above J, K, and L are all positive integers, J is a positive integer greater than K, and L is a positive integer more than three times greater than J.

[0044] During the above waveform generation process, if the pulse width counter 32 discriminates and tracks the pulse time width of the input data Din and the obtained frequency discrimination code Dfin is not equal to the default value, the comprehensive counter mode selection signal sel0 output by the counting period selection circuit 33 will change, thereby adjusting the magnitudes of J, K, and L in proportion, and finally adjusting the output clock frequencies of the control clock Ck1 and the control clock Ck2.

[0045] From Figure 5 It can be seen from the adopted working timing that the working timing generation circuit 3 provided by the present invention can generate different Dfin codes according to the pulse width of the input data Din, thereby adjusting the output clock frequencies of the control clock Ck1 and the control clock Ck2, and further adjusting the load detection time during the effective period of the control clock Ck1 to improve the detection accuracy.

[0046] For the 2-bit Dfin code, if the Dfin code = 11, it means that the input pulse width is very wide and the switching frequency of the input data Din is very low, and the output clocks of the control clock Ck1 and the control clock Ck2 can output the control timing with a long clock cycle; if the Dfin code = 00, it means that the input pulse width is very narrow and the switching frequency of the input data Din is very high, and the output clocks of the control clock Ck1 and the control clock Ck2 need to output the control timing with the shortest clock cycle.

[0047] Figure 6 It is a structural block diagram of the load comparison and quantization circuit 4 of the present invention. The load comparison and quantization circuit 4 includes: a quantization voltage generation circuit 41, a high / low speed mode selection circuit 42, N comparators, an error filtering circuit 43, a path selection circuit 44, a serial shift register 45, a serial-to-parallel conversion circuit 46, and an M-bit buffer output circuit 47. Both M and N are integers greater than 1.

[0048] The input end of the quantization voltage generation circuit 41 is connected to the reference voltage Vr, the control clock Ck1, and the mode control signal mod output by the high / low speed mode selection circuit 42. The quantization voltage generation circuit 41 converts the reference voltage Vr into N quantization reference voltages Vr1 to VrN under the control of the control clock Ck1, and respectively connects them to the reference voltage input ends of the N comparators. The detection voltage input ends of the N comparators are all connected to the drive signal VO. The N comparators compare the drive signal VO with the N quantization reference voltages Vr1 to VrN to obtain N-bit quantization values D1 to DN, and enter the error filtering circuit 43 to obtain the N-bit quantization code Dlo.

[0049] The high / low speed mode selection circuit 42 changes the mode control signal mod according to the magnitude of the frequency discrimination code Dfin, thereby changing the mode of the load comparison quantization circuit 4, and finally changing the speed and power consumption of the load comparison quantization circuit 4. The mode control signal mod is respectively connected to the quantization voltage generation circuit 41, N comparators, the error filtering circuit 43, and the path selection circuit 44.

[0050] Under the control of the mode control signal mod, the path selection circuit 44 selects the signal path of the N-bit quantization code Dlo. The high-speed path output port of the path selection circuit 44 outputs N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit 47. The low-speed path output port of the path selection circuit 44 outputs 1-bit serial data, which first enters the serial shift register 45, and then passes through the serial-to-parallel conversion circuit 46 to obtain M-bit parallel quantization code Dlp, and then outputs it to the second data input port of the M-bit buffer output circuit 47. The M-bit buffer output circuit 47 obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

[0051] The load comparison quantization circuit 4 has two modes: high-speed mode and low-speed mode. When in the high-speed mode, the quantization voltage generation circuit 41 outputs N quantization reference voltages Vr1~VrN simultaneously under the control of the control clock Ck1, and N comparators simultaneously compare the drive signal VO with the N quantization reference voltages Vr1~VrN to obtain the quantization values D1~DN of N-bit parallel output, and then pass through the error filtering circuit 43 to obtain the N-bit quantization code Dlo. At this time, the N-bit quantization code Dlo is N-bit parallel data, which will be directly output to the first data input port of the M-bit buffer output circuit 47, and the M-bit buffer output circuit 47 obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

[0052] When in the low-speed mode, only one comparator in the N comparators works, assumed to be the first comparator, and the remaining N-1 comparators are in the sleep state. The quantization voltage generation circuit 41 outputs N quantization reference voltages Vr1~VrN in sequence according to the time sequence from the Vr1 output port under the control of the control clock Ck1. The first comparator compares the drive signal VO with the N quantization reference voltages Vr1~VrN output by Vr1 in sequence according to the time sequence, and outputs the quantization values D1~DN of N-bit serial output in sequence at its output port, and then passes through the error filtering circuit 43 to obtain the N-bit quantization code Dlo. At this time, the N-bit quantization code Dlo is 1-bit serial data, and this 1-bit serial data first enters the serial shift register 45, and then passes through the serial-to-parallel conversion circuit 46 to obtain M-bit parallel quantization code Dlp, and then outputs it to the second data input port of the M-bit buffer output circuit 47. The M-bit buffer output circuit 47 obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

[0053] The significance of the load comparison quantization circuit 4 adopting two modes of high speed and low speed lies in saving the power consumption of the circuit and reducing the circuit power consumption in the low speed mode. The above-mentioned N reference voltages Vr1 to VrN can be set at uniform intervals using thermometer code or set with different binary weights. Therefore, in actual implementation, an appropriate comparator type and combination strategy can be selected according to the requirements of the driving chip application system. Since there is a certain offset in the comparator, and the higher the operating speed of the comparator, the more serious the offset, it is necessary to filter the errors of the N-bit quantization values D1 to DN, and there are great differences in the implementation strategies of the error filtering circuit 43. If N comparators work in parallel, a digital algorithm for offset calibration of Flash ADC comparators needs to be used for error filtering; if the first comparator is multiplexed for work, a digital algorithm for offset calibration of SAR ADC needs to be used for error filtering.

[0054] Figures 7 to 10 This is a schematic diagram of the application of the present invention in various existing controller systems.

[0055] Figure 7 The following is a schematic diagram of the application of the present invention in an AC-DC controller chip. The AC-DC control chip can be divided into four major blocks according to its functions, which are briefly described as follows:

[0056] (1) Reference generation module. It mainly includes: a high-voltage regulator circuit in the upper right corner, which is used to receive the high voltage from the VDD pin of the chip and convert it into an internal 5V power supply voltage; a bandgap reference voltage source circuit, which is used to generate a bandgap reference voltage to provide a reference level for the internal circuit voltage of the chip; a reference current source circuit, which provides a reliable current reference for the internal circuit of the chip; and overvoltage and undervoltage protection circuits.

[0057] (2) Constant voltage control module. In the constant voltage loop, it is roughly divided into a constant voltage turn-on signal generation loop and a constant voltage turn-off signal generation loop. In the turn-on signal generation loop, the output voltage is sampled, and together with the FB sample / hold circuit, the error amplifier EA and the negative feedback resistor, they form an inverting amplifier with a fixed gain of 40 times. The FB sampled voltage is connected to the inverting input terminal of the error amplifier through a resistor, and the non-inverting input terminal of the error amplifier is connected to a 2.5V reference voltage. The output voltage Vcomp of the error amplifier is sent to the first PWM comparator to generate the turn-on signal CV_ON of the power transistor; the Vcomp signal is processed by resistor voltage division and the filter LPF and then sent to the constant voltage current protection circuit CV_OCP to generate the turn-off signal CV_OFF of the power transistor in the constant voltage mode.

[0058] (3) Constant current control module. In the constant current loop, the constant current turn-on signal and the constant current turn-off signal are mainly generated. The primary peak current sampling signal CS is compared with the reference voltage of the transconductance op-amp through the CS sampling and holding circuit, and after being scaled by a certain ratio through the buffer Buffer, it is sent to the second PWM comparator. The second PWM comparator compares with the output of the previous-stage circuit and the corresponding reference voltage CS to generate the turn-off signal of the constant current loop. The constant current conduction signal enables the switching transistor to complete the switching conversion when the voltage crosses zero ZVS (Zero Voltage Switching), realizes valley conduction, and generates the conduction signal of the corresponding constant current loop.

[0059] (4) Logic control and output buffer driving module. The system starts in the constant current mode, judges the current load condition according to the sampling signals of each port, and in the logic control circuit, selects the required constant voltage or constant current turn-on / turn-off signal, and generates the driving signal of the power transistor, finally maintaining the constancy of the output voltage or current. The output buffer circuit 00 with self-adaptive adjustment of driving characteristics proposed by the present invention is connected between the driving signal output end of the logic control circuit and the DRV pin, and is used to provide self-adaptive adjustment of output driving ability for the DRV pin.

[0060] Figure 8 It is a schematic diagram of the application of the present invention in a DC-DC controller. The DC-DC controller adopts the synchronous rectification method, and its normal working mode is the continuous mode CCM, and the modulation method is selected as the PWM method. Figure 8 The differential amplifier DIFFAMP in it is used to realize differential remote sampling, and its output port leads out pins for users to select. The output DRS of the differential remote sampling is then divided by the sampling resistors R A and R B to obtain the feedback voltage V FB , V FB is error-amplified with the internally generated 0.6V voltage reference to obtain the signal V EA . The inductor DCR current sampling is a non-destructive current sampling method. In the figure, a negative temperature coefficient resistor RNTC is placed near the inductor L for temperature sampling and input to the temperature compensation module, and then the inductor temperature compensation is completed by the ramp clamping circuit.

[0061] In the normal working mode, the clock signal CLK sets the RS latch to turn on the MOS transistor MT, and the current comparator I CMP output signal PWM resets the RS latch to turn off the MOS transistor MT. The sampling threshold of I CMP is controlled by the current I THC . Under the condition that the delay blanking current I LIM is configured and determined, the current I THC is determined by the output result V EAControl. The output buffer circuit 00 with self - adaptive adjustment of driving characteristics proposed by the present invention is connected between the driving signal output terminal of the switching logic control circuit and the TG pin and BG pin for driving the external MOSFET on the right side of the chip, and is used to provide self - adaptive adjusted output driving ability for the TG pin and BG pin. When the load becomes heavier, the output voltage Vo decreases, which causes I THC to increase, and the threshold of the current comparator I CMP increases, that is, the conduction time becomes longer, and more current is transmitted to Vo. When the load becomes lighter, the control process is opposite to the above.

[0062] Figure 8 The on - chip power supply module and reference and bias module on the upper part provide power supply, reference voltage, current bias, etc. for the normal operation of the system circuit. The reverse current comparator assists in completing functions such as synchronous rectification and light - load operation mode. In addition, Figure 8 the controller system shown also integrates functions such as under - voltage protection, over - voltage protection, start - up enable, soft - start configuration, etc.

[0063] Figure 9 is a schematic diagram of the application of the present invention in a motor controller. The motor controller chip has 14 pins, from pin 1 to pin 14 are: VBB, VCP, GND1, GND2, MODE, PHASE, ENABLE, nSLEEP, OUT +, OUT -, SENSE, nFAULT, VREG, NC (not marked in the figure). Among them, the MODE, PHASE, nSLEEP, and ENABLE pins are control signal input ports. The nFAULT is an error alarm signal output port. The OUT + and OUT - are H - bridge output ports, providing driving current. The motor drive usually adopts an H - bridge structure, and the motor load is connected between the OUT + pin and OUT - pin of the H - bridge output.

[0064] Figure 9 The functional modules of the motor controller shown generally include:

[0065] (1) Power supply module: It consists of a band - gap reference voltage source and a self - starting high - voltage LDO, and provides a stable low - voltage power supply for the subsequent low - voltage module.

[0066] (2) Oscillator OSC and high - voltage charge pump module: By controlling the on - off of the switch to charge and discharge the pump capacitor to achieve the lifting of the potential, and then stabilizing the output voltage at a voltage 5.5V higher than the input power supply voltage VBB through the PSM control loop, and providing a driving voltage for the gate terminal of the power MOS tube.

[0067] (3) Mode control module: Through control logic, the externally input MODE, PHASE, nSLEEP, and ENABLE signals are converted into 4 gate control signals through a series of digital logics to respectively control the forward and reverse rotation, fast and slow deceleration, low-power sleep mode, and PWM control of the motor.

[0068] (4) The output buffer circuit 00 proposed by the present invention: It is connected between the control signal output by the control logic and the H-bridge output ports OUT+ and OUT-, providing an external gate drive voltage and current to enable the power transistors in the external motor to conduct and turn off quickly.

[0069] (5) Protection circuit: Integrated with various protection modules, which will not be elaborated here.

[0070] Figure 10 It is a schematic diagram of the application of the present invention in a PWM controller. Figure 10 It is a functional block diagram. The PWM controller mainly includes: a reference module, an LDO module, an undervoltage protection module, a logic module, an oscillator module, a PWM waveform generation module, a dead-time control module, a synchronous rectification control module, and 2 output buffer circuit modules proposed by the present invention, etc.

[0071] The high-side and low-side two-way pulse output signals output by the PWM waveform generation module generate the pulse drive signals required by the 2 output buffer circuit modules proposed by the present invention through the dead-time control module. The dead-time control module sets the external resistor RDLY to set the timing between the half-bridge gate drive signal and the synchronous rectification drive signal. Considering the rise time and fall time of the drive port when the chip is working, the dead time is usually set to 50ns - 500ns. The output buffer circuit 00 with self-adaptive adjustment of drive characteristics proposed by the present invention is connected between the dead-time control module and the HO pin and LO pin for driving the external MOSFET, and is used to provide self-adaptive adjustment of output drive capabilities for the HO pin and LO pin.

[0072] As described in the above embodiments, the present invention can be widely applied to various high-voltage integrated circuit chips.

[0073] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An output buffer circuit with adaptive adjustment of driving characteristics, characterized by comprising: P-terminal inverter chain, N-terminal inverter chain, n P-terminal output inverters, n N-terminal output inverters, n P-terminal output PMOS transistors, n N-terminal output NMOS transistors, n P-terminal output inverter control switches, n N-terminal output inverter control switches, sampling switch, working timing generation circuit, load comparison quantization circuit, and drive current selection circuit; the internal structures of the P-terminal inverter chain and the N-terminal inverter chain are the same, both are cascaded inverters, and the driving capabilities of the inverters gradually increase from the front stage to the rear stage; the input ends of the P-terminal inverter chain and the N-terminal inverter chain are both connected to the input data Din, the outputs of the P-terminal inverter chain are respectively connected to the input ends of n P-terminal output inverters through n P-terminal output inverter control switches, and the output ends of the n P-terminal output inverters are respectively connected to the gate ends of n P-terminal output PMOS transistors; the outputs of the N-terminal inverter chain are respectively connected to the input ends of n N-terminal output inverters through n N-terminal output inverter control switches, and the output ends of the n N-terminal output inverters are respectively connected to the gate ends of n N-terminal output NMOS transistors; the source ends of the n P-terminal output PMOS transistors are all connected to the power supply voltage VCC, the source ends of the n N-terminal output NMOS transistors are all connected to the ground, and the drain ends of the n P-terminal output PMOS transistors and the drain ends of the n N-terminal output NMOS transistors are connected together to generate the drive signal VO; The drive signal VO is sampled by the sampling switch and then connected to the load comparison quantization circuit. The load comparison quantization circuit is also connected to the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin output by the working timing generation circuit. The load comparison quantization circuit obtains the load quantization code Dlot under the control of the reference voltage Vr, the control clock Ck1, and the frequency discrimination code Dfin, and is connected to the drive current selection circuit; the input end of the working timing generation circuit is connected to the input data Din, tracks and discriminates the frequency of the input data Din, obtains the frequency discrimination code Dfin of Din, and generates non-overlapping high-level control clock Ck1 and control clock Ck2; the control clock Ck1, the control clock Ck2, and the load quantization code Dlot output by the load comparison quantization circuit enter the drive current selection circuit simultaneously, generating the switch control signals Kp1~Kpn of the n P-terminal output inverter control switches and the switch control signals Kn1~Knn of the n N-terminal output inverter control switches; where n is any positive integer.

2. The output buffer circuit with self-adaptive adjustment of driving characteristics according to claim 1, wherein After the power supply voltage is powered on, the working timing generation circuit tracks and discriminates the frequency of the input data Din to obtain the frequency discrimination code Dfin, and generates the control clock Ck1 and the control clock Ck2; when the Ck1 clock is valid, the load comparison and quantization circuit generates a set of default load quantization codes Dlot_pre according to the driving signal VO sampled by the sampling switch, the reference voltage Vr, and the status of the frequency discrimination code Dfin, and enters the drive current selection circuit. The drive current selection circuit will output a set of default switch control signals Kp1_pre~Kpn_pre and switch control signals Kn1_pre ~Knn_pre to control the n P-terminal output inverter control switches and the n N-terminal output inverter control switches respectively; the driving signal VO will drive the external load under the action of the default driving current and gradually increase the voltage of the driving signal VO; when the Ck1 clock ends, the load quantization code Dlot_pre will be adjusted according to the magnitude of the driving signal VO at this time to obtain the adjusted load quantization code Dlot_lock and remain unchanged; when the Ck2 clock is valid, the drive current selection circuit will output a new set of switch control signals Kp1_lock ~Kpn_lock and switch control signals Kn1_lock ~Knn_lock according to the load quantization code Dlot_lock to control the n P-terminal output inverter control switches and the n N-terminal output inverter control switches respectively; the driving signal VO will drive the external load under the action of the new driving current and quickly increase the voltage of the driving signal VO to the power supply voltage VCC; when the Ck2 clock ends, the load quantization code Dlot will be cleared, and the output switch control signals Kp1 ~Kpn of the drive current selection circuit will be cleared synchronously, turning off the n P-terminal output inverter control switches, and at the same time turning on the switch control signals Kn1 ~Knn to turn on the n N-terminal output inverter control switches, and the driving signal VO will be quickly pulled down from the power supply voltage VCC to the ground voltage GND, thereby turning off the external load power device.

3. The output buffer circuit with adaptive adjustment of driving characteristics according to claim 1, characterized in that, The working timing generation circuit includes: an oscillator (31), a pulse width counter (32), a counting period selection circuit (33), a comprehensive counter (34), a first clock waveform generation circuit (35), and a second clock waveform generation circuit (36); the OSC signal generated by the oscillator (31) is connected to the pulse width counter (32) and the comprehensive counter (34), and the input data Din is simultaneously connected to the pulse width counter (32) and the comprehensive counter (34); the pulse width counter (32) counts the pulse time width of the input data Din according to the OSC signal, and performs tracking discrimination and comparison quantization on the counted pulse time width size to output a frequency discrimination code Dfin; the frequency discrimination code Dfin is connected to the counting period selection circuit (33) to generate a comprehensive counter mode selection signal sel0; the comprehensive counter (34) generates a clock control signal ct1 and a clock control signal ct2 according to the mode selection signal sel0, the OSC signal, and the input data Din; finally, the clock control signal ct1 and the clock control signal ct2 are respectively connected to the first clock waveform generation circuit (35) and the second clock waveform generation circuit (36), and the first clock waveform generation circuit (35) and the second clock waveform generation circuit (36) respectively output the final control clocks Ck1 and Ck2.

4. The output buffer circuit with adaptively adjusted driving characteristics according to claim 3, characterized in that, After the chip is powered on, the OSC signal becomes valid; when the input data Din starts to appear the rising edge of low level to high level, both the pulse width counter (32) and the comprehensive counter (34) start counting, and at the same time the frequency discrimination code Dfin outputs a default initial intermediate value, and then the counting period selection circuit (33) outputs a default initial comprehensive counter mode selection signal sel0; the comprehensive counter (34) first starts counting the clock control signal ct1 according to the comprehensive counter mode selection signal sel0, the OSC signal, and the input data Din, and changes the clock control signal ct1 from low level to high level, and then after J OSC time periods of counting delay, ends the counting of the clock control signal ct1, and changes the clock control signal ct1 from high level to low level; then after K OSC time periods of counting delay, the comprehensive counter (34) starts counting the clock control signal ct2, and changes the clock control signal ct2 from low level to high level; then after L OSC time periods of counting delay, and when the input data Din starts to appear the falling edge of high level to low level, the comprehensive counter (34) ends the counting of the clock control signal ct2, and changes the clock control signal ct2 from high level to low level; the waveforms generated by the clock control signal ct1 and the clock control signal ct2 in the above process are respectively buffered by the first clock waveform generation circuit (35) and the second clock waveform generation circuit (36) to obtain the final control clocks Ck1 and Ck2; During the above waveform generation process, if the pulse width counter (32) discriminates and tracks the pulse time width of the input data Din and obtains that the frequency discrimination code Dfin is not equal to the default value, the comprehensive counter mode selection signal sel0 output by the counting period selection circuit (33) will change, thereby adjusting the sizes of J, K, and L proportionally, and finally adjusting the output clock frequencies of the control clock Ck1 and the control clock Ck2; where J, K, and L are all positive integers, J is a positive integer greater than K, and L is a positive integer more than 3 times larger than J.

5. The output buffer circuit with self-adaptive adjustment of driving characteristics according to claim 1, characterized in that, The load comparison quantization circuit (4) includes: a quantization voltage generation circuit (41), a high / low speed mode selection circuit (42), N comparators, an error filtering circuit (43), a path selection circuit (44), a serial shift register (45), a serial-to-parallel conversion circuit (46), and an M-bit buffer output circuit (47); the input end of the quantization voltage generation circuit (41) is connected to the reference voltage Vr, the control clock Ck1, and the mode control signal mod output by the high / low speed mode selection circuit (42). The quantization voltage generation circuit (41) converts the reference voltage Vr into N quantization reference voltages Vr1~VrN under the control of the control clock Ck1, and respectively connects them to the reference voltage input ends of the N comparators; the detection voltage input ends of the N comparators are all connected to the drive signal VO, and the N comparators respectively compare the drive signal VO with the N quantization reference voltages Vr1~VrN and output N-bit quantization values D1~DN; then the N-bit quantization values D1~DN enter the error filtering circuit (43) and output N-bit quantization codes Dlo; the high / low speed mode selection circuit (42) outputs the mode control signal mod according to the magnitude of the frequency discrimination code Dfin, thereby changing the mode of the load comparison quantization circuit (4), and finally changing the speed and power consumption of the load comparison quantization circuit (4). The mode control signal mod is respectively connected to the quantization voltage generation circuit (41), the N comparators, the error filtering circuit (43), and the path selection circuit (44); the path selection circuit (44) selects the signal path of the N-bit quantization code Dlo under the control of the mode control signal mod; the high-speed path output port of the path selection circuit (44) is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit (47). The low-speed path output port of the path selection circuit (44) is 1-bit serial data, which is first connected to the serial shift register (45), and then enters the serial-to-parallel conversion circuit (46) after output to obtain M-bit parallel quantization codes Dlp, which are connected to the second data input port of the M-bit buffer output circuit (47); the M-bit buffer output circuit (47) outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1; where M and N are both integers greater than 1.

6. The output buffer circuit with adaptively adjusted driving characteristics according to claim 5, characterized in that, The load comparison quantization circuit (4) includes two modes: high-speed mode and low-speed mode; when in the high-speed mode, the quantization voltage generation circuit (41) outputs N quantization reference voltages Vr1 to VrN simultaneously under the control of the control clock Ck1. N comparators respectively compare the drive signal VO with the N quantization reference voltages Vr1 to VrN simultaneously and output N-bit parallel quantization values D1 to DN. Then, through the error filtering circuit (43), an N-bit quantization code Dlo is obtained. At this time, the N-bit quantization code Dlo is N-bit parallel data, which is directly output to the first data input port of the M-bit buffer output circuit (47) through the high-speed path output port of the path selection circuit (44). The M-bit buffer output circuit (47) outputs the final M-bit load quantization code Dlot under the control of the control clock Ck1. When in the low-speed mode, only the first comparator among the N comparators works, and the remaining N - 1 comparators are in a dormant state. The quantization voltage generation circuit (41) outputs N quantization reference voltages in sequence according to the time sequence from the Vr1 output port under the control of the control clock Ck1. The first comparator compares the drive signal VO with the N quantization reference voltages output by Vr1 in sequence according to the time sequence, and outputs N-bit serial quantization values D1 to DN in sequence at the output port of the first comparator. Then, through the error filtering circuit (43), an N-bit quantization code Dlo is obtained. At this time, the N-bit quantization code Dlo is 1-bit serial data, which enters the serial shift register (45) in sequence through the low-speed path output port of the path selection circuit (44). The output of the serial shift register (45) then enters the serial-to-parallel conversion circuit (46) to obtain an M-bit parallel quantization code Dlp, which is output to the second data input port of the M-bit buffer output circuit (47). The M-bit buffer output circuit (47) obtains the final M-bit load quantization code Dlot under the control of the control clock Ck1.

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