System and method for digital-to-analog conversion frequency distortion compensation

Abstract

The present disclosure relates to systems and methods for digital-to-analog conversion frequency distortion compensation. The systems and methods discussed herein relate to digital-to-analog conversion. A digital-to-analog conversion, compensation circuit, and a digital-to-analog conversion circuit. The compensation circuit includes a filter configured to provide roll-off compensation in a baseband frequency using real coefficients. The compensation circuit is configured to convert the first digital signal to a second digital signal such that the second digital signal can be filtered by the filter using the real coefficients.

Description

Technical Field

[0001] This disclosure generally relates to systems and methods for compensation in digital-to-analog conversion operations or digital-to-analog converters (DACs). Background Technology

[0002] Over the past few decades, the market for integrated circuit devices has grown exponentially due to the increasing demand for portable devices and the growing connectivity and data transmission between various devices. Digital-to-analog (DAC) technology is widely used in integrated circuit devices. DACs are commonly found in communication circuits and other types of circuits that use both analog and digital signals. Generally, radio frequency transmitters used in wireless base stations include DACs. A DAC converts digital signals into electrical analog signals. Summary of the Invention

[0003] In one aspect, this disclosure relates to an apparatus comprising: a compensation circuit including a filter configured to provide roll-off compensation in a baseband frequency using real coefficients, wherein the compensation circuit is configured to convert a first digital signal into a second digital signal such that the second digital signal can be filtered by the filter using the real coefficients; and a digital-to-analog converter circuit including a digital input configured to receive a filtered signal or a first version of the filtered signal from the filter, and to provide an analog signal at an analog output.

[0004] On the other hand, this disclosure relates to a method comprising: upsampling and rotating a digital signal having real and imaginary values ​​to provide a digital signal in a real domain; filtering the digital signal in the real domain to provide a distortion-compensated signal; derotating the distortion-compensated signal; and converting the distortion-compensated signal into an analog signal.

[0005] On the other hand, this disclosure relates to a transmitter comprising: a compensation circuit including a rotator, a filter, and a derotator, wherein the rotator is configured to receive an in-phase digital signal and a quadrature digital signal, and to provide a rotated in-phase signal and a rotated quadrature signal; wherein the filter is configured to receive the rotated in-phase signal and the rotated quadrature signal, and to provide a filtered in-phase signal and a filtered quadrature signal; the filter is configured to compensate for digital-to-analog conversion distortion; wherein the derotator is configured to receive the filtered in-phase signal and the filtered quadrature signal, and to provide a derotated in-phase signal and a derotated quadrature signal; a frequency converter configured to receive the derotated in-phase signal and the derotated quadrature signal, and to provide an up-converted in-phase signal and an up-converted quadrature signal; and a digital-to-analog converter configured to receive the up-converted in-phase signal and the up-converted quadrature signal, and to provide an analog signal at an analog output. Attached Figure Description

[0006] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood through reference to the detailed description taken in conjunction with the accompanying drawings, in which similar reference characters consistently identify corresponding elements. In the drawings, similar reference numerals generally indicate equivalent, functionally similar, and / or structurally similar elements.

[0007] Figure 1 This is a general schematic block diagram of a wired communication system including a digital-to-analog conversion system with frequency response distortion compensation, according to some embodiments.

[0008] Figure 2 This is a general schematic block diagram of a wireless communication system including a digital-to-analog converter with frequency response distortion compensation, according to some embodiments.

[0009] Figure 3 According to some embodiments, it is used for Figure 1 Or a more detailed schematic block diagram of a digital-to-analog converter system with frequency response distortion compensation in the communication system described in section 2;

[0010] Figure 4 It is based on some embodiments and in Figure 3 The diagram illustrates the frequency response of a baseband x / sinx FIR filter with frequency response distortion compensation for a digital-to-analog converter system previously used, compared to a 3x interpolation-1 filter.

[0011] Figure 5 Compensation based on some embodiments Figure 3 The diagram illustrates the baseband equivalent of the desired x / sinx filter response and the baseband x / sinx FIR filter response for a digital-to-analog converter system with frequency response distortion compensation at the desired mixer frequency.

[0012] Figure 6 According to some embodiments Figure 3 The diagram shows the output residual error in dB between the expected x / sinx filter response and the x / sinx FIR filter response of the exemplary filter for a digital-to-analog converter system with frequency response distortion compensation as illustrated in the figure.

[0013] Figure 7 According to some embodiments Figure 3 The diagram illustrates the DAC distortion, x / sinx compensation, and combined response of a digital-to-analog converter system with frequency response distortion compensation.

[0014] Figure 8 According to some embodiments Figure 3The diagram shows the impulse response of an exemplary filter for a digital-to-analog converter system with frequency response distortion compensation, as illustrated in the figure.

[0015] Figure 9 According to some embodiments Figure 3 The power spectral density versus frequency plot of the exemplary filter with frequency response distortion compensation for a digital-to-analog converter system illustrated in the figure at the baseband frequency;

[0016] Figure 10 According to some embodiments Figure 3 The diagram illustrates the power spectral density versus frequency of the output of a digital-to-analog converter system with frequency response distortion compensation at radio frequency; and

[0017] Figure 11 This is to demonstrate, according to some embodiments, the... Figure 3 The flowchart illustrates the exemplary operation performed by a digital-to-analog converter system with frequency response distortion compensation. Detailed Implementation

[0018] The entire contents of the following standards (including any draft versions of such standards) are hereby incorporated by reference and form part of this disclosure for all purposes: 4G LTE, 5G, IEEE 802.11x, IEEE 802.11ad, IEEE 802.11ah, IEEE 802.11aj, IEEE 802.16 and 802.16a, and IEEE 802.11ac, IEEE P802.3TM and Cable Data Service Interface Specifications (D3.1 and D4.0). Although this disclosure may reference aspects of these standards, it is in no way limited to these standards.

[0019] For the purpose of reading the descriptions of the various embodiments below, the following description of the sections of the specification and their corresponding contents may be helpful:

[0020] Section A describes embodiments of systems and methods for digital-to-analog conversion; and

[0021] Section B describes the network and computing environments that can be used to practice the embodiments described herein.

[0022] A. Systems and methods for digital-to-analog conversion

[0023] Digital-to-analog converters (DACs) are used in a variety of wireless and wired communication devices and other mixing signal systems. DACs are also used in processors, microcontrollers, and other circuitry that processes digital data and transmits or processes analog signals. In one exemplary application, a 5G direct-conversion transmitter uses one or more DACs.

[0024] In some embodiments, a digital-to-analog converter system with frequency response distortion compensation compensates for roll-off during digital-to-analog conversion. In some embodiments, the roll-off is characterized by T s sin(πfT s ) / (πfT s The characteristics of (sin(x) / x) and the inverse sinc filter compensate for roll-off. Some embodiments of systems and methods with frequency response distortion compensation utilize filters that do not operate at the DAC sampling rate to match the entire DAC frequency response, thereby eliminating the need for large filter coefficients and higher power consumption. In some embodiments, the digital-to-analog converter with frequency response distortion compensation performs compensation at the baseband frequency (e.g., before up-conversion to radio frequency (RF)). In some embodiments, the digital-to-analog converter with frequency response distortion compensation performs compensation at the baseband frequency (e.g., before up-conversion to RF or transmission frequency) without requiring complex-valued baseband finite-infinite response (FIR) filtering, which requires more filter coefficients and power consumption than real-valued baseband FIR filtering. In some embodiments, the systems and methods with frequency response distortion compensation use real-valued baseband FIR filtering.

[0025] Some embodiments relate to a device. The device includes compensation circuitry and a digital-to-analog converter (DAC). The compensation circuitry includes a filter configured to provide roll-off compensation in a baseband frequency using real coefficients. The compensation circuitry is configured to convert a first digital signal into a second digital signal such that the second digital signal can be filtered by the filter using the real coefficients. The DAC includes a digital input configured to receive a filtered signal or a first version of the filtered signal from the filter, and provides an analog signal at an analog output.

[0026] Some embodiments relate to a method. The method includes: rotating a digital signal having real and imaginary values ​​to provide a digital signal in a real domain; filtering the digital signal in the real domain to provide a distortion-compensated signal; and derotating the distortion-compensated signal. The method further includes converting the distortion-compensated signal into an analog signal.

[0027] Some embodiments relate to a transmitter. The transmitter includes compensation circuitry comprising a rotator, a filter, and a derotator. The rotator is configured to receive in-phase and quadrature digital signals and provide rotated in-phase and rotated quadrature signals. The filter is configured to receive the rotated in-phase and rotated quadrature signals and provide filtered in-phase and filtered quadrature signals. The derotator is configured to receive the filtered in-phase and filtered quadrature signals and provide derotated in-phase and derotated quadrature signals. The transmitter further includes a frequency converter configured to receive the derotated in-phase and derotated quadrature signals and provide up-converted in-phase and up-converted quadrature signals. The transmitter also includes a digital-to-analog converter configured to receive the up-converted in-phase and up-converted quadrature signals and provide an analog signal at an analog output.

[0028] Some embodiments relate to a device. The device includes a compensation circuit and a digital-to-analog converter (DAC). The compensation circuit includes a filter configured to provide roll-off compensation in a baseband frequency. The compensation circuit is configured to provide two paths through the filter. A first value is filtered through a first path of the filter, and a second value is filtered through a second path of the filter. The second value is a coefficient of the square root of negative one. The DAC includes a digital input configured to receive a filtered signal or a first version of the filtered signal from the filter, and provides an analog signal at an analog output.

[0029] refer to Figure 1 In some embodiments, the communication system 9 includes a first transceiver 10 and a second transceiver 12 that communicate via a twisted-pair conductive medium, a single-pair conductive medium, a coaxial cable, an optical fiber, or a conductor 17. In some embodiments, the communication system 19 includes a wireless communication system ( Figure 2 The first transceiver 30 and the second transceiver 32 communicate with each other and do not include conductor 17. Communication systems 9 and 19 can be any type of communication system, including (but not limited to) wireless networks (e.g., 4G LTE or 5G), Cable Data Service Interface Specification (DOCSIS) systems, Ethernet systems, automotive communication systems, 802.11 systems, etc. In some embodiments, conductor 17 can be a single-ended conductor or a differential conductor pair, and can be any communication medium used for communication.

[0030] Transceivers 10, 12, 30, and 32 may be part of other devices (not specified), such as access points, vehicle components, television systems, satellite systems, cable modems, telephone devices, computing devices, cameras, displays, network devices, or any other type and form of electronic device utilizing a communication system. Transceivers 10, 12, 30, and 32 may be part of a local area network (LAN) or a wide area network (WAN), and may include DOCSIS transmitters, Ethernet transmitters, wireless transmitters, or other communication circuitry.

[0031] In some embodiments, transceivers 10, 12, 30, and 32 each include a digital-to-analog converter system with frequency response distortion compensation, comprising compensation circuitry 14, up-converter 16, and DAC 18. A digital signal is provided to compensation circuitry 14, which provides compensation for distortion (e.g., roll-off). In some embodiments, compensation is performed by an inverse sinc(x) filter at the baseband frequency. In some embodiments, the inverse sinc(x) filter is implemented as a real-valued baseband FIR filter. The filtered digital signal is up-converted by up-converter 16 and provided to DAC 18. DAC 18 converts the up-converted digital signal to provide an analog signal. Up-converter 16 is a digital mixer circuit and in some embodiments may also include an interpolator.

[0032] refer to Figure 3 A digital-to-analog converter (DAC) system 100 with frequency response distortion compensation is provided on a physical (PHY) chip or integrated circuit (IC) within a package. In some embodiments, the DAC system 100 with frequency response distortion compensation is a chip design and can be used as a DAC system with frequency response distortion compensation in transceivers 10, 12, 30, and 32. The DAC system 100 with frequency response distortion compensation can be part of a transmitter and can be a radio frequency DAC device (e.g., in a direct conversion transceiver). The systems and methods described herein with respect to the DAC system 100 with frequency response distortion compensation can be used in a wide range of devices, including (but not limited to) devices used in high-speed and high-resolution applications, across various DAC architectures.

[0033] A digital-to-analog converter system 100 with frequency response distortion compensation includes a compensation circuit 104, an up-converter circuit 106, and a DAC 108. In some embodiments, the compensation circuit 104, the up-converter circuit 106, and the DAC 108 can be similar to the compensation circuit 14, the up-converter 16, and the DAC 18, respectively. Figures 1 to 2The compensation circuit 104 receives the baseband digital signal and provides the compensated digital signal to the upconverter 16. The upconverter 16 converts the compensated digital signal from baseband to a frequency higher than the baseband. In some embodiments, the higher frequency and the baseband frequency are in the gigahertz (GHz) range. In some embodiments, the baseband is lower than the transmission frequency of the analog signal (e.g., in a direct converter application).

[0034] The compensation circuit 104 includes a digital interface 110, interpolation filters 112a and 112b, a rotation circuit 113, x / sin(x) FIR filters 114a and 114b, and a de-rotation circuit 116. In some embodiments, the digital interface 110 is a JESD2048B interface and is coupled to a digital signal source, such as an ASIC, modem, storage device, user interface, or other digital signal source. The digital interface 110 provides in-phase digital signals and quadrature digital signals to the interpolation filters 112a through 112b, respectively.

[0035] With sampling frequency F s The digital signal is sampled. In some embodiments, for baseband signals, the sampling frequency F s It is capable of sampling frequencies between 0.5 and 3 gigahertz (GHz) (e.g., 1.77 GHz). The sampled digital signal is upsampled and filtered by interpolation filters 112a to b. In some embodiments, filters 112a to b have a response 206 as shown in FIG200, where the Y-axis 202 of FIG200 represents the magnitude and the X-axis 204 represents time. In some embodiments, filters 112a to b are 2X half-band (HB) interpolation FIR filters and in F... s2x =2F s The system provides 16-bit I and Q interpolated signals. In some embodiments, the interpolated signals are upsampled by filters 112a to b, and the outputs of the interpolation filters 112a to b are defined as z. 2x =I 2x +j*Q 2x Filters 112a to b can interpolate by a factor N and provide a combination of upsampling and filtering via zero padding (e.g., setting zeros between samples).

[0036] The interpolated signals from filters 112a to b are provided to the rotation circuit 113. The rotation circuit 113 is then multiplied by rot(n) = e j2πnF / Fs2x The frequency-shifted interpolated digital signal can be represented as:

[0037] y2x(n)=Z2x(n)e j2πnF / Fs2x

[0038] Where: rot(n) = cos(2πnF / F)s2x )+j*sin(2πnF / F s2x In some embodiments, cos(2πnF / F) s2x )+j*sin(2πnF / F s2x The sequence can be stored in a lookup table (LUT) that repeats every 4 cycles, as shown in Table 1, where F = F s2x / 4, and n is the symbol index. Other sequences are possible.

[0039] n <![CDATA[cos(2*π*n*F / F s2x )]]> <![CDATA[j*sin(2*π*n*F / F s2x )]]> 0 1 0 1 0 1 2 -1 0 3 0 -1

[0040] Table 1. F = F s2x / 4 complex-valued frequency shift LUT

[0041] Advantageously, in some embodiments, multiplying this sequence requires only addition / NOT and multiplication operations in hardware. The real term {y²x} and the imaginary term {y²x} are applied separately to the equivalent inverse sinc(x)(x / sin(x)) compensated digital FIR filter blocks or filters 114a to b. If the bandwidth or carrier frequency of the signal changes, corresponding pre-designed DAC compensated filter coefficients can be loaded into the FIR filters 114a to b. By performing a frequency shift, the band of interest is not a complex envelope centered on direct current (DC), and in some embodiments, it is a real signal. By using real signals and real filter coefficients, complex filter taps are avoided, and in some embodiments, fewer taps (e.g., 15) are used. In some embodiments, the FIR filters 114a to b use fewer than 32 taps in total, and all coefficients are real coefficients (e.g., not complex coefficients containing both real and imaginary values).

[0042] The de-rotation circuit 116 passes through the sampling rate F s2x The digital compensation signal will be multiplied by signal e. -j2πn / 4 The digitally compensated signals from FIR filters 114a to b are frequency-shifted. A similar lookup table can be used to derotate the filtered signals. Signals Ix, Qx, Iy, Qy, Iz, and Qz are all real signals, where I+jQ is the complex representation of the real signal. Derotation circuit 116 provides Iz and Qz signals centered at DC. In some embodiments, the output of derotation circuit 116 is downsampled by 2 and provided to 3x3 interpolation filters 130a to b (e.g., performing zero-filling and filtering), which are frequency-shifted by FIR filters 114a to b. s A sampling rate of x9 (e.g., 16 GHz) and a signal frequency of 6 GHz provide a 16-bit signal. Filters 130a to b provide interpolated digital signals to mixers 140a to b, and mixers 140a to b provide up-converted signals to adder 144.

[0043] Upconverter circuit 106 includes circuit 142, mixers 140a to 140b, and adder 144. Filters 130a to 130b provide interpolation signals at the mixer data rate for multiplication with a numerically controlled oscillator carrier frequency signal from circuit 142. The numerically controlled oscillator carrier frequency signal is a 20-bit signal. The modulated real-valued output signal is used as input to DAC 108. In some embodiments, DAC 108 provides a modulated 6 GHz frequency signal.

[0044] Figure 170 shows the DAC output response on line 172, where the Y-axis is amplitude and the X-axis is frequency. Line 178 represents the frequency of interest and is a portion of the roll-off characteristic of the response shown by line 172. Compensation circuitry 104 provides compensation as indicated by line 174, which flattens the associated response shown by line 178. Advantageously, in some embodiments, only a small portion of the roll-off characteristic is compensated. Compensation at other frequencies is achieved by adjusting the coefficients of filters 114a to b. In some embodiments, the coefficients can be changed by loading new coefficients into the firmware (e.g., for the appropriate mixer frequency).

[0045] Adder 144 provides a digital summation signal to amplifier 150. DAC 108 converts the amplified signal into an analog signal provided at output 160 for reception by variable gain amplifier 162. DAC 108 may be a current-mode or voltage-mode conversion circuit. In some embodiments, DAC 108 is 9XF s Sampling rate operation.

[0046] In some embodiments, the digital components of the digital-to-analog converter system 100 with frequency response distortion compensation may be implemented using dedicated or non-dedicated circuitry or processor-based circuitry, including (but not limited to): a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), complementary metal-oxide-semiconductor (CMOS), or the like. In some instances, memory for storing data and computer instructions is included, such as random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, or the like. The hardware of filters 130a, 130b, 112a, 112b can advantageously be part of the system design of a larger device, and in some embodiments, no additional hardware is required.

[0047] refer to Figure 4Figure 400 includes a Y-axis 402 representing amplitude in decibels (dB) and an X-axis 404 representing frequency in GHz. The solid line 408 indicates... Figure 3 The exemplary baseband x / sinx FIR filter of the digital-to-analog converter system with frequency response distortion compensation described in the figure represents the estimated response of a 3X interpolation FIR filter (filters 130a to b) previously applied, and line 406 represents the estimated response of a 2X interpolation -1 FIR filter (filters 112a to b).

[0048] refer to Figure 5 Figure 500 includes a Y-axis 502 representing amplitude in decibels (dB) and an X-axis 504 representing frequency across DC. The solid line 506 represents the desired response of the transfer function (H) objective (e.g., with...). Figure 3 The line 174 is associated with the portion of the line, and the dashed line 508 represents the estimated response of the transfer function (H) of the FIR filter (e.g., the response of filters 114a to b).

[0049] refer to Figure 6 Figure 510 includes a Y-axis 512 representing amplitude in decibels (dB) and an X-axis 514 representing frequency. The solid line 516 represents the residual error between the solid line 506 and the dashed line 508 of the FIR filter (e.g., filters 114a to b). The estimated error is approximately sinusoidal and has a magnitude of 0.04 dB.

[0050] refer to Figure 7 Figure 520 includes a Y-axis 522 representing amplitude in decibels (dB) and an X-axis 524 representing frequency. Solid line 526 represents the response of sin x / x (e.g., corresponding to the roll-off characteristic associated with line 178). Dashed line 530 represents the response of the x / sin x FIR filter (e.g., filters 114a to b). Dashed line 528 represents the response of the sin x / x–x / sin x FIR filter (the difference between lines 526 and 530). The flatness of line 528 indicates appropriate compensation.

[0051] refer to Figure 8 Figure 540 includes a Y-axis 542 representing amplitude and an X-axis 544 representing time. The solid line 546 represents the impulse response of the FIR filter (e.g., filters 114a to b).

[0052] refer to Figure 9 Figure 600 includes a Y-axis 602 representing power divided by frequency in decibels (dB) and an X-axis 604 representing frequency. Solid lines 606 represent inputs to mixers 140a to 140b. Figure 3 The power spectral density of the signal prior to this. (Reference) Figure 10Figure 700 includes a Y-axis 702 representing power in decibels (dB) divided by frequency and an X-axis 704 representing frequency in GHz. The solid line 706 represents the output at 160° at mixers 140a to b. Figure 3 The power spectral density of the signal after (). Figures 5 to 10 The responses and estimates shown are for illustrative purposes only.

[0053] refer to Figure 11 The process 800 can be executed by a digital-to-analog converter system with frequency response distortion compensation 100. Process 800 includes operation 802, wherein digital signals (I and Q in some embodiments) are transmitted at a rate F. s Sampling is performed. At operation 804, the digital signal is interpolated to provide 2X F. s Sample. At operation 806, press F. s2x / 4 The interpolated digital signal is rotated to provide a digital signal as a real value. At operation 808, the rotated digital signal is filtered by an x / sin(x) filter. At operation 812, the digital signal is derotated. The downsampling and interpolation stages can be combined to save computation time and resources. At operation 814, the digital signal is downsampled to provide 1X F s Sample. At operation 818, the digital signal is interpolated to provide 9XF. s Sample. At operation 820, the digital signal is mixed to upconvert the signal to a higher frequency range. At operation 822, the digital signal is converted into an analog signal.

[0054] B. Computing and Networking Environment

[0055] After discussing specific embodiments of this solution, it may be helpful to describe the operating environment and associated system components (e.g., hardware elements) in conjunction with the methods and systems described herein. The network environment includes wired or wireless communication systems comprising one or more access points, one or more wireless communication devices (which may include transceivers 10, 12, 30, and 32), and network hardware components. The network environment may include a DOCSIS modem that enables high-bandwidth data transmission via existing coaxial cable systems associated with the transmission of cable television program signals (CATV). Wireless communication devices may include, for example, televisions, laptop computers, tablet computers, personal computers, and / or cellular telephone devices. In one embodiment, the network environment may be an Ethernet, ad hoc network, infrastructure wireless network, subnet, etc.

[0056] Access points (APs) can be operatively coupled to network hardware via a local area network (LAN) connection. The network hardware (which may include routers, gateways, switches, bridges, modems, system controllers, devices, etc.) provides LAN connectivity to the communication system. Each access point may have an associated antenna or antenna array to communicate with wireless communication devices in its area. Wireless communication devices may register with a specific access point to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communication), some wireless communication devices may communicate directly via assigned channels and communication protocols. Some wireless communication devices may be mobile or relatively static relative to the access point.

[0057] The network connection may include any type and / or form of network, and may include any of the following: point-to-point network, broadcast network, telecommunications network, data communication network, computer network. The network topology may be a bus, star, or ring network topology. The network may be any such network topology known to those skilled in the art capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0058] A digital-to-analog converter system with frequency response distortion compensation may include a central processing unit, and the digital signal processor is any logic circuit system that responds to and processes instructions fetched from memory. The memory may be any type or variant of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash, NOR flash, and solid-state drive (SSD).

[0059] While the examples of communication systems described above may include devices and access points operating according to the 802.11 standard, it should be understood that embodiments of the systems and methods may operate according to other standards and use wireless communication devices other than those configured as devices and access points. For example, without departing from the scope of the systems and methods described herein, multi-cell communication interfaces associated with cellular networks, satellite communications, vehicle communication networks, and other non-802.11 wireless networks can utilize the systems and methods described herein to achieve improved overall capacity and / or link quality.

[0060] It should be noted that certain paragraphs of this disclosure may use terms such as "first" and "second" in conjunction with devices, operating modes, transmission chains, antennas, etc., to identify or distinguish them from each other or for other purposes. These terms are not intended to relate entities (e.g., first device and second device) temporally or sequentially, although in some cases these entities may imply such a relationship. These terms also do not limit the number of possible entities (e.g., devices) that can operate within a system or environment.

[0061] It should be understood that the system described above may provide any or more of the components, and these components may be provided on a standalone machine or, in some embodiments, on multiple machines in a distributed system. For example, any type of interpolation filter may be used. Half-band filters are particularly efficient because approximately half of the coefficients are zero. Furthermore, the system and method described above may be provided as one or more computer-readable programs or executable instructions embodied in or therein one or more articles of manufacture. The articles of manufacture may be floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or magnetic tapes. Generally, computer-readable programs may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#, PROLOG) or any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or therein in one or more articles of manufacture.

[0062] While the foregoing written description of the methods and systems enables those skilled in the art to make and use what is currently considered the best mode of implementation, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples described herein. Therefore, these methods and systems should not be limited to the embodiments, methods, and examples described above, but rather to all embodiments and methods within the scope and spirit of this disclosure.

[0063] The foregoing describes a transmitter and digital-to-analog converter system with frequency response distortion compensation by means of functional building blocks that illustrate the performance of certain significant functions. For ease of description, the boundaries of these functional building blocks are arbitrarily defined. Functions and structures can be integrated together across such boundaries. Alternative boundaries can be defined as long as certain significant functions are properly performed. Similarly, flowchart blocks can be arbitrarily defined herein to illustrate certain significant functions. Within the scope used, flow boundaries and sequences can be defined in other ways, while still performing certain significant functionalities. Therefore, this alternative definition of both functional building blocks and flowchart blocks and sequences is within the scope and spirit of the claimed invention. Those skilled in the art will also recognize that the functional building blocks and other illustrative blocks, modules, and components described herein can be implemented as described or by discrete components, application-specific integrated circuits, processors executing appropriate software, and the like or any combination thereof.

Claims

1. An apparatus comprising: A compensation circuit includes a filter configured to provide roll-off compensation in a baseband frequency using real coefficients, wherein the compensation circuit is configured to convert a first digital signal into a second digital signal, the filter is configured to filter the second digital signal using the real coefficients to provide a filtered signal, and the second digital signal includes a rotated in-phase signal and a rotated quadrature signal, wherein the first digital signal originates from a signal source external to the device, and wherein the compensation circuit further includes: A rotating circuit configured to receive the first digital signal and provide the second digital signal; and A de-rotation circuit configured to receive the filtered signal and provide a first version of the filtered signal; and A digital-to-analog converter circuit configured to receive the first version of the filtered signal at a digital input and to provide an analog signal corresponding to the first digital signal at an analog output for transmission.

2. The device of claim 1, further comprising a mixer circuit disposed between the filter and the digital-to-analog converter circuit and configured to upconvert the filtered signal or a second version of the filtered signal, and to provide the first version of the filtered signal as an upconverted signal to the digital input at a frequency higher than the baseband frequency.

3. The device of claim 2, wherein the device is part of a direct transmitter provided in a single-chip device.

4. The device of claim 1, wherein the filter comprises fewer than 32 tap coefficients.

5. The device according to claim 4, wherein the real coefficients do not include imaginary values.

6. The apparatus of claim 1, wherein the first version of the filtered signal comprises a derotated in-phase signal and a derotated quadrature signal.

7. A method for a transmitter, comprising: The transmitter receives the raw digital signal from a signal source outside the transmitter. The original digital signal, which has real and imaginary values, is upsampled and rotated to provide a digital signal in the real domain. The digital signal in the real domain is filtered to provide a distortion compensation signal, the digital signal including a rotated in-phase signal and a rotated quadrature signal; Derotate the distortion compensation signal to provide a derotated distortion compensation signal; and The de-rotation distortion compensated signal is converted into an analog signal corresponding to the original digital signal for transmission.

8. The method of claim 7, wherein the distortion compensation signal digital signal is de-rotated to have real and imaginary components.

9. The method of claim 7, further comprising: The de-rotation distortion compensated signal is mixed to a higher frequency range before conversion.

10. The method of claim 7, wherein filtering is performed by an FIR filter.

11. The method of claim 7, wherein filtering is performed at the baseband by an x / sin(x) filter.

12. The method of claim 7, wherein the digital signal comprises an in-phase signal and a quadrature signal.

13. The method of claim 7, wherein the distortion compensation signal reduces the roll-off characteristics of the digital-to-analog converter.

14. A transmitter comprising: A compensation circuit includes a rotator, a filter, and a derotator, wherein the rotator is configured to receive in-phase and quadrature digital signals corresponding to original digital signals from a signal source outside the transmitter, and to provide rotated in-phase and rotated quadrature signals; wherein the filter is configured to receive the rotated in-phase and rotated quadrature signals, and to provide filtered in-phase and filtered quadrature signals, the filter being configured to compensate for digital-to-analog conversion distortion; and wherein the derotator is configured to receive the filtered in-phase and filtered quadrature signals, and to provide derotated in-phase and derotated quadrature signals. A frequency converter configured to receive the derotated in-phase signal and the derotated quadrature signal, and to provide the upconverted in-phase signal and the upconverted quadrature signal; as well as A digital-to-analog converter configured to receive the upconverted in-phase signal and the upconverted quadrature signal, and to provide an analog signal at the analog output corresponding to the original digital signal for transmission.

15. The transmitter of claim 14, wherein the filter has a response for compensating for conversion roll-off and comprises a first FIR filter and a second FIR filter.

16. The transmitter of claim 15, wherein the filter is configured to have a response that compensates for digital-to-analog conversion distortion at the baseband.

17. The transmitter of claim 15, wherein the filter is an x / sin(x) FIR filter.

18. The transmitter of claim 15, wherein the filter has 32 or fewer coefficients.

19. The transmitter of claim 15, wherein the filter has 16 or fewer real coefficients.

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