Semiconductor memory

Abstract

A semiconductor memory may include: a first variable resistor element including a first terminal and a second terminal; a second variable resistor element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first wire and the first terminal of the first variable resistor element; a second transistor configured to control an electrical connection between the first wire and the first terminal of the second variable resistor element; a connection layer configured to electrically connect the second terminal of the first variable resistor element to the second terminal and the third terminal of the second variable resistor element; and a third wire electrically connected to the connection layer.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and benefit to Korean Patent Application No. 10-2021-0146832, filed on October 29, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This patent document relates to memory circuits or devices. Background Technology

[0004] Recent trends in the electrical and electronics industry toward miniaturization, low power consumption, high performance, and versatility have compelled semiconductor manufacturers to focus on high-performance, high-capacity semiconductor devices. Examples of such high-performance, high-capacity semiconductor devices include memory devices that can store data by switching between different resistance states according to the applied voltage or current, such as resistive random access memory (RRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and electric fuses (E-fuse). Summary of the Invention

[0005] The technologies disclosed in this patent document include various embodiments of semiconductor memories with excellent operating characteristics and high integration.

[0006] In one embodiment, a semiconductor memory includes: a first variable resistor element including a first terminal and a second terminal; a second variable resistor element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first wire and the first terminal of the first variable resistor element; a second transistor configured to control an electrical connection between the first wire and the first terminal of the second variable resistor element; a connection layer configured to electrically connect a second terminal of the first variable resistor element to the second and third terminals of the second variable resistor element; and a third wire electrically connected to the connection layer.

[0007] In another embodiment, a semiconductor memory includes: a first transistor including a first gate electrode disposed on a substrate; a second transistor including a second gate electrode disposed on the substrate; a first variable resistor element disposed on the substrate and electrically connected to a first terminal of the first transistor; a second variable resistor element disposed on the substrate and electrically connected to the first terminal of the second transistor; a source line disposed on the substrate and electrically connected to a second terminal of the first transistor and a second terminal of the second transistor; a connection layer disposed on the first and second variable resistor elements and electrically connected to the first variable resistor element while contacting the entire upper surface of the second variable resistor element; a bit line disposed on the connection layer and electrically connected to the connection layer; a first contact plug configured to connect the source line to the second terminal of the first transistor and the second terminal of the second transistor; a second contact plug configured to connect the first variable resistor element to the first terminal of the first transistor; a third contact plug configured to connect the second variable resistor element to the first terminal of the second transistor; and a fifth contact plug configured to connect the bit line to the connection layer. Attached Figure Description

[0008] Figure 1 A storage unit based on some embodiments of the disclosed technology is shown.

[0009] Figure 2A Show Figure 1 An example of the first variable resistor element.

[0010] Figure 2B Show Figure 1 Another example of a first variable resistor element.

[0011] Figure 2C Show Figure 1 Another example of a first variable resistor element.

[0012] Figure 3 Show Figure 1 An example of a second variable resistor element.

[0013] Figure 4 Show Figure 1 The current path when the first variable resistor element of the storage cell is driven.

[0014] Figure 5 Show Figure 1 The current path when the second variable resistor element of the storage cell is driven.

[0015] Figure 6A It is shown Figure 1 The flowchart shows the programming operation of the first variable resistor element of the storage cell.

[0016] Figure 6B It is shown Figure 1 The flowchart shows the read operation of the first variable resistor element of the storage cell.

[0017] Figure 6C It is shown Figure 1 The flowchart shows the programming operation of the second variable resistor element of the storage cell.

[0018] Figure 7 This is a perspective view illustrating some embodiments of a storage device based on the disclosed technology.

[0019] Figure 8 Is with Figure 7 The corresponding cross-sectional view in the first direction. Detailed Implementation

[0020] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0021] The accompanying drawings are not necessarily drawn to scale. In some instances, the scale of at least some structures in the drawings has been enlarged to clearly illustrate certain features of the described embodiments. When a particular example of a multilayer structure with two or more layers is presented in the drawings or description, the relative positional relationship of these layers or the order in which these layers are arranged reflects a particular implementation of the described or illustrated example, and different relative positional relationships or orders in which these layers are arranged may exist. Furthermore, the example of a multilayer structure described or illustrated may not reflect all the layers present in a particular multilayer structure (e.g., one or more additional layers may exist between the two layers shown). As a particular example, when the first layer in a described or illustrated multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0022] Figure 1 A storage unit based on some embodiments of the disclosed technology is shown.

[0023] refer to Figure 1 The storage unit based on some embodiments of the disclosed technology may include a first variable resistor element 102, a second variable resistor element 104, a first transistor 112, and a second transistor 114.

[0024] Each of the first variable resistor element 102 and the second variable resistor element 104 can store different data values ​​by switching its resistance between different resistance states in response to an applied voltage or current. As an example, each of the first variable resistor element 102 and the second variable resistor element 104 can store data corresponding to a logic high state 1 by having a first resistance state (e.g., a low resistance state), or it can store data corresponding to a logic low state 0 by having a second resistance state (e.g., a high resistance state) that can be distinguished from the first resistance state.

[0025] Here, the first variable resistor element 102 may have two terminals, a first terminal A1 and a second terminal A2, and can be programmed or read through these two terminals. In some embodiments, the variable resistor element is "programmed" when data is written to it. That is, the first variable resistor element 102 can switch between different resistance states according to the voltage or current applied through the first terminal A1 and the second terminal A2. Here, different resistance states represent different data values, and the resistance states can be detected by circuitry capable of detecting voltage and / or current. The first variable resistor element 102 may have a single-layer or multi-layer structure, comprising various materials that can be used in RRAM, PRAM, FRAM, MRAM, etc., such as metal oxides (e.g., transition metal oxides or perovskite-based oxides), phase change materials (e.g., chalcogenide-based materials), ferromagnetic materials, ferroelectric materials, etc. In embodiments where the first variable resistor element 102 includes a ferroelectric material, the first variable resistor element 102 can be programmed using a spin-transfer torque (STT) method, and in this case, the first variable resistor element 102 includes an STT element. For example, Figures 2A to 2C Any one of the components shown can be used as the first variable resistor element 102.

[0026] Figure 2A Show Figure 1 An example of the first variable resistor element.

[0027] refer to Figure 2A The variable resistance element based on some embodiments of the disclosed technology may include a first electrode layer 211, a second electrode layer 215, and a variable resistance material layer 213 inserted between the first electrode layer 211 and the second electrode layer 215.

[0028] The first electrode layer 211 and the second electrode layer 215 can be respectively disposed at both ends of the variable resistive element (e.g., at its lower and upper ends), and can be used to transmit the voltage or current required for the operation of the variable resistive element. The first electrode layer 211 and / or the second electrode layer 215 can comprise various conductive materials, such as metals (e.g., platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), etc.), metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.) or combinations thereof. One of the first electrode layer 211 and the second electrode layer 215 can correspond to... Figure 1 The first terminal A1 of the first variable resistor element 102, and the other of the first electrode layer 211 and the second electrode layer 215 can correspond to Figure 1 The second terminal A2 of the first variable resistor element 102.

[0029] The variable resistance material layer 213 may include a metal oxide that can be used in RRAM, a phase change material that can be used in PRAM, or a ferroelectric material that can be used in FRAM. The variable resistance material layer 213 may have a single-layer structure or a multi-layer structure. In embodiments where the variable resistance material layer 213 includes a phase change material, the variable resistance material layer 213 can have different resistance states by switching between a crystalline phase and an amorphous phase. In embodiments where the variable resistance material layer 213 includes a metal oxide, the variable resistance material layer 213 can have different resistance states depending on whether a conductive path is formed in the metal oxide through metal ions or oxygen holes. In embodiments where the variable resistance material layer 213 includes a ferroelectric material, the variable resistance material layer 213 can have different resistance states depending on the polarization direction and / or polarization state of the ferroelectric material.

[0030] Figure 2B Show Figure 1 Another example of a first variable resistor element.

[0031] refer to Figure 2B The variable resistor element based on some embodiments of the disclosed technology may include: a first electrode layer 221; a second electrode layer 229; and a magnetic tunnel junction (MTJ) structure, which is inserted between the first electrode layer 221 and the second electrode layer 229 and includes a fixed layer 223, a tunnel barrier layer 225 and a free layer 227.

[0032] The fixing layer 223 may have a fixed magnetization direction. For example, in one embodiment, as indicated by the arrow in the fixing layer 223, the fixing layer 223 may have a specific magnetization direction parallel to the surface of the fixing layer 223 (e.g., in...). Figure 2B(From left to right in the middle). In another embodiment, the fixing layer 223 may have a magnetization direction opposite to the magnetization direction described above for the fixing layer 223 (e.g., in...). Figure 2B (From right to left in the middle). Free layer 227 can have a variable magnetization direction. For example, as indicated by the arrow in free layer 227, free layer 227 can have a magnetization direction parallel to the surface of free layer 227 (e.g., in...). Figure 2B (From left to right or right to left). The fixed layer 223 and the free layer 227 can have a single-layer or multi-layer structure, comprising various ferromagnetic materials such as Fe-Pt alloys, Fe-Pd alloys, Co-Pd alloys, Co-Pt alloys, Fe-Ni-Pt alloys, Co-Fe-Pt alloys, Co-Ni-Pt alloys, etc. A tunnel barrier layer 225 can be inserted between the fixed layer 223 and the free layer 227, and can allow electrons to tunnel through to change the magnetization direction of the free layer 227 when needed (e.g., during programming operations that change the resistance state of a variable resistor element). The tunnel barrier layer 225 can have a single-layer or multi-layer structure, comprising oxides such as MgO, CaO, SrO, TiO, VO, NbO, etc.

[0033] Here, the variable resistor element based on some embodiments of the disclosed technology can be an STT element. That is, the magnetization direction of the free layer 227 can be changed by a programming current I passing through the variable resistor element. Therefore, the magnetization direction of the free layer 227 can be parallel or antiparallel to the magnetization direction of the fixed layer 223. When the magnetization direction of the free layer 227 is parallel to the magnetization direction of the fixed layer 223, the variable resistor element can have a low resistance state. Conversely, when the magnetization direction of the free layer 227 is antiparallel to the magnetization direction of the fixed layer 223, the variable resistor element can have a high resistance state.

[0034] Figure 2C Show Figure 1 Another example of the first variable resistor element.

[0035] refer to Figure 2C The variable resistor element based on some embodiments of the disclosed technology may include: a first electrode layer 231; a second electrode layer 239; and a magnetic tunnel junction (MTJ) structure, which is inserted between the first electrode layer 231 and the second electrode layer 239 and includes a fixed layer 233, a tunnel barrier layer 235 and a free layer 237.

[0036] and Figure 2BSimilar to the variable resistor element, the variable resistor element in some embodiments based on the disclosed technology can also be an STT element. That is, the magnetization direction of the free layer 237 can be changed by a programming current I passing through the variable resistor element to be parallel to or antiparallel to the magnetization direction of the fixed layer 233. However, with Figure 2B The difference in the variable resistor element may be that, as indicated by the arrows in the fixed layer 233 and the free layer 237, the magnetization directions of the fixed layer 233 and the free layer 237 are perpendicular to the surfaces of the fixed layer 233 and the free layer 237. In one embodiment, the fixed layer 233 may have a specific magnetization direction perpendicular to the surfaces of the fixed layer 233 and the free layer 237 (e.g., Figure 2C (from bottom to top). In another embodiment, the fixing layer 233 may have a magnetization direction opposite to the magnetization direction described above (e.g., Figure 2C (From top to bottom in the middle). Free layer 237 can have a magnetization direction from top to bottom or from bottom to top.

[0037] Return to reference Figure 1 The first terminal A1 of the first variable resistor element 102 can be connected to the source line SL via the first transistor 112. That is, the first transistor 112 can control the electrical connection between the first variable resistor element 102 and the source line SL. The gate of the first transistor 112 can be connected to the first word line WL1 and can be turned on or off according to the voltage applied to the first word line WL1. The second terminal A2 of the first variable resistor element 102 can be connected to the bit line BL via the interconnect layer 120.

[0038] The second variable resistor element 104 may have three terminals: a first terminal B1, a second terminal B2, and a third terminal B3, and can be programmed by selecting two of the three terminals or read by selecting the other two. As an example, the second variable resistor element 104 may switch between different resistance states based on the voltage or current applied through the second terminal B2 and the third terminal B3, and its resistance state may be sensed based on the voltage or current applied through the first terminal B1 and the third terminal B3. As an example, the second variable resistor element 104 may include an element programmed using the spin orbital moment (SOT) method, i.e., an SOT element, in which a current carrying spin orbital moment (SOT) charge carriers is injected to flow through the MTJ to facilitate switching of the magnetization of the free layer of the MTJ. For example, Figure 3 The element shown can be used as a second variable resistor element 104.

[0039] Figure 3 Some embodiments based on the disclosed technology are shown. Figure 1An example of a second variable resistor element.

[0040] refer to Figure 3 The variable resistor element may include: a first electrode layer 311; a second electrode layer 312; a conductive layer 313 inserted between the first electrode layer 311 and the second electrode layer 312; a magnetic tunnel junction (MTJ) structure disposed on the conductive layer 313 and including a free layer 314, a tunnel barrier layer 315, and a fixed layer 316; and a third electrode layer 317 disposed on the magnetic tunnel junction (MTJ) structure. In some embodiments, the conductive layer 313 may be formed of a heavy metal or ferromagnetic oxide material, wherein a spin-orbit moment (SOT) is applied to the free layer 314 by a spin current generated by the spin Hall effect or the Lashpa effect to control (with) Figure 3 The magnetization of the free layer 314 in the MTJ (connected in a 3-terminal configuration shown) is provided by a conductive path through the MTJ between terminal 317 and one of terminals 311 and 312, where another spin-polarized current is provided to provide spin-transfer torque (STT) for magnetization of the free layer 314.

[0041] One of the first electrode layer 311 and the second electrode layer 312 can correspond to Figure 1 The second terminal B2 of the second variable resistor element 104, and the other of the first electrode layer 311 and the second electrode layer 312 can correspond to Figure 1 The third terminal B3 of the second variable resistor element 104. The conductive layer 313 can correspond to Figure 1 A portion of the connection layer 120, for example, the portion disposed between the second terminal B2 and the third terminal B3. The third electrode layer 317 may correspond to... Figure 1 The first terminal B1 of the second variable resistor element 104. The first electrode layer 311 and the second electrode layer 312 may be spaced apart from each other in a first direction (e.g., in the horizontal direction). The third electrode layer 317 may be disposed between the first electrode layer 311 and the second electrode layer 312 in the horizontal direction, and may be spaced apart from the first electrode layer 311 and the second electrode layer 312 in a second direction perpendicular to the first direction (e.g., in the vertical direction).

[0042] Conductive layer 313 can provide an interface capable of altering the magnetization direction of free layer 314 in a magnetic tunnel junction (MTJ) structure. As indicated by the dashed arrow in conductive layer 313, a programming current I can flow in conductive layer 313 in a direction parallel to the surface of conductive layer 313, and can induce a vertically aligned magnetization direction of free layer 314. That is, the variable resistor element based on some embodiments of the disclosed technology can be an SOT element. Due to the programming current I in the opposite direction, free layer 314 can have a magnetization direction in the opposite direction. For example, as indicated by the arrow in free layer 314, free layer 314 can have a bottom-up or top-down magnetization direction. For this purpose, the entire surface of free layer 314 facing conductive layer 313 can contact a portion of conductive layer 313. In one embodiment, conductive layer 313 can be located below free layer 314, and the entire lower surface of free layer 314 can contact a portion of the upper surface of conductive layer 313, but this disclosure is not limited thereto. In another embodiment, the top and bottom of the MTJ structure can be inverted so that a conductive layer can be disposed above the free layer, in which case the entire upper surface of the free layer can contact a portion of the lower surface of the conductive layer. A fixed layer 316 can be positioned facing the surface of the free layer 314, which is opposite to the surface of the contact conductive layer 313 of the free layer 314, with a tunnel barrier layer 315 interposed between them. The fixed layer 316 can have a perpendicular magnetization direction different from the magnetization direction of the free layer 314.

[0043] In one embodiment, the free layer 314 and the fixed layer 316 have a vertical magnetization direction. In another embodiment, a horizontal magnetization direction can be induced in the free layer 314 by a programming current I. That is, the free layer 314 can have a magnetization direction from left to right or from right to left. The fixed layer 316 can have a horizontal magnetization direction different from that of the free layer 314.

[0044] Return to reference Figure 1 The first terminal B1 of the second variable resistor element 104 can be connected to the source line SL via the second transistor 114. That is, the second transistor 114 can control the connection between the second variable resistor element 104 and the source line SL. The gate of the second transistor 114 can be connected to the second word line WL2 and can be turned on or off according to the voltage applied to the second word line WL2. The second terminal B2 and the third terminal B3 of the second variable resistor element 104 can be connected to the connection layer 120 and can be connected to the bit line BL via the connection layer 120. That is, the connection layer 120 can be connected to the second terminal B2 and the third terminal B3 of the second variable resistor element 104, and extends in the direction toward the first variable resistor element 102 to be connected to the second terminal A2 of the first variable resistor element 102.

[0045] As described above, because the memory cell includes a first variable resistor element 102 and a second variable resistor element 104 capable of storing 1 bit of data respectively, and two transistors (i.e., the first transistor 112 and the second transistor 114), it can be said that one transistor is provided for each bit. That is, a 1T memory cell can be implemented. Therefore, a memory device comprising multiple memory cells with high integration is possible.

[0046] Figure 4 and Figure 5 It shows the driver Figure 1 A diagram illustrating the method for storing memory units. Specifically, Figure 4 Show Figure 1 The current path when the first variable resistor element of the storage cell is driven. Figure 5 Show Figure 1 The current path when the second variable resistor element of the storage cell is driven.

[0047] refer to Figure 4 During a programming operation that stores data 0 or 1 in a first variable resistor element 102 connected in a two-terminal configuration, the first transistor 112 can be turned on, thereby generating a current path through the source line SL, the first transistor 112, the first variable resistor element 102, the interconnect layer 120, and the bit line BL (e.g., Figure 4 (See arrow ① in the diagram). The first variable resistor element 102 can be programmed by current flowing through the first terminal A1 and the second terminal A2. For example, in some embodiments, the current flowing through the MTJ via terminals A1 and A2 can be a spin-polarized current, which affects the magnetization direction of the free layer of the MTJ based on spin-transfer torque (STT). In this case, the direction of the current can determine whether the first variable resistor element 102 is programmed to 0 or 1 (i.e., whether 0 or 1 is written to the first variable resistor element 102). For such a programming operation, an appropriate programming voltage can be applied through the source line SL and the bit line BL. During this programming operation, the second transistor 114 can be turned off.

[0048] Furthermore, during a read operation for reading data stored in the first variable resistor element 102 of the two-terminal configuration, the first transistor 112 can be turned on, thereby generating a current path through the source line SL, the first transistor 112, the first variable resistor element 102, the interconnect layer 120, and the bit line BL (e.g., Figure 4(See arrow ② in the diagram). The data stored in the first variable resistor element 102 can be read by sensing the current flowing through the first terminal A1 and the second terminal A2 of the first variable resistor element 102. For this read operation, an appropriate read voltage can be applied through the source line SL and the bit line BL. The magnitude of this read voltage can be less than the programming voltage of the first variable resistor element 102. During this read operation, the second transistor 114 can be turned off.

[0049] refer to Figure 5 During programming operations that store data 0 or 1 in a second variable resistor element 104 connected in a 3-terminal configuration, the first transistor 112 can be turned on, thereby generating a current path through the source line SL, the first transistor 112, the first variable resistor element 102, the interconnect layer 120, and the bit line BL (e.g., Figure 4 (See arrow ③ in the diagram). The second variable resistor element 104 can be programmed by current flowing through the second terminal B2 and the third terminal B3. The current in the conductive layer 313, parallel to the layers of the MTJ, is a spin current generated by the spin Hall effect or Lashpa effect, and applies a spin-orbit moment (SOT) to the free layer 314 to manipulate the magnetization of the free layer 314. In this case, the direction of the current determines whether the second variable resistor element 104 is programmed to 0 or 1 (i.e., whether 0 or 1 is written to the second variable resistor element 104). For such a programming operation, an appropriate programming voltage can be applied through the source line SL and the bit line BL. The programming voltage of the second variable resistor element 104 can be the same as or different from the programming voltage of the first variable resistor element 102. During this programming operation, the second transistor 114 can be turned off.

[0050] On the other hand, during a read operation that reads the data stored in the second variable resistor element 104, the second transistor 114 can be turned on, thereby generating a current path through the source line SL, the second transistor 114, the second variable resistor element 104, the interconnect layer 120, and the bit line BL (e.g., Figure 4 (See arrow ④ in the image). Data of the second variable resistor element 104 can be read by sensing the current flowing through the first terminal B1 and the third terminal B3. For this read operation, an appropriate read voltage can be applied through the source line SL and the bit line BL. The magnitude of the read voltage can be less than the magnitude of the programming voltage of the second variable resistor element 104. Furthermore, the read voltage of the second variable resistor element 104 can be the same as or different from the read voltage of the first variable resistor element 102. During this read operation, the first transistor 112 can be turned off.

[0051] In the case of the second variable resistor element 104, the current path ③ during the programming operation and the current path ④ during the reading operation can be different. In this case, each of the programming and reading operations can be optimized independently, and the stress on the second variable resistor element 104 during the programming operation can be reduced or prevented, thereby improving the reliability of the second variable resistor element 104. Furthermore, because the second variable resistor element 104 can be programmed using a low operating current, a low-power storage cell can be realized.

[0052] refer to Figure 4 and Figure 5 The current path ① during the programming operation of the first variable resistor element 102, the current path ② during the reading operation of the first variable resistor element 102, and the current path ③ during the programming operation of the second variable resistor element 104 can be the same. In this case, mutual interference may occur, affecting the second variable resistor element 104 during the programming and reading operations of the first variable resistor element 102, or affecting the first variable resistor element 102 during the programming operation of the second variable resistor element 104. To reduce or prevent such mutual interference, the following reference can be performed. Figures 6A to 6C The described operation.

[0053] Figure 6A It is shown Figure 1 The flowchart shows the programming operation of the first variable resistor element of the storage cell.

[0054] In one embodiment, the magnitude of the first programming current flowing through the first variable resistor element 102 during programming operation of the first variable resistor element 102 may be greater than the magnitude of the second programming current flowing through the second terminals B2 and B3 of the second variable resistor element 104 during programming operation of the second variable resistor element 104. In this case, when the resistance state of the first variable resistor element 102 is not changed during programming operation of the second variable resistor element 104, the resistance state of the second variable resistor element 104 may be undesirably changed during programming operation of the first variable resistor element 102. In some embodiments, the disclosed technique may be implemented to perform... Figure 6A The operation described above minimizes unwanted changes in resistance state.

[0055] refer to Figure 6A Before programming the first variable resistor element 102, a read operation can be performed on the second variable resistor element 104 (S601). Therefore, the data stored in the second variable resistor element 104 can be verified.

[0056] Next, a programming operation can be performed on the first variable resistor element 102 (S602). As described above, when the first variable resistor element 102 is programmed, the second variable resistor element 104 may be undesirably affected, and therefore an undesirable change in the resistance state of the second variable resistor element 104 may occur.

[0057] Next, a reprogramming operation (S603) can be performed on the second variable resistor element 104. The reprogramming operation can refer to the operation of re-storing or rewriting the data of the second variable resistor element 104 checked at S601. Therefore, the effect exerted on the second variable resistor element 104 at S602 can be eliminated. However, if the data of the second variable resistor element 104 checked in step S601 was not changed at S602, then the operation at S603 does not need to be performed and can therefore be omitted.

[0058] Figure 6B It is shown Figure 1 The flowchart shows the read operation of the first variable resistor element of the storage cell.

[0059] In one embodiment, the magnitude of the first read current flowing through the first variable resistor element 102 during a read operation of the first variable resistor element 102 may be greater than the magnitude of the second programming current flowing through the second terminals B2 and B3 of the second variable resistor element 104 during a programming operation of the second variable resistor element 104. In this case, when the resistance state of the first variable resistor element 102 does not change during the programming operation of the second variable resistor element 104, the resistance state of the second variable resistor element 104 may be undesirably changed during the read operation of the first variable resistor element 102. To prevent this, the following can be performed: Figure 6B The operations described in [the document].

[0060] refer to Figure 6B Before the read operation of the first variable resistor element 102, a read operation can be performed on the second variable resistor element 104 (S604). Therefore, the data stored in the second variable resistor element 104 can be verified.

[0061] Next, a read operation can be performed on the first variable resistor element 102 (S605). As described above, when the data stored in the first variable resistor element 102 is read out, the second variable resistor element 104 may be undesirably affected, such that the resistance state of the second variable resistor element 104 is changed.

[0062] Next, a reprogramming operation (S606) can be performed on the second variable resistor element 104. The reprogramming operation refers to the operation of re-storing the data of the second variable resistor element 104 examined in step S604. Therefore, the effect applied to the second variable resistor element 104 in step S605 can be eliminated. However, if the data of the second variable resistor element 104 examined in step S604 was not changed at S605, then the operation at S606 does not need to be performed and can be omitted.

[0063] Figure 6C It is shown Figure 1 The flowchart shows the programming operation of the second variable resistor element of the storage cell.

[0064] In one embodiment, the magnitude of the second programming current flowing through the second terminal B2 and the third terminal B3 of the second variable resistor element 104 during programming operation of the second variable resistor element 104 may be greater than the magnitude of the first programming current flowing through the first variable resistor element 102 during programming operation of the first variable resistor element 102. In this case, when the resistance state of the second variable resistor element 104 is not changed during programming operation of the first variable resistor element 102, the resistance state of the first variable resistor element 102 may be undesirably changed during programming operation of the second variable resistor element 104. In some embodiments, the disclosed technique may be implemented to perform... Figure 6C The operation described above minimizes unwanted changes in resistance state.

[0065] refer to Figure 6C Before programming the second variable resistor element 104, a read operation can be performed on the first variable resistor element 102 (S607). Therefore, the data stored in the first variable resistor element 102 can be verified.

[0066] Next, a programming operation can be performed on the second variable resistor element 104 (S608). As described above, when the second variable resistor element 104 is programmed, the first variable resistor element 102 may be undesirably affected, causing a change in the resistance state of the first variable resistor element 102.

[0067] Next, a reprogramming operation (S609) can be performed on the first variable resistor element 102. The reprogramming operation can refer to the operation of re-storing or rewriting the data of the first variable resistor element 102 examined in step S607. Therefore, the effect applied to the first variable resistor element 102 in step S608 can be eliminated. However, if the data of the first variable resistor element 102 examined at S607 was not changed at S608, then the operation at S609 does not need to be performed and can be omitted.

[0068] Figure 7 This is a perspective view illustrating some embodiments of a storage device based on the disclosed technology. Figure 8 Is with Figure 7 The corresponding cross-sectional view in the first direction.

[0069] refer to Figure 7 and Figure 8 The memory device based on some embodiments of the disclosed technology may include: a first transistor TR1 and a second transistor TR2 formed in a substrate 500; a first variable resistor element 520, one end of which is electrically connected to one end of the first transistor TR1; a second variable resistor element 540, one end of which is electrically connected to one end of the second transistor TR2; a source line SL that electrically connects the other end of the first transistor TR1 to the other end of the second transistor TR2; a connection layer 550 that is electrically connected to the other end of the first variable resistor element 520 and in contact with the other end of the second variable resistor element 540; and a bit line BL that is electrically connected to the connection layer 550.

[0070] The substrate 500 may include various semiconductor materials, such as silicon. Junction regions 515, 516, and 517 of the first transistor TR1 and the second transistor TR2 may be formed in the substrate 500. Junction regions 515, 516, and 517 may be formed by doping the substrate 500 with impurities.

[0071] A first gate electrode 512 and a second gate electrode 514 may be formed on a substrate 500. The first gate electrode 512 and the second gate electrode 514 may be spaced apart from each other in a first direction and extend in a second direction. The first gate electrode 512 may form a first word line WL1, and the second gate electrode 514 may form a second word line WL2. A first gate insulating layer 511 may be inserted between the first gate electrode 512 and the substrate 500, and a second gate insulating layer 513 may be inserted between the second gate electrode 514 and the substrate 500.

[0072] Two junction regions 515 and 516 can be respectively disposed on both sides of the first gate electrode 512. The first gate electrode 512, the first gate insulating layer 511, and the two junction regions 515 and 516 on both sides of the first gate electrode 512 can form a first transistor TR1. Two junction regions 516 and 517 can be respectively disposed on both sides of the second gate electrode 514. The second gate electrode 514, the second gate insulating layer 513, and the two junction regions 516 and 517 on both sides of the second gate electrode 514 can form a second transistor TR2. The junction region 516 between the first gate electrode 512 and the second gate electrode 514 can be shared by the first transistor TR1 and the second transistor TR2. In the following text, junction region 515 will be referred to as the drain region of the first transistor TR1, junction region 517 will be referred to as the drain region of the second transistor TR2, and junction region 516 will be referred to as the common source region of the first transistor TR1 and the second transistor TR2.

[0073] A first interlayer insulating layer ILD1 having a thickness covering the first gate electrode 512 and the second gate electrode 514 can be formed on the substrate 500.

[0074] The source line SL can be formed on the first interlayer insulating layer ILD1. The source line SL can extend in a first direction and can be connected to the common source region 516 through a first contact plug C1 that penetrates the first interlayer insulating layer ILD1.

[0075] A second interlayer insulating layer ILD2, having a thickness covering the source line SL, can be formed on top of the first interlayer insulating layer ILD1.

[0076] The first variable resistor element 520 can be formed on the second interlayer insulating layer ILD2. The first variable resistor element 520 can be connected to the drain region 515 of the first transistor TR1 through the second contact plug C2 that penetrates the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2.

[0077] Furthermore, a second variable resistor element 540 can be formed on the second interlayer insulating layer ILD2. The second variable resistor element 540 can be connected to the drain region 517 of the second transistor TR2 via a conductive pattern 530 and a third contact plug C3 penetrating the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2. The conductive pattern 530 can be used to adjust the horizontal position of the second variable resistor element 540. For example, to facilitate the formation of a connection layer 550 connecting the second variable resistor element 540 and the first variable resistor element 520, the conductive pattern 530 can have a line shape extending in the direction from the third contact plug C3 to the first variable resistor element 520, and the second variable resistor element 540 can be disposed at the end of the conductive pattern 530. Therefore, the first variable resistor element 520 can overlap with the second contact plug C2, while the second variable resistor element 540 can not overlap with the third contact plug C3. The conductive pattern 530 can be omitted, in which case the second variable resistor element 540 can overlap with and directly contact the third contact plug C3.

[0078] The third interlayer insulating layer ILD3 can be formed on top of the second interlayer insulating layer ILD2. The third interlayer insulating layer ILD3 can have a thickness that covers the upper surface of the first variable resistor element 520 and exposes the upper surface of the second variable resistor element 540.

[0079] The connection layer 550 can be formed on the third interlayer insulating layer ILD3. The connection layer 550 can be connected to the upper surface of the first variable resistor element 520 through a fourth contact plug C4 that penetrates the third interlayer insulating layer ILD3. In addition, the connection layer 550 can contact the entire upper surface of the second variable resistor element 540 exposed by the third interlayer insulating layer ILD3.

[0080] A fourth interlayer insulating layer ILD4 with a thickness covering the bonding layer 550 can be formed on top of the third interlayer insulating layer ILD3.

[0081] Bit line BL can be formed on the fourth interlayer insulating layer ILD4. Bit line BL can extend in the first direction and can be connected to the connection layer 550 through a fifth contact plug C5 that penetrates the fourth interlayer insulating layer ILD4.

[0082] In this embodiment, each of the first contact plugs C1 to the fifth contact plugs C5 is shown as having a single-pillar shape, but this disclosure is not limited thereto. In another embodiment, each of the first contact plugs C1 to the fifth contact plugs C5 may be formed by a combination of multiple conductive patterns. Each of the multiple conductive patterns may have a pillar shape or a plate shape having an area larger than that of a pillar shape and a height lower than that of a pillar shape.

[0083] Furthermore, in this embodiment, the first variable resistance element 520 is shown as being disposed above the second interlayer insulating layer ILD2, but this disclosure is not limited thereto. In another embodiment, the first variable resistance element 520 can be disposed at various heights, assuming it is set above the upper surface of the substrate 500 and below the lower surface of the interconnect layer 550. If the first variable resistance element 520 can be driven by two terminals, then the upper surface of the first variable resistance element 520 can directly contact the lower surface of the interconnect layer 550. In this case, the fourth contact plug C4 can be omitted. On the other hand, because the upper surface of the first variable resistance element 520 is in direct contact with the interconnect layer 550, the first variable resistance element 520 can be disposed directly below the interconnect layer 550.

[0084] In some embodiments of the above-described memory device, the first variable resistor element 520 and the second variable resistor element 540 can be driven by the first transistor TR1 and the second transistor TR2, and no additional lines are required besides the source line SL and bit line BL, the first word line WL1 and the second word line WL2. Therefore, a highly integrated memory device can be obtained.

[0085] While this patent document contains numerous specific details, it should not be construed as limiting the scope of any invention or claim, but rather as a description of features that may be specifically used in particular embodiments of a particular invention. Certain features described in the context of separate embodiments in this patent document may be implemented in combination in a single embodiment. Conversely, multiple features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, while multiple features may have been described above in a particular combination and even initially claimed, one or more features from the claimed combination may be removed from the combination in some cases, and the claimed combination may involve sub-combinations or variations thereof.

[0086] Similarly, although multiple operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown, or sequentially, or requiring the performance of all shown operations to obtain the desired result. Furthermore, the separation of multiple system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0087] Only a few embodiments and examples have been described. Improvements, variations, and other embodiments can be made to the disclosed embodiments based on what is described and shown in this patent document.

Claims

1. A semiconductor memory, comprising: The first variable resistor element includes a first terminal and a second terminal; The second variable resistor element includes a first terminal, a second terminal, and a third terminal; A first transistor controls the electrical connection between a first wire and the first terminal of the first variable resistor element; The second transistor controls the electrical connection between the first wire and the first terminal of the second variable resistor element; A connection layer is configured to electrically connect the second terminal of the first variable resistor element to the second terminal and the third terminal of the second variable resistor element; as well as The third conductor is electrically connected to the connection layer. Specifically, data is written to or read from the first variable resistor element by the current flowing through the first and second terminals of the first variable resistor element, and Specifically, the data is written to the second variable resistor element by the current flowing through the second terminal and the third terminal of the second variable resistor element, and the data is read out by the current flowing through the first terminal and the third terminal of the second variable resistor element.

2. The semiconductor memory according to claim 1, wherein, The first transistor is turned on and the second transistor is turned off to: write data to the first variable resistor element; read data from the first variable resistor element; or write data to the second variable resistor element, and In this configuration, the first transistor is turned off and the second transistor is turned on to read data from the second variable resistor element.

3. The semiconductor memory according to claim 1, wherein, Data is written to the first variable resistor element via a first current path, the data is read from the first variable resistor element via a second current path, and the data is written to the second variable resistor element via a third current path, wherein the first current path, the second current path, and the third current path are identical to each other. The data is read from the second variable resistor element via a fourth current path, and the fourth current path is different from the first current path to the third current path.

4. The semiconductor memory according to claim 3, wherein, Each of the first current path to the third current path flows through the first conductor, the first transistor, the first variable resistor element, the connection layer, and the third conductor. The fourth current path flows through the first conductor, the second transistor, the second variable resistor element, the connection layer, and the third conductor.

5. The semiconductor memory according to claim 1, wherein, A first programming current flows through the first and second terminals of the first variable resistor element to write data to the first variable resistor element, and a second programming current flows through the second and third terminals of the second variable resistor element to write data to the second variable resistor element, wherein the magnitude of the first programming current is greater than the magnitude of the second programming current. Specifically, a read operation is performed on the second variable resistor element to read data from the second variable resistor element before writing data to the first variable resistor element, and Specifically, after writing data to the first variable resistor element, a reprogramming operation is performed on the second variable resistor element to write data to the second variable resistor element.

6. The semiconductor memory according to claim 1, wherein, A read current flows through the first and second terminals of the first variable resistor element to read data from the first variable resistor element, and a programming current flows through the second and third terminals of the second variable resistor element to write data to the second variable resistor element, wherein the magnitude of the read current is greater than the magnitude of the programming current. Specifically, a read operation of the second variable resistor element is performed before data is read from the first variable resistor element to read data from the second variable resistor element, and Specifically, after reading data from the first variable resistor element, a reprogramming operation is performed on the second variable resistor element to write data to the second variable resistor element.

7. The semiconductor memory according to claim 1, wherein, A first programming current flows through the first and second terminals of the first variable resistor element to write data to the first variable resistor element, and a second programming current flows through the second and third terminals of the second variable resistor element to write data to the second variable resistor element, wherein the amplitude of the first programming current is smaller than the amplitude of the second programming current. Specifically, a read operation of the first variable resistor element is performed before writing data to the second variable resistor element to read data from the first variable resistor element, and Specifically, after writing data to the second variable resistor element, a reprogramming operation is performed on the first variable resistor element to write data to the first variable resistor element.

8. The semiconductor memory according to claim 1, wherein, The first variable resistor element includes a metal oxide, a phase change material, a ferroelectric material, or a spin-transition torque (STT) element, and The second variable resistance element includes a spin-orbit momentum (SOT) element.

9. A semiconductor memory, comprising: A first transistor, which includes a first gate electrode disposed on a substrate; The second transistor includes a second gate electrode disposed on the substrate; A first variable resistor element is disposed on the substrate and electrically connected to the first terminal of the first transistor; A second variable resistor element is disposed on the substrate and electrically connected to the first terminal of the second transistor; A source line is disposed on the substrate and is electrically connected to the second terminal of the first transistor and the second terminal of the second transistor. A connecting layer is disposed above the first variable resistor element and the second variable resistor element, and is electrically connected to the first variable resistor element and in contact with the entire upper surface of the second variable resistor element; Bit lines are disposed on the connection layer and electrically connected to the connection layer; A first contact plug is configured to connect the source line to a second terminal of the first transistor and a second terminal of the second transistor; The second contact plug is configured to connect the first variable resistor element to the first terminal of the first transistor; A third contact plug is configured to connect the second variable resistor element to the first terminal of the second transistor; as well as The fifth contact plug is configured to connect the bit line to the connection layer.

10. The semiconductor memory according to claim 9, further comprising: A fourth contact plug is disposed between the first variable resistor element and the connection layer and connects the first variable resistor element to the connection layer.

11. The semiconductor memory according to claim 9, wherein, The first transistor includes a first junction region and a second junction region formed on both sides of the first gate electrode in the substrate. The second transistor includes a second junction region and a third junction region formed on both sides of the second gate electrode in the substrate, and a third junction region therein. The second junction region is shared by the first transistor and the second transistor.

12. The semiconductor memory according to claim 11, wherein, The first contact plug is connected to the second junction region. Wherein, the second contact plug is connected to the first junction region, and The third contact plug is connected to the third junction region.

13. The semiconductor memory according to claim 9, further comprising: A conductive pattern is inserted between the third contact plug and the second variable resistor element.

14. The semiconductor memory according to claim 13, wherein, The conductive pattern is connected to the third contact plug and extends in the direction toward the first variable resistor element.

15. The semiconductor memory according to claim 13, wherein, The first variable resistor element is disposed at a position overlapping with the second contact plug, and The second variable resistor element is positioned on the conductive pattern at a location that does not overlap with the third contact plug.

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