Lightweight high-speed random number generation encryption method and device

Abstract

The application belongs to the technical field of information security, and specifically provides a kind of lightweight high-speed random number generation encryption method and device, wherein the method comprises: standard random number device generates random number array, main memory reads in random number array data, processor accepts request instruction, and reads updated main memory data according to preset rule;User configures high-speed encryption device as encryption mode or random number generation mode according to actual demand, and transmits corresponding mode instruction to processor, and processor transmits mode instruction to high-speed encryption device;Parameter key storage unit and seed register determine corresponding update rule according to mode instruction, encryption controller controls adder to carry out overall operation process, and expansion encryption module registers and encrypts update for each operation result data.The scheme can improve the problem that the efficiency of random number generator and encryption device, the quality of random number and the consumption of resources are difficult to balance, and reduce the consumption of area resources.

Description

Technical Field

[0001] This invention relates to the field of information security technology, and more specifically, to a lightweight, high-speed random number generation encryption method and apparatus. Background Technology

[0002] In recent years, with the rapid development of the information age, information security issues have become increasingly prominent. Ensuring the security of information systems has become a concern for the entire society. Among these applications, generated random number sequences are widely used in secure communication fields such as information encryption, electronic transactions, and network transmission.

[0003] Commonly used random number generators are divided into true random number generators (also called physical random number generators) and pseudo random number generators. True random number generators are limited by the bandwidth of the physical entropy source, and their current speed is still in the Mb / s range, which cannot meet the high throughput requirements of applications such as video encryption and military image encryption. Currently, there are three common types of true random number generators: high-frequency / low-frequency sampling, chaotic dynamics, and thermal noise. High-frequency / low-frequency sampling uses low-frequency data to sample high-frequency data; the quality of its random number generation is related to the frequency of the high-frequency clock, resulting in low throughput and requiring a long time to obtain a certain number of random numbers. The quality of random number generation based on chaotic dynamics is directly related to the complexity of the chaotic dynamics algorithm and the quantization algorithm; generating a large number of random numbers leads to high algorithm resource consumption and long algorithm cycle times. True random number generators based on thermal noise are closely related to ambient temperature, and their random number throughput and mathematical statistical effects are unstable. It is evident that true random number generators often use a single random physical process as the reference random source and generate random bit sequences at a single rate with high power consumption.

[0004] Currently, common pseudo-random number generators include linear congruent generators, linear feedback shift registers, DES, and AES. Pseudo-random number generators are simple to construct and generate numbers quickly. The criteria for evaluating pseudo-random number generators are periodicity, balance, and correlation. Linear congruent generators are simple in structure and fast in generation, but they exhibit regularity in the encryption process, making them easily crackable through mathematical and statistical analysis. The quality of random numbers generated by linear feedback shift registers is related to the complexity of the linear feedback combinational logic; each cycle generates 1 bit of data, resulting in limited throughput. DES has a simple structure and high operating efficiency, but its short key makes it vulnerable to brute-force attacks. AES offers better confidentiality, but its area and clock resource consumption increases accordingly. Therefore, the periodicity and predictability of pseudo-random numbers make it difficult for pseudo-random number generators to ensure the security of encrypted information.

[0005] In summary, current random number generators have the following drawbacks:

[0006] Random number generators currently have relatively low speeds, with the highest reaching only 6.78Gbps, which cannot meet the requirements of high-speed systems or high-speed encryption. Most pseudo-random number generators produce random number sequences with obvious periodic variations, making them difficult to apply effectively in encryption processes.

[0007] For example, the published patent CN110795063A, "A Physical Random Number Generation Method with Adjustable Power Consumption and Rate," includes an entropy source module, an entropy sampling module, and a clock signal. The entropy source module consists of M ring oscillators, with each node simultaneously acting as a signal output. By adjusting the operating voltage of the digital logic circuit, the node outputs exhibit both periodic and chaotic signals. The entropy sampling module uses D flip-flops to quantize and sample the output signals from each ring oscillator, generating a random bit sequence. The random bit sequence generates a periodic signal when the digital logic circuit is under low voltage and a chaotic signal when it is under high voltage. This scheme combines chaotic circuitry with oscillation sampling, controlling the rate and power consumption of the physical random number generator by adjusting the voltage. However, this scheme exhibits an unbalanced characteristic in terms of sequence complexity, random number rate, and resource consumption of the random number generator. Typically, random number generators with high throughput and high random number sequence complexity require large area resources, making them unsuitable for low-power chips with high area requirements. Summary of the Invention

[0008] This invention addresses the technical problems of low speed and high power consumption in existing random number generators.

[0009] This invention provides a lightweight, high-speed random number generation and encryption method, comprising:

[0010] The standard random number generator generates a random number array and sends a transmission request command. The main memory receives the request command and reads the random number array data. The processor receives the request command and reads the updated main memory data according to preset rules.

[0011] Users configure the high-speed encryption device to encryption mode or random number generation mode according to their actual needs, and pass the corresponding mode instructions to the processor, which then passes the mode instructions to the high-speed encryption device.

[0012] The parameter key storage unit and seed register determine the corresponding update rules according to the mode instructions. The encryption controller controls the adder to perform the overall operation process. The extended encryption module stores and encrypts the result data of each operation.

[0013] The present invention also provides a lightweight high-speed random number generation encryption, comprising: a standard encryption device for generating a random number array, wherein the random number array is a true random number array or a strong pseudo-random number array;

[0014] The acquisition device, including a main memory and a main processor, is used to determine the corresponding reading rules according to the requirements and send a random number array and a mode selection signal to the high-speed encryption device.

[0015] A high-speed encryption device includes an encryption configuration module, an encryption controller, an adder (ADD), a parameter configuration module, a counting control module, and an extended encryption module; it is used to encrypt corresponding key data or generate corresponding random number arrays based on a mode selection signal and a random number array.

[0016] The present invention also provides an electronic device, including a memory and a processor, wherein the processor is used to implement a lightweight high-speed random number generation encryption method when executing a computer management program stored in the memory.

[0017] Beneficial Effects: This invention provides a lightweight, high-speed random number generation and encryption method and apparatus. The method includes: a standard random number generator generating a random number array and sending a transmission request instruction; the main memory receiving the request instruction and reading the random number array data; the processor receiving the request instruction and reading the updated main memory data according to preset rules; the user configuring the high-speed encryption device to encryption mode or random number generation mode according to actual needs and transmitting the corresponding mode instruction to the processor; the processor transmitting the mode instruction to the high-speed encryption device; the parameter key storage unit and seed register determining the corresponding update rules according to the mode instruction; the encryption controller controlling the adder to perform the overall calculation process; and the extended encryption module storing and encrypting the result data of each calculation and updating it.

[0018] This solution enables high-speed data encryption, addressing the current challenge of balancing efficiency, random number quality, and resource consumption in random number generators and encryption devices. Furthermore, by configuring the shift-and-XOR method of the generated random number sequence via the processor, and by extensively reusing hardware logic resources, it reduces area resource consumption. This invention can be used for random number key generation or for secondary encryption of highly secure random number generation devices to enhance data security and increase data generation speed. Attached Figure Description

[0019] Figure 1 A flowchart of a lightweight, high-speed random number generation and encryption method provided by the present invention;

[0020] Figure 2 A schematic diagram of the hardware structure of a possible electronic device provided by the present invention;

[0021] Figure 3 A schematic diagram of the hardware structure of a possible computer-readable storage medium provided by the present invention;

[0022] Figure 4aThe original image provided by this invention;

[0023] Figure 4b The present invention provides the use of random number pairs Figure 4a An image obtained through encryption;

[0024] Figure 4c The present invention provides a method for using pseudo-random number pairs Figure 4b The image obtained by decryption;

[0025] Figure 5 The present invention provides a principle block diagram of a lightweight, high-speed random number generation and encryption method. Detailed Implementation

[0026] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0027] Example 1

[0028] refer to Figure 1 The present invention provides a lightweight, high-speed random number generation and encryption method, comprising:

[0029] The standard random number generator generates a random number array and sends a transmission request command. The main memory receives the request command and reads the random number array data. The processor receives the request command and reads the updated main memory data according to preset rules.

[0030] Users configure the high-speed encryption device to encryption mode or random number generation mode according to their actual needs, and pass the corresponding mode instructions to the processor, which then passes the mode instructions to the high-speed encryption device.

[0031] The parameter key storage unit and seed register determine the corresponding update rules according to the mode instructions. The encryption controller controls the adder to perform the overall operation process. The extended encryption module stores and encrypts the result data of each operation.

[0032] In a specific implementation scenario, the following steps are included:

[0033] In step S100, the processor sends a request command, and the user simultaneously sends the encryption mode selection and the initial seed through the processor. The specific principle is as follows:

[0034] This device can be used as a random number generator. The user selects the random number generation mode of this device and provides the initial seed. The data processed by the random number generator is extended and shifted through eight channels, and the output is affected by the output register several times to determine the output state.

[0035] Furthermore, the random number generation effect of this device is related to the configuration parameters of the parameter key storage unit. It is understandable that the configuration parameters of the parameter key storage unit are calculated multiple times, and the final generated random value is affected by the parameter key storage unit.

[0036] The parameter key storage unit in this device introduces true random values. Specifically, it is implemented by sampling lengthy combinational logic through a high-frequency clock. It can be understood that the random numbers output by the combinational logic of this device exhibit better mathematical and statistical characteristics as the number of loops increases, and can be regarded as random numbers.

[0037] A high-frequency clock samples the random values ​​of lengthy logic. Due to the uncertain level transition time, it exhibits an uncertain sampling time characteristic. The least significant bit of the counter is used as interference value to update the parameter key. The resulting encrypted data exhibits the characteristics of truly random numbers, and this characteristic shows better mathematical and statistical properties with the increase of the number of iterations. It is understandable that the random number period obtained in this way is close to infinity, and it is compatible with the characteristics of pseudo-random number generators generating random numbers at a high rate and true random number generators outputting unpredictable random numbers.

[0038] This device can also be used as an encryption device. Specifically, the user selects the device mode as encryption mode, provides the encryption parameter key, and the remaining modules are shared with the random number generator. To avoid logical complexity, these details will not be elaborated further.

[0039] In this mode, users can choose whether to configure a parameter key. If no parameter key is configured, it will be automatically configured by the processor. In user-configured parameter key mode, users can update the parameter key in real time for better encryption. Essentially, users can store the parameter key and use it to decrypt data later, achieving both encryption and decryption. This two-key encryption / decryption method offers enhanced security.

[0040] It should be noted that this device is not limited to the current functions of the two modes of random number generator and encryption device. Accordingly, users can use it as an encryption device in random number generator mode, and users can also use it as a random number generator device in encryption mode.

[0041] In step S200, after receiving the processor request instruction, the seed storage unit judges the processor configuration selection signal. If it is a self-configuration parameter mode, the seed storage unit is updated to the preset value. If a seed key is provided, the seed register is updated to the corresponding seed key.

[0042] The key storage unit is selected based on the processor configuration signal, specifically:

[0043] In encrypted mode, the parameter key storage unit reads and updates the parameter data sent by the processor and configured by the user.

[0044] In the random number generation mode, the parameter key storage unit reads and updates the preset parameter data.

[0045] The computation process uses adder logic, which is reused multiple times. Considering the large data throughput, a design approach that uses Wallace trees and adders in parallel can be adopted, which will be explained in detail in the subsequent device section. Specific operations include:

[0046] The adder first reads data from the second seed register, data from the fifth seed register, and a portion of the parameter key storage unit, and performs an addition operation to obtain the result of the first addition operation. The second seed register stores the data from the first two operations, and the fifth seed register stores the data from the first five operations. It can be understood that storing and using the data from the first two and first five operations can be considered as superimposing and encrypting interference terms, and the periodicity of the encrypted random number sequence is also correspondingly increased.

[0047] The adder is used as a subtractor for the second time. The adder reads the data from the second seed register and the second parameter key storage unit, takes the two's complement data, and performs the addition operation to obtain the result of the second addition operation.

[0048] The adder operation module is used for the third modulo operation. The adder operation module reads the result of the first addition operation and the data of the second parameter key storage unit, takes the complement code, and performs the addition operation to obtain the result of the third addition operation.

[0049] The adder evaluates the result of the third addition operation. If the result is negative, it selects the result of the first addition operation. If the result is positive, the adder performs a fourth addition operation. This fourth addition operation is used for modulo operation. Specifically, the adder reads the result of the third addition operation and the data from the second parameter key storage unit, takes the two's complement, and performs the addition operation to obtain the result of the fourth addition operation.

[0050] Whether the adder performs a fifth addition operation is determined by the most significant bit of the fourth addition operation result and the borrow signal, and so on.

[0051] It's important to note that the length of encrypted data is positively correlated with the chip manufacturing process; that is, the better the chip process, the more clock speed it supports, and the greater the supported data length and throughput. Taking 128-bit encrypted data as an example, using a TSMC 28nm chip with a 250MHz clock frequency, a combinational logic circuit with automatic synthesis can be directly used. However, if a less advanced chip process with a faster clock frequency is used, direct adder synthesis may result in timing violations. In such cases, the adder can be designed as follows: Use a Wallace tree adder, decomposing the 129-bit adder into four parts: 0-35, 36-68, 69-99, and 100-129, to mitigate timing violations. Specifically, the addition operations from 0 to 35, 36 to 68, 69 to 99, and 100 to 129 are performed in parallel. Using 36 bits of data, the result of additions from 36 to 68 is selected. If the 36th bit is 0, the sum of additions from 69 to 99 is directly selected. If the 36th bit is 0, the sum of additions from 69 to 99 is added with a carry. Using 69 bits of data, the result of additions from 69 to 99 is selected. If the 69th bit is 0, the sum of additions from 69 to 99 is directly selected. If the 69th bit is 0, the sum of additions from 69 to 99 is added with a carry. Using 100 bits of data, the result of additions from 100 to 129 is selected. If the 100th bit is 0, the sum of additions from 100 to 129 is directly selected. If the 100th bit is 0, the sum of additions from 100 to 129 is added with a carry. This design minimizes hardware area to the greatest extent possible without timing violations.

[0052] In step S300, the processor configures the shift rules for the extended encryption module, while the other groups are configured with shift rules in an incremental manner. Specifically, if the processor receives an encryption request, it configures it to a fixed value. After obtaining the output data, it selects the rated position of the data as the number of bits to shift, and the shift rules for the other data paths are incremental relationships of that data.

[0053] Optionally, in one feasible method provided by the embodiments of the present invention, since the encrypted object is an image constructed by 256×256 gray values, the encryption process of the encrypted object is as follows: obtain the gray value matrix corresponding to the encrypted object, wherein the gray value matrix corresponds to the aforementioned 256×256 gray values; use the generated pseudo-random number to encrypt the gray value matrix, thereby completing the encryption of the encrypted object.

[0054] Optionally, in one feasible approach, after the device encrypts and generates random number data, the computer encrypts the aforementioned grayscale matrix using a key. It is easy to understand that the process of generating the key using pseudo-random numbers is something that can be configured according to the actual situation.

[0055] To better illustrate the beneficial effects of the encryption method provided in the embodiments of the present invention, please refer to... Figure 4a , Figure 4b and Figure 4c The images shown are, respectively, the image before encryption, the image after encryption, and the image after decryption, provided in the embodiments of the present invention. It is not difficult to understand that... Figure 4b To employ the encryption method of this embodiment of the invention, after generating a random number, the random number is used to... Figure 4a The image obtained through encryption. Figure 4c To utilize pseudo-random number pairs Figure 4b The image obtained after decryption shows that the grayscale value distribution is good, indicating a good encryption effect.

[0056] The specific encryption method of the extended encryption module is as follows:

[0057] The extended encryption module obtains the result of the first addition operation in step S200, performs a configured shift operation, and updates the shift register group data. It then obtains the result of the second addition operation in step S200, performs a configured shift operation, and XORs it with the shift register group data, updating the shift register group data. Similarly, it obtains the result of the third addition operation in step S200, performs a configured shift operation, and XORs it with the shift register group data, updating the shift register group data. If the adder continues to be used, the extended encryption module continues updating according to the above rules.

[0058] Users can choose between random number generator mode and data encryption mode based on their configuration settings.

[0059] Preferably, when the configuration mode is random number generation mode, the parameter scrambling sampling module uses a high-frequency clock for sampling calculation, and the specific steps are as follows:

[0060] The parameter scrambling sampling module obtains the result of the first addition operation in step S200. Under high-frequency data, the timing register group performs timing reading operation on the specified bit of the result of the first addition operation. The data level period is obtained by XORing the last two registers. The clock counter performs timing under high-frequency data and selects the least significant bit as the interference value. The interference storage unit stores the interference value data.

[0061] The parameter scrambling sampling module obtains the result of the second addition operation in step S200. Under high-frequency data, the timing register group performs timing reading operation on the specified bit of the result of the second addition operation. The data level period is obtained by XORing the last two registers. The clock counter performs timing under high-frequency data and selects the least significant bit as the interference value. The interference storage unit stores the interference value data.

[0062] The parameter scrambling sampling module obtains the result of the third addition operation in step S200. Under high-frequency data, the timing register group performs a timing reading operation on the specified bit of the result of the first addition operation. The data level period is obtained by XORing the last two registers. The clock counter performs timing under high-frequency data and selects the least significant bit as the interference value. The interference storage unit stores the interference value data.

[0063] The parameter scrambling sampling module judges the result of the third addition operation in step S200. If there is a borrow, sampling stops. If there is no borrow, the processing method for subsequent addition operation results is still the same as described above.

[0064] Understandably, the parameter scrambling and sampling module indicates the end of the operation when it receives the borrow signal of the addition result. The parameter key storage unit then updates its value to the scrambling storage unit value.

[0065] It should be noted that when using this high-frequency sampling method, the sampling level data is defined according to the actual situation, and this device can sample using different sampling levels.

[0066] Furthermore, it should be noted that when updating the parameter key storage unit value in this way, the data and sampling logic of the scrambling storage unit are defined according to the actual situation. Correspondingly, the scrambling storage unit data can also be further encrypted before updating the parameter key storage unit value.

[0067] Preferably, when the configuration mode is encryption device mode, the scrambling module is selected to continue running, and the parameter configuration unit does not select the result of the scrambling module to reduce the selection logic. After receiving the borrow signal of the addition operation result in S200, the parameter configuration unit reads the encrypted parameter value configured by the user.

[0068] It should be noted that steps S300 and S200 are performed in parallel and do not consume additional clock resources.

[0069] In step S400, the seed register is updated to the addition result of step S200. Specifically, the value is the addend of the addition result that generates the borrow signal and the result of the previous addition operation. The seed register is then shifted.

[0070] It should be noted that users can select the length of the random numbers generated by this device according to their actual needs. It is understandable that if the number of loops is large enough, the parameter key storage unit and seed register data will conform more closely to mathematical and statistical characteristics, and the corresponding randomness and encryption effect will be better.

[0071] Finally, timing analysis was performed. The circuit's clock frequency is 250MHz, and the bandwidth for generating random numbers ranges from 32Gbps to 48Gbps. This can meet most requirements, such as image and video encryption. Taking high-bandwidth video as an example: 6Mbps for FHD and 32Mbps for UHD, it can also meet the Gbps speed requirements for enterprise or higher military applications, far exceeding the speed achievable by existing pseudo-random number algorithms.

[0072] The true random perturbation obtained through high and low frequency sampling enables the random numbers generated in this invention to have unpredictable characteristics. It is understood that this device generates random number sequences and encrypts them multiple times by updating the parameter key storage unit of the device with the true random number perturbation. Compared with previous true random number generators, both the speed and random number quality are significantly improved. Furthermore, this invention proposes a novel algorithm and solution. In the hardware implementation process, the multiple logic reuse of this invention's device can save a significant amount of area resources, enabling the device to have excellent PPA characteristics when used in chips. Taking SMIC's 40nm process as an example, the area of ​​this device is 11905.641768 square micrometers, demonstrating the excellent PPA characteristics of this invention.

[0073] Example 2

[0074] refer to Figure 5 This invention provides a lightweight, high-speed random number generation and encryption device, comprising:

[0075] Standard encryption device for generating random number arrays, which can be either true random number arrays or strong pseudo-random number arrays;

[0076] The acquisition device, including a main memory and a main processor, is used to determine the corresponding reading rules according to the requirements and send a random number array and a mode selection signal to the high-speed encryption device.

[0077] A high-speed encryption device includes an encryption configuration module, an encryption controller, an adder (ADD), a parameter configuration module, a counting control module, and an extended encryption module; it is used to encrypt corresponding key data or generate corresponding random number arrays based on a mode selection signal and a random number array.

[0078] The standard encryption device, i.e., the random number array generation unit, comprises hyperchaotic systems L1 and L2, which are iterated using the RK4 iterative algorithm. The specific equations are shown below:

[0079] Four-dimensional hyperchaotic system L1:

[0080]

[0081]

[0082]

[0083]

[0084] In this chaotic system, a = 10, b = 8 / 3, c = 28; when r = (-1.52, -0.06), there will be two positive Lyapunov exponents, i.e., hyperchaos occurs.

[0085] Four-dimensional hyperchaotic system L2:

[0086]

[0087]

[0088]

[0089]

[0090] When a = 50, b = 24, c = 13, f = 8, g = 33, h = 30, and b = 10-28, there are two positive Lyapunovs, which means that hyperchaos occurs.

[0091]

[0092] k1=f(x i ,y i )

[0093]

[0094]

[0095] k4=f(x i +h,y i +k3h)

[0096] [1] The L1 system inputs x, y, z, w, and parameters a, b, c, r; the L2 system inputs x, y, z, w, and parameters a, c, d, f. The initial seed input is defined and enters the matrix x[2,8] in the order from left to right and from top to bottom, where x[1,:] is the parameter and initial seed of the hyperchaotic L1 system, and x[2,:] is the parameter and initial seed of the hyperchaotic L2 system.

[0097] [2] Update the perturbation values ​​of the matrix system parameters, x[2,2] is updated to x[2,2]+x[1,2] / 20, x[1,4]=-1+x[1,1] / 100. By controlling the parameter range, the L1 and L2 systems are maintained as hyperchaotic systems and the parameters are constantly changing.

[0098] [3] The L2 chaotic system generates output through the RK4 algorithm, and the output is stored in matrix x[2,1:4]. Matrix x is updated.

[0099] [4] The x-value of matrix is ​​updated as follows

[0100] x[2,1]=x[2,1]+x[1,1] / 2024,

[0101] x[2,2]=x[2,2]+x[1,3] / 2024,

[0102] x[2,3]=x[2,3]+x[1,2] / 2024,

[0103] x[2,4]=x[2,4]+x[1,1] / 2024.

[0104] [5] Determine the value of x[2,1:4]. x[2,1:4] should not be greater than the values ​​500, 500, 1500, and 2000. Otherwise, take the modulo of x[2,1:4] according to the values ​​500, 500, 1500, and 2000 respectively.

[0105] [6] The L1 chaotic system generates output through the RK4 algorithm, and the output is stored in matrix x[1,1:4]. Matrix x is updated.

[0106] [7] The x-value of matrix is ​​updated as follows

[0107] x[1,1]=x[1,1]+x[2,1] / 100000,

[0108] x[1,2]=x[1,2]+x[2,2] / 100000,

[0109] x[1,3]=x[1,3]+mod(x[2,2]*2^24,256) / 100000,

[0110] x[1,4]=x[1,4]+x2 / 16

[0111] [8]x[1,1],x[1,2],x[1,3],x[1,4],x[2,1],x[2,2],x[2,3],x[2,4] values ​​are updated to store the decimal part of the numerical value.

[0112] [9] Scramble the combination, define the y = zeros[2,4] matrix, and extract as many parameters as possible to complicate the random effect.

[0113] y[1,1]=x[2,1]+x[2,2]+x[1,1];

[0114] y[1,2]=x[2,2]+x[2,4]+x[1,2];

[0115] y[1,3]=x[2,3]+x[2,4]+x[1,2];

[0116] y[1,4]=x[2,4]+x[1,1]+x[1,4];

[0117] y[2,1]=x[2,1]+x[1,1]+x[1,2];

[0118] y[2,2]=x[2,2]+x[1,2]+x[1,3];

[0119] y[2,3]=x[2,3]+x[1,3]+x[1,4];

[0120] y[2,4]=x[2,1]+x[2,3]+x[2,4];

[0121]

[10] Equilibrium variables, define variables x1 and x2, x1 = abs(x[2,1])*4+abs(x[2,2])*4+abs(x[2,3])*2+abs(x[1,1]) / 2+abs(x[1,2])+abs(x[1,3]) / 4+abs(x[1,4]) / 4, x2 is the decimal part of x1.

[0122]

[11] The iteration count is grouped into four. The y matrix is ​​stored in the z[16,2] matrix. The sampling matrix is ​​quantized. The z[i,j] is multiplied by 2^24 and modulo 256. The z[i,j] is then updated. The z[i,j] value is converted to binary and stored in the w1[8,16] and w2[8,16] matrices from left to right and from top to bottom.

[0123]

[12] The data in the first row of w1 is updated by XORing the data of w1[6,:] with w2[3,:] and w2[8,:] from left to right.

[0124] The data in the second row of w1 is updated by XORing the data of w1[7,:] with w2[4,:] and w2[5,:] from left to right.

[0125] The data in the third row of w1 is updated by XORing the data of w1[8,:] with w2[1,:] and w2[6,:] from left to right.

[0126] The data in the fourth row of w1 is updated by XORing the data of w1[5,:] with w2[2,:] and w2[7,:] from left to right.

[0127] The data in the fifth row of w1 is updated by XORing the data of w1[4,:] with w2[2,:] and w2[7,:] from left to right.

[0128] The data in the sixth row of w1 is updated by XORing the data of w1[1,1] with w2[8,:] and w2[3,:] from left to right.

[0129] The data in the seventh row of w1 is updated by XORing the data of w1[2,:] with w2[4,:] and w2[5,:] from left to right.

[0130] The data in the eighth row of w1 is updated by XORing the data of w1[3,:] with w2[1,:] and w2[6,:] from left to right.

[0131] The data in the first row of w2 is updated by XORing the data of w1[1,:] with w1[5,:] and w2[5,:] from left to right.

[0132] The data in the second row of w2 is updated by XORing the data of w1[2,:] with w1[6,:] and w2[6,:] from left to right.

[0133] The data in the third row of w2 is updated by XORing the data of w1[3,:] with w1[7,:] and w2[7,:] from left to right.

[0134] The data in the fourth row of w2 is updated by XORing the data of w1[4,:] with w1[8,:] and w2[8,:] from left to right.

[0135] The data in the fifth row of w2 is updated by XORing the data of w1[5,:] with w1[6,:], w2[1,:], and w2[2:] from left to right.

[0136] The data in the sixth row of w2 is updated by XORing the data of w1[1,:] with w1[2,:], w1[3,:], and w1[4,:] from left to right.

[0137] The data in the seventh row of w2 is updated by XORing the data of w1[1,:] with w1[4,:], w1[5,:], and w1[8,:] from left to right.

[0138] The data in the eighth row of w2 is updated by XORing the data of w1[7,:] with w1[8,:], w2[3,:], and w2[4,:] from left to right.

[0139]

[13] Output the 256-bit data in w1 and w2 in order from left to right and from top to bottom.

[0140] It should be noted that this random number array has been tested extensively by the inventors and can achieve excellent randomness. It can be implemented using computer-readable storage media or software. Alternatively, it can be used to construct chaotic systems L1 and L2 using analog circuits. It is understood that constructing L1 and L2 systems using analog circuits allows for the generation of standard random number arrays through amplification of minute thermal noise disturbances between resistors using this device.

[0141] It should also be noted that the standard random number generation device in this embodiment is not limited to this method, and other methods can also be used to generate random number arrays. The above method is merely a reference example for understanding purposes.

[0142] The processor CPU includes main memory RAM. The main memory RAM reads and updates the random number array in the random number array generation unit RNG_DEVICE. The processor CPU sends the configuration mode mode_cfg, the data valid signal data_vld, the extended encryption mode srt_cfg, and the random number array input data_in signal to the random number encryption device RNG_MOUDLE according to the preset rules.

[0143] The CONFIG encryption configuration module configures the random number generator mode, encryption mode, and extended encryption methods. Based on the number of encryption attempts and the processor's CPU configuration mode (mode_cfg) signal, the CONFIG module configures the corresponding encryption and reading methods.

[0144] The encryption controller CONTROL module includes a parameter key storage unit, a seed register, and a state machine controller. This module performs encryption operations by instantiating the adder ADD.

[0145] This state machine controller is divided into two parts: an initial state machine and a cyclic state machine, to maximize bandwidth. The initial state machine is responsible for configuring the encryption method for the first set of data and configuring the parameters of the key storage unit and seed register. It's understandable that when the first set of seed data enters, the seed register has no output data, and the corresponding key storage unit has no relevant data. The initial state machine is set up to improve encryption efficiency.

[0146] The specific operating modes of the state machine controller are as follows:

[0147] Initial state machine:

[0148] When the random number array generation unit RNG_DEVICE is in the state of RNG_IDLE: idle state, it enters the RNG_READY: data preparation state of the random number array generation unit RNG_DEVICE when data_vld=1.

[0149] RNG_READY: Data preparation. Determine the CPU configuration mode (mode_cfg) and assign values ​​to the parameter key storage unit. If in encryption mode, the CPU transmits 128*4 bits of data_in in parallel, and the parameter key storage unit and seed register read the corresponding data according to preset rules. If in random number generator mode, the CPU transmits 128*4 bits of data_in in parallel, storing the high-order bits and setting the low-order bits to 0. The seed register is truncated, and the parameter key storage unit reads the data as follows:

[0150] First parameter key storage

[0151] b=130'h2_0087_d542_6fe0_5dab_9ed5_398d_e20d_efdf,

[0152] param_c1=128'h6ba6_781c_c698_2a17_2442_d7b0_fb0e_4e32,

[0153] param_c2=128'h5ab2_8c5f_01fe_38de_e4d7_283d_5e40_1de1,

[0154] param_c3=128'h12f2_8c5f_01fe_38de_e4d7_283d_5e40_1de1.

[0155] Assign data_in to the seed register.

[0156] Reg_n, Reg_n_1, Reg_n_2, Reg_n_3, Reg_n_4. If it is an encryption mode, the first parameter key storage unit Reg_b = b, Reg_n_a = param_c3. If it is a parameter configurable mode, Reg_b and Reg_n_a are key values.

[0157] RNG_ADD: Instantiation call to adder for computation

[0158] {2'b00,Reg_n_1[127:0]}+{2'b00,Reg_n_4[127:0]}+{2b'00,Reg_n_a[127:0]}. And assign Reg_b to Reg_add_b_pre in the adder ADD.

[0159] Set Reg_add_c_pre to 0. Based on the mode selection, the sampling register performs high-frequency sampling to update parameters for combinational logic addition.

[0160] RNG_ADD_SECOND: count_mux increments by one, while the adder is reused to perform subtraction, calculating Reg_c + Reg_b, and storing the data in Reg_c. The data in Reg_c_pre is then shifted and XORed with Reg_out_b to Reg_out_i and updated in Reg_out_b to Reg_out_i.

[0161] RNG_REG_C: Determine if Reg_c_

[129] = 0. When Reg_c

[129] = 0 and count_mux = 3'b001, Reg_n_a = param_c2, and re-enter the RNG_ADD_SECOND state. When Reg_c

[129] = 1 and count_mux = 1'b001, Reg_n_a = param_c1. When count_mux = 3'b111 or rng_rst = 1'b1 or the status signal RNG_CIR_is_mux_a is high, count_mux = 3'b0.

[0162] RNG_END: ​​State end signal. Pull the RNG_is_End signal high to enter the next state machine cycle.

[0163] Cyclic state machine:

[0164] RNG_CIR_IDLE: Initial state, which remains in the RNG_CIR_IDLE state during the first state machine operation.

[0165] RNG_CIR_MUX_A:(~p_rst&&RNG_is_END)||empty=0,

[0166] Enter the RNG_CIR_MUX_A state. Pull the RNG_cir_is_mux_a signal high to perform data selection.

[0167] If data_vld is 1, then the data_in is selected and sequentially enters Reg_n to Reg_n_4, and the next state machine jumps to the RNG_CIR_IDLE state;

[0168] If data_vld is 0, the combinational logic data to be output, rng_out_pre, is selected and sequentially entered into Reg_n to Reg_n_4. The CPU configuration mode, mode_cfg, is determined. If mode_cfg = 1, the parameter key storage unit data is updated to the processor configuration data; if mode_cfg = 0, the parameter key storage unit data is updated to the parameter configuration module perturbation register data.

[0169] RNG_CIR_REG_N: Waits for assignments to Reg_n~Reg_n_4, selects Reg_n_1, pads it with 2'b00 bits (big-endian), and assigns it to reg_add_a_pre.

[0170] The big-endian padding 2'b00 of Reg_n_4 is assigned to reg_add_b_pre, and the big-endian padding 2'b00 of reg_n_a is assigned to reg_add_c_pre.

[0171] RNG_CIR_ADD:reg_add_a_pre is assigned to reg_add_a,

[0172] reg_add_b_pre is assigned to reg_add_b, and reg_add_c_pre is assigned to reg_add_c.

[0173] Simultaneously, RNG_out_b to Rng_out_i are XORed with Reg_c for the last time, the rng_out_ready signal is pulled high, and RNG_out_a to RNG_out_i are output. The counter starts counting, and when the counter counts to counter_full, the counter is set to 0, and the p_rst signal is output.

[0174] The counting controller makes a control selection. When the set value is not reached, it chooses to update the parameter key automatically. The data of Reg_out_b to Reg_out_i are sent to Reg_n_a and Reg_b after selection, XOR and truncation operations. The specific logic is to calculate out_b^out_c^out_d^out_e, select out_f to out_i values ​​through (out_b^out_c^out_d^out_e)[128:127], XOR the above results again, and store the result in the first parameter key storage unit Reg_n_a.

[0175] Calculate out_f^out_g^out_h^out_i,

[0176] The values ​​of out_b to out_e are selected by (out_f^out_g^out_h^out_i)[128:127]. The results are then encrypted using combinational logic and stored in the second parameter key storage unit Reg_b, thus updating the parameters. When the count controller set value is reached, the CPU reads the random number array from the main memory RAM to update the data in the parameter key storage unit.

[0177] RNG_CIR_PREPARE: Determines p_rst. If p_rst = 1, the next state machine jumps to RNG_CIR_IDLE; if p_rst = 0, the next state machine jumps to...

[0178] RNG_CIR_ADD_SECOND, instantiate and call the adder to perform calculations.

[0179] {2'b00,Reg_n_1[127:0]}+{2'b00,Reg_n-4[127:0]}+{2b'00,Reg_n_a[127:0]}. RNG_out_b~RNG_out_i stores the addition results.

[0180] Assign the value reg_add_b_pre to Reg_b, and set reg_add_c_pre to 0.

[0181] RNG_CIR_ADD_SECOND: reg_c is assigned the value reg_add_a_pre, reg_add_a, reg_add_b, and reg_add_c are updated, and the adder is reused for calculation.

[0182] The reg_c_pre value is shifted and XORed with RNG_out_b to RNG_out_i, and the result is stored in RNG_out_b to RNG_out_i, thus updating the data.

[0183] RNG_CIR_REG_C: Determine reg_c_pre

[129] . If reg_c

[129] = 1 or p_rst = 1, the next state machine jumps to RNG_CIR_IDLE.

[0184] When Reg_c

[129] = 0 and count_mux = 3'b001, Reg_n_a = param_c2.

[0185] Re-enter RNG_CIR_ADD_SECOND.

[0186] When the RNG_ADD_SECOND state is Reg_c

[129] =1 and count_mux=1'b001, Reg_n_a=param_c1.

[0187] count_mux = 3'b111 or rng_rst = 1'b1

[0188] Alternatively, the status signal RNG_CIR_is_mux_a is high, and count_mux = 3'b0.

[0189] Calculate out_b^out_c^out_d^out_e,

[0190] The values ​​of out_f to out_i are selected by (out_b^out_c^out_d^out_e)[128:127], and then XORed with the above results again. The result is stored in the parameter key storage unit Reg_n_a.

[0191] Calculate out_f^out_g^out_h^out_i,

[0192] The values ​​of out_b to out_e are selected by (out_f^out_g^out_h^out_i)[128:127]. The results are then encrypted using combinational logic. The results are XORed with the parameter key storage unit Reg_b to update the register value.

[0193] The adder ADD is multiplexed into an adder, subtractor, and modulo operator. The module is a three-input adder, which is transformed into a two-input adder through Wallace tree processing to reduce combinational logic resources. In addition, multiple adders are used for parallel processing to prevent timing violations caused by excessively high clock frequencies. For specific methods, refer to the adder module in Example 1.

[0194] The parameter configuration module PARAM_MUX includes a high-frequency sampling unit and a parameter key register unit. The high-frequency sampling unit includes a high-frequency clock and forty sets of three-level registers and a counter group. The three-level register group samples the high-order bits of the adder_c data. The clock counter counts under the high-frequency clock, using the XOR value of the second-level register and the third-level register as the stop signal for the clock counter. The least significant bit of the clock counter is read, and the perturbation register is updated from least to most significant bit. The adder is multiplexed three times; this means that each time the adder is multiplexed, the perturbation register is updated from least to most significant bit. Three multiplexings allow the perturbation register group to update 120 bits of data. The high-order bits can be preprocessed by the processor, and the bandwidth of the high-order bits can be set according to the device's operating principle.

[0195] The counting control module CNT_RST is responsible for controlling the device's shutdown. The processor sets the cnt_full parameter. When it receives the signal_vld signal, the loop counter increments by 1. When the cnt_full parameter is reached, the local reset p_rst signal is pulled high and sent to the state machine controller for reset. When the counter is non-zero, an empty signal is sent to the state machine controller, facilitating the transition from the initial state machine to the loop state machine.

[0196] The extended encryption module SRT_EE is controlled via state machine signals and a register controller. When the state machine is in the state of RNG_CIR_ADD_SECOND or RNG_ADD_SECOND, the control register state_muxa toggles to 1.

[0197] (cir_state==RNG_CIR_ADD_SECOND||fir_state==RNG_ADD_SECOND)&~state_muxa situation,

[0198] (cir_state==RNG_CIR_REG_C||fir_state==RNG_REG_C)&~state_muxa situation,

[0199] (cir_state==RNG_CIR_ADD_SECOND||fir_state==RNG_ADD_SECOND)&state_muxa situation,

[0200] When cir_state == RNG_CIR_ADD, the reg_c data is read sequentially and entered into the encryption section. The encryption section has eight encryption methods. The shift register shift method is configured by the encryption configuration module CONFIG. Specifically, the CPU reads the low-order data of the random number array in the main memory RAM, sends it to the selector logic for selection to obtain the shift data, and sends the shift data to the encryption configuration module CONFIG. CONFIG configures the shift method of the extended encryption module SRT_EE through instantiation.

[0201] The parameter configuration module PARAM_MUX includes a high-frequency sampling and encryption selection section. Specifically, the clock counter samples the adder combinational logic result adder_c under a high-frequency clock. The perturbation register reads the high-frequency clock data for updating. If the configuration mode signal mode_cfg = 0, the parameter key storage unit value is updated with the perturbation register data. If mode_cfg = 1, the counter controller selects to read the random number key from the processor CPU main memory RAM or the SRT_EE data from the extended encryption module to update the parameter key storage unit data. It is understandable that the main memory random number data update is relatively slow; this method ensures that the parameter key storage unit data is updated with each encryption, enhancing the data encryption quality.

[0202] Please see Figure 2 This is a schematic diagram illustrating an embodiment of the electronic device provided in this invention. For example... Figure 2 As shown, an embodiment of the present invention provides an electronic device, including a memory 1310, a processor 1320, and a computer program 1311 stored in the memory 1310 and executable on the processor 1320. When the processor 1320 executes the computer program 1311, it implements the steps of a lightweight high-speed random number generation and encryption method.

[0203] Please see Figure 3 This is a schematic diagram illustrating an embodiment of a computer-readable storage medium provided by the present invention. (See diagram below.) Figure 3 As shown, this embodiment provides a computer-readable storage medium 1400, on which a computer program 1411 is stored. When the computer program 1411 is executed by a processor, it implements the steps of a lightweight high-speed random number generation encryption method.

[0204] The present invention has at least the following beneficial effects:

[0205] Firstly, this invention uses a configuration register for mode selection, allowing the main processor to choose between encryption and random number generation modes, thus reusing logic resources and supporting multi-mode processing for different application scenarios. This device supports both encryption and random number generation modes. In encryption mode, a parameter key is provided and stored through processor configuration. Users can perform encryption and decryption operations based on this parameter key. By configuring the parameter key and having it held by the user, the security of this device is enhanced.

[0206] Secondly, this device fully considers encryption efficiency. Through the design of the first state machine and the cyclic state machine, the device can generate a stable random number array without waiting, even with the first seed key. The size of the parameter data is controlled by pre-computation, thereby controlling the bandwidth of the generated random number data. During the update of the parameter key storage unit, the low-order data is updated through pre-computation. The encryption of the low-order data affects the value of the high-order data, thus enhancing the randomness of the generated random number array. The bandwidth for generating random numbers is maintained within the range of 32Gbps-42Gbps by configuring the high-order data. The parameter key storage unit is configurable, achieving the design goal of autonomously controllable output bandwidth.

[0207] Thirdly, the parameter key storage unit is encrypted through multi-level encryption, the adder is reused for adder, adder and modulo operation, and the logic resources of the digital expansion encryption module are reused, saving the logic resources required by this device.

[0208] Fourthly, during the adder's operation, the redundancy of the adder's combinational logic and the uncertainty between logic gates are utilized to perform high-frequency sampling of the high-order data of the adder to update the parameter key storage unit data. This introduces interference into the pseudo-random operation process to achieve true random number generation. The advantage is that this device utilizes a high-speed, lightweight structure to generate high-bandwidth random number data. During the device's operation, the uncertainty of the high-order data of the adder's redundant logic is used for high-frequency sampling. This gives the device the characteristics of high operational efficiency, small logic resources, and high bandwidth for generating random numbers, while also being compatible with the unpredictable nature of data generated by true random number generators.

[0209] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0210] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A lightweight, high-speed random number generation and encryption method, characterized in that, include: The standard random number generator generates a random number array and sends a transmission request command. The main memory receives the request command and reads the random number array data. The processor receives the request command and reads the updated main memory data according to preset rules. Users configure the high-speed encryption device to encryption mode or random number generation mode according to their actual needs, and pass the corresponding mode instructions to the processor, which then passes the mode instructions to the high-speed encryption device. The parameter key storage unit and seed register determine the corresponding update rules according to the mode instructions. The encryption controller controls the adder to perform the overall operation process. The extended encryption module stores and encrypts the result data of each operation and updates it. The extended encryption module is configured by the processor to perform shift operations on the calculation result data and perform an XOR operation with the data in the shift register group to update the data in the shift register group.

2. The lightweight high-speed random number generation and encryption method according to claim 1, characterized in that, The standard random number generator uses high and low frequency sampling, chaotic dynamics, or thermal noise principles to generate a standard true random number array, and the main memory reads the corresponding stored data to update it.

3. The lightweight high-speed random number generation and encryption method according to claim 1, characterized in that, When the processor sends a mode instruction for encryption mode, the processor reads the random number array from the main memory to update the seed register and parameter key storage unit of the high-speed encryption device; The seed register and parameter key storage unit are updated to a random number array; Meanwhile, the counter controller updates the data in the parameter key storage unit with a random number array at regular intervals, and updates the data in the parameter key storage unit with combinational logic encryption using the data from the extended encryption module at other times. When the processor sends a mode instruction for random number generation mode, the processor reads data from the main memory to update the seed register of the high-speed encryption device. The high-frequency sampling unit samples the high-order data level of the result data of each combinational logic operation under a high-frequency clock. The clock counter group in the high-frequency sampling unit counts the duration of the level, and the count data is stored in the seed register. At the end of each operation, the parameter key storage unit data is updated to the seed register data.

4. The lightweight high-speed random number generation and encryption method according to claim 3, characterized in that, The register unit includes a parameter key storage unit and a seed register, wherein the seed register includes a first seed register, a second seed register, a third seed register, a fourth seed register, and a fifth seed register, and the parameter key storage unit includes a first parameter key storage unit and a second parameter key storage unit; When processing the first set of encrypted data, the data in the first to fifth seed registers are all updated to the same set of data. The first parameter key storage unit needs to specify the encryption parameters. When processing subsequent encrypted data, the first to fifth seed registers store the results of the previous few operations. The data in the first parameter key storage unit is updated by selection logic during the previous operation.

5. The lightweight high-speed random number generation and encryption method according to claim 4, characterized in that, The first parameter key storage unit includes a selector, a first encryption parameter, and a second encryption parameter. When an encryption request is received, the first encryption parameter and the second encryption parameter will update the values ​​of the random number array in the main memory. The selector will select between the first encryption parameter and the second encryption parameter. When an encryption request is received, the selector will select the first encryption parameter. When the adder is multiplexed to perform the third operation, the first encryption parameter key storage unit will select the corresponding encryption parameter according to the high-order bit signal.

6. The lightweight high-speed random number generation and encryption method according to claim 5, characterized in that: When the main processor sends an encryption request and selects an encryption mode, the first seed register, the second seed register, the third seed register, the fourth seed register, and the fifth seed register are updated to the same random number array in the main memory. The value of the first parameter key storage unit is updated according to a preset method, and the value of the second parameter key storage unit is updated to a random number array at a different address in the main memory. When the main processor sends an encryption request and selects a random number generation mode, the first seed register, the second seed register, the third seed register, the fourth seed register, and the fifth seed register are updated to the same random number array in the main memory. The first parameter key storage unit is updated according to a preset method, and the second parameter key storage unit is updated to the original parameter value.

7. The lightweight high-speed random number generation and encryption method according to claim 6, characterized in that, The first parameter key storage unit includes a selector, a first encryption parameter, and a second encryption parameter. The first and second encryption parameters are automatically updated to a random number array in the main memory when an encryption request is received. The selector selects from the first and second encryption parameters. When an encryption request is received, the selector selects the first encryption parameter. After the data is subjected to addition combinational logic operation, multiple high-frequency sampling modules perform high-frequency sampling and timing on the selected high-order addition result. The counter counts the duration period and selects the least significant bit of the clock counter as the disturbance source to update the data in the first, second, and second parameter key storage units.

8. The lightweight high-speed random number generation and encryption method according to claim 1, characterized in that, The generation of the first set of random number array data is controlled by an initial state machine, and the generation of subsequent random number array data is controlled by a loop state machine. Two state machines are set up to control the overall device for different situations, one for the first group of encrypted data and the other for subsequent encrypted data. Specifically, the data in the first seed register to the fifth seed register of the first group of encrypted data is updated to the same set of data, and the encryption parameters need to be specified in the first parameter key storage unit. When processing subsequent encrypted data, the first seed register to the fifth seed register stores the predetermined results of the previous few operations, and the data in the first parameter key storage unit is updated by selection logic during the previous operation.

9. A lightweight, high-speed random number generation and encryption device, characterized in that, include: Standard encryption device for generating random number arrays, which can be either true random number arrays or strong pseudo-random number arrays; The acquisition device, including a main memory and a main processor, is used to determine the corresponding reading rules according to the requirements and send a random number array and a mode selection signal to the high-speed encryption device. A high-speed encryption device includes an encryption configuration module, an encryption controller, an adder (ADD), a parameter configuration module, a counting control module, and an extended encryption module; used to encrypt corresponding key data or generate corresponding random number arrays based on a mode selection signal and a random number array. The extended encryption module is configured by the processor to perform shift operations on the calculation result data and perform an XOR operation with the data in the shift register group to update the data in the shift register group.

10. An electronic device, characterized in that, It includes a memory and a processor, wherein the processor is used to implement the steps of the lightweight high-speed random number generation and encryption method as described in any one of claims 1-8 when executing a computer management program stored in the memory.

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