Audio processing circuit, method, chip and electronic device
By working together with the caching module and the audio signal processing module, the problem of insufficient computing power in portable electronic devices is solved, enabling low-cost and low-power processing of complex sound effects and protection algorithms, thus improving system efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI AWINIC TECH CO LTD
- Filing Date
- 2023-01-10
- Publication Date
- 2026-06-12
Smart Images
Figure CN116089081B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, specifically to an audio processing circuit, method, chip, and electronic device. Background Technology
[0002] For portable electronic devices such as mobile phones and wearable products on low-end platforms, low-end main control CPUs (central processing units) are usually used, which cannot support rich audio effect processing algorithms and speaker protection algorithms. Therefore, digital audio power amplifiers need to have certain audio effect processing capabilities and built-in protection algorithms, which places high demands on the hardware computing power of the power amplifier.
[0003] Furthermore, the aforementioned portable electronic devices are highly sensitive to the cost and power consumption of digital power amplifiers. Based on power consumption and cost considerations, the built-in processors are usually low-power and low-cost on-chip processors. Such processors are difficult to meet the computing power requirements of complex sound effect algorithms and protection algorithms. Summary of the Invention
[0004] In view of this, this application provides an audio processing circuit, method, chip, and electronic device to solve the problem that the processors of portable electronic devices are difficult to meet the computing power requirements of complex sound effect algorithms and protection algorithms.
[0005] This application provides an audio processing circuit including a cache module, a main processor, and at least one audio signal processing module, wherein the cache module and the main processor are respectively connected to each of the audio signal processing modules via a system bus;
[0006] The caching module is used to cache the input audio signal, provide the input audio signal to the main processor, and cache the output audio signal;
[0007] The main processor is used to perform a first signal processing on the input audio signal to obtain an intermediate audio signal, write the intermediate audio signal into the memory of the audio signal processing module, read the output audio signal generated by the audio signal processing module from the memory of the audio signal processing module, and write the output audio signal into the buffer module; the first signal processing is used to characterize the set audio signal processing process;
[0008] The audio signal processing module is used to perform a second signal processing on the intermediate audio signal to obtain the output audio signal; the second signal processing is used to characterize other audio processing processes besides the first signal processing.
[0009] Optionally, the caching module includes a first caching unit, a second caching unit, and a flag generator; the first caching unit and the second caching unit are used to cache the input audio signal or the output audio signal in turn; the flag generator is used to identify the storage address of the input audio signal, and when the address of the input audio signal switches to the starting address of the next caching unit, a processing flag is sent, and the processing flag is used to instruct the main processor to process the input audio signal cached by the first caching unit or the second caching unit.
[0010] Optionally, the caching module further includes a first arbiter and a second arbiter; the first arbiter is used to arbitrate the order in which audio signals are written to the first cache unit or the second cache unit; the second arbiter is used to arbitrate the order in which corresponding audio signals are read from the first cache unit or the second cache unit.
[0011] Optionally, the audio processing circuit further includes an interrupt generator; the first input terminal of the interrupt generator is connected to the flag output terminal of the buffer module, the second input terminal is used to receive the input audio signal, the third input terminal is connected to the main processor via a bus, and the output terminal is used to connect to the main processor; the main processor is in sleep mode before performing the first signal processing; the interrupt generator is used to generate an interrupt signal according to the input audio signal and the processing flag, and receive a clear instruction fed back by the main processor after completing the corresponding first signal processing, clearing the interrupt signal, and the interrupt signal is used to wake up the main processor to perform the first signal processing.
[0012] Optionally, the interrupt generator includes an amplitude detection unit, a latch, and an instruction parsing unit; the input terminal of the amplitude detection unit serves as the second input terminal of the interrupt generator, used to receive the input audio signal, and its output terminal is connected to the first input terminal of the latch; the input terminal of the instruction parsing unit serves as the third input terminal of the interrupt generator, connected to the main processor via the system bus, and its output terminal is connected to the second input terminal of the latch; the third input terminal of the latch serves as the first input terminal of the interrupt generator, connected to the flag output terminal of the buffer module, and its output terminal is connected to the main processor; the amplitude... The amplitude detection unit monitors the amplitude of the input audio signal. When the amplitude of the input audio signal is lower than a preset amplitude within a set time period, it generates a high-level Reset signal. The latch sets the interrupt signal to a low level when the Reset signal is high, and sets the interrupt signal to a low level when it receives a clear signal from the instruction parsing unit. The interrupt signal wakes up the main processor by going high. The instruction parsing unit receives a clear instruction from the main processor, generates the clear signal, and sends the clear signal to the latch.
[0013] Optionally, the main processor is woken up when the interrupt signal is high to perform first signal processing. After completing the first signal processing, it sends the clear instruction to the instruction parsing unit through the system bus and enters sleep mode.
[0014] Optionally, the audio signal processing module includes an audio signal processor, a third arbitrator, and a memory; the audio signal processor is connected to the main processor via the system bus and to the third arbitrator via a high-speed bus; the third arbitrator is connected to the main processor and the memory via the system bus; the audio signal processor is used to read the intermediate audio signal from the memory, perform second signal processing on the intermediate audio signal, generate the output audio signal, and write the output audio signal into the memory; the memory serves as the memory of the audio signal processing module, used to store the intermediate audio signal written by the main processor and the output audio signal written by the audio signal processor; the third arbitrator is used to determine the order in which devices access the memory according to a preset priority relationship.
[0015] Optionally, the audio processing circuit further includes a verifier, which is connected to the third arbitrator of each of the audio signal processing modules. The verifier is used to check whether the instructions and configuration files stored in each of the memories are correct. When the instructions and configuration files stored in each of the memories are correct, the audio processing circuit is started. When at least one of the instructions and configuration files stored in each of the memories is incorrect, the program instructions of the audio processing circuit are reloaded.
[0016] Optionally, the third arbitrator and the verifier are also connected to the interface bus respectively; the priority relationship includes: from high to low priority, the verifier, the audio signal processor, the main processor and the interface bus; or, from high to low priority, the audio signal processor, the main processor, the interface bus and the verifier.
[0017] Optionally, the computational complexity of the first signal processing is less than that of the second signal processing.
[0018] Optionally, the audio signal processor includes a system bus interface, a clock management unit, a timer, a pointer management unit, a register group, a high-speed read / write management unit, a main state machine, and an arithmetic unit. The system bus interface is used to receive configuration parameters sent by the main processor, identify start commands, and receive access commands sent by the main processor through the system bus. The clock management unit is used to generate an internal clock based on an externally input system clock. The internal clock is used to define the operating clocks of the clock management unit, the timer, the pointer management unit, the register group, the high-speed read / write management unit, the main state machine, and the arithmetic unit. The timer is used to provide a timing reference for the main state machine and the arithmetic unit. The pointer management unit is used to manage the pointers of the memory in real time. The register group is used to temporarily store intermediate audio signals to be processed and output audio signals after processing. The high-speed read / write management unit is used to generate high-speed bus signals for accessing the memory. The main state machine is used to schedule other components to perform second signal processing according to the mode parameters and configuration parameters sent by the main processor. The arithmetic unit is used to calculate the audio signals in the register group according to the scheduling of the main state machine and write the calculation results back into the register group.
[0019] This application also provides an audio processing method, applied to any of the above-mentioned audio processing circuits, the audio processing method comprising the following steps:
[0020] A caching module is used to cache the input audio signal, provide the input audio signal to the main processor, and cache the output audio signal;
[0021] The main processor performs first signal processing on the audio signal provided by the cache module to obtain an intermediate audio signal. The intermediate audio signal is then written into the memory of the audio signal processing module. The output audio signal generated by the audio signal processing module is read from the memory of the audio signal processing module and written into the cache module. The first signal processing is used to characterize the set audio signal processing process.
[0022] The intermediate audio signal is subjected to a second signal processing using the audio signal processing module to obtain the output audio signal; the second signal processing is used to characterize other audio processing processes besides the first signal processing.
[0023] This application also provides a chip including any of the above-described audio processing circuits.
[0024] This application also provides an electronic device, including any of the above-described audio processing circuits or any of the above-described chips.
[0025] The audio processing circuit, method, chip, and electronic device provided in this application cache the input audio signal through a cache module. This allows the main processor to read the input audio signal from the cache module, perform relatively simple first signal processing to obtain an intermediate audio signal, and write the intermediate audio signal into the memory of the audio signal processing module. In this way, the audio signal processing module can perform second signal processing on the intermediate audio signal, including complex sound effect algorithms and / or protection algorithms. This reduces the audio processing pressure on the main processor, improves the operating efficiency of the main processor, and is lower in cost and stronger in computing power compared to general single-core systems. Furthermore, the main processor and the audio signal processing module can work concurrently, which can significantly improve the system efficiency of the entire audio processing circuit. The main processor and the audio signal processing module can share the cache module, realizing a storage space sharing mechanism, which can significantly reduce data migration time and avoid communication bottlenecks between multi-core processors.
[0026] Furthermore, the cache module of this application includes multiple storage areas such as a first cache unit and a second cache unit, which can significantly increase the bandwidth of the high-speed bus and improve data access efficiency.
[0027] Furthermore, this application is able to dynamically manage the main processor's operating mode through an interrupt generator, resulting in extremely low static power consumption for the entire circuit system. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1a and Figure 1b This is a schematic diagram of the audio processing scheme during the research process;
[0030] Figure 2 This is a schematic diagram of an audio processing circuit structure according to an embodiment of this application;
[0031] Figure 3 This is a schematic diagram of an audio processing circuit structure according to another embodiment of this application;
[0032] Figure 4a and Figure 4b This is a schematic diagram of the cache module structure according to an embodiment of this application;
[0033] Figure 5 This is a schematic diagram of an audio processing circuit structure according to another embodiment of this application;
[0034] Figure 6This is a schematic diagram of an interrupt generator structure according to an embodiment of this application.
[0035] Figure 7 This is a schematic diagram of the memory management state according to an embodiment of this application;
[0036] Figure 8 This is a schematic diagram of an audio processing circuit structure according to another embodiment of this application;
[0037] Figure 9 This is a schematic diagram of an audio processing circuit structure according to another embodiment of this application;
[0038] Figure 10 This is a schematic diagram of the operation process of a CRC check circuit according to an embodiment of this application;
[0039] Figure 11 This is a schematic diagram of interface permissions according to an embodiment of this application;
[0040] Figure 12a and Figure 12b This is a schematic diagram of an audio processing circuit structure according to another embodiment of this application;
[0041] Figure 13 This is a schematic diagram of the workflow of an embodiment of this application;
[0042] Figure 14 This is a schematic diagram of the workflow of another embodiment of this application. Detailed Implementation
[0043] The inventors researched audio processing solutions for portable electronic devices and found that some solutions chose simplified algorithms, sacrificing some performance to reduce the requirements on the power amplifier, such as... Figure 1a As shown, the simplified algorithm will result in the inability to achieve the ultimate sound effects and complete protection, leading to poor audio processing performance. Other solutions integrate a general-purpose DSP (digital signal processing) module into the power amplifier to improve hardware computing power, such as... Figure 1b As shown, however, general-purpose DSP solutions are very expensive and consume a lot of power.
[0044] To address the aforementioned issues, this application reduces the audio processing load on the main processor, improves the main processor's operating efficiency, and offers lower cost and stronger computing power compared to general single-core systems, resulting in relatively low power consumption for the entire circuit system.
[0045] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0046] The first aspect of this application provides an audio processing circuit, referenced... Figure 2 and Figure 3 As shown, the audio processing circuit includes a cache module 110, a main processor 120, and at least one audio signal processing module 200. The cache module 110 and the main processor 120 are respectively connected to each of the audio signal processing modules 200 through a system bus.
[0047] The cache module 110 is used to cache the input audio signal, providing the input audio signal to the main processor 120, and cache the output audio signal, which is the audio signal processed by the audio signal processing module 200. The cache module 110 may include data structures such as FIFO (First-In-First-Out queue). The cache module 110 is used for data caching, and its design depth can be N. It may include multiple cache units such as Block0 and Block1 for ping-pong operations.
[0048] The main processor 120 is used to obtain an intermediate audio signal from the input audio signal, write the intermediate audio signal into the memory of the audio signal processing module 200, and read the output audio signal generated by the audio signal processing module 200 from the memory of the audio signal processing module 200, and write the output audio signal into the buffer module 110. The first signal processing is used to characterize the set audio signal processing procedure; the set audio signal processing procedure may include audio signal processing procedures with relatively small computational load, such as logical operations and / or simple data processing.
[0049] The audio signal processing module 200 is used to perform a second signal processing on the intermediate audio signal to obtain the output audio signal; the second signal processing is used to characterize other audio processing processes besides the first signal processing. The aforementioned second signal processing includes computationally intensive audio signal processing tasks such as complex sound effect algorithm processing and / or protection algorithm processing. Specifically, the main processor 120 can set the first signal processing and the second signal processing according to the computational workload of the audio signal processing process. In this way, the main processor 120 can perform the first signal processing, such as logical operations and simple data processing, and treat the complex processing involving audio data as the second signal processing, which is completed by calling the audio signal processing module 200. This allows the main processor 120 and the audio signal processing module 200 to work concurrently, which can significantly improve system efficiency. Here, the main processor 120 is the only main processor 120 on the system bus. The audio signal processing module 200 is mounted under the system bus and can be called by the main processor 120 as a slave to perform relatively complex audio signal processing. This architecture eliminates the need for the main processor 120 to perform arbitration and relatively computationally intensive volume signal processing, which can reduce the requirements for the speed and performance of the main processor 120.
[0050] Specifically, the number of audio signal processing modules 200 can be set according to the application scenario of the corresponding audio processing circuit. If the audio processing circuit faces an application scenario with relatively simple input audio signals or small signal quantities, then the number of audio signal processing modules 200 is one, as shown in Figure 1, to simplify the structure of the audio processing circuit. If the audio processing circuit faces an application scenario with relatively complex input audio signals or multi-channel input, then the number of audio signal processing modules 200 is multiple, such as... Figure 2 As shown, multiple audio signal processing modules 200 are used to process the input audio signal in parallel. For example, each audio signal processing module 200 processes the input audio signal corresponding to one channel, so as to improve the audio processing efficiency.
[0051] The aforementioned audio processing circuit caches the input audio signal through the cache module 110, allowing the main processor 120 to read the input audio signal from the cache module 110 and perform relatively simple first signal processing to obtain an intermediate audio signal. The intermediate audio signal is then written into the memory of the audio signal processing module 200, enabling the audio signal processing module 200 to perform second signal processing on the intermediate audio signal, including complex sound effect algorithms and / or protection algorithms. This reduces the audio processing pressure on the main processor 120 and improves its operating efficiency. Furthermore, the main processor 120 and the audio signal processing module 200 can work concurrently, significantly improving the overall system efficiency of the audio processing circuit.
[0052] In one embodiment, reference Figure 4aAs shown, the cache module 110 includes a first cache unit 111, a second cache unit 112, and a flag generator 113.
[0053] The first cache unit 111 and the second cache unit 112 are used to alternately cache the input audio signal or the output audio signal to improve the caching capacity by performing a ping-pong operation on the input audio signal or the output audio signal. The first cache unit 111 and the second cache unit 112 can each adopt a FIFO structure. The input audio signal is the audio signal before the main processor 120 performs the first signal processing, and the output audio signal is the audio signal after the audio signal processing module 200 performs the second signal processing. After the audio signal processing module 200 performs the second signal processing to obtain the output audio signal, the main processor 120 can read the output audio signal from the memory of the audio signal processing module 200 and write the output audio signal into the first cache unit 111 or the second cache unit 112 to overwrite the existing input audio signal in the first cache unit 111 or the second cache unit 112.
[0054] The flag generator 113 is used to identify the storage address of the input audio signal. When the address of the input audio signal is switched to the starting address of the next cache unit (first cache unit 111 or second cache unit 112), a processing flag is sent. The processing flag is used to instruct the main processor 120 to process the input audio signal cached in the first cache unit 111 or the second cache unit 112 in the cache module.
[0055] In one example, reference Figure 4b As shown, the cache module 110 further includes a first arbitrator 114 and a second arbitrator 115; the first arbitrator 114 is disposed at the input terminal of the cache module 110.
[0056] The first arbiter 114 is used to arbitrate the order in which audio signals are written to the first cache unit 111 or the second cache unit 112. Specifically, each cache unit can also store input audio signals (H-Write), and the main processor 120 can write output audio signals (S-Write) to each cache unit via the system bus. The first arbiter 114 can arbitrate the order in which the audio signals are written to each cache unit according to the principle that the read and write operations of the main processor 120 have higher priority or other priority rules set by the main processor 120. Here, the audio signals written to each cache unit can include both input and output audio signals.
[0057] The second arbiter 115 is used to arbitrate the order in which corresponding audio signals (input audio signals and output audio signals) are read from the first cache unit 111 or the second cache unit 112. Specifically, the main processor 120 can read input audio signals (S-Read) from each cache unit via the system bus and can read output audio signals (H-Read) to output to the next-level module. The second arbiter 115 can arbitrate the order in which audio signals are read from each cache unit according to the principle that the read and write operations of the main processor 120 have higher priority or other priority rules set by the main processor 120.
[0058] Accordingly, the flag generator 113 can generate a processing flag based on the current operation address. Whenever the address of H-Read switches to the starting address of the next cache unit, a pulse signal with the width of a sample slot can be sent as a processing flag to components such as the interrupt generator 130.
[0059] In one example, reference Figure 5 As shown, the audio processing circuit also includes an interrupt generator 130; the first input terminal of the interrupt generator 130 is connected to the flag output terminal of the buffer module 110, the second input terminal is used to receive the input audio signal, the third input terminal is connected to the main processor 120 via a bus, and the output terminal is used to connect to the main processor 120. The main processor 120 is in sleep mode before performing the first signal processing.
[0060] The interrupt generator 130 is used to generate an interrupt signal based on the input audio signal and the processing flag, and to receive a clear instruction from the main processor 120 after completing the corresponding first signal processing, thereby clearing the interrupt signal. The interrupt signal is used to wake up the main processor 120 to perform the first signal processing. In this example, the interrupt generator 130 can generate an interrupt signal based on the input audio signal and the processing flag to wake up the main processor 120 to work. After the main processor 120 completes the corresponding data processing, it can send a clear instruction through the system bus to clear the interrupt signal, and then the main processor 120 continues to enter sleep mode. This achieves the purpose of dynamically managing the working mode of the main processor 120, resulting in extremely low static power consumption for the main processor 120.
[0061] In one example, the interrupt generator 130 includes an amplitude detection unit 131, a latch 132, and an instruction parsing unit 133. The input terminal of the amplitude detection unit 131 serves as the second input terminal of the interrupt generator 130, used to receive the input audio signal. The output terminal of the amplitude detection unit 131 is connected to the first input terminal of the latch 132. The input terminal of the instruction parsing unit 133 serves as the third input terminal of the interrupt generator 130 and is connected to the main processor 120 via the system bus. The output terminal of the instruction parsing unit 133 is connected to the second input terminal of the latch 132. The third input terminal of the latch 132 serves as the first input terminal of the interrupt generator 130 and is connected to the flag output terminal of the cache module 110. The output terminal of the latch 132 is connected to the main processor 120.
[0062] The amplitude detection unit 131 is used to monitor the amplitude of the input audio signal. When the amplitude of the input audio signal is lower than a preset amplitude within a set time period, a high-level Reset signal is generated; otherwise, no response is made, and the Reset signal remains at a low level. The set time period here includes a time period ending at the current time, which can be set according to the application scenario and other characteristics of the audio processing circuit. For example, a time period of 2 seconds ending at the current time can be set.
[0063] The latch 132 is used to set the interrupt signal to a low level when the Reset signal is high. When the Reset signal is low, the interrupt signal does not need to be processed. At this time, when the input signal amplitude is low, the main processor 120 does not need to perform data processing, which can significantly reduce system power consumption. The latch 132 also sets the interrupt signal to a low level when it receives a clear signal sent by the instruction parsing unit 133; the interrupt signal wakes up the main processor 120 by going high.
[0064] The instruction parsing unit 133 is used to receive the clear instruction sent by the main processor 120, generate a clear signal, and send the clear signal to the latch 132. Optionally, the instruction parsing unit 133 may include components such as a decoder, and the clear signal may be characterized by a high-level segment in some signals.
[0065] Optionally, the instruction parsing unit 133 can monitor the system bus. When it receives a clear instruction from the main processor 120, it can generate a high-level pulse signal (Clear signal) for one clock cycle. When the latch 132 receives a high-level Clear signal, it can set the interrupt signal to a low level (0); when the Clear signal is low, the interrupt signal is unaffected. Correspondingly, if the processing flag is denoted as the Flag signal, the latch 132 will set the interrupt signal to a low level (0) if either the Reset signal or the Clear signal is high; the latch 132 will set the interrupt signal to a high level if it detects a rising edge of the Flag signal and both the Reset and Clear signals are low. The Reset and Clear signals have higher priority than the Flag signal.
[0066] In one example, the main processor 120 is woken up when the interrupt signal is high to perform the first signal processing. After completing the first signal processing, it sends a clear instruction to the instruction parsing unit 133 via the system bus and enters sleep mode to reduce the system's static power consumption. In this example, the main processor 120 can be woken up when the interrupt signal is high to perform the first signal processing. After completing the first signal processing, the main processor 120 sends a clear instruction to the interrupt generator 130 via the system bus, causing the interrupt signal of the interrupt generator 130 to go low. Then, the main processor 120 enters sleep mode again, which makes the dynamic management process of the main processor 120's working mode more orderly.
[0067] Optionally, the cache module 110 can also be used to store the program instructions of the main processor 120. The main processor 120 adopts a low-cost, low-power on-chip processor that supports sleep mode. All program instructions can be stored in the cache module 110 so that the processor 120 can read the corresponding program instructions from the cache module 110 in real time.
[0068] In one embodiment, referring to Figure 1 and... Figure 5 As shown, the audio signal processing module 200 includes an audio signal processor 210, a third arbitrator 231, and a memory 232; the audio signal processor 210 is connected to the main processor 120 through the system bus, the audio signal processor 210 is connected to the third arbitrator 231 through a high-speed bus, and the third arbitrator 231 is connected to the main processor 120 and the memory 232 through the system bus.
[0069] The audio signal processor 210 is used to read the intermediate audio signal from the memory 232, perform second signal processing on the intermediate audio signal, generate the output audio signal, and write the output audio signal into the memory 232. The second signal processing can be customized according to the application scenario of the corresponding audio processing circuit, and may specifically include computationally intensive audio processing processes such as sound effect algorithm processing and / or protection algorithm processing. The audio signal processor 210 is mounted on the system bus and can be called by the master processor 120 as a slave device of the master processor 120. At the same time, the audio signal processor 210 can access the memory 232 through the high-speed bus, the bandwidth of which is N times that of the system bus, to further improve the efficiency of audio signal processing. Optionally, the audio signal processor 210 can set a completion flag. After completing one second signal processing operation, the completion flag can be set high so that the master processor 120 can recognize the high completion flag and determine that the corresponding second signal processing has been completed, and then call the audio signal processor 210 to perform other work, or determine that the current second signal processing is complete.
[0070] The memory 232 serves as the RAM of the audio signal processing module 200, storing the intermediate audio signals written by the main processor 120 and the output audio signals written by the audio signal processor 210. The memory 232 stores data such as intermediate audio signals and / or output audio signals, and also stores system information such as instructions and configuration files of the audio signal processing module 200. It may include RAM, ROM, Flash, etc. Optionally, to ensure efficient operation of the audio signal processor 210, the memory 232 can be divided into blocks, for example, referencing... Figure 7 As shown, Figure 7 The memory is divided into N blocks, such as Memory0, Memory1, ..., MemoryN-1, which can improve data transmission bandwidth and reduce the dynamic power consumption of the 232 memory.
[0071] The third arbitrator 231 is used to determine the order in which devices access the memory 232 according to a preset priority relationship.
[0072] In one example, reference Figure 8 and Figure 9As shown, the audio processing circuit also includes a verifier 140, which is connected to the third arbitrator 231 of each of the audio signal processing modules 200. The verifier 231 checks whether the instructions and configuration files stored in each of the memories 232 are correct. If the instructions and configuration files stored in each of the memories 232 are correct, the audio processing circuit is started. If at least one of the instructions and configuration files stored in each of the memories 232 contains an error, the program instructions of the audio processing circuit are reloaded, and then the audio processing circuit is started again, to ensure the stability of the audio processing circuit in subsequent operation.
[0073] Specifically, in the audio signal processing module 200, the program instructions in the memory 232 are typically loaded only once upon power-on and not subsequently loaded again to enable rapid startup of the corresponding chip. However, during use, it is difficult to guarantee that there will be no abnormalities that could lead to tampering with the program instructions in the memory 232. Therefore, a verifier 140 is set up to check in real time whether the instructions and configuration files in the memory 232 are correct. If at least one error is found in the instructions and configuration files stored in each memory 232, the program instructions of the audio processing circuit are reloaded, and the audio processing circuit is restarted, thereby improving the reliability of the audio processing circuit.
[0074] In one example, the third arbiter 231 and the verifier 140 are also connected to an interface bus. The interface bus has read and write access to the entire storage area of the audio processing circuit. The interface bus can be a general-purpose control interface bus such as IIC or SPI bus, used to complete system configuration, memory 232 initialization, verifier 140 control, etc.
[0075] Specifically, the verifier 140 may include a CRC check circuit. The operation of the CRC check circuit can be found in [reference needed]. Figure 10 As shown, the audio processing circuit can configure the memory range to be verified (such as configuring the start and end addresses of memory 232) and the reference check code RefDat via the interface bus. Then, it configures the enable switch Enable signal to a high level (1), and the CRC verification circuit starts working, sending a memory read request. The interface signal converter converts the received signal into a control bus MEMCtrl that matches the memory interface and sends it to the third arbitrator 231 to request access to memory 232. Then, it verifies the received memory data MemDat and outputs the final calculation result CrcDat and the verification completion flag signal to the corresponding register. The audio processing circuit can also read the calculation result CrcDat via the interface bus. If the calculation result CrcDat matches the expected value, it indicates that the instructions and configuration files stored in each memory 232 are correct, i.e., the verification passes.
[0076] In one example, a third arbitrator 231 is used to arbitrate when multiple buses simultaneously access memory 232 according to a fixed priority relationship. This priority relationship can be preset by the main processor 120.
[0077] Optionally, the priority relationship includes, from highest to lowest priority, the verifier, the audio signal processor, the main processor, and the interface bus. This priority relationship provides higher security.
[0078] Optionally, the priority relationship includes the following order from highest to lowest: audio signal processor, main processor, interface bus, and checker. This priority relationship has a relatively low cost.
[0079] In the above priority relationships, the audio signal processor has a higher priority than the main processor. The advantages of this priority relationship include: ① The audio signal processor 210 works more efficiently, improving the computing power per unit time; ② The audio signal processor 210 does not need to have an arbitration and hold circuit built in, which greatly simplifies the design complexity and cost of the audio signal processor; ③ The main processor 120 generally has a built-in wait function when the slave is busy, which does not require additional design and reduces the overall system complexity.
[0080] In one example, the third arbitrator 231 has a built-in write protection unit. Different interfaces have different access permissions to the memory area 232. The permissions for each interface can be selected from [reference]. Figure 11 As shown, Figure 11 Of the permissions shown, the interface bus has read and write permissions for the entire memory area, therefore no write protection module is needed. The audio signal processor 210 and the main processor 120 have read permissions for the entire memory area, but only a limited address field can be written to prevent unrecoverable errors caused by tampering with program instructions in case of an anomaly. MEMCtrl is the output control signal of the verifier 140, having read permissions for the entire memory area but no write permissions. The arbitration hold permission includes: when other high-priority buses are accessing memory, the current access is suspended, a memory 232 busy status is returned to the main processor 120 via the bus, and the access request status is maintained until the current access is successful. Then, a success flag and corresponding data are returned to the main processor 120 via the bus. The instruction parsing permission includes: decoding bus signals according to the bus protocol and converting them into memory interface control signals.
[0081] In one example, the computational complexity of the first signal processing is less than that of the second signal processing. In this way, the audio signal processing module 200 can be called by the main processor 120 as a slave to perform relatively complex second signal processing. While ensuring the audio processing effect, this can improve the operating speed of the main processor 120.
[0082] In one example, reference Figure 12a As shown, the audio signal processor 210 includes a system bus interface 211, a clock management unit 212, a timer 213, a pointer management unit 214, a register group 215, a high-speed read / write management unit 216, a main state machine 217, and an arithmetic unit 218.
[0083] The system bus interface 211 is used to receive configuration parameters sent by the main processor 120, identify startup commands, and receive access commands sent by the main processor 120 through the system bus. Specifically, the configuration parameters may include the operating mode, the address of the intermediate audio signal to be processed in the memory 232, the address of the processed output audio signal in the memory 232, the length of the data to be processed, the data precision, etc. Optionally, the main processor 120 can also access the current operating status register of the audio signal processor 210 through the system bus, etc.
[0084] The clock management unit 212 generates an internal clock based on an externally input system clock. This internal clock defines the operating clocks of the clock management unit 212, the timer 213, the pointer management unit 214, the register group 215, the high-speed read / write management unit 216, the main state machine 217, and the arithmetic unit 218. The clock management unit 212 is an internal clock gating system, capable of generating an internal clock based on an externally input system clock. All components within the audio signal processor 210, except for the system bus interface 211, use this internal clock.
[0085] The timer 213 is used to provide a timing reference for the main state machine 217 and the arithmetic unit 218. The timer 213 operates using an internal clock. If the current task is not completed after a preset time, it can trigger timeout protection, forcibly terminate the current task, send an abnormal interrupt, and then enter sleep mode.
[0086] The pointer management unit 214 is used to manage the pointers of the memory 232 in real time. The pointer management unit 214 can manage the pointers related to the memory 232 in real time. The initial value comes from the configuration parameters sent by the main processor 120, and is dynamically managed according to the operation of the main state machine 217.
[0087] The register group 215 is used to temporarily store the intermediate audio signal to be processed and the output audio signal after processing; the depth of the register group 215 can be determined according to the computing power of the arithmetic unit 218, and is usually a small depth parameter.
[0088] The high-speed read / write management unit 216 is used to generate high-speed bus signals for accessing the memory 232. Specifically, it can read and write memory data according to the requirements of the main state machine 217 and the memory address provided by the pointer management unit 214.
[0089] The main state machine 217 is used to schedule other components to perform second signal processing according to the mode parameters and configuration parameters sent by the main processor 120; the main state machine 217 can also update the status register of the audio signal processor 210 and set the completion flag to high.
[0090] The arithmetic unit 218 is used to calculate the intermediate audio signal in the register group 215 according to the scheduling of the main state machine 217, and write the calculation result back into the register group 215. Specifically, the arithmetic unit 218 can have multiple multipliers, adders and other circuits built in to complete the calculation task, calculate the corresponding data in the register group 215 according to the scheduling of the main state machine 217, and write the result back into the register group 215.
[0091] In one example, reference Figure 12b As shown, the audio signal processor also includes a zero-oscillation monitor 219, which is used to monitor whether the computing unit 218 experiences zero oscillation during the calculation process, and to perform zero-oscillation processing when zero oscillation occurs, so as to improve the stability of the calculation process.
[0092] Optionally, such as Figure 12b As shown, the audio signal processor 220 also includes a timeout protection unit 221. The timeout protection unit 221 can provide timeout protection function when the timeout protection is triggered. The timeout protection function can forcibly terminate the current task, avoid the audio signal processor 210 from failing to handshake with the main processor 120 due to abnormal operation, and avoid problems such as infinite loop.
[0093] In one example, the audio signal processor 220 can perform secondary signal processing such as IIR filtering. This example uses IIR filtering as an example. Figure 12b The workflow of the audio signal processor 220 shown is explained below, with reference to... Figure 13 As shown, the corresponding workflow includes steps S301 to S332.
[0094] S301, the audio processing circuit is powered on.
[0095] S302, Audio Signal Processor 210 enters sleep mode.
[0096] S303, main processor 120 sends configuration parameters.
[0097] S304, main processor 120 sends a startup command.
[0098] S305, pointer initialization of the pointer management unit 214.
[0099] S306. Has a startup command been detected? If yes, proceed to step S307; otherwise, return to step S302.
[0100] S307, the clock management unit 212 pulls Clk_Gate high to generate an internal clock.
[0101] S308, timer 213 started.
[0102] S309, the main state machine 217 starts up according to the configuration parameters and enters IIR mode.
[0103] S310, the main state machine 217 calls the high-speed bus to download data, which can download data from memory 232 to register group 215 (DataBuffer). This data may include intermediate audio signals.
[0104] S311, pointer++, that is, the pointer of the pointer management unit 214 performs an increment operation.
[0105] S312, the arithmetic unit 218 accesses the DataBuffer data (data in register group 215) and performs IIR calculation.
[0106] S313, Zero oscillation monitor 219 monitors whether zero oscillation has occurred. If it has, proceed to step S314; otherwise, proceed to step S315.
[0107] S314, zero-oscillation monitor 219 performs zero-oscillation processing.
[0108] S315, the arithmetic unit 218 writes the processed data back to the DataBuffer (register group 215).
[0109] S316, pointer++, means that the pointer in the pointer management unit 214 is incremented by 1.
[0110] S317, the main state machine 217 calls the high-speed bus Save function to save data from the DataBuffer to memory 232. This data may include the output audio signal.
[0111] S318, pointer++, means that the pointer in the pointer management unit 214 is incremented by 1.
[0112] S319, the main state machine 217 calls the high-speed bus Load (download) function to download data from memory 232 to the DataBuffer. This data may include intermediate audio signals.
[0113] S320, pointer++, means that the pointer in the pointer management unit 214 performs an increment operation.
[0114] S321, the arithmetic unit 218 accesses the DataBuffer data and performs IIR calculations.
[0115] S322, Zero oscillation monitor 219 monitors whether zero oscillation has occurred. If it has, proceed to step S324; otherwise, proceed to step S323.
[0116] S323, the arithmetic unit 218 writes the processed data back to the DataBuffer.
[0117] S324, zero-oscillation monitor 219 performs zero-oscillation processing.
[0118] S325, the main state machine 217 calls the high-speed bus Save function to save data from the DataBuffer to memory 232. This data may include the output audio signal.
[0119] S326, pointer++, that is, the pointer of the pointer management unit 214 performs an increment operation.
[0120] S327, pointer++, means that the pointer in the pointer management unit 214 is incremented by 1.
[0121] S328, and so on, causes the main state machine 217 to save all the obtained output audio signal and other data from the DataBuffer to the memory 232.
[0122] S329, data processing is complete. Set the system status register corresponding to the audio processing circuit to normal and set the completion flag to high.
[0123] S330: Determine if execution timeout has occurred. If yes, proceed to step S331; otherwise, return to step S330.
[0124] S331 sets the system status register to an exception and the completion flag to high.
[0125] S332, Clock Management Unit 212 pulls Clk_Gate low.
[0126] In one example, the main processor 120 can perform logical operations and simple data processing tasks according to program instructions in the entire audio processing circuit. Complex processing tasks involving audio data are handled by the audio signal processing module 200. The main processor 120 and the audio signal processing module 200 can work concurrently to significantly improve system efficiency. The working process of the main processor 120 can be found in [reference needed]. Figure 14 As shown, it includes steps S401 to S421.
[0127] S401, power on.
[0128] S402, initialize memory 232.
[0129] S403, determine whether the verification was successful. If yes, proceed to step S404; otherwise, proceed to step S402. Specifically, the verifier 140 checks whether the instructions and configuration files stored in each memory 232 are correct. If the instructions and configuration files stored in each memory 232 are correct, the verification is deemed successful.
[0130] S404, main processor 120 boot.
[0131] S405, main processor 120 enters hibernation mode.
[0132] S406, determine whether an interrupt signal exists to realize interrupt monitoring. If yes, proceed to step S407; otherwise, proceed to step S405. Specifically, the interrupt generator 130 can generate an interrupt signal based on the input audio signal and processing flag to wake up the main processor 120 for operation.
[0133] S407, Data Load (Download), specifically, it can download the input audio signal from the FIFO (buffer module 110).
[0134] S408, the main processor 120 performs first signal processing such as logical operations and / or data processing on the input audio signal to output intermediate audio data and write the intermediate audio data into the memory 232.
[0135] S409, main processor 120 calls audio signal processor 210.
[0136] S410, the audio signal processor 210 performs second data processing, specifically by reading intermediate audio data from the memory 232 and performing second data processing on the intermediate audio data.
[0137] S411, Audio signal processor 210 has successfully processed the signal, and the complete flag is set high.
[0138] S412, does the main processor 120 obtain the completion flag? If yes, proceed to step S413; otherwise, proceed to step S412.
[0139] S413, the main processor 120 performs first signal processing such as logical operations and / or data processing on the input audio signal.
[0140] S414, main processor 120 calls audio signal processor 210.
[0141] S415, the audio signal processor 210 performs second data processing, specifically by reading intermediate audio data from the memory 232 and performing second data processing on the intermediate audio data.
[0142] S416, Audio signal processor 210 has successfully processed the signal, and the complete flag is set high.
[0143] S417: Does the main processor 120 obtain the completion flag? If yes, the main processor 120 performs the first signal processing, such as logical operation and / or data processing; otherwise, step S417 is executed.
[0144] S418, and so on, until the main processor 120 calls the audio signal processor 210 to process all the intermediate audio signals that need to be processed.
[0145] S419, Data processing complete.
[0146] S420, Data Load (download), specifically, can download data such as the output audio signal obtained from the second signal processing from the memory 232 to the FIFO (buffer module 110).
[0147] S421, main processor 120 sends a clear command.
[0148] In one embodiment, such as Figure 8 and Figure 9 As shown, the audio processing circuit also includes a watchdog timer 150. The watchdog timer 150 is connected to the system bus and is used to monitor the first signal processing process of the main processor 120. Specifically, the watchdog timer 150 can be implemented using an M-bit decrementing counter. This counter is connected to the system bus and can be read and written by the main processor 120, and its data can be accessed and read by the interface bus. When the counter value is not 0, it decrements by 1 after each storage of data corresponding to the input audio signal, until it reaches 0, at which point it stops counting and requests an interrupt from the interface bus. When the audio processing circuit is working, each time the main processor 120 is woken up by an interrupt signal and finishes executing the program, it assigns a preset value to the counter corresponding to the watchdog timer 150. If the main processor 120's program crashes without assigning a value, the counter will decrement to 0 after a period of time, generating an interrupt. By checking whether the watchdog timer 150 is 0, the normal operation of the main processor 120 can be effectively monitored.
[0149] The audio processing circuit described above uses a cache module 110 to cache the input audio signal. This allows the main processor 120 to read the input audio signal from the cache module 110, perform relatively simple first signal processing to obtain an intermediate audio signal, and write the intermediate audio signal into the memory of the audio signal processing module 200. The audio signal processing module 200 then performs second signal processing on the intermediate audio signal, including complex sound effect algorithms and / or protection algorithms. This reduces the audio processing load on the main processor 120, improves its operating efficiency, and is lower in cost and more powerful than a typical single-core system. Furthermore, the main processor 120 and the audio signal processing module 200 can work concurrently, significantly improving the overall system efficiency of the audio processing circuit. The main processor 120 and the audio signal processing module 200 can share the cache space of the cache module 110, implementing a storage space sharing mechanism, which can significantly reduce data migration time and avoid communication bottlenecks between multi-core processors. In addition, the cache module 110 includes multiple storage areas such as a first cache unit 111 and a second cache unit 112, which can significantly increase the bandwidth of the high-speed bus and improve data access efficiency. The interrupt generator 130 can dynamically manage the operating mode of the main processor 120, resulting in extremely low static power consumption for the entire circuit system.
[0150] This application provides a second aspect of an audio processing method, which is applied to the audio processing circuit described in any of the above embodiments. The audio processing method includes the following steps:
[0151] A caching module is used to cache the input audio signal, provide the input audio signal to the main processor, and cache the output audio signal;
[0152] The main processor performs first signal processing on the audio signal provided by the cache module to obtain an intermediate audio signal. The intermediate audio signal is then written into the memory of the audio signal processing module. The output audio signal generated by the audio signal processing module is read from the memory of the audio signal processing module and written into the cache module. The first signal processing is used to characterize the set audio signal processing process.
[0153] The intermediate audio signal is subjected to a second signal processing using the audio signal processing module to obtain the output audio signal; the second signal processing is used to characterize other audio processing processes besides the first signal processing.
[0154] The above-described audio processing method can be applied to the audio processing circuit described in any of the above embodiments, and has all the beneficial effects of the audio processing circuit described in any of the above embodiments, which will not be repeated here.
[0155] In a third aspect, this application provides a chip including the audio processing circuit described in any of the above embodiments. The audio processing circuit has high operating efficiency, lower cost and stronger computing power compared to a general single-core system. Furthermore, the main processor and the audio signal processing module can work concurrently, which can significantly improve the system efficiency of the entire audio processing circuit. By adopting a storage space sharing mechanism, data migration time can be significantly reduced, audio signal processing costs can be reduced, and communication bottlenecks between multi-core processors can be avoided.
[0156] In a fourth aspect, this application provides an electronic device including the audio processing circuit or the chip described in any of the above embodiments. The audio processing circuit has high operating efficiency, lower cost, stronger computing power, and lower power consumption compared to a general single-core system.
[0157] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.
[0158] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.
[0159] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0160] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.
Claims
1. An audio processing circuit, characterized in that, The audio processing circuit includes a cache module, a main processor, and at least one audio signal processing module. The cache module and the main processor are respectively connected to each of the audio signal processing modules via a system bus. The caching module is used to cache the input audio signal, provide the input audio signal to the main processor, and cache the output audio signal; The main processor is used to perform a first signal processing on the input audio signal to obtain an intermediate audio signal, write the intermediate audio signal into the memory of the audio signal processing module, read the output audio signal generated by the audio signal processing module from the memory of the audio signal processing module, and write the output audio signal into the buffer module; the first signal processing is used to characterize the set audio signal processing process; The audio signal processing module is used to perform a second signal processing on the intermediate audio signal to obtain the output audio signal; the second signal processing is used to characterize other audio processing processes besides the first signal processing. The audio processing circuit also includes an interrupt generator; the first input terminal of the interrupt generator is connected to the flag output terminal of the buffer module, the second input terminal is used to receive the input audio signal, the third input terminal is connected to the main processor through a bus, and the output terminal is used to connect to the main processor. The interrupt generator includes an amplitude detection unit, a latch, and an instruction parsing unit. The input terminal of the amplitude detection unit serves as the second input terminal of the interrupt generator, used to receive the input audio signal, and its output terminal is connected to the first input terminal of the latch. The input terminal of the instruction parsing unit serves as the third input terminal of the interrupt generator, connected to the main processor via the system bus, and its output terminal is connected to the second input terminal of the latch. The third input terminal of the latch serves as the first input terminal of the interrupt generator, connected to the flag output terminal of the cache module, and its output terminal is connected to the main processor.
2. The audio processing circuit according to claim 1, characterized in that, The cache module includes a first cache unit, a second cache unit, and a flag generator; The first buffer unit and the second buffer unit are used to buffer the input audio signal or the output audio signal in turn; The flag generator is used to identify the storage address of the input audio signal. When the address of the input audio signal switches to the first address of the next cache unit, a processing flag is sent. The processing flag is used to instruct the main processor to process the input audio signal cached in the first cache unit or the second cache unit.
3. The audio processing circuit according to claim 2, characterized in that, The cache module also includes a first arbitrator and a second arbitrator; The first arbiter is used to arbitrate the order in which audio signals are written to the first buffer unit or the second buffer unit; The second arbitrator is used to arbitrate the order in which the corresponding audio signal is read from the first buffer unit or the second buffer unit.
4. The audio processing circuit according to claim 2, characterized in that, The interrupt generator is used to generate an interrupt signal based on the input audio signal and the processing flag, and to receive a clear instruction fed back by the main processor after completing the corresponding first signal processing, thereby clearing the interrupt signal. The interrupt signal is used to wake up the main processor to perform the first signal processing.
5. The audio processing circuit according to claim 4, characterized in that, The amplitude detection unit is used to monitor the amplitude of the input audio signal. When the amplitude of the input audio signal is lower than the preset amplitude within a set time period, a high-level Reset signal is generated. The latch is used to set the interrupt signal to a low level when the Reset signal is high, and to set the interrupt signal to a low level when a clear signal is received from the instruction parsing unit; the interrupt signal wakes up the main processor by going high. The instruction parsing unit is used to receive the clear instruction sent by the main processor, generate the clear signal, and send the clear signal to the latch.
6. The audio processing circuit according to claim 5, characterized in that, The main processor is woken up when the interrupt signal is high to perform the first signal processing. After completing the first signal processing, it sends the clear instruction to the instruction parsing unit through the system bus and enters the sleep mode.
7. The audio processing circuit according to claim 1, characterized in that, The audio signal processing module includes an audio signal processor, a third arbitrator, and a memory; the audio signal processor is connected to the main processor via the system bus and to the third arbitrator via a high-speed bus; the third arbitrator is connected to the main processor and the memory via the system bus. The audio signal processor is used to read the intermediate audio signal from the memory, perform a second signal processing on the intermediate audio signal, generate the output audio signal, and write the output audio signal into the memory; The memory serves as the memory of the audio signal processing module, used to store the intermediate audio signal written by the main processor and the output audio signal written by the audio signal processor. The third arbitrator is used to determine the order in which devices access the memory according to a preset priority relationship.
8. The audio processing circuit according to claim 7, characterized in that, The audio processing circuit also includes a verifier, which is connected to the third arbitrator of each of the audio signal processing modules. The verifier is used to check whether the instructions and configuration files stored in each of the memories are correct. When the instructions and configuration files stored in each of the memories are correct, the audio processing circuit is started. When at least one of the instructions and configuration files stored in each of the memories is incorrect, the program instructions of the audio processing circuit are reloaded.
9. The audio processing circuit according to claim 8, characterized in that, The third arbitrator and the verifier are also connected to the interface bus, respectively. The priority relationship includes: from high to low priority, the order is: verifier, audio signal processor, main processor and interface bus; or, from high to low priority, the order is: audio signal processor, main processor, interface bus and verifier.
10. The audio processing circuit according to claim 7, characterized in that, The computational complexity of the first signal processing is less than that of the second signal processing.
11. The audio processing circuit according to claim 7, characterized in that, The audio signal processor includes a system bus interface, a clock management unit, a timer, a pointer management unit, a register group, a high-speed read / write management unit, a main state machine, and an arithmetic unit; The system bus interface is used to receive configuration parameters sent by the main processor, identify startup commands, and receive access commands sent by the main processor through the system bus. The clock management unit is used to generate an internal clock based on the externally input system clock. The internal clock is used to define the operating clocks of the clock management unit, the timer, the pointer management unit, the register group, the high-speed read / write management unit, the main state machine, and the arithmetic unit. The timer is used to provide a timing reference for the main state machine and the arithmetic unit; The pointer management unit is used to manage the pointers of the memory in real time; The register group is used to temporarily store intermediate audio signals to be processed and output audio signals after processing. The high-speed read / write management unit is used to generate high-speed bus signals for accessing the memory; The master state machine is used to schedule other components to perform second signal processing based on the mode parameters and configuration parameters sent by the master processor. The arithmetic unit is used to calculate the audio signal in the register group according to the scheduling of the master state machine, and write the calculation result back into the register group.
12. An audio processing method, characterized in that, The audio processing method is applied to the audio processing circuit according to any one of claims 1 to 11, and the audio processing method includes: A caching module is used to cache the input audio signal, provide the input audio signal to the main processor, and cache the output audio signal; The main processor performs first signal processing on the audio signal provided by the cache module to obtain an intermediate audio signal. The intermediate audio signal is then written into the memory of the audio signal processing module. The output audio signal generated by the audio signal processing module is read from the memory of the audio signal processing module and written into the cache module. The first signal processing is used to characterize the set audio signal processing process. The intermediate audio signal is subjected to a second signal processing using the audio signal processing module to obtain the output audio signal; the second signal processing is used to characterize other audio processing processes besides the first signal processing.
13. A chip, characterized in that, Includes the audio processing circuit according to any one of claims 1 to 11.
14. An electronic device, characterized in that, It includes the audio processing circuit according to any one of claims 1 to 11 or the chip according to claim 13.