A dynamically reconfigurable bin packing method, reconfigurable module, and FPGA chip
By detecting interactive signals and creating an interface logic unit set in the FPGA chip, the communication problem between the static area and the reconfigurable area is solved, the layout and routing are optimized, and the dynamic reconfigurability performance of the FPGA chip is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- EHIWAY MICROELECTRONIC SCI & TECH (SUZHOU) CO LTD
- Filing Date
- 2022-12-28
- Publication Date
- 2026-05-26
AI Technical Summary
In FPGA chips, how to achieve effective communication and reasonable layout and routing between the static area and the reconfigurable area, especially in dynamic local reconfigurable functions, how to divide the area and optimize the packing method to overcome the implementation difficulties.
By detecting the interaction signals between the static area and the reconfigurable area, input and output logic units for interface connection are created, and an interface logic unit set is generated to realize data interaction between the static area and the reconfigurable area. Incremental packing method is used to optimize layout and routing.
Effective communication between the static and reconfigurable regions was achieved, the dynamic reconfigurability of the FPGA chip was optimized, the module integration and flexibility were improved, and the hardware resource requirements and power consumption were reduced.
Smart Images
Figure CN116107962B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of reconfigurable computing technology, specifically relating to a dynamically reconfigurable packing method and module, and a corresponding FPGA chip. Background Technology
[0002] (Dynamic) reconfigurability refers to dynamically changing the circuit structure while the electronic module is in operation. This is mainly achieved by reconfiguring or partially reconfiguring the programmable logic devices within the module. Using reconfigurable technology, a module can combine the advantages of both software and hardware implementations with only a small increase in hardware resources.
[0003] Taking FPGA chips as an example, the dynamic reconfigurability of FPGAs refers to the dynamic functional transformation of some logic resources during module operation, thereby improving the integration of digital modules, enhancing flexibility, improving fault tolerance, and reducing cost and power consumption. For the dynamic partial reconfigurability of FPGAs, this function is divided into a static area and a reconfigurable area. Configuration files need to be generated for the different logic functions between two functional requirements and loaded into the designated reconfigurable area in the FPGA for reconfiguration. The logic circuits in the designated static area of the FPGA do not need to be changed. Because dynamic partial reconfigurability only reconfigures a portion of the area, the reconfigurable content in the configuration file is correspondingly smaller, and the reconfiguration time is shortened. However, the difficulty in implementing dynamic partial reconfigurability lies in whether the size division of the static and reconfigurable areas can meet the functional needs of the module. Furthermore, the key issues are how modules located in the two areas communicate and how to perform reasonable layout and routing in the reconfigurable area.
[0004] In the field of automated integrated circuit design, the synthesis process typically transforms circuits described in hardware description languages or schematics into basic gate netlists. Packing combines several look-up tables (LUTs) and registers into a single logic unit block, considering constraints such as the maximum number of LUTs a logic unit block can contain, the number of independent input signals and clock inputs, and shared input signals. The optimization goal of the packing step is to group interconnected LUTs together, i.e., pack the most related ones together, to reduce the number of signals to be routed between logic unit blocks and to minimize the tolerance of each logic unit block, thus using the fewest possible logic unit blocks.
[0005] Proper layout and routing in reconfigurable areas requires boxing, but how to box in a way that overcomes the difficulties in achieving dynamic local reconfigurability is a problem that urgently needs to be solved.
[0006] Therefore, it is necessary to study a dynamically reconfigurable packing method and module to optimize the implementation of dynamic reconfigurable functions and further improve the overall performance of FPGA chips. Summary of the Invention
[0007] This invention aims to solve all or part of the problems of the prior art. On one hand, it provides a dynamically reconfigurable packing method that enables communication between two regions while rationally laying out wiring. On the other hand, it provides a reconfigurable module and a corresponding FPGA chip.
[0008] One aspect of the present invention provides a dynamically reconfigurable boxing method, comprising: acquiring logic units of a reconfigurable region and a static region respectively; detecting an interaction signal connecting the static region and the reconfigurable region; creating an input logic unit and an output logic unit for the interface connection between the static region and the reconfigurable region based on the interaction signal; and boxing the reconfigurable region logic unit, the static region logic unit, the input logic unit, and the output logic unit respectively to generate a first boxing file.
[0009] The interaction signal connecting the static area and the reconfigurable area can be detected by searching for the signal connecting the input / output port of the reconfigurable area to the static area. The input logic unit and the output logic unit can also be collectively referred to as the interface logic unit.
[0010] By detecting the interactive signals of the connection, interface units are created. This enables the generation of interface logic units from signals passing through the reconfigurable and static areas throughout the entire module, and bridges these signals. An interface interaction method is employed; it determines whether a signal is connected to the input / output port of the reconfigurable area. Interface logic units are generated based on the interaction between the static and dynamically reconfigurable areas, providing a solution for establishing communication between the static and reconfigurable areas.
[0011] In general, the dynamically reconfigurable boxing method further includes: parsing the first boxing file to obtain the interface logic unit set (current_need_interface_le_list) corresponding to the current signal, denoted as the first signal set; creating new interface logic units in the first signal set in the reconfigurable area; and boxing the newly created interface logic units and all other logic units in the reconfigurable area to generate a second boxing file. When performing dynamic reconfigurable function boxing separately, an incremental boxing method is used. The interface logic units boxed in the reconfigurable area use the information of the interface logic units of the entire module.
[0012] The second packing file has the same structure as the first packing file; the second packing file is used for layout and routing.
[0013] The first packing file is a binary data file containing the full module packing layout and routing results. The process of obtaining the first signal set includes: parsing the first packing file to obtain data information; the data information includes static area data information, dynamic area data information, and interactive interface data information; based on the data information, obtaining the signal set (reference_signal_list) connecting the static area and the reconfigurable area as the second signal set, and obtaining the interface logic unit set (refer_in_out_interface_le_list); retrieving the current signals of the input / output ports of the reconfigurable area connected to the static area, and obtaining the input / output signal set (current_signal_list) as the third signal set; comparing the second signal set and the third signal set to determine whether they are a complete match, and if so, searching for and obtaining the first signal set in the interface logic unit set.
[0014] If the first signal set and the second signal set are not completely matched, an error message is displayed and no further processing is performed.
[0015] The method for finding and obtaining the first signal set includes: searching for and obtaining the interaction interface by matching port names.
[0016] Creating the input logic unit and the output logic unit includes setting attributes for the input logic unit and the output logic unit respectively; setting attributes includes marking the connection interaction interface. By setting attributes, it is easier to use for subsequent layout and routing, and at the same time, when the reconfigurable module is boxed, the interface positions of the entire module can be obtained through the set attributes.
[0017] In the reconfigurable region, a new interface logic unit is created from the first signal set, while keeping the attributes unchanged.
[0018] In another aspect, this invention provides a reconfigurable module. The logic units with reconfigurable functions are packaged using the dynamic reconfigurable packaging method of this invention, including a first logic unit in a static area, a second logic unit in a reconfigurable area, and an interface logic unit. The interface logic unit is communicatively connected to the first logic unit and the second logic unit, respectively. The interface logic unit is divided into an input logic unit and an output logic unit. Each input logic unit corresponds one-to-one with an input port of the reconfigurable area, and each output logic unit corresponds one-to-one with an output port of the reconfigurable area. A connection interface is created between the reconfigurable area and the static area, and this connection interface is determined based on the input and output ports of the reconfigurable area module (the number of interfaces equals the number of input and output ports).
[0019] The interface logic unit is located in the reconfigurable area.
[0020] The present invention also provides an FPGA chip that includes the reconfigurable module of the present invention.
[0021] Compared with the prior art, the main beneficial effects of the present invention are:
[0022] 1. The dynamically reconfigurable packing method of the present invention creates a connection interface between the reconfigurable area and the static area based on the input and output ports, and generates a data interaction interface by parsing the input and output ports of the dynamically reconfigurable area module, thereby realizing data interaction between the static area and the reconfigurable area. This overcomes the difficulty of achieving dynamic local reconfigurability and provides a solution for further optimizing the dynamic reconfigurable function of FPGAs.
[0023] 2. The reconfigurable module of the present invention has corresponding advantages in adopting the dynamic reconfigurable packing method of the present invention, with reasonable wiring layout, and realizes communication between the static area and the reconfigurable area.
[0024] 3. The FPGA chip of the present invention has corresponding advantages by including the reconfigurable module of the present invention. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of a dynamically reconfigurable packing method according to an embodiment of the present invention.
[0026] Figure 2 This is a schematic diagram of the full module packing process according to an embodiment of the present invention.
[0027] Figure 3 This is a schematic diagram of the reconfigurable area packing process according to an embodiment of the present invention.
[0028] Figure 4 This is a schematic diagram of a reconfigurable module according to an embodiment of the present invention. Detailed Implementation
[0029] The technical solutions in specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0030] In this embodiment, the provided dynamically reconfigurable bin packing method, such as Figure 1As shown, the process includes acquiring logic units in the reconfigurable region and the static region respectively; detecting the interaction signals connecting the static region and the reconfigurable region; creating input logic units and output logic units for the interface connection between the static region and the reconfigurable region based on the interaction signals; and boxing the logic units in the reconfigurable region, the logic units in the static region, the input logic units, and the output logic units to generate a first boxing file. In some embodiments, after generating the first boxing file, the first boxing file is parsed to obtain the interface logic unit set (current_need_interface_le_list) corresponding to the current signal, which is denoted as the first signal set; new interface logic units in the first signal set are created in the reconfigurable region; and the newly created interface logic units and logic units in the reconfigurable region other than the newly created interface logic units are boxed to generate a second boxing file.
[0031] Reference Figure 1 and Figure 2 This document provides an exemplary description of the implementation process of the dynamically reconfigurable packing method in this embodiment, but does not limit the invention in any way. In the example, Step 1: The user sets the system as a dynamically reconfigurable system. Step 2: The user sets the physical region where the dynamically reconfigurable system is located; this region is called the reconfigurable region. The area outside this region is called the static region. Step 3: The user designs the dynamically reconfigurable modules. Based on user requirements and the design of the dynamically reconfigurable modules, the user needs to specify reconfigurable modules (replaceable functional modules) in the existing circuit design. The user needs to ensure that the input / output ports of the reconfigurable region modules remain consistent. Step 4: The entire module process needs to save the logic units of the reconfigurable region and the static region to logic unit sets respectively. Step 5: The entire module process needs to detect the signals connecting the static region and the reconfigurable region. Detection is achieved by retrieving the signals connecting the input / output ports of the dynamically reconfigurable region to the static region, i.e., the input / output port signals. Step 6: Using the interface logic units connecting the static region and the reconfigurable region created in Step 5, i.e., the interface logic units for interaction, and setting the attributes of the interface logic units for subsequent layout and routing. In this embodiment, attributes are set, including feature values such as the location coordinates of the interface, marking the connection interaction interface for easy layout and routing later. Simultaneously, during the reconfigurable module binning, the interface positions of the entire module are obtained through the attributes of the interface logic units. Step 7. Bind the logic units obtained in steps 5 and 6 respectively. All logic units of the entire module are saved to the corresponding logic unit set (container). The example of separate binning involves binning the logic unit sets. Step 8. Generate the binned binary file ECP (i.e., the first binning file). The first binning file contains the binning layout and routing results of the entire module, including the data information from steps 4, 5, 6, and 7. In this binning system, in the entire module, interface logic units are generated by signals passing through dynamic and static areas, and the signals are bridged. For example... Figure 2As shown, in the software's execution flow, the first step is to determine whether to execute the entire module process; if so, execution begins. The process includes: detecting the logic units in the static and reconfigurable areas; placing these logic units into containers; detecting the signals of interaction between the static and reconfigurable areas; generating IN (input) and OUT (output) interface logic units based on the interaction signals; packing the logic units in the four containers; completing the packing and generating the ecp file, i.e., the first packing file.
[0032] In this embodiment, in the FPGA system, the EDA software implements the dynamic reconfigurable function by interacting with the static area and the dynamic reconfigurable area, that is, by generating and subsequently using the interaction interface logic unit block, to pack the full module and the dynamic reconfigurable module of the reconfigurable function.
[0033] Reference Figure 3 After step 8 and before the reconfigurable module process, the layout and routing results of the entire module are required. These results are in ECP file format, but are not limited to this format. Figure 3In the illustrated process, first determine whether a reconfigurable module needs to be processed; otherwise, return to the full module PACK (packaging) process described above. Step 9. Obtain the first packing file. Step 10. Parse the first packing file to obtain data information, including but not limited to static area data information, dynamic area data information, and interaction interface data information. Step 11. Obtain the signal set (reference_signal_list) connecting the static area and the reconfigurable area using the ECP from Step 10. Step 12. Obtain the interface logic unit block set (refer_in_out_interface_le_list) using the ECP from Step 10. Step 13. Retrieve the current signals connecting the input / output ports of the dynamic reconfigurable area to the static area to obtain the input / output signal set (current_signal_list) of the reconfigurable module. Step 14. Compare the current_signal_list and reference_signal_list from Steps 11 and 13. If they do not match completely, an error message is displayed, and the process ends without further processing. Step 15. If the matching result in Step 14 is a complete match, find the interface logic unit set (current_need_interface_le_list) corresponding to the current signal in the refer_in_out_interface_le_list of Step 12. Since the interaction interface is generated through input / output ports, the example uses port name for matching. Step 16. Create new interface logic units from current_need_interface_le_list in the reconfigurable area, keeping their attributes unchanged (i.e., the coordinates and other markers of the newly created interface logic units use the attributes set by the interface logic units during the entire module process). Step 17. Pack the interface logic units from Step 16 and other logic units in the reconfigurable area separately, and generate an ECP file. This ECP file has the same structure as the first packing file, only the data is different; the second packing file is used for placement and routing. In this packing system, incremental packing is used when performing dynamic reconfigurable function packing separately. The interface logic units packed in the reconfigurable area use the information of the interface logic units of the entire module.
[0034] This embodiment also provides an FPGA chip that includes a reconfigurable module. The reconfigurable module is as follows: Figure 4As shown, the reconfigurable logic unit is packaged using the dynamic reconfigurable packing method of this invention, including a first logic unit 1 in multiple static areas, a second logic unit 2 in a reconfigurable area, and an interface logic unit 3. The interface logic unit is divided into input logic units and output logic units, respectively stored in the input logic unit set In_cluster1 and the output logic unit set Out_cluster1. The interface logic unit 3 is communicatively connected to the first logic unit 1 and the second logic unit 2 (see reference). Figure 4 The schematic diagram shows the signals connecting the static area to the reconfigurable area (inputs and outputs). In this embodiment, the input logic units correspond one-to-one with the input ports of the reconfigurable area, and the output logic units correspond one-to-one with the output ports of the reconfigurable area. A connection interface is created between the reconfigurable area and the static area. This interface is determined based on the input and output ports of the reconfigurable area module (the number of interfaces equals the number of input and output ports), and is placed in the reconfigurable area and connected to the static area. In this embodiment, dynamic reconfigurability allows any module with consistent input and output ports to be reconfigured, without requiring specific functional modules. For software, it eliminates the need for virtual interfaces based on physical ports; instead, interfaces are generated based on the input and output ports of the reconfigurable area module in the circuit design. The design of the interaction between the static area and the reconfigurable area overcomes the difficulties in implementing dynamic reconfigurability.
[0035] Figure 4 In the example scenario, interface logic unit 3 is located in the reconfigurable area. The reconfigurable module in this embodiment can be fully boxed, and the dynamically reconfigurable area can also be boxed individually. Subsequent system processes can perform placement and routing of the individually packaged reconfigurable logic unit blocks and generate a dynamically reconfigurable code stream. Without power interruption to the FPGA chip, the dynamically reconfigurable code stream is downloaded, changing the functionality of the current FPGA chip system. This results in high system flexibility and saves compilation time.
[0036] The common English terms or letters used in this invention for the purpose of clear description should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.
Claims
1. A dynamically reconfigurable bin packing method, characterized in that: include: Obtain the logical units of the reconfigurable region and the static region respectively; Detect the interaction signal connecting the static region and the reconfigurable region; The input logic unit and output logic unit that create the interface connection between the static area and the reconfigurable area based on the interaction signal; The reconfigurable area logic unit, the static area logic unit, the input logic unit, and the output logic unit are respectively boxed to generate a first boxing file; Parse the first packing file to obtain the set of interface logic units corresponding to the current signal, denoted as the first signal set; The first packing file is a binary data file containing the full module packing layout and routing results; The process of obtaining the first signal set includes: The first packing file is parsed to obtain data information; the data information includes static area data information, dynamic area data information, and interactive interface data information; Based on the data information, the signal set connecting the static area and the reconfigurable area is obtained and denoted as the second signal set, and the interface logic unit set is obtained; Retrieve the current signals connected to the static region from the input / output ports of the reconfigurable region, and obtain the input / output signal set, denoted as the third signal set; Compare the second signal set and the third signal set to determine if they match completely. If they do, search for and obtain the first signal set in the interface logic unit set.
2. The dynamically reconfigurable bin packing method according to claim 1, characterized in that: Also includes: Parse the first packing file to obtain the set of interface logic units corresponding to the current signal, denoted as the first signal set; In the reconfigurable region, a new interface logic unit is created from the first signal set; The newly created interface logic unit and the logic units in the reconfigurable area other than the newly created interface logic unit are respectively boxed to generate a second boxing file.
3. The dynamically reconfigurable bin packing method according to claim 2, characterized in that: The second packing file has the same structure as the first packing file; the second packing file is used for layout and routing.
4. The dynamically reconfigurable packing method according to claim 1, characterized in that: If the first signal set and the second signal set are not completely matched, an error message is displayed and no further processing is performed.
5. The dynamically reconfigurable bin packing method according to claim 1, characterized in that: The method for finding and obtaining the first signal set includes: searching for and obtaining the interaction interface by matching port names.
6. The dynamically reconfigurable packing method according to any one of claims 2 to 5, characterized in that: Creating the input logic unit and the output logic unit includes setting the attributes of the input logic unit and the output logic unit respectively; setting the attributes includes marking the connection interaction interface.
7. The dynamically reconfigurable packing method according to claim 6, characterized in that: In the reconfigurable region, a new interface logic unit is created from the first signal set, while keeping the attributes unchanged.
8. A reconfigurable module, characterized in that: The reconfigurable logic unit is packaged using the dynamic reconfigurable packaging method described in any one of claims 1 to 7, comprising a first logic unit in a static area, a second logic unit in a reconfigurable area, and an interface logic unit; the interface logic unit is communicatively connected to the first logic unit and the second logic unit, respectively. The interface logic unit is divided into an input logic unit and an output logic unit; the input logic unit corresponds one-to-one with the input port of the reconfigurable area, and the output logic unit corresponds one-to-one with the output port of the reconfigurable area.
9. The reconfigurable module according to claim 8, characterized in that: The interface logic unit is located in the reconfigurable area.
10. An FPGA chip, characterized in that: It includes the reconfigurable module as described in claim 8 or 9.