Read / write assist circuit and static random access memory

Abstract

The present disclosure provides a read-write assist circuit and a static random access memory, the read-write assist circuit comprising: a first transistor and a third transistor connected to each other, a second transistor and a fourth transistor connected to each other; a transistor capacitor; and a fifth transistor; wherein the first transistor and the third transistor are connected to a first electrode plate of the transistor capacitor respectively, the second transistor and the fourth transistor are connected to a second electrode plate of the transistor capacitor respectively; the first transistor and the second transistor are connected to a power supply respectively; the third transistor and the fourth transistor are connected to the fifth transistor respectively; the first transistor and the second transistor are not turned on at the same time, so that when the fifth transistor is turned off, the power supply charges the transistor capacitor; and when the fifth transistor is turned on, the charged transistor capacitor raises or lowers the voltage of a storage array.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a read / write auxiliary circuit and a static random access memory. Background Technology

[0002] As the cell supply voltage decreases, the write capability and read stability of SRAM (Static Random Access Memory) decrease. This causes data to fail to be correctly written to the memory cell during write operations, resulting in write failure. During read operations, the data stored inside the SRAM cell is easily altered, causing SRAM malfunction.

[0003] Raising and lowering the power supply voltage of the memory array are two traditional read and write auxiliary circuits, respectively. However, these traditional circuits are single-function. To improve SRAM performance, both read and write auxiliary circuits need to be introduced, resulting in additional area overhead. Therefore, how to reduce the SRAM area while maintaining its read and write performance has become a pressing technical problem. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] To address the existing technical problems, this disclosure provides a read / write auxiliary circuit and a static random access memory, which at least partially solve the above-mentioned technical problems.

[0006] (II) Technical Solution

[0007] This disclosure provides a read / write auxiliary circuit, including: a first transistor and a third transistor connected to each other; a second transistor and a fourth transistor connected to each other; a transistor capacitor; and a fifth transistor; wherein the first transistor and the third transistor are respectively connected to the first plate of the transistor capacitor, and the second transistor and the fourth transistor are respectively connected to the second plate of the transistor capacitor; the first transistor and the second transistor are respectively connected to a power supply; the third transistor and the fourth transistor are respectively connected to the fifth transistor; the first transistor and the second transistor are not turned on simultaneously, so that when the fifth transistor is turned off, the power supply charges the transistor capacitor; and when the fifth transistor is turned on, the charged transistor capacitor raises or lowers the voltage of the storage array.

[0008] Optionally, the read / write auxiliary circuit further includes: a sixth transistor; wherein the first transistor, second transistor, third transistor, fourth transistor, and fifth transistor are all PMOS transistors; when no read / write operation is performed, a high-level read auxiliary enable signal is applied to the first transistor, a low-level write auxiliary enable signal is applied to the second transistor, and a high-level auxiliary circuit enable signal is applied to the fifth transistor; and the first plate is grounded through the conducting sixth transistor, so that the power supply charges the transistor capacitor.

[0009] Optionally, the sixth transistor is an NMOS transistor; wherein, when no read / write operation is performed, a low-level auxiliary circuit enable signal is applied to the sixth transistor.

[0010] Optionally, during a read operation, a low-level read assist enable signal is applied to the first transistor, a high-level write assist enable signal is applied to the second transistor, a high-level write enable signal is applied to the third transistor, a low-level read enable signal is applied to the fourth transistor, and a high-level auxiliary circuit enable signal is applied to the fifth transistor, so that the charged transistor capacitor raises the voltage of the memory array.

[0011] Optionally, during a write operation, a high-level read assist enable signal is applied to the first transistor, a low-level write assist enable signal is applied to the second transistor, a low-level write enable signal is applied to the third transistor, a high-level read enable signal is applied to the fourth transistor, and a low-level auxiliary circuit enable signal is applied to the fifth transistor, so that the charged transistor capacitor pulls down the voltage of the memory array.

[0012] Optionally, the read / write auxiliary circuit further includes a seventh transistor; wherein the seventh transistor is connected to the fifth transistor and to a power supply, such that the power supply supplies power to the memory array when the fifth transistor is turned off.

[0013] Optionally, the seventh transistor is a PMOS transistor; wherein, when the fifth transistor is turned off, a low-level auxiliary circuit turn-off signal is applied to the seventh transistor.

[0014] Optionally, the transistor capacitor is a PMOS transistor capacitor.

[0015] Another aspect of this disclosure provides a static random access memory, including read / write auxiliary circuitry according to any embodiment of this disclosure.

[0016] (III) Beneficial Effects

[0017] Compared with the prior art, the read / write auxiliary circuit and static random access memory provided in this disclosure have at least the following advantages:

[0018] (1) This disclosure enhances the read and write capabilities of the static random access memory by controlling the on and off states of the first, second, third, and fourth transistors connected to the transistor capacitors, thereby allowing the voltage of the memory array to be instantaneously raised or lowered by the transistor capacitors. Furthermore, by combining the first, second, third, and fourth transistors, the read auxiliary circuit and the write auxiliary circuit are integrated into one unit, resulting in a simple structure and reduced area overhead of the static random access memory.

[0019] (2) This disclosure controls the conduction and disconnection of each transistor by adjusting the level of the input signal of each transistor. The adjustment method is simple and facilitates device integration. Attached Figure Description

[0020] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0021] Figure 1 A circuit diagram of a read / write auxiliary circuit according to an embodiment of the present disclosure is shown schematically;

[0022] Figure 2 The schematic diagram illustrates the working principle of a read / write auxiliary circuit according to an embodiment of the present disclosure. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0024] It should be noted that similar or identical parts are referred to by the same reference numerals in the accompanying drawings or description. The technical features of the various embodiments exemplified in the specification can be freely combined to form new solutions without conflict. Furthermore, each claim can stand alone as an embodiment, or the technical features in the various claims can be combined to form new embodiments. In the drawings, the shape or thickness of the embodiments may be enlarged and indicated in a simplified or convenient manner. Moreover, elements or implementations not shown or described in the drawings are those known to those skilled in the art. Additionally, although this document provides examples of parameters containing specific values, it should be understood that the parameters need not be exactly equal to the corresponding values, but can approximate the corresponding values ​​within acceptable error tolerances or design constraints.

[0025] Unless there are technical obstacles or contradictions, the various embodiments described above in this disclosure can be freely combined to form other embodiments, all of which are within the protection scope of this disclosure.

[0026] Although this disclosure has been described in conjunction with the accompanying drawings, the embodiments disclosed in the drawings are intended to illustrate preferred embodiments of this disclosure and should not be construed as limiting the disclosure. The dimensions in the drawings are merely illustrative and should not be construed as limiting the disclosure.

[0027] While some embodiments of the general concept of this disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this disclosure, the scope of which is defined by the claims and their equivalents.

[0028] The read / write auxiliary circuit of this disclosure includes, for example, a first transistor and a third transistor interconnected, a second transistor and a fourth transistor interconnected, a transistor capacitor, and a fifth transistor. The first and third transistors are respectively connected to the first plate of the transistor capacitor, and the second and fourth transistors are respectively connected to the second plate of the transistor capacitor. The first and second transistors are respectively connected to a power supply. The third and fourth transistors are respectively connected to the fifth transistor. The first and second transistors are not simultaneously turned on, such that when the fifth transistor is turned off, the power supply charges the transistor capacitor, and when the fifth transistor is turned on, the charged transistor capacitor raises or lowers the voltage of the memory array.

[0029] Figure 1 A circuit diagram of a read / write auxiliary circuit according to an embodiment of the present disclosure is shown schematically.

[0030] According to embodiments of this disclosure, such as Figure 1 As shown, the read / write auxiliary circuit includes, for example, a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, and a transistor capacitor CAP.

[0031] For example, the sources of the first transistor MP1 and the second transistor MP2 are both connected to the positive terminal of the power supply VDD. The drains of the first transistor MP1 and the sources of the third transistor MP3 are both connected to the left plate of the transistor capacitor CAP. The drains of the second transistor MP2 and the sources of the fourth transistor MP4 are both connected to the right plate of the transistor capacitor CAP. The drains of the third transistor MP3 and the fourth transistor MP4 are both connected to the source of the fifth transistor MP5. The drain of the fifth transistor MP5 is connected to the power supply VDDCORE of the memory array (corresponding to...). Figure 2 The signal V (VDDCORE) in the middle is connected.

[0032] According to embodiments of this disclosure, the read / write auxiliary circuit may further include, for example, a sixth transistor. When no read / write operation is performed, a high-level read auxiliary enable signal is applied to the first transistor, a low-level write auxiliary enable signal is applied to the second transistor, a high-level auxiliary circuit enable signal is applied to the fifth transistor, a low-level auxiliary circuit enable signal is applied to the sixth transistor, and the first plate is grounded through the conducting sixth transistor, thereby charging the transistor capacitor with power.

[0033] For example, the drain of the sixth transistor MN1 is connected to the left plate of the transistor capacitor CAP. And the drain of the sixth transistor MN1 is connected to the power supply VDDCORE of the memory array (corresponding to...). Figure 2 The signal V (VDDCORE) in the middle is connected.

[0034] For example, regarding the input signals of each transistor, the gate of the first transistor MP1 and the read-assist enable signal ReadEn (corresponding to...) Figure 2 The signal V (ReadEn) in the middle is connected, and the gate of the second transistor MP2 is connected to the write auxiliary enable signal WriteEn (corresponding to Figure 2 The signal V(WriteEn) in the circuit is connected. The gate of the fifth transistor MP5 is connected to the auxiliary circuit enable signal AssistEn (corresponding to...). Figure 2 The signal V (AssistEn) in the middle. The gate of the sixth transistor MN1 is connected to the auxiliary circuit enable signal AssistEn (corresponding to...). Figure 2 The signal V(AssistEn) in the signal is connected to the source of the sixth transistor MN1, which is connected to ground GND.

[0035] For example, transistors MP1, MP2, MP3, MP4, and MP5 are all PMOS transistors. The sixth transistor MN1 is an NMOS transistor. When no read or write operations are performed: the auxiliary circuit enable signal AssistEn is high, the read auxiliary enable signal ReadEn is high, and the write auxiliary enable signal WriteEn is low. At this time, transistors MP1 and MP5 are off, while transistors MP2 and MN1 are on. The left plate of transistor capacitor CAP is grounded through transistor MN1, and the right plate is connected to the power supply VDD through transistor MP2, thus keeping transistor capacitor CAP in a charging state.

[0036] According to embodiments of this disclosure, when the transistor capacitor CAP is charging, the voltage of the memory array is VDD. During a read operation, a low-level read assist enable signal is applied to the first transistor, a high-level write assist enable signal is applied to the second transistor, a high-level write enable signal is applied to the third transistor, a low-level read enable signal is applied to the fourth transistor, and a high-level auxiliary circuit enable signal is applied to the fifth transistor, so that the charged transistor capacitor raises the voltage of the memory array.

[0037] For example, the gate of the third transistor is connected to the write enable signal WEN (corresponding to...). Figure 2 The signal V(WEN) in the middle, the gate of the fourth transistor is connected to the read enable signal WE (corresponding to Figure 2 The signal V(WE) in the memory is used. During a read operation: the auxiliary circuit enable signal AssistEn is low, the read auxiliary enable signal ReadEn is low, the write auxiliary enable signal WriteEn is high, the read enable signal WE is low, and the write enable signal WEN is high. At this time, the first transistor MP1, the fourth transistor MP4, and the fifth transistor MP5 are turned on, while the second transistor MP2, the third transistor MP3, and the sixth transistor MN1 are turned off. Since the voltage across the capacitor does not change abruptly, the voltage VDDCORE of the memory array will change from the voltage VDD to a voltage that is momentarily raised by the first transistor MP1, the transistor capacitor CAP, the fourth transistor MP4, and the fifth transistor MP5, thereby improving the read speed of the SRAM.

[0038] According to embodiments of this disclosure, during a write operation, a high-level read assist enable signal is applied to the first transistor, a low-level write assist enable signal is applied to the second transistor, a low-level write enable signal is applied to the third transistor, a high-level read enable signal is applied to the fourth transistor, and a low-level auxiliary circuit enable signal is applied to the fifth transistor, so that the charged transistor capacitor pulls down the voltage of the memory array.

[0039] For example, during a write operation: the auxiliary circuit enable signal AssistEn is low, the read auxiliary enable signal ReadEn is high, the write auxiliary enable signal WriteEn is low, the read enable signal WE is high, and the write enable signal WEN is low. At this time, the second transistor MP2, the third transistor MP3, and the fifth transistor MP5 are turned on, while the first transistor MP1, the fourth transistor MP4, and the sixth transistor MN1 are turned off. Since the voltage across the capacitor does not change abruptly, the storage array voltage VDDCORE will change from voltage VDD to the voltage after being momentarily pulled low by the second transistor MP2, transistor capacitor CAP, the third transistor MP3, and the fifth transistor MP5, making it easier for data to be written into the storage cells.

[0040] According to embodiments of this disclosure, the read / write auxiliary circuit may further include, for example, a seventh transistor. The seventh transistor is connected to the fifth transistor and to a power supply such that the power supply supplies power to the memory array when the fifth transistor is turned off.

[0041] For example, the power supply VDDCORE of the memory array is connected to the power supply VDD via the seventh transistor MP6. The source of the seventh transistor MP6 is connected to the power supply VDD, and the gate of the seventh transistor MP6 is connected to the auxiliary circuit turn-off signal AssistEnb (corresponding to...). Figure 2 The signal V (AssistEnb) in the middle.

[0042] For example, the seventh transistor MP6 is a PMOS transistor. When the fifth transistor MP5 is off, a low-level auxiliary circuit shutdown signal AssistEnb is applied to the seventh transistor MP6. When the auxiliary circuit shutdown signal AssistEnb is low, the seventh transistor MP6 is on; when the auxiliary circuit shutdown signal AssistEnb is high, the seventh transistor MP6 is off.

[0043] Figure 2 The schematic diagram illustrates the working principle of a read / write auxiliary circuit according to an embodiment of the present disclosure.

[0044] According to embodiments of this disclosure, such as Figure 2As shown, when no read / write operations are performed, transistors MP2, MN1, and MP6 are turned on, while MP1 and MP5 are turned off. The right plate of transistor capacitor CAP is connected to power supply VDD via transistor MP2 for charging. The power supply VDDCORE of the memory array is connected to power supply VDD, and the voltage remains stable. When a read operation is performed, transistors MP1, MP4, and MP5 are turned on. The left plate of transistor capacitor CAP is connected to power supply VDD via transistor MP1, and the right plate of transistor capacitor CAP is connected to the power supply VDDCORE of the memory array via transistors MP4 and MP5. Due to the voltage difference between the two plates of transistor capacitor CAP, and the fact that the voltage across the capacitor does not change abruptly, the voltage of the power supply VDDCORE of the memory array is momentarily boosted, thereby increasing the read speed of the SRAM. After the read operation ends, transistor capacitor CAP returns to the charging state. During a write operation, transistors MP2, MP3, and MP5 are turned on. The right plate of transistor capacitor CAP is connected to the power supply VDD through transistor MP2, and the left plate of transistor capacitor CAP is connected to the power supply VDDCORE of the memory array through transistors MP3 and MP5. Because there is a voltage difference between the two plates of transistor capacitor CAP, and the voltage across the capacitor does not change abruptly, the power supply VDDCORE voltage of the memory array is momentarily pulled down, making it easier for data to be written into the memory cell.

[0045] Optionally, the transistor capacitor CAP is a PMOS transistor capacitor.

[0046] In summary, this disclosure presents a read / write auxiliary circuit. Within the same circuit structure, by configuring input signals to control the connection method of the two plates of the transistor capacitor, the power supply voltage of the memory array is instantaneously raised or lowered, thereby enhancing the read / write capability of the SRAM. This achieves the integration of the read / write auxiliary circuit within the same circuit structure, reducing the area overhead of the static random access memory.

[0047] In another aspect, this disclosure provides a static random access memory (SRAM) including a read / write auxiliary circuit according to any embodiment of this disclosure. The read / write auxiliary circuit of any embodiment of this disclosure reduces the area of ​​the SRAM while ensuring its read / write performance, thus facilitating integration.

[0048] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to a specific order or hierarchy.

[0049] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted when they may cause confusion in understanding this disclosure. Furthermore, the shapes, sizes, and positional relationships of the components in the drawings do not reflect their actual size, scale, or actual positional relationships.

[0050] In the detailed description above, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, this disclosure is in a state of having fewer features than all of the features of the single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, with each claim representing a separate preferred embodiment of this disclosure.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly specified. The term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as "including" is used as a conjunction in the claims. The use of any term "or" in the specification or claims is intended to mean "non-exclusive or."

[0052] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A read / write auxiliary circuit, characterized in that, include: The first and third transistors are interconnected, as are the second and fourth transistors; Transistor capacitor; as well as The fifth transistor; Wherein, the first transistor and the third transistor are respectively connected to the first plate of the transistor capacitor, and the second transistor and the fourth transistor are respectively connected to the second plate of the transistor capacitor; The first transistor and the second transistor are respectively connected to a power supply; The third transistor and the fourth transistor are respectively connected to the fifth transistor; The first transistor and the second transistor are not turned on simultaneously, such that when the fifth transistor is turned off, the power supply charges the transistor capacitor; and When the fifth transistor is turned on, the charged transistor capacitor raises or lowers the voltage of the memory array; In the case of a read operation, a low-level read assist enable signal is applied to the first transistor, a high-level write assist enable signal is applied to the second transistor, a high-level write enable signal is applied to the third transistor, a low-level read enable signal is applied to the fourth transistor, and a high-level auxiliary circuit enable signal is applied to the fifth transistor, so that the charged transistor capacitor raises the voltage of the memory array. During a write operation, a high-level read assist enable signal is applied to the first transistor, a low-level write assist enable signal is applied to the second transistor, a low-level write enable signal is applied to the third transistor, a high-level read enable signal is applied to the fourth transistor, and a low-level auxiliary circuit enable signal is applied to the fifth transistor, so that the charged transistor capacitor pulls down the voltage of the memory array.

2. The circuit according to claim 1, characterized in that, Also includes: The sixth transistor; Wherein, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all PMOS transistors; Without any read / write operations, a high-level read assist enable signal is applied to the first transistor, a low-level write assist enable signal is applied to the second transistor, and a high-level auxiliary circuit enable signal is applied to the fifth transistor; and The first plate is grounded through the conducting sixth transistor, so that the power supply charges the transistor capacitor.

3. The circuit according to claim 2, characterized in that, The sixth transistor is an NMOS transistor; In the absence of read / write operations, a low-level auxiliary circuit enable signal is applied to the sixth transistor.

4. The circuit according to claim 1, characterized in that, Also includes: The seventh transistor; The seventh transistor is connected to the fifth transistor and to the power supply, such that the power supply supplies power to the memory array when the fifth transistor is turned off.

5. The circuit according to claim 4, characterized in that, The seventh transistor is a PMOS transistor; When the fifth transistor is turned off, a low-level auxiliary circuit turn-off signal is applied to the seventh transistor.

6. The circuit according to claim 2, characterized in that, The transistor capacitor is a PMOS transistor capacitor.

7. A static random access memory, characterized in that, Includes the read / write auxiliary circuit as described in any one of claims 1 to 6.

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