A gm-tia based low power receiver analog front end equalization circuit

Abstract

This invention discloses a low-power receiver analog front-end equalization circuit based on gm-TIA, belonging to the fields of integrated circuits and communications. The CTLE of this invention includes an adjustable source degradation structure and a transconductance enhancement structure. The adjustable source degradation structure can change the DC gain at low frequencies by altering the control voltage value; the transconductance enhancement structure improves the DC gain at high frequencies compared to traditional CTLEs. The TIA of this invention includes a single-stage differential structure and a super-source-level follower structure. The super-source-level follower structure solves the trade-off between large size and high parasitic capacitance. The gm-TIA topology, composed of a feedback resistor and a feedback inductor, further enhances the overall equalization capability of the circuit. This invention is simple to design, has high gain and energy efficiency, and low design cost; it can meet the needs of future high-speed data transmission and provides a reliable equalization solution for inter-symbol interference problems generated during data transmission.

Description

Technical Field

[0001] This invention relates to a low-power receiver analog front-end equalization circuit based on gm-TIA, belonging to the fields of integrated circuits and communications. Background Technology

[0002] In the era of rapid development of IoT technology, high-speed serial interfaces (SerDes) are widely used for data transmission between chips and backplanes. However, design errors in filters and variations in channel characteristics inevitably lead to inter-symbol interference (ISI) at system sampling times, ultimately severely impacting system performance. Therefore, equalization circuits are needed to compensate for this. In high-speed data transmission, frequency-domain equalization has been replaced by time-domain equalization, and nonlinear time-domain equalization is currently receiving significant attention as a key module in the receiver analog front-end. In integrated circuit (IC) design, critical issues such as high bandwidth, low power consumption, and feature size urgently need to be addressed. Therefore, the design of a high-efficiency, low-power, and highly integrated CTLE receiver analog front-end circuit is crucial.

[0003] Patent CN110022277A discloses a CTLE with adjustable power consumption, and the circuit design of this solution is as follows: Figure 8 As shown, it includes a CTLE circuit and a bias circuit connected to the CTLE circuit. The bias circuit consists of several sub-circuits connected in sequence with MOS transistors, so as to achieve adjustable power consumption of the equalizer while keeping the basic function of the CTLE structure unchanged, thus meeting the low power consumption requirements.

[0004] Although this solution can meet the system's low power consumption requirements, CTLE still uses a traditional source degradation structure, and the circuit's high-frequency compensation capability is limited, making it difficult to achieve higher-speed signal transmission. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a low-power receiver analog front-end equalization circuit based on gm-TIA, the technical solution of which is as follows:

[0006] The first objective of this invention is to provide a receiver analog front-end equalization circuit, comprising a cascaded continuous-time linear equalizer (CTLE) and a transimpedance amplifier (TIA), wherein the CTLE and TIA adopt a gm-TIA topology.

[0007] The output and input terminals of the transimpedance amplifier TIA are connected in series with a feedback resistor and a feedback inductor.

[0008] Optionally, the continuous-time linear equalizer CTLE includes: an adjustable source degradation structure and a transconductance enhancement structure;

[0009] The adjustable source degradation structure includes: a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, a third NMOS transistor N3, and a fourth NMOS transistor N4;

[0010] The gate of the first NMOS transistor N1 is connected to the first input signal as the first input terminal of the CTLE. The drain of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1. The source of the first NMOS transistor N1 is connected to the drain of the third NMOS transistor N3 and the adjustable source degradation circuit.

[0011] The gate of the second NMOS transistor N2 is connected to the second input signal as the second input terminal of CTLE. The drain of the second NMOS transistor N2 is connected to the drain of the second PMOS transistor P2. The source of the second NMOS transistor N2 is connected to the drain of the fourth NMOS transistor N4 and the adjustable source degradation circuit.

[0012] The gate of the first PMOS transistor P1 is connected to the PMOS bias voltage input by the PMOS current mirror circuit, the source of the first PMOS transistor P1 is connected to the power supply VDD, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1.

[0013] The gate of the second PMOS transistor P2 is connected to the PMOS bias voltage input of the PMOS current mirror circuit, the source of the second PMOS transistor P2 is connected to the power supply VDD, and the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2.

[0014] The gate of the third NMOS transistor N3 is connected to the NMOS current mirror circuit input NMOS bias voltage, the source of the third NMOS transistor N3 is grounded, and the drain of the third NMOS transistor N3 is connected to the source of the first NMOS transistor N1.

[0015] The gate of the fourth NMOS transistor N4 is connected to the NMOS current mirror circuit input NMOS bias voltage, the source of the fourth NMOS transistor N4 is grounded, and the drain of the fourth NMOS transistor N4 is connected to the source of the second NMOS transistor N2.

[0016] The transconductance enhancement structure includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first resistor R1, and a second resistor R2.

[0017] The gate of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor P1, respectively. The source of the third PMOS transistor P3 is connected to the power supply VDD, and the drain is connected to the adjustable source degradation circuit and the source of the first NMOS transistor N1.

[0018] The gate of the fourth PMOS transistor P4 is connected to the drain of the second NMOS transistor N2 and the drain of the second PMOS transistor, respectively. The source of the fourth PMOS transistor is connected to the power supply VDD, and the drain is connected to the adjustable source degradation circuit and the source of the second NMOS transistor N2.

[0019] The gate of the fifth PMOS transistor P5 is connected to the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor P1, respectively. The source of the fifth PMOS transistor P5 is connected to the power supply VDD, and the drain is connected to the first output terminal of CTLE and the first terminal of the first resistor R1.

[0020] The gate of the sixth PMOS transistor P6 is connected to the drain of the second NMOS transistor N2 and the drain of the second PMOS transistor P2. The source of the sixth PMOS transistor P6 is connected to the power supply VDD, and the drain is connected to the second output terminal of CTLE and the first terminal of the second resistor R2.

[0021] The first end of the first resistor R1 is connected to the drain of the fifth PMOS transistor P5 and the first output terminal of the CTLE, and the second end of the first resistor R1 is grounded.

[0022] The first end of the second resistor R2 is connected to the drain of the sixth PMOS transistor P6 and the second output terminal of CTLE, and the second end of the second resistor R2 is grounded.

[0023] The adjustable source degradation circuit changes the overall low-frequency DC gain of the circuit by adjusting the resistance value, thereby adapting to signals with different transmission rates.

[0024] Optionally, the adjustable source degradation circuit includes: a first source degradation resistor Rg1, a second source degradation resistor Rg2, a first source degradation capacitor Cg1, a second source degradation capacitor Cg2, and a first NMOS switch Nt1;

[0025] The first source degradation resistor Rg1 and the second source degradation resistor Rg2 are connected in series and then connected across the drains of the first NMOS transistor N1 and the second NMOS transistor N2, and are connected in parallel with the first NMOS switch Nt1.

[0026] After the first source degradation capacitor Cg1 and the second source degradation capacitor Cg2 are connected in series, they are connected across the drain of the first NMOS transistor N1 and the second NMOS transistor N2, and are connected in parallel with the first source degradation resistor Rg1 and the second source degradation resistor Rg2, and are also connected in parallel with the first NMOS switch Nt1.

[0027] The gate of the first NMOS switch Nt1 is connected to the tuning voltage input as the control voltage, the drain is connected to the source of the first NMOS transistor N1, and the source is connected to the source of the second NMOS transistor N2.

[0028] Optionally, the transimpedance amplifier (TIA) includes: a single-stage differential structure and a super source follower structure;

[0029] The first-level differential structure includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a seventh PMOS transistor P7, and an eighth PMOS transistor P8;

[0030] The gate of the fifth NMOS transistor N5 is connected to the drain of the ninth NMOS transistor N9 in the super source follower, the drain of the fifth NMOS transistor N5 is connected to the drain of the seventh PMOS transistor P7, and the source of the fifth NMOS transistor N5 is connected to the drain of the seventh NMOS transistor P7 and the first output terminal of the TIA.

[0031] The gate of the sixth NMOS transistor N6 is connected to the drain of the tenth NMOS transistor N10 in the super source follower, the drain of the sixth NMOS transistor N6 is connected to the drain of the eighth PMOS transistor P8, and the source of the sixth NMOS transistor N6 is connected to the drain of the eighth NMOS transistor P8 and the second output terminal of TIA.

[0032] The gate of the seventh PMOS transistor P7 is connected to the input bias voltage of the PMOS current mirror circuit, the source of the seventh PMOS transistor P7 is connected to the power supply VDD, and the drain of the seventh PMOS transistor P7 is connected to the drain of the fifth NMOS transistor N5.

[0033] The gate of the eighth PMOS transistor P8 is connected to the input bias voltage of the PMOS current mirror circuit, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the drain of the eighth PMOS transistor P8 is connected to the drain of the sixth NMOS transistor N6.

[0034] The gate of the seventh NMOS transistor N7 is connected to the input bias voltage of the NMOS current mirror circuit, the source of the seventh NMOS transistor N7 is grounded, and the drain of the seventh NMOS transistor N7 is connected to the source of the fifth NMOS transistor and the first output terminal of the TIA.

[0035] The gate of the eighth NMOS transistor N8 is connected to the input bias voltage of the NMOS current mirror circuit, the source of the eighth NMOS transistor N8 is grounded, and the drain of the eighth NMOS transistor N8 is connected to the source of the sixth NMOS transistor N6 and the second output terminal of TIA.

[0036] The super source follower includes: a ninth NMOS transistor N9, a tenth NMOS transistor N10, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;

[0037] The gate of the ninth NMOS transistor N9 is connected to the first output terminal of CTLE as the first input terminal of TIA. The drain of the ninth NMOS transistor N9 is connected to the second terminal of the third resistor R3 and the gate of the fifth NMOS transistor N5. The source of the ninth NMOS transistor N9 is connected to the first terminal of the fifth resistor R5.

[0038] The first end of the third resistor R3 is connected to the power supply VDD, and the second end of the third resistor R3 is connected to the drain of the ninth NMOS transistor N9.

[0039] The first end of the fifth resistor R5 is connected to the source of the ninth NMOS transistor N9, and the second end of the fifth resistor R5 is grounded.

[0040] The gate of the tenth NMOS transistor N10 is connected to the second output terminal of CTLE as the second input terminal of TIA. The drain of the tenth NMOS transistor N10 is connected to the second terminal of the fourth resistor R4 and the gate of the sixth NMOS transistor N6. The source of the ninth NMOS transistor N9 is connected to the first terminal of the sixth resistor R6.

[0041] The first end of the fourth resistor R4 is connected to the power supply VDD, and the second end of the fourth resistor R4 is connected to the drain of the tenth NMOS transistor N10.

[0042] The first end of the sixth resistor R6 is connected to the source of the tenth NMOS transistor N10, and the second end of the sixth resistor R6 is grounded.

[0043] Optionally, the feedback resistor and feedback inductor include: a seventh resistor R7, an eighth resistor R8, a first inductor L1, and a second inductor L2;

[0044] The first end of the first inductor L1 is connected to the first input terminal of TIA, and the second end of the first inductor L1 is connected to the first end of the seventh resistor R7.

[0045] The first end of the seventh resistor R7 is connected to the second end of the first inductor L1, and the second end of the seventh resistor R7 is connected to the first output terminal of the TIA.

[0046] The first end of the second inductor L2 is connected to the second input terminal of the TIA, and the second end of the second inductor L2 is connected to the first end of the eighth resistor R8;

[0047] The first end of the eighth resistor R8 is connected to the second end of the second inductor L2, and the second end of the eighth resistor R8 is connected to the second output terminal of the TIA.

[0048] Optionally, the transfer function of CTLE is expressed as:

[0049]

[0050] Where, ω Z For zero, ω P1 For the first pole, ω P2 The second pole has the following values:

[0051]

[0052] Among them, g m R is the transconductance of the first NMOS transistor N1 and the second NMOS transistor N2, and A0 is the gain applied to the transconductance of the first NMOS transistor N1 and the second NMOS transistor N2, where R S C is the source degradation resistance value. S R is the source degradation capacitance value. L C represents the parasitic load resistance value of the CTLE output node. L This represents the parasitic load capacitance value of the CTLE output node.

[0053] Optionally, the DC gain of the CTLE is:

[0054]

[0055] Optionally, the transfer function formula for the receiver analog front-end circuit is:

[0056]

[0057] in:

[0058]

[0059]

[0060] In the above formula, for ease of expression, let

[0061] Among them, A DC G represents the overall DC gain. m,TIA R represents the total transconductance of TIA. F Indicates the feedback resistance value, C LLR represents the parasitic load capacitance value of the TIA output node. D L represents the parasitic load resistance value of the TIA output node. F Indicates the feedback inductance value

[0062] Optionally, the values ​​of the third resistor R3 and the fourth resistor R4 are greater than the values ​​of the fifth resistor R5 and the sixth resistor R6.

[0063] The second objective of this invention is to provide a receiver analog front-end equalization method, implemented based on the aforementioned receiver analog front-end equalization circuit, comprising: receiving an input AC signal from the first and second input terminals of the CTLE, and outputting a signal from the first and second output terminals of the TIA after equalization by the receiver analog front-end equalization circuit.

[0064] The beneficial effects of this invention are:

[0065] The low-power receiver analog front-end equalization circuit based on gm-TIA of the present invention includes a continuous-time linear equalizer (CTLE) and a transimpedance amplifier (TIA), and adopts a gm-TIA structure as a whole, which can significantly improve the performance of the circuit.

[0066] Furthermore, the continuous-time linear equalizer (CTLE) of this invention utilizes a third and fourth PMOS transistor as a transconductance enhancement circuit. It samples signals from the drains of the first and second NMOS transistors and establishes feedback by connecting the drains to the source degradation resistor and capacitor. The third and fourth PMOS transistors can be equivalent to an operational amplifier. Based on their virtual short and virtual open circuits, they lock the drain voltages of the first and second NMOS transistors and sample their output voltages. Since the sampled voltage is the output voltage, to ensure that the output voltage sampled by the feedback equals the input voltage, the output impedance of the circuit is reduced, effectively increasing the transconductance gm. The fifth and sixth PMOS transistors are connected to the output terminal and the load resistor, acting as source followers to improve linearity and reduce gain loss caused by low impedance. The source-degraded capacitor and resistor still function as a high-frequency pass and low-frequency block, adding zeros and poles to the basic filter structure to meet the high-gain requirement at high frequencies. The addition of an adjustable structure allows the resistance value to be adjusted according to different input voltages, thereby changing the overall low-frequency DC gain of the circuit and adapting to signals with different transmission rates. Compared with the traditional source-degraded CTLE, the CTLE designed in this invention can achieve better equalization effect with a smaller area and lower power consumption.

[0067] Furthermore, the transimpedance amplifier (TIA) of this invention improves upon the traditional differential amplifier structure. In the traditional gm-TIA structure, there is a trade-off between the DC operating point and circuit performance. To obtain a suitable DC operating point, the PMOS size needs to be increased, which introduces a large parasitic capacitance at the output node, resulting in a reduction in circuit bandwidth. To solve this problem, a super source follower structure is used in the TIA design. This structure can reduce output impedance by increasing the total current flowing into the output node, avoiding the trade-off between gain and bandwidth caused by excessively large PMOS size.

[0068] The overall circuit power consumption of this invention is only 9.7mW, which is lower than that of traditional equalizers. At the same time, it has a simple structure that is easy to implement and has a better equalization effect. Attached Figure Description

[0069] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0070] Figure 1 This is a complete architecture diagram of the receiver analog front-end equalization circuit of the present invention.

[0071] Figure 2 This is an adjustable source degradation circuit of the present invention.

[0072] Figure 3 The present invention provides an equivalent circuit diagram of an NMOS input current mirror and a PMOS input current mirror, wherein (a) is an NMOS input current mirror and (b) is a PMOS input current mirror.

[0073] Figure 4 This is a frequency response curve of the analog front end of the integrated receiver of the present invention as the source degradation circuit adjusts the voltage Vctrl.

[0074] Figure 5 The insertion loss and return loss curves for a PCIe 3.0 channel according to the present invention are shown.

[0075] Figure 6 This is an eye diagram of the receiver circuit with and without the PCIe 3.0 channel transmission line turned on and off at 10Gbps, according to an embodiment of the present invention.

[0076] Figure 7 This is an eye diagram of the receiver circuit with and without the PCIe 3.0 channel transmission line turned on and off at 14Gbps, according to an embodiment of the present invention.

[0077] Figure 8 This is a circuit diagram of a power-adjustable CTLE in the prior art.

[0078] The annotations in the attached figures are explained as follows:

[0079] 1. CTLE circuit, 101, CTLE first input terminal, 102, CTLE second input terminal, 103, PMOS transistor bias voltage CTLE first input terminal, 104, PMOS transistor bias voltage CTLE second input terminal, 105, NMOS transistor bias voltage CTLE first input terminal, 106, NMOS transistor bias voltage CTLE second input terminal, 107, CTLE first output terminal, 108, CTLE second output terminal.

[0080] 2. TIA circuit: 201, TIA first input terminal; 202, TIA second input terminal; 203, PMOS transistor bias voltage TIA first input terminal; 204, PMOS transistor bias voltage TIA second input terminal; 205, NMOS transistor bias voltage TIA first input terminal; 206, NMOS transistor bias voltage TIA second input terminal; 207, TIA first output terminal; 208, TIA second output terminal.

[0081] 3. Feedback resistor and feedback inductor.

[0082] 4. Return loss.

[0083] 5. Insertion loss.

[0084] N1, first NMOS transistor; N2, second NMOS transistor; P1, first PMOS transistor; P2, second PMOS transistor; P3, third PMOS transistor; P4, fourth PMOS transistor; N3, third NMOS transistor; N4, fourth NMOS transistor; P5, fifth PMOS transistor; P6, sixth PMOS transistor; R1, first resistor; R2, second resistor; C1, first capacitor; C2, second capacitor; N5, fifth NMOS transistor; N6, sixth NMOS transistor; N7, seventh NMOS transistor; N8, eighth NMOS transistor; N9, ninth NMOS transistor; N10, the... Ten NMOS transistors, P7 (seventh PMOS transistor), P8 (eighth PMOS transistor), R3 (third resistor), R4 (fourth resistor), R5 (fifth resistor), R6 (sixth resistor); L1 (first inductor), L2 (second inductor), R7 (seventh resistor), R8 (eighth resistor); C3 (third capacitor), C4 (fourth capacitor); Rg1 (first source degradation resistor), Rg2 (second source degradation resistor), Cg1 (first source degradation capacitor), Cg2 (second source degradation capacitor); Nt1 (NMOS switch); Vbiasp (PMOS bias voltage), Vbiasn (NMOS bias voltage). Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0086] Example 1:

[0087] This embodiment provides a receiver analog front-end equalization circuit, including a cascaded continuous-time linear equalizer (CTLE) and a transimpedance amplifier (TIA), wherein the continuous-time linear equalizer (CTLE) and the transimpedance amplifier (TIA) adopt a gm-TIA topology.

[0088] The output and input terminals of the transimpedance amplifier TIA are connected in series with a feedback resistor and a feedback inductor.

[0089] Example 2:

[0090] This embodiment provides a receiver analog front-end equalization circuit, including a cascaded continuous-time linear equalizer (CTLE) and a transimpedance amplifier (TIA), wherein the continuous-time linear equalizer (CTLE) and the transimpedance amplifier (TIA) adopt a gm-TIA topology.

[0091] The output and input terminals of the transimpedance amplifier TIA are connected in series with a feedback resistor and a feedback inductor.

[0092] The continuous-time linear equalizer (CTLE) includes: an adjustable source degradation structure and a transconductance enhancement structure.

[0093] The adjustable source degradation structure in this embodiment includes: a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, a third NMOS transistor N3, and a fourth NMOS transistor N4;

[0094] The gate of the first NMOS transistor N1 is connected to the first input signal as the first input terminal of CTLE. The drain of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1. The source of the first NMOS transistor N1 is connected to the drain of the third NMOS transistor N3 and the adjustable source degradation circuit.

[0095] The gate of the second NMOS transistor N2 is connected to the second input signal as the second input terminal of CTLE. The drain of the second NMOS transistor N2 is connected to the drain of the second PMOS transistor P2. The source of the second NMOS transistor N2 is connected to the drain of the fourth NMOS transistor N4 and the adjustable source degradation circuit.

[0096] The gate of the first PMOS transistor P1 is connected to the PMOS bias voltage input by the PMOS current mirror circuit, the source of the first PMOS transistor P1 is connected to the power supply VDD, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1.

[0097] The gate of the second PMOS transistor P2 is connected to the PMOS bias voltage input by the PMOS current mirror circuit, the source of the second PMOS transistor P2 is connected to the power supply VDD, and the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2.

[0098] The gate of the third NMOS transistor N3 is connected to the NMOS bias voltage input by the NMOS current mirror circuit, the source of the third NMOS transistor N3 is grounded, and the drain of the third NMOS transistor N3 is connected to the source of the first NMOS transistor N1.

[0099] The gate of the fourth NMOS transistor N4 is connected to the NMOS bias voltage input by the NMOS current mirror circuit, the source of the fourth NMOS transistor N4 is grounded, and the drain of the fourth NMOS transistor N4 is connected to the source of the second NMOS transistor N2.

[0100] The transconductance enhancement structure in this embodiment includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first resistor R1, and a second resistor R2.

[0101] The gate of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor P1, respectively. The source of the third PMOS transistor P3 is connected to the power supply VDD, and the drain is connected to the adjustable source degradation circuit and the source of the first NMOS transistor N1.

[0102] The gate of the fourth PMOS transistor P4 is connected to the drain of the second NMOS transistor N2 and the drain of the second PMOS transistor, respectively. The source of the fourth PMOS transistor is connected to the power supply VDD, and the drain is connected to the adjustable source degradation circuit and the source of the second NMOS transistor N2.

[0103] The gate of the fifth PMOS transistor P5 is connected to the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor P1, respectively. The source of the fifth PMOS transistor P5 is connected to the power supply VDD, and the drain is connected to the first output terminal of CTLE and the first terminal of the first resistor R1.

[0104] The gate of the sixth PMOS transistor P6 is connected to the drain of the second NMOS transistor N2 and the drain of the second PMOS transistor P2. The source of the sixth PMOS transistor P6 is connected to the power supply VDD, and the drain is connected to the second output terminal of CTLE and the first terminal of the second resistor R2.

[0105] The first end of the first resistor R1 is connected to the drain of the fifth PMOS transistor P5 and the first output terminal of CTLE, and the second end of the first resistor R1 is grounded.

[0106] The first end of the second resistor R2 is connected to the drain of the sixth PMOS transistor P6 and the second output terminal of CTLE, and the second end of the second resistor R2 is grounded.

[0107] The adjustable source degradation circuit changes the overall low-frequency DC gain of the circuit by adjusting the resistance value, thereby adapting to signals with different transmission rates.

[0108] The adjustable source degradation circuit in this embodiment includes: a first source degradation resistor Rg1, a second source degradation resistor Rg2, a first source degradation capacitor Cg1, a second source degradation capacitor Cg2, and a first NMOS switch Nt1;

[0109] The first source degradation resistor Rg1 and the second source degradation resistor Rg2 are connected in series and then connected across the drains of the first NMOS transistor N1 and the second NMOS transistor N2, and are connected in parallel with the first NMOS switch Nt1.

[0110] After the first source degradation capacitor Cg1 and the second source degradation capacitor Cg2 are connected in series, they are connected across the drain of the first NMOS transistor N1 and the second NMOS transistor N2, and are connected in parallel with the first source degradation resistor Rg1 and the second source degradation resistor Rg2, and are also connected in parallel with the first NMOS switch Nt1.

[0111] The gate of the first NMOS switch Nt1 is connected to the tuning voltage input as the control voltage, the drain is connected to the source of the first NMOS transistor N1, and the source is connected to the source of the second NMOS transistor N2.

[0112] The transimpedance amplifier (TIA) in this embodiment includes: a single-stage differential structure and a super source follower structure;

[0113] The first-level differential structure in this embodiment includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a seventh PMOS transistor P7, and an eighth PMOS transistor P8;

[0114] The gate of the fifth NMOS transistor N5 is connected to the drain of the ninth NMOS transistor N9 in the super source follower. The drain of the fifth NMOS transistor N5 is connected to the drain of the seventh PMOS transistor P7. The source of the fifth NMOS transistor N5 is connected to the drain of the seventh NMOS transistor P7 and the first output terminal of TIA.

[0115] The gate of the sixth NMOS transistor N6 is connected to the drain of the tenth NMOS transistor N10 in the super source follower, the drain of the sixth NMOS transistor N6 is connected to the drain of the eighth PMOS transistor P8, and the source of the sixth NMOS transistor N6 is connected to the drain of the eighth NMOS transistor P8 and the second output terminal of TIA.

[0116] The gate of the seventh PMOS transistor P7 is connected to the input bias voltage of the PMOS current mirror circuit, the source of the seventh PMOS transistor P7 is connected to the power supply VDD, and the drain of the seventh PMOS transistor P7 is connected to the drain of the fifth NMOS transistor N5.

[0117] The gate of the eighth PMOS transistor P8 is connected to the input bias voltage of the PMOS current mirror circuit, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the drain of the eighth PMOS transistor P8 is connected to the drain of the sixth NMOS transistor N6.

[0118] The gate of the seventh NMOS transistor N7 is connected to the input bias voltage of the NMOS current mirror circuit, the source of the seventh NMOS transistor N7 is grounded, and the drain of the seventh NMOS transistor N7 is connected to the source of the fifth NMOS transistor and the first output terminal of TIA.

[0119] The gate of the eighth NMOS transistor N8 is connected to the input bias voltage of the NMOS current mirror circuit, the source of the eighth NMOS transistor N8 is grounded, and the drain of the eighth NMOS transistor N8 is connected to the source of the sixth NMOS transistor N6 and the second output terminal of TIA.

[0120] The super source follower in this embodiment includes: a ninth NMOS transistor N9, a tenth NMOS transistor N10, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;

[0121] The gate of the ninth NMOS transistor N9 is connected to the first output terminal of CTLE as the first input terminal of TIA. The drain of the ninth NMOS transistor N9 is connected to the second terminal of the third resistor R3 and the gate of the fifth NMOS transistor N5. The source of the ninth NMOS transistor N9 is connected to the first terminal of the fifth resistor R5.

[0122] The first end of the third resistor R3 is connected to the power supply VDD, and the second end of the third resistor R3 is connected to the drain of the ninth NMOS transistor N9.

[0123] The first end of the fifth resistor R5 is connected to the source of the ninth NMOS transistor N9, and the second end of the fifth resistor R5 is grounded.

[0124] The gate of the tenth NMOS transistor N10 is connected to the second output terminal of CTLE as the second input terminal of TIA. The drain of the tenth NMOS transistor N10 is connected to the second terminal of the fourth resistor R4 and the gate of the sixth NMOS transistor N6. The source of the ninth NMOS transistor N9 is connected to the first terminal of the sixth resistor R6.

[0125] The first end of the fourth resistor R4 is connected to the power supply VDD, and the second end of the fourth resistor R4 is connected to the drain of the tenth NMOS transistor N10.

[0126] The first end of the sixth resistor R6 is connected to the source of the tenth NMOS transistor N10, and the second end of the sixth resistor R6 is grounded.

[0127] The feedback resistor and feedback inductor in this embodiment include: a seventh resistor R7, an eighth resistor R8, a first inductor L1, and a second inductor L2;

[0128] The first end of the first inductor L1 is connected to the first input terminal of TIA, and the second end of the first inductor L1 is connected to the first end of the seventh resistor R7.

[0129] The first end of the seventh resistor R7 is connected to the second end of the first inductor L1, and the second end of the seventh resistor R7 is connected to the first output terminal of TIA.

[0130] The first end of the second inductor L2 is connected to the second input terminal of TIA, and the second end of the second inductor L2 is connected to the first end of the eighth resistor R8.

[0131] The first end of the eighth resistor R8 is connected to the second end of the second inductor L2, and the second end of the eighth resistor R8 is connected to the second output terminal of TIA.

[0132] This embodiment provides a SerDes receiver analog front-end circuit composed of a power-adjustable CTLE and TIA. Under lossy channel conditions, it transmits a signal at a specific rate, allowing observation of the circuit's overall signal equalization capability.

[0133] To further verify the equalization effect of the equalization circuit of the present invention on signal transmission, experimental verification was conducted, such as... Figure 1 As shown, the circuit in this experiment consists of a 100-ohm differential impedance terminal, a CTLE, and a TIA. A 100-ohm resistor is used to match the circuit input to the device, allowing for the input of NRZ signals of different frequencies. This embodiment verifies the high efficiency and feasibility of the invention using 10Gbps and 14Gbps rates. The CTLE and TIA employ a gm-TIA topology to compensate for channel loss at 5GHz and 7GHz Nyquist frequencies, respectively, and adjust the output amplitude without affecting bandwidth attenuation.

[0134] The first and second input terminals of CTLE are connected to input AC signals. After being equalized by the entire circuit, the signals are output by the first and second output terminals of TIA, and then the data is processed.

[0135] The circuit design diagram of CTLE is as follows: Figure 1 As shown, the first stage of the SerDes receiver front-end circuit utilizes a tunable source degradation structure, which can be tuned to match the amplitude of the input signal and the attenuation loss of the channel, achieving good linearity. Figure 2 In the circuit, resistors Rg1 and Rg2, and capacitors Cg1 and Cg2 are connected to the first NMOS switch as source degradation resistors and capacitors. The resistance values ​​are adjusted by the input voltage Vctrl, which changes the position of the circuit's zeros and poles, thereby meeting the requirements of different signal transmission rates. After passing through the channel, the signal is equalized by the receiver analog front-end circuit designed in this invention. Finally, the signal is output through the first output terminal and the second output terminal of the TIA.

[0136] The external current mirrors for the first PMOS transistor P1, the second PMOS transistor P2, the seventh PMOS transistor P7, and the eighth PMOS transistor P8 are as follows: Figure 3 As shown, Vbiasn and Vbiasp serve as bias voltage inputs to drive the circuit and maintain high-frequency stability. The CTLE at the AFE front end is as follows... Figure 1 As shown, to meet the requirements of high bandwidth and high gain, the first consideration is to use transconductance enhancement technology to improve the DC gain of the equalizer at high frequencies. The third PMOS transistor P3 and the fourth PMOS transistor P4 can be equivalent to operational amplifier structures, while the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are equivalent to source followers. The gates of the third PMOS transistor P3 and the fourth PMOS transistor P4 can be considered as input terminals, and the output terminals are located at the drains of the third PMOS transistor P3 and the fourth PMOS transistor P4, connected with source degradation resistors and source degradation capacitors. Feedback is completed from the source terminals of the first NMOS transistor N1 and the second NMOS transistor N2. A gain is applied to the transconductance of the first NMOS transistor N1 and the second NMOS transistor N2, i.e., the small-signal open-loop gain A0 of the transconductance amplifier. This is the product of their transconductance multiplied by the output node impedance. The improved transconductance becomes g. m (1+A0). Where g m The first NMOS transistor N1 and the second NMOS transistor N2 are transconductances. The first PMOS transistor P1, the second PMOS transistor P2, the third NMOS transistor N3, and the fourth NMOS transistor N4 are responsible for generating quiescent current, replacing the current source drive circuit.

[0137] The transfer function of CTLE can be expressed as:

[0138]

[0139] Where ω Z For zero, ω P1 For the first pole, ω P2 For the second pole, their values ​​are as follows:

[0140]

[0141] According to the formula, compared with the traditional CTLE structure, this invention improves the DC gain at high frequencies due to the increased transconductance, and through a stable tunable source degradation structure, the low-frequency DC gain of the circuit is adjustable. The DC gain of the circuit is expressed as follows:

[0142]

[0143] This invention employs a cascaded TIA and CTLE to improve the bandwidth and gain of the equalization circuit, such as... Figure 1As shown, the TIA, based on a single-stage differential structure, employs a super source-follower structure. The total transconductance of the TIA is equivalent to the parallel sum of the transconductances of the fifth NMOS transistor N5 and the ninth PMOS transistor P9. This structure keeps the product of the resistance and capacitance of the parasitic node output constant and minimizes it to achieve greater bandwidth operation.

[0144] like Figure 1 As shown, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 serve as the amplification stage, receiving the signal after equalization by the first-stage equalizer. The seventh PMOS transistor P7 and the eighth PMOS transistor P8 are driven by the PMOS current mirror, replacing the load resistor to maintain the gain at high frequencies. The seventh NMOS transistor N7 and the eighth NMOS transistor N8 are connected to the NMOS current mirror to input the NMOS bias voltage, effectively acting as a high-impedance current source to drive the entire circuit. The ninth NMOS transistor N9 and the tenth NMOS transistor N10, together with the third resistor R3 and the fifth resistor R5, and the fourth resistor R4 and the sixth resistor R6, respectively, form a super source follower to improve the amplifier's bandwidth and gain. The resistors control the circuit current. From a DC perspective, this essentially replaces the current source with resistors. Therefore, the values ​​of the third and fourth resistors must be greater than the values ​​of the fifth resistor R5 and the sixth resistor R6 to make the DC current equivalent to the AC current generated by the amplifier, thus enabling the normal operation of the TIA.

[0145] like Figure 1 The diagram illustrates the gm-TIA topology of the TIA circuit and CTLE, which connects the output of the CTLE to the input of the TIA. A feedback resistor and a feedback inductor are connected across the output and input of the TIA to extend its peak value to a higher frequency.

[0146] In this invention, the transfer function formula for the overall SerDes receiver analog front-end circuit is as follows:

[0147]

[0148] in:

[0149]

[0150]

[0151] In the above expression, for ease of expression, let

[0152] As can be seen, this transfer function introduces an additional zero and a pole compared to the traditional CTLE, and also improves the transconductance compared to the traditional CTLE, thus solving the shortcomings of the traditional CTLE in terms of high gain and low bandwidth.

[0153] The verification example proposed in this invention uses PCIe 3.0 protocol hard disk data transfer to verify the feasibility of this invention.

[0154] In the verification example proposed in this invention, NRZ coded signals at rates of 10Gbps and 14Gbps were simulated and generated by the transmitter for verification. The frequency response curve of the designed receiver front-end equalization circuit is shown in the figure below. Figure 4 As shown, its peak frequency is 7GHz, and the gain is 13.2dB. Since the source degradation resistor shown is adjustable, different input voltages Vctrl can change the DC gain at different low frequencies while maintaining a constant peak gain, making it suitable for channels with different propagation speeds and losses. The insertion loss and return loss data of the PCIe 3.0 channel used in the verification example are shown below. Figure 5 As shown.

[0155] First, a signal with a simulated transmission rate of 10Gbps is transmitted through a channel. The channel has an insertion loss of -13.3dB and a return loss of -16.5dB at its Nyquist frequency of 5GHz. After equalization by the receiver's analog front-end circuit designed in this invention, the loss caused by the channel skin effect is compensated, resulting in the eye diagram shown below. Figure 6 As shown, when the equalization circuit is not turned on, the eye diagram is completely closed. When the equalization circuit is turned on, the eye height is about 1.07V, and the eye width is opened by about 0.83UI, resulting in an ideal equalization effect.

[0156] When a 14Gbps signal passes through the channel, the DC gain at low frequencies is affected by changing the regulating voltage Vctrl while maintaining a constant high-frequency gain to prevent over-equalization. The channel losses at its Nyquist frequency of 7GHz are -18.2dB and -22.2dB, respectively. The signal is equalized by the designed receiver front-end to compensate for losses caused by the channel skin effect. The eye diagram after equalization is shown below. Figure 7 As shown, with the unequalizer opening at 0, the eye height after equalization is approximately 0.68V, while the eye width opens by approximately 0.82UI, achieving the same ideal equalization effect.

[0157] In summary, the SerDes receiver analog front-end circuit designed in this invention utilizes transconductance boosting technology, a gm-TIA topology, and a TIA employing super source-follower technology, resulting in greater bandwidth and higher high-frequency gain. Furthermore, the source degradation resistor value can be adjusted using an NMOS switch, thereby changing the DC gain at low frequencies to adapt to different transmission rates. In the verification example, signals at different rates can be effectively equalized after passing through a PCIe 3.0 channel, reducing trailing effects and eliminating intersymbol interference from a system perspective.

[0158] Some steps in the embodiments of the present invention can be implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0159] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A receiver analog front end equalization circuit, comprising: The receiver analog front-end equalization circuit includes a cascaded continuous-time linear equalizer (CTLE) and a transimpedance amplifier (TIA), wherein the continuous-time linear equalizer (CTLE) and the transimpedance amplifier (TIA) adopt a gm-TIA topology. A feedback resistor and a feedback inductor are connected in series between the output and input terminals of the transimpedance amplifier TIA. The continuous-time linear equalizer CTLE includes: an adjustable source degradation structure and a transconductance enhancement structure; The adjustable source degradation structure includes: a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, a second PMOS transistor P2, a third NMOS transistor N3, and a fourth NMOS transistor N4; The gate of the first NMOS transistor N1 is connected to the first input signal as the first input terminal of the CTLE. The drain of the first NMOS transistor N1 is connected to the drain of the first PMOS transistor P1. The source of the first NMOS transistor N1 is connected to the drain of the third NMOS transistor N3 and the adjustable source degradation circuit. The gate of the second NMOS transistor N2 is connected to the second input signal as the second input terminal of CTLE. The drain of the second NMOS transistor N2 is connected to the drain of the second PMOS transistor P2. The source of the second NMOS transistor N2 is connected to the drain of the fourth NMOS transistor N4 and the adjustable source degradation circuit. The gate of the first PMOS transistor P1 is connected to the PMOS bias voltage input by the PMOS current mirror circuit, the source of the first PMOS transistor P1 is connected to the power supply VDD, and the drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1. The gate of the second PMOS transistor P2 is connected to the PMOS bias voltage input of the PMOS current mirror circuit, the source of the second PMOS transistor P2 is connected to the power supply VDD, and the drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2. The gate of the third NMOS transistor N3 is connected to the NMOS current mirror circuit input NMOS bias voltage, the source of the third NMOS transistor N3 is grounded, and the drain of the third NMOS transistor N3 is connected to the source of the first NMOS transistor N1. The gate of the fourth NMOS transistor N4 is connected to the NMOS current mirror circuit input NMOS bias voltage, the source of the fourth NMOS transistor N4 is grounded, and the drain of the fourth NMOS transistor N4 is connected to the source of the second NMOS transistor N2. The transconductance enhancement structure includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a first resistor R1, and a second resistor R2. The gate of the third PMOS transistor P3 is connected to the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor P1, respectively. The source of the third PMOS transistor P3 is connected to the power supply VDD, and the drain is connected to the adjustable source degradation circuit and the source of the first NMOS transistor N1. The gate of the fourth PMOS transistor P4 is connected to the drain of the second NMOS transistor N2 and the drain of the second PMOS transistor, respectively. The source of the fourth PMOS transistor is connected to the power supply VDD, and the drain is connected to the adjustable source degradation circuit and the source of the second NMOS transistor N2. The gate of the fifth PMOS transistor P5 is connected to the drain of the first NMOS transistor N1 and the drain of the first PMOS transistor P1, respectively. The source of the fifth PMOS transistor P5 is connected to the power supply VDD, and the drain is connected to the first output terminal of CTLE and the first terminal of the first resistor R1. The gate of the sixth PMOS transistor P6 is connected to the drain of the second NMOS transistor N2 and the drain of the second PMOS transistor P2. The source of the sixth PMOS transistor P6 is connected to the power supply VDD, and the drain is connected to the second output terminal of CTLE and the first terminal of the second resistor R2. The first end of the first resistor R1 is connected to the drain of the fifth PMOS transistor P5 and the first output terminal of the CTLE, and the second end of the first resistor R1 is grounded. The first end of the second resistor R2 is connected to the drain of the sixth PMOS transistor P6 and the second output terminal of CTLE, and the second end of the second resistor R2 is grounded. The adjustable source degradation circuit changes the overall low-frequency DC gain of the circuit by adjusting the resistance value, thereby adapting to signals with different transmission rates.

2. The receiver analog front-end equalization circuit of claim 1, wherein, The adjustable source degradation circuit includes: a first source degradation resistor Rg1, a second source degradation resistor Rg2, a first source degradation capacitor Cg1, a second source degradation capacitor Cg2, and a first NMOS switch Nt1; The first source degradation resistor Rg1 and the second source degradation resistor Rg2 are connected in series and then connected across the drains of the first NMOS transistor N1 and the second NMOS transistor N2, and are connected in parallel with the first NMOS switch Nt1. After the first source degradation capacitor Cg1 and the second source degradation capacitor Cg2 are connected in series, they are connected across the drain of the first NMOS transistor N1 and the second NMOS transistor N2, and are connected in parallel with the first source degradation resistor Rg1 and the second source degradation resistor Rg2, and are also connected in parallel with the first NMOS switch Nt1. The gate of the first NMOS switch Nt1 is connected to the tuning voltage input as the control voltage, the drain is connected to the source of the first NMOS transistor N1, and the source is connected to the source of the second NMOS transistor N2.

3. The receiver analog front-end equalization circuit of claim 2, wherein, The transimpedance amplifier (TIA) includes: a single-stage differential structure and a super source follower structure; The first-level differential structure includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a seventh PMOS transistor P7, and an eighth PMOS transistor P8; The gate of the fifth NMOS transistor N5 is connected to the drain of the ninth NMOS transistor N9 in the super source follower, the drain of the fifth NMOS transistor N5 is connected to the drain of the seventh PMOS transistor P7, and the source of the fifth NMOS transistor N5 is connected to the drain of the seventh NMOS transistor P7 and the first output terminal of the TIA. The gate of the sixth NMOS transistor N6 is connected to the drain of the tenth NMOS transistor N10 in the super source follower, the drain of the sixth NMOS transistor N6 is connected to the drain of the eighth PMOS transistor P8, and the source of the sixth NMOS transistor N6 is connected to the drain of the eighth NMOS transistor P8 and the second output terminal of TIA. The gate of the seventh PMOS transistor P7 is connected to the input bias voltage of the PMOS current mirror circuit, the source of the seventh PMOS transistor P7 is connected to the power supply VDD, and the drain of the seventh PMOS transistor P7 is connected to the drain of the fifth NMOS transistor N5. The gate of the eighth PMOS transistor P8 is connected to the input bias voltage of the PMOS current mirror circuit, the source of the eighth PMOS transistor P8 is connected to the power supply VDD, and the drain of the eighth PMOS transistor P8 is connected to the drain of the sixth NMOS transistor N6. The gate of the seventh NMOS transistor N7 is connected to the input bias voltage of the NMOS current mirror circuit, the source of the seventh NMOS transistor N7 is grounded, and the drain of the seventh NMOS transistor N7 is connected to the source of the fifth NMOS transistor and the first output terminal of the TIA. The gate of the eighth NMOS transistor N8 is connected to the input bias voltage of the NMOS current mirror circuit, the source of the eighth NMOS transistor N8 is grounded, and the drain of the eighth NMOS transistor N8 is connected to the source of the sixth NMOS transistor N6 and the second output terminal of TIA. The super source follower includes: a ninth NMOS transistor N9, a tenth NMOS transistor N10, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6; The gate of the ninth NMOS transistor N9 is connected to the first output terminal of CTLE as the first input terminal of TIA. The drain of the ninth NMOS transistor N9 is connected to the second terminal of the third resistor R3 and the gate of the fifth NMOS transistor N5. The source of the ninth NMOS transistor N9 is connected to the first terminal of the fifth resistor R5. The first end of the third resistor R3 is connected to the power supply VDD, and the second end of the third resistor R3 is connected to the drain of the ninth NMOS transistor N9. The first end of the fifth resistor R5 is connected to the source of the ninth NMOS transistor N9, and the second end of the fifth resistor R5 is grounded. The gate of the tenth NMOS transistor N10 is connected to the second output terminal of CTLE as the second input terminal of TIA. The drain of the tenth NMOS transistor N10 is connected to the second terminal of the fourth resistor R4 and the gate of the sixth NMOS transistor N6. The source of the ninth NMOS transistor N9 is connected to the first terminal of the sixth resistor R6. The first end of the fourth resistor R4 is connected to the power supply VDD, and the second end of the fourth resistor R4 is connected to the drain of the tenth NMOS transistor N10. The first end of the sixth resistor R6 is connected to the source of the tenth NMOS transistor N10, and the second end of the sixth resistor R6 is grounded.

4. The receiver analog front-end equalization circuit of claim 3, wherein, The feedback resistor and feedback inductor include: a seventh resistor R7, an eighth resistor R8, a first inductor L1, and a second inductor L2; The first end of the first inductor L1 is connected to the first input terminal of TIA, and the second end of the first inductor L1 is connected to the first end of the seventh resistor R7. The first end of the seventh resistor R7 is connected to the second end of the first inductor L1, and the second end of the seventh resistor R7 is connected to the first output terminal of the TIA. The first end of the second inductor L2 is connected to the second input terminal of the TIA, and the second end of the second inductor L2 is connected to the first end of the eighth resistor R8; The first end of the eighth resistor R8 is connected to the second end of the second inductor L2, and the second end of the eighth resistor R8 is connected to the second output terminal of the TIA.

5. The receiver analog front-end equalization circuit of claim 4, wherein, The transfer function of the CTLE is expressed as: wherein is a zero point, is a first pole point, is a second pole point, and take values of: in, The transconductance of the first NMOS transistor N1 and the second NMOS transistor N2 is... The gain applied to the transconductance of the first NMOS transistor N1 and the second NMOS transistor N2; The source degradation resistance value, The source degradation capacitance value, The parasitic load resistance value of the CTLE output node. This represents the parasitic load capacitance value of the CTLE output node.

6. The receiver analog front-end equalization circuit of claim 5, wherein, The DC gain of the CTLE is: 。 7. The receiver analog front-end equalization circuit of claim 6, wherein, The transfer function formula for the receiver analog front-end circuit is: wherein let , ， ， ， ， in, Indicates the overall DC gain. This represents the total transconductance of the TIA device. Indicates the feedback resistor value. This indicates the parasitic load capacitance value of the TIA output node. This indicates the parasitic load resistance value of the TIA output node. This indicates the value of the feedback inductance.

8. The receiver analog front-end equalization circuit according to claim 4, characterized in that, The values ​​of the third resistor R3 and the fourth resistor R4 are greater than the values ​​of the fifth resistor R5 and the sixth resistor R6.

9. A receiver analog front end equalization method, characterized by, The method is implemented based on the receiver analog front-end equalization circuit according to any one of claims 1-8, and includes: receiving an input AC signal from the first input terminal and the second input terminal of the CTLE, and outputting a signal from the first output terminal and the second output terminal of the TIA after equalization by the receiver analog front-end equalization circuit.

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