Method for identifying line defects on a substrate and apparatus for identifying line defects on a substrate

Abstract

A method for identifying a line defect on a substrate having a display located on the substrate is described. The method includes determining the line defect using a first test, the line defect having a first orientation; setting line test parameters for line retesting; and testing one or more first strips oriented along the first orientation, the one or more first strips being parallel to the line defect, the one or more first strips having a first dimension and a second dimension, the first dimension extending at least along a field of view of a charged particle beam device, and the second dimension extending only along a portion of the field of view.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to testing of substrates, particularly large area substrates used in display manufacturing. Embodiments relate to defect identification. Embodiments of the present disclosure relate generally to testing systems for large area substrates having electronic devices formed thereon, and more particularly to line defects in electronic devices. In particular, embodiments relate to a method for identifying defects on a substrate having a plurality of pixels of a display located thereon, a computer-readable medium containing a program for use with the corresponding method, and an apparatus for identifying line defects on a substrate. Background Art

[0002] In many applications, substrates must be inspected to monitor their quality. For example, glass substrates, onto which layers of coating materials are deposited, are manufactured for the display market. Because defects can occur during substrate processing, such as during coating or structuring of the coating, inspecting the substrates to detect defects and monitor display quality is essential.

[0003] Displays are typically manufactured on large-area substrates, whose sizes are constantly increasing. Furthermore, displays such as TFT displays are in constant need of improvement. For example, bezels are becoming increasingly narrower, and OLED displays are increasingly being used in laptops, desktop PC monitors, and TVs in addition to mobile devices. The first μ-LED displays are already on the market.

[0004] Active-matrix liquid crystal displays (LCDs) and OLED displays are commonly used in applications such as computer and television monitors, mobile phone displays, personal digital assistants (PDAs), and a growing number of other devices. Typically, an active-matrix LCD or OLED display comprises two flat panels or panels, each having a layer of liquid crystal material or a layer of OLED material, respectively, sandwiched between the flat panels. The flat panels are typically made of glass, a polymer, or other material suitable for forming electronic devices thereon. The display typically comprises an array of thin-film transistors (TFTs), each coupled to a pixel. Each pixel is activated by providing a signal to a driver circuit such as a data line and a gate line, as well as a transistor, and pixel activation can be provided by simultaneously addressing the appropriate data line and gate line. The TFT can be turned on or off to generate an electric field between the corresponding TFT and a portion of the color filter. The TFT can be turned on or off to drive current through the OLED or μ-LED. Due to the high pixel density, the close proximity of the gate and data lines, and the complexity of forming the TFTs, the potential for defects during the manufacturing process is high.

[0005] As described above, TFT arrays can be used for LCD displays. However, OLED and μ-LED displays, as well as other displays, can also be based on TFT array backplanes, where the pixel electrodes are charged to activate the pixels of the display.

[0006] For display testing, particularly during display manufacturing, tests with specialized test patterns can be performed. For example, specific tests can be provided for specific defects such as open and short lines. To reduce the display bezel to provide a zero-margin panel, or for OLED technology, for example, additional lines may be provided. The likelihood of line defects increases. Therefore, additional testing can be beneficial, however, this can increase cycle time and reduce throughput.

[0007] To further improve the throughput of defect detection, further improvements in detection methods and detection equipment are beneficial. Summary of the Invention

[0008] In view of the foregoing, a method for identifying defects on a substrate, a computer-readable medium including a program for identifying defects on a substrate, and an apparatus for identifying line defects on a substrate having a plurality of pixels located thereon are provided. Further aspects, advantages, and features are apparent from the dependent claims, the description, and the accompanying drawings.

[0009] According to one embodiment, a method for identifying a line defect on a substrate having a display located on the substrate is provided. The method comprises: determining the line defect using a first test, the line defect having a first orientation; setting line test parameters for a line-retest; and testing one or more first strips oriented along the first orientation, the one or more first strips being parallel to the line defect, the one or more first strips having a first dimension and a second dimension, the first dimension extending at least along a field of view of a charged particle beam device, and the second dimension extending only along a portion of the field of view.

[0010] According to one embodiment, a device for identifying linear defects on a substrate having a plurality of pixels disposed thereon is provided. The device includes: a detector configured to generate a voltage contrast image on the substrate; and a computer-readable medium containing a program for identifying linear defects on the substrate having the plurality of pixels disposed thereon. When the program is executed by a processor, the method according to any one of the embodiments of the present disclosure is performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope, and other equally effective embodiments may be admitted.

[0012] Figure 1 An electron beam testing device that can be used for electron beam testing according to one embodiment of the present disclosure is shown;

[0013] Figure 2 An exemplary large-area flat panel substrate having an array of thin-film transistors (TFTs), each TFT coupled to a pixel and having a gate driver and gate and data lines that can be tested according to embodiments described herein is shown;

[0014] Figure 3A and Figure 3B shows a table illustrating a test sequence according to an embodiment of the present disclosure;

[0015] Figure 4 A glass substrate with multiple displays fabricated thereon and a test area associated with a beam testing apparatus are shown to illustrate embodiments of the present invention;

[0016] Figure 5 A portion of a glass substrate and a display on the substrate are respectively shown to illustrate a method of identifying defects on a substrate, particularly line defects on a substrate, according to an embodiment of the present disclosure;

[0017] Figure 6 A portion of a glass substrate and a display on the substrate are respectively shown to illustrate a method of identifying defects on a substrate, particularly line defects on a substrate, according to an embodiment of the present disclosure;

[0018] Figure 7 A portion of a glass substrate and a display on the substrate are respectively shown to illustrate a method of identifying defects on a substrate, particularly line defects on a substrate, according to an embodiment of the present disclosure;

[0019] Figure 8 A portion of a glass substrate and a display on the substrate are respectively shown to illustrate a method of identifying defects on a substrate, particularly line defects on a substrate, according to an embodiment of the present disclosure;

[0020] Figure 9 A portion of a glass substrate and a display on the substrate are respectively shown to illustrate a method of identifying defects on a substrate, particularly line defects on a substrate, according to an embodiment of the present disclosure;

[0021] Figure 10 A charged particle beam apparatus according to an embodiment of the present disclosure is shown; and

[0022] Figure 11 is a flow chart of example operations for identifying whether a line defect is present, according to an embodiment of the present disclosure.

[0023] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to exemplary embodiments, one or more examples of which are shown in the figures. Each example is provided by way of explanation and is not intended to be limiting. For example, features shown or described as part of one embodiment may be used on or in conjunction with other embodiments to produce yet another embodiment. This disclosure is intended to encompass such modifications and variations.

[0025] In the following description of the various figures, the same reference numerals refer to the same components. Only the differences with respect to the individual embodiments are described. The structures shown are not necessarily drawn to scale, but are provided for a better understanding of the embodiments.

[0026] Embodiments of the present disclosure provide techniques and apparatus for determining the presence of line defects within a display, and in particular for characterizing line defects. Embodiments of the present disclosure particularly provide increased throughput for line defect detection. For a specific example, a gate line open in a large, high-resolution display, which would typically be detected in approximately 20 seconds, can now be detected in less than two seconds. Consequently, a significant reduction in test time can be achieved.

[0027] According to embodiments of the present disclosure, for a specific test for identifying line defects, testing of the entire display area or the entire field of view of the charged particle beam device can be omitted. Line defects can be detected using a first test strip (i.e., a reduced number of pixels to be tested) or a standard test. One or more subsequent second test strips can be provided along or parallel to the detected line defect to locate and / or identify the line open or line short position.

[0028] Generally, analog scanning techniques and digital scanning techniques can be distinguished. Analog scanning techniques may include an analog sawtooth signal provided to a scanning deflector assembly at a predetermined frequency. The sawtooth signal may be combined with continuous or quasi-continuous substrate movement toward the scanning area of ​​the substrate. Digital scanning techniques provide discrete values ​​for the x-position and y-position of the charged particle beam on the substrate, and the individual pixels of the scanned image are addressed pixel by pixel by coordinate values, i.e., digital addressing. Analog scanning techniques ("flying stages") that may be considered more suitable for semiconductor wafer SEM inspections due to scanning speed and reduced complexity may allow for use in predetermined areas, where the entire area is measured. According to some embodiments of the present disclosure, the area to be scanned may be scanned digitally (i.e., by providing a list of desired beam position coordinates). That is, a specific strip on a display or substrate may be scanned using digital scanning techniques (i.e., a digital scanner). Individually addressing coordinates allows variable definition of scanning areas such as test strips, which may increase the throughput of the test substrate.

[0029] Figure 1 An external view of an exemplary electron beam test system 100 (e-beam test system) that can be used for electron beam testing in conjunction with one or more embodiments of the present disclosure is shown. The electron beam test system 100 is an integrated system that requires minimal space and is capable of testing large glass panel substrates up to and exceeding 1.25 meters by 1.5 meters, for example, up to and exceeding 2.94 meters by 3.37 meters. The electron beam test system 100 may include a load lock chamber 104 and a test chamber 150. In addition, a detector storage assembly and / or a detector transport assembly may optionally be provided.

[0030] According to some embodiments, the large area substrate may have a thickness of at least 1.375 m 2 Size. Size can be from about 1.375m 2 (1100mm×1250mm, 5th generation) to about 9m 2 , more specifically from about 2m 2 to about 9m 2 Or even up to 12m 2 The substrate or substrate receiving area used to provide the structures, apparatus and methods according to the embodiments described herein can be a large area substrate as described herein. For example, the large area substrate or carrier can be a 5th generation (which corresponds to about 1.375m 2 Substrate (1.1m×1.25m)), 7.5th generation (which corresponds to about 4.39m 2 substrate (1.95m×2.25m)), 8.5th generation (which corresponds to about 5.7m 2substrate (2.2m×2.5m)) or even 10.5th generation, which corresponds to about 10.5 substrates (2.94m×3.37m). Even higher generations, such as 11th and 12th generations, and corresponding substrate areas, can be similarly achieved.

[0031] A detector storage assembly may be provided and may, for example, accommodate one or more detectors or may include a detector rod adjacent to the test chamber 150 for ease of use and retrieval. According to an advantageous embodiment, which may be combined with other embodiments described herein, the test chamber 150 includes a detector rod that can accommodate various configurations or designs of displays on large-area substrates. Thus, specialized detectors for display layouts on substrates and detector storage assemblies may be avoided.

[0032] The electron beam test system 100 may also include four or more electron beam test (EBT) columns 125, such as ten or more EBT columns. The EBT columns may be disposed on the upper surface of the test chamber 150. During electron beam testing, a specific voltage may be applied to the TFT using one or more detectors, and the electron beam from the EBT column is directed to the contact pads of the individual pixels and / or driver circuits being studied. In particular, secondary electrons or signal electrons may provide a voltage contrast image. An energy filter may be used to detect the signal electrons to generate a voltage contrast image.

[0033] According to some embodiments, which can be combined with other embodiments described herein, testing of large area substrates can include operation of two or more electron beam test columns. In certain implementations, the operation of adjacent test columns can be synchronized to reduce crosstalk between adjacent columns.

[0034] Each of the electron beam test columns (i.e., charged particle beam devices) has a field of view (FOV). According to some embodiments that can be combined with other embodiments described herein, the charged particle beam device or EBT column has a field of view of 200 mm or larger. Those skilled in the art will appreciate that, in view of the limited size of the field of view of such devices, scanning electron microscopes used for high-resolution imaging in, for example, the semiconductor industry may not be suitable equipment for high-speed testing of large area substrates.

[0035] A large area substrate with one or more displays disposed thereon can be transported from a load lock chamber to a test chamber. The first portion of the display can be disposed below an EBT column so that the first portion of the display can be tested within the field of view of the EBT column. Multiple tests can be performed on the first portion of the display. After these tests on the first portion of the display are completed, the substrate can be moved so that the second portion of the display is disposed below the test column. Each EBT test column can test a sub-portion of the display with the FOV of an EBT column or a charged particle beam device. The region of the FOV of the charged particle beam device can also be referred to as a sub-display for testing purposes.

[0036] Each sub-display can be tested using a series of different tests. The different tests can include retests of a main test, where the same test pattern is generated on the sub-display as in the main test. For example, the retest can confirm the results of the main test under the same conditions. Additionally or alternatively, the retest can be performed using different patterns, different voltages, or different signal timings compared to the main test. Thus, the retest can provide defect characterization or identification of further defects. According to another embodiment, which can be combined with other embodiments described herein, the series of tests can also include different main tests, wherein retests can optionally be provided for one or more of the main tests.

[0037] Figure 2 A portion of a flat panel substrate 200 is shown having a plurality of pixels 12. The flat panel substrate 200 is typically a flat rectangular piece of glass, polymer material, or other suitable material on which electronic devices can be formed, and typically has a large surface area. One or more thin film transistors 18 (TFTs) and, for example, one or more capacitors can be associated with each pixel 12. The flat panel substrate 200 also includes data lines 14 and gate lines 16. In addition, common lines and other lines can be provided if desired. The pixels 12, thin film transistors 18, data lines 14, and gate lines 16 can be formed on the flat panel substrate 200 by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), photolithography, or other suitable manufacturing processes.

[0038] A drive circuit 20, such as a gate drive circuit, is connected to corresponding lines, such as gate line 16. During testing of the flat panel substrate 200, the drive circuit 20 can be operated to drive the pixels 12. The drive circuit 20, as a gate drive circuit, can be operated in conjunction with the operation of the data lines (i.e., signal lines). The data lines can be operated by an external drive circuit, by biasing one or more shorting bars, or by another operating method.

[0039] Pixel 12 can be tested by, for example, determining a voltage contrast measurement of the charge provided on the pixel. For example, the transistor of pixel 12 can be turned on by applying +15V to the gate of the transistor, a voltage of 5V can be provided to the pixel electrode via a signal line, the transistor can be turned off with a gate voltage of -15V, and when the transistor is turned off, a voltage of -10V can be provided to the signal line. In the absence of defects such as short circuits or open circuits, the turned-off transistor on the pixel electrode should retain a 5V charge. Defects and even types can be identified based on the deviation of the measured voltage values ​​of one or more pixels in the rows and / or columns of the display from the expected values. A variety of patterns and test algorithms can be provided to detect line defects, transistor defects, or other defects. Defects on a flat substrate can include pixel defects, line defects, and / or defects in the driver circuit. Pixel defects may include pixel gate line shorts and pixel data line shorts. Line defects may include line-to-line shorts (e.g., between data lines or between gate lines), crossover shorts (e.g., from data line to gate line), and open circuit defects. Other flat circuit boards, such as printed circuit boards and multi-chip modules, can also be tested according to the various embodiments described herein.

[0040] Figure 3A and Figure 3B A table illustrating an example of a test sequence that may be provided on a substrate is shown. Implementations of line testing and line retesting are described in more detail below. Typically, there is a test sequence. Optionally, for one or more tests of a test sequence, a retest may be provided. Figure 3A In the example shown, the first test (i.e., "Test 1") is a standard main test. Thereafter, further main tests are provided, i.e., "Special Test 1" or "Test 2." According to some embodiments, which can be combined with other embodiments described herein, additional main tests can be provided with different patterns, different voltages, and / or different timings (e.g., delays between driven and tested pixels) on the display or sub-display. The aforementioned test properties and additional test properties may be referred to as test parameters.

[0041] Depending on the results of "Test 2," one or more retests may be provided. For example, "Retest 1" and / or "Retest 2" may be provided, particularly based on the results of a further main test. The retests may provide the same test parameters or different test parameters. Following "Test 2," an additional main test, "Test 3," may be provided.

[0042] According to embodiments of the present disclosure, the main test or retest may be a line test, wherein line defects are identified using a test strip according to embodiments of the present disclosure. For example, "Test 4" may be a specific main test for line defects. Furthermore, a retest for line defects may be provided as a retest of "Test 4."

[0043] According to an embodiment of the present disclosure, identifying line defects includes at least one retest to further characterize the line defects of the main test and / or identify the line defects. Generally, the main test can be a standard main test or a specific main test. In addition, the main test can be a line test.

[0044] exist Figure 3B In the example shown, the retest used to identify line defects is a retest of a standard main test (e.g., "Test 1"). Additional tests may be provided, such as Figure 3A and Figure 3B As shown and described above.

[0045] Figure 4 A substrate, such as a flat panel substrate 200, is shown. In the example shown, six displays 402 are fabricated on the substrate. As indicated by reference numerals 420-431, a plurality of fields of view or sub-displays are provided. Each field of view or sub-display corresponds to a display such as a display 402. Figure 10 The field of view of the charged particle beam device shown. Multiple charged particle beam devices can be provided to test corresponding fields of view simultaneously. During the test, the display can be driven, for example, by a drive circuit. For example, each display can be driven from the left side of the corresponding display and / or from the right side of the corresponding display. Figure 3A and Figure 3B A plurality of tests of the test sequence shown exemplarily are performed in the fields of view or sub-displays indicated by reference numerals 420 - 431. After completion of the testing of a sub-display, the substrate can be moved as indicated by arrow 432. A further sub-display is arranged at the field of view of the charged particle beam device.

[0046] According to an embodiment of the present disclosure, multiple tests of a test sequence are provided for each field of view or each sub-display. The test results of a charged particle beam device corresponding to a field of view (FOV) define further tests of the same charged particle beam device and the corresponding same field of view (FOV). The test results of different charged particle beam devices can be analyzed independently of each other.

[0047] According to an embodiment of the present disclosure, a method for identifying a linear defect on a substrate having a plurality of pixels of a display located on the substrate is provided. The method includes determining the linear defect using a first test, wherein the linear defect has a first orientation. After the first test, a line test pattern is set for line retesting. At least a first strip oriented along the first orientation is tested. For example, one or more first strips may be tested. The one or more first strips are parallel to the linear defect. The one or more first strips have a first dimension and a second dimension, the first dimension extending at least along a field of view of a charged particle beam device, and the second dimension extending only along a portion of the field of view. According to some embodiments that may be combined with other embodiments described herein, the aspect ratio between the first dimension and the second dimension can be at least 10:1, particularly at least 40:1, and more particularly at least 100:1. Thus, the strip can have a length of at least the entire field of view or sub-display in one dimension and a width of only a few tens of pixels. For example, the number of pixels (i.e., display pixels) of the strip tested on the sub-display can be 200 or less, such as 100 or less, such as approximately 50. Therefore, the area to be tested is much smaller than the size of the sub-display. Since individual pixels can be digitally scanned, the time for a single test or retest can be significantly reduced. This can increase the throughput of tests, such as those for substrates with one or more displays.

[0048] According to some embodiments, which can be combined with other embodiments described herein, a second test (i.e., a retest) can be performed as a stripe test parallel to the detected line defects (e.g., data line defects) of the first test. The software performing the test can look for line defects perpendicular to the scan direction and report the intersection as a short circuit location.

[0049] Figure 5 Display 402 is shown and illustrates a testing process according to an embodiment of the present disclosure. Figure 5 Shown are all the test operations of the method 1100 for identifying line defects on a substrate. Figure 11 In addition, Figure 5 The results of the method of identifying line defects (ie, defective gate lines 510) and corresponding gate open locations within frame 504 are shown. Figure 5 As shown in FIG, the defective gate line and the corresponding gate open position are also as described below Figure 5 Results of the method for identifying line defects after further test operations are shown.

[0050] At operation 190, a first test is performed to determine line defects. The first test may be Figure 5 The strip test of strip 502 is shown. Horizontal lines (such as gate lines of display 402) can be obtained from Figure 5The left side of the display 402 is driven. The vertical strip 502 is tested on the right side of the display 402. Figure 5 As shown, a vertical strip 502 is tested on the right side of each sub-display 420-1 to 421-2. According to some embodiments, which can be combined with other embodiments described herein, the lines can be driven from a first side of the display and the strip test can be provided on a second side of the display or sub-display, respectively, where the second side is opposite the first side.

[0051] According to some embodiments, which may be combined with other embodiments described herein, since the resistance and / or capacitance of a line may exceed a favorable value for a large display, a larger display may be driven from two opposing sides. Therefore, for some displays, a line (such as a gate line) may be driven from two sides. When driven from both sides, a line open (such as a gate line open) cannot be detected. An additional test may be performed that drives only one side (e.g., a test for only one gate) for line open detection. Such a test may be performed by strip testing. For example, a subsequent strip test on opposite sides of a sub-display may be provided.

[0052] According to some embodiments, the display may be very small, i.e., the display may be equal to or smaller than the field of view of the charged particle beam device. In this case, the testing of the sub-display as described herein may be performed for testing of the display, i.e., the entire area of ​​the optoelectronic device, since the display size is completely within the field of view.

[0053] Thus, according to some embodiments, a first test may include testing a first strip (e.g., strip 502) on an opposite second side when the display is driven from the first side, and may include testing a second strip (e.g., strip 502) on the opposite first side when the display is driven from the second side. Figure 5 (not shown). Figure 5 As shown, and according to some embodiments, the first test may be a main test in the form of a strip test. The first test reveals the defective lines (eg, gate lines) within the frame 504, i.e., the corresponding crossover locations. Figure 11 At operation 192 in , line test parameters are provided for line retesting.

[0054] According to some embodiments, which can be combined with other embodiments described herein, the line test parameters can include different patterns, different voltages, and / or different timings (e.g., delays between driving pixels and testing pixels) on a display or sub-display. According to some embodiments, during testing of one or more sub-displays, the entire display is driven with a set of line test parameters.

[0055] The defect line within frame 504 has a first orientation, e.g. Figure 5In the example of FIG. 5 , strip 512 in the first orientation is tested in operation 194 . Test strip 512 can be considered a retest of the first test of test strip 502 . The line test parameters set for the retest can be the same test parameters as the first test or different parameters. Figure 5 In the example shown, strip 512 is located to include the line defect determined in block 504. According to some embodiments, the strip being tested may include a line defect. Figure 11 Operation 196 reveals Figure 5 The gate open position shown in the block 514 corresponds to the cross position. Therefore, the line defect on the substrate can be identified.

[0056] The above about Figure 5 and Figure 11 The described embodiments relate to testing of the display 402. According to some embodiments, which can be combined with other embodiments described herein, a method for identifying line defects on a substrate may relate to a sub-display or a field of view, respectively, of a charged particle beam device. Figure 5 Four sub-displays 420-1, 421-1, 420-2 and 421-2 are shown. At the first substrate position, the upper sub-displays 420-1 and 421-2 are tested. The first test (i.e., the first main strip test) does not reveal defects. The substrate can be removably positioned below the charged particle beam device corresponding to the two fields of view so that the sub-displays 420-2 and 421-2 below can be tested. Therefore, strip 502 is tested by successively testing the first portion of the strip (i.e., the upper portion of the strip) and the second portion of the strip (i.e., the lower portion of the strip). When the lower portion of the strip is tested, the line defect is determined to be in frame 504. In other words, the corresponding cross position is revealed. The sub-displays 420-2 and 421-2 below are subsequently retested with 512. The gate open position in identification frame 514 is identified.

[0057] According to some embodiments, which can be combined with other embodiments described herein, determining line defects using the first test may include using one or more second strips (e.g., Figure 5 The strip 502 shown is used to perform a main strip test, and one or more second strips have a first dimension and a second dimension. The second strip (i.e., strip 502) is perpendicular to the line defect. The second dimension extends at least along the field of view of the charged particle beam device, and the first dimension extends only along a portion of the field of view. As described above, the aspect ratio between the first dimension and the second dimension can be at least 10:1, particularly at least 40:1, more particularly at least 100:1. Therefore, the strip can have at least the length of the entire field of view or sub-display in one dimension, and can have a width of only a few 10 pixels.

[0058] According to some embodiments, which may be combined with other embodiments described herein, testing a first main stripe may include driving the display from a first side of the display and testing a second stripe on a second side of the display opposite the first side. For example, testing the first main stripe may further include driving the display from a second side of the display and testing a third stripe on the first side of the display. According to still further additional or alternative embodiments, identifying line defects may include locating an intersection between a first line and a second line. At least the first stripe and / or the second stripe may be scanned using a digital scanner. The digital scanner may provide the flexibility to define various stripes for each sub-display or field of view, thereby providing flexible improvements in testing throughput.

[0059] Figure 6 Another example of a method for identifying line defects on a substrate having one or more displays on the substrate is shown. Figure 6 Display 402 is shown as part of a substrate. Sub-displays, indicated by reference numerals 420 through 424, are also shown. The top row of sub-displays shows a test under multiple fields of view. The middle row of sub-displays shows a subsequent test under multiple fields of view. The bottom row of sub-displays shows an even further subsequent test under a field of view. Hereinafter, a test sequence will be described with respect to testing one of one or more displays on a substrate. It will be appreciated that, depending on embodiments of the present disclosure, a test sequence may be provided for a sub-display.

[0060] According to some embodiments, and as Figure 6 As exemplarily shown, the standard main test reveals a gate line defect of gate line 510. The standard main test includes testing the entire field of view of the corresponding sub-display. Accordingly, determining line defects with a first test (e.g., the standard main test) includes setting main test parameters that are different from line test parameters. In addition, the first test may include testing the field of view using an extension along the field of view in a first dimension and a second dimension. A retest of the standard main test may be provided (see, e.g., Figure 3B ) to test strip 512. Retesting (ie, testing at least the first strip along the first orientation of gate lines 510) reveals data lines 610 and crossing locations within frame 514.

[0061] Figure 7 Another example of a method for identifying line defects on a substrate using a strip test is shown. Figure 7 In the example of FIG, the first test is a standard main test that reveals a defective vertical line (e.g., data line 712). The test line parameters are set for line retesting. The data line 712 indicated by the standard main test is Figure 7In the example shown, the three strips 713 are tested in the retest. The strips 713 are parallel to the data lines 712. According to some embodiments that can be combined with other embodiments described herein, at least the first strip tested based on the results of the main test is parallel to the line defect of the first test and / or excludes the line defect tested by the first test. Additionally or alternatively, at least the first drive can be multiple strips within the field of view. For example, Figure 7 A strip 713 is shown extending in the upper field of view.

[0062] In some examples described herein, the strip can extend along the display. According to some embodiments, which can be combined with other embodiments described herein, the strip extends along the sub-display. In particular, because each sub-display is tested separately, the strip according to embodiments of the present disclosure extends along the sub-display.

[0063] exist Figure 7 In FIG. 7 , a defective gate line 710 is revealed during retesting of strip 713, as shown in block 714. For example, Figure 7 The test shown identifies a data-com short defect.

[0064] Figure 8 Tests relating to display 402. Similar to the above-described embodiments, the sub-displays indicated by reference numerals 420-424 are tested individually. Referring to the test of display 402. The sub-displays may be tested individually. When testing the various sub-displays indicated by reference numerals 420-424 (particularly testing the upper sub-display simultaneously), and after moving the substrate so that the sub-display and the lower sub-display are centered within the corresponding fields of view of the charged particle beam device, a main test using a horizontal strip (e.g., strip 512) reveals that the data line 712 is a line defect. The data line 712 provides an intersection position within the frame 813. Subsequently, testing of the strip 713 (particularly the strip 713 including the frame 813) reveals an intersection position with the gate line 510 within the frame 814. For example, as Figure 8 The test shown can identify Com-Shield short circuit defects.

[0065] Figure 9 An example of a main test as a strip test is shown. Figure 8In comparison, the order of the directions or orientations being tested is reversed. The first sub-display 420-1 to 424-1 is tested through the corresponding field of view of the strip 713. Subsequently, the second sub-display 420-2 to 424-2 is tested through the corresponding field of view of the strip 713. Subsequently, the third sub-display 420-3 to 424-3 is tested through the corresponding field of view of the strip 713. For the test of the third sub-display, a line defect of the gate line 510 is detected. This is indicated by box 514. Box 514 is arranged within the sub-displays 421-3 to 424-3. The gate line 510 is Figure 9 Horizontal gate lines are shown. Strip retesting is provided within sub-displays 421-3 to 424-3, thereby determining the line defects of the first test using strip 713. Strip retesting can be provided by strip 512. The strip retesting shows that data line 712 has a crossover position within box 914. According to an embodiment of the present disclosure, line defects of gate line 512 do not occur in sub-display 420-3 and sub-displays with reference numerals having suffixes "-1" and "-2". Therefore, strip 512 is not provided in these sub-displays. For example, Figure 9 The test shown can identify Com-Shield short circuit defects, where a vertical strip is provided as the main test.

[0066] The examples described herein refer to horizontally oriented gate lines and vertically oriented data lines. In addition, the orientation of the lines of the display may be provided and they may be particularly perpendicular to each other. Implementations of the present disclosure are not limited to horizontal gate lines and vertical data lines. The gate lines may be oriented vertically and the data lines may be oriented horizontally. In addition, more lines may be oriented horizontally and / or vertically. Furthermore, lines on a display are often described as being vertical or horizontal. According to implementations of the present disclosure, the lines to be detected for line defects may be provided in any other arbitrary coordinate system.

[0067] Figure 10 An electron beam (e-beam) test apparatus (e.g., a charged particle beam device 900) for locating defects (e.g., defects in pixels and / or lines associated with failed pixels of a large area substrate (such as a TFT array)) is shown. The charged particle beam device can be an EBT column. In the test apparatus, power to a charged particle beam gun (e.g., an e-beam gun) can be supplied by a power supply. A controller can also control the operation of a deflection element (e.g., a deflection coil or deflection plates) (e.g., via executable software) in an effort to scan the electron beam to individual pixels of a pixel array fabricated on a TFT array or to generate a voltage contrast image (e.g., a SEM image). A detector can be provided to sense the voltage from signal particles (e.g., backscattered or secondary electrons).

[0068] Figure 10A charged particle beam device or charged particle beam device 900 is shown. According to some embodiments, which may be combined with other embodiments described herein, the charged particle beam device or charged particle beam microscope has a field of view of 200 mm or larger. Those skilled in the art will appreciate that, in view of the limited size of the field of view of such devices, scanning electron microscopes used for high resolution imaging, for example in the semiconductor industry, may not be suitable equipment for high speed testing of large area substrates. The electron beam (dashed line) may be generated by an electron beam source 912. Within the gun chamber 910, additional beam shaping elements, such as suppressors, extractors and / or anodes may be provided. The electron beam source may include a TFE emitter. The gun chamber may be evacuated to 10 -8 mbar to 10 -9 Although reference is made in the examples to a scanning electron beam apparatus, generally a charged particle beam apparatus may be utilized.

[0069] A condenser lens may be provided in a further vacuum chamber 920 of a column (e.g., an EBT column) of the charged particle beam device 900. Further electron optical elements may be provided in the further vacuum chamber. Other electron optical elements may be selected from the group consisting of a dissipator, a correction element for chromatic aberration and / or spherical aberration.

[0070] A primary electron beam or a primary charged particle beam can be focused on the substrate 200 by the objective lens 924. The substrate 200 is positioned on a substrate position on the substrate support 935. When the electron beam impinges on the substrate 200, signal electrons (e.g., secondary electrons and / or backscattered electrons) and / or x-rays are released from the substrate 200, which can be detected by the detector 940. According to some embodiments that can be combined with other embodiments described herein, a voltage contrast filter, such as a grid 941, can be provided. The grid 941 can be biased to a potential that allows electrons above a certain voltage to pass through the grid while repelling electrons with energies below the corresponding voltage. According to another embodiment that can be combined with other embodiments described herein, a voltage can be provided to the substrate (the voltage provided can be offset) to generate a field for energy filtering on the secondary electrons, that is, to generate a voltage contrast image.

[0071] In About Figure 9 In the exemplary embodiment described, a focusing lens 923 is provided. Figure 9 As shown, the objective lens 924 may have a magnetic lens component having a pole piece and a coil. The objective lens focuses the primary electron beam on the substrate 200. The objective lens may be an electrostatic-magnetic composite lens having, for example, an axial gap or a radial gap, or an electrostatic delayed field lens.

[0072] Furthermore, a scanning deflector assembly may be provided. The scanning deflector assembly may be, for example, a magnetic and / or electrostatic scanning deflector assembly configured for high pixel rates. The scanning deflector assembly may be a single-stage assembly. Alternatively, a two-stage or even a three-stage deflector assembly may be provided for scanning. Each stage may be positioned at a different location along the optical axis.

[0073] According to some embodiments, which may be combined with other embodiments described herein, the magnetic scanning deflector 971 and the electrostatic scanning deflector 972 may be combined. The combination of the magnetic scanning deflector and the electrostatic scanning deflector allows for a large field of view, for example, provided by the magnetic scanning deflector. In addition, within a larger field of view, the electrostatic scanning deflector may be utilized to scan sub-regions of the field of view at a faster speed. Thus, fast image acquisition may be provided by the combination of the magnetic scanning deflector and the electrostatic scanning deflector. According to some embodiments, the magnetic scanning deflector may direct the beam to a sub-region. The electrostatic scanning deflector may scan the beam within the sub-region, for example, with a resolution of 20 μm or less (e.g., 5 μm). After the sub-region is scanned, the magnetic scanning deflector may direct the beam to a more distant region, which is in turn scanned by the electrostatic scanning deflector. Thus, the precision of the magnetic scanning deflector may be combined with the lack of hysteresis (and the corresponding reduced scanning speed) of the electrostatic deflector. Figure 9 The charged particle beam device 900 shown comprises a detector 940. The detector 940 comprises a scintillator arrangement and, for example, a photomultiplier tube.

[0074] According to an embodiment of the present disclosure, a charged particle beam device and / or a test system including a charged particle beam device includes a controller 930, which is connected to the charged particle beam device with a signal line 932 to provide control of the charged particle beam device or the EBT column to identify line defects using a strip test according to an embodiment of the present disclosure.

[0075] The controller of the charged particle beam device and / or the test system may include a central processing unit (CPU), a memory, and, for example, support circuits. To facilitate control of the charged particle beam device, the CPU may be one of any form of general-purpose computer processor that can be used in an industrial environment to control various components and subprocessors. The memory is coupled to the CPU. The memory or computer-readable medium may be one or more readily available memory devices, such as random access memory, read-only memory, a floppy disk, a hard disk, or any other form of digital storage device, locally or remotely. The support circuits may be coupled to the CPU to support the processor in a conventional manner. The circuits include caches, power supplies, clock circuits, input / output circuit systems, and related subsystems. Test processing instructions and / or instructions for identifying line defects may be stored in the memory as software routines, typically referred to as recipes. The software routines may also be stored and / or executed by a second CPU located at the far end of the hardware controlled by the CPU. According to any one of the embodiments of the present disclosure, when executed by the CPU, the software routines convert the general-purpose computer into a dedicated computer (controller) that controls the charged particle beam device and can provide identification of line defects. Although the methods and / or processes of the present disclosure are discussed as being implemented as software routines, some of the method operations disclosed therein may be performed in hardware as well as by a software controller. Thus, embodiments may be implemented as software executed on a computer system and in hardware that may be embodied as an application specific integrated circuit or other type of hardware, or in a combination of software and hardware. According to embodiments of the present disclosure, a controller may execute or perform a method for identifying defects on a substrate having a plurality of pixels of a display located on the substrate, for example, for use in display manufacturing.

[0076] According to the embodiments described herein, the methods of the present disclosure may be performed using a computer program, software, computer software product and an interrelated controller that may have a CPU, memory, a user interface and input and output means for communicating with corresponding components of the apparatus.

[0077] Methods and corresponding apparatus for testing display substrates, particularly during display manufacturing (i.e., before the manufacturing process is complete), typically include testing of lines and / or substrate pixels. Determining a faulty pixel in a large-area substrate, such as a liquid crystal display (LCD) panel or an OLED panel, can be based on the pixel, the pixel's driver circuitry, a line (gate, signal, or other line), or a combination thereof. Furthermore, locating line defects is beneficial, particularly with a shortened test period.

[0078] According to one embodiment, a device for identifying linear defects on a substrate having a plurality of pixels disposed thereon is provided. The device includes: a detector configured to generate a voltage contrast image on the substrate; and a computer-readable medium containing a program for identifying linear defects on the substrate having the plurality of pixels disposed thereon. When the program is executed by a processor, the method according to any one of the embodiments of the present disclosure is performed.

[0079] For example, in addition to the pixels on the substrate, the testing of line defects on the substrate may include voltage contrast imaging. For example, as described below, a scanning electron microscope image including voltage contrast performed by an EBT column may be provided. According to some embodiments that may be combined with other embodiments described herein, a strip test may be additionally provided as a high-resolution scan, i.e., an imaging scan compared to a pixel scan. A high-resolution scan may be provided along one or more lines (e.g., data lines, gate lines, or other lines) to help locate the short circuit location.

[0080] Shorts along parallel lines (e.g., gate / common, data / common, or for borderless panels also vertical gate or common to data) can be difficult to locate because typically only one coordinate (gate or data) can be clearly identified. A high-resolution (e.g., 5 μm pixel pitch) strip image can be provided along the detected data or gate line. The defect location can be found by comparing the image of the line next to each pixel with the image of the adjacent pixel. At the short location, the image may deviate from the non-defective neighborhood. Therefore, the identification of line defects can be further improved by high-resolution images.

[0081] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be envisaged without departing from the basic scope thereof, and the scope of the disclosure is to be determined by the scope of the appended claims.

Claims

1. A method for identifying line defects on a substrate having a display located thereon, the method comprising: determining a line defect using a first test, the line defect having a first orientation; Set line test parameters for line retesting; as well as One or more first strips oriented in a first orientation are tested, the one or more first strips being parallel to the line defect, the one or more first strips having a first dimension and a second dimension, the first dimension extending at least along a field of view of the charged particle beam device, and the second dimension extending only along a portion of the field of view. 2 . The method of claim 1 , wherein the aspect ratio between the first dimension and the second dimension is at least 10:

1.

3. The method of claim 1, wherein an aspect ratio between the first dimension and the second dimension is at least 40:

1.

4. The method of claim 1, wherein an aspect ratio between the first dimension and the second dimension is at least 100:

1. The method of claim 1 , wherein the one or more first stripes comprise the linear defect. The method of claim 1 , wherein the one or more first stripes exclude the line defect. The method of claim 1 , wherein the one or more first strips are a plurality of strips within the field of view.

8. The method of claim 1 , wherein determining the line defect using the first test comprises: Set main test parameters that are different from the line test parameters.

9. The method according to any one of claims 1 to 8, wherein the step of determining the line defect using the first test comprises: The field of view is tested using an extension along the field of view in the first dimension and the second dimension.

10. The method according to any one of claims 1 to 8, wherein the step of determining the line defect using the first test comprises: The main stripe test is performed with one or more second strips oriented in a second orientation different from the first orientation, the one or more second strips having a first dimension and a second dimension, the second dimension extending at least along the field of view of the charged particle beam device, and the first dimension extending only along a portion of the field of view.

11. The method of claim 10, wherein the main stripe test comprises: The display is driven from a first side of the display and a second strip disposed on a second side of the display opposite the first side is tested.

12. The method of claim 11, wherein the main stripe test further comprises: The display is driven from the second side of the display and a third strip at the first side of the display is tested.

13. The method according to any one of claims 1 to 8, further comprising: A high-resolution image is scanned along the line having the line defect.

14. The method according to any one of claims 1 to 8, wherein the step of identifying the line defect comprises locating an intersection position between a vertical line and a horizontal line formed on the substrate.

15. The method of any one of claims 1 to 8, wherein the one or more first strips are scanned with a digital scanner.

16. The method of any one of claims 1 to 8, wherein the one or more first strips oriented along the first orientation are tested using an electron beam testing system.

17. An apparatus for identifying line defects on a substrate having a plurality of pixels disposed thereon, the apparatus comprising: a detector configured for voltage contrast image generation on the substrate; as well as A computer-readable medium comprising a program for identifying line defects on a substrate having a plurality of pixels thereon, wherein when the program is executed by a processor, the method according to any one of claims 1 to 8 is performed.

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