Display substrate, manufacturing method thereof and display device

Abstract

This invention provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes a substrate, a first signal line, a first planarization layer, a second signal line, and a second planarization layer sequentially disposed along a direction away from the substrate. The second signal line is electrically connected to the first signal line through a via penetrating the first planarization layer. The display substrate includes a first region, a second region, and a third region. A first height difference between the height of the second planarization layer in the second region and its height in the third region is less than 0.3 micrometers. By controlling the height difference of the second planarization layer in the second and third regions, embodiments of this invention allow liquid crystal to more easily enter the via region, reducing the potential obstruction effect on the liquid crystal due to the higher height of the second planarization layer in the second region. This helps to reduce potential bubble defects and improve the reliability of the display substrate.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display substrate, its manufacturing method, and a display device. Background Technology

[0002] With the development of display technology, high resolution and narrow bezels have become important requirements for users' experience with display devices. One related technology uses a display substrate fabricated through a 12-step mask process (mask exposure and etching process). In the display area, the display signal lines are designed directly above the touch signal lines to reduce space occupation and increase the aperture ratio of the display panel. In the non-display area, scan lines, display signal lines, and touch signal lines are stacked to reduce the bezel width. However, this display substrate may have a bubble defect problem. Summary of the Invention

[0003] This invention provides a display substrate, a method for manufacturing the same, and a display device to solve the problem of potential bubble defects in the display substrate.

[0004] In a first aspect, embodiments of the present invention provide a display substrate, including a substrate, a first signal line, a first planarization layer, a second signal line, and a second planarization layer sequentially disposed along a direction away from the substrate, wherein the second signal line is electrically connected to the first signal line through a via penetrating the first planarization layer;

[0005] The display substrate includes a first region, a second region, and a third region, wherein the height difference between the second planarization layer in the second region and the height in the third region is less than 0.3 micrometers.

[0006] Wherein, the first region is the region corresponding to the via, the orthographic projection of the second region on the substrate covers the first orthographic projection, the first orthographic projection is the portion of the orthographic projection of the first signal line and / or the second signal line on the substrate outside the first region, the third region is the region outside the first region and the second region, and the height of the second planarization layer is the distance between the surface of the second planarization layer away from the substrate and the substrate.

[0007] In some embodiments, the first height difference is less than 0.2 micrometers.

[0008] In some embodiments, the thickness of the second planarization layer in the second region is less than the thickness in the third region.

[0009] In some embodiments, the distance between the side surface of the second flattening layer away from the substrate and the side surface of the first flattening layer away from the substrate is in a ratio of less than 1:1 and greater than or equal to 1:1.05 in the second region and the third region.

[0010] In some embodiments, in the second region, the thickness of the second planarization layer decreases sequentially along the direction from the first region to the third region.

[0011] In some embodiments, the orthographic projection of the second planarization layer on the substrate overlaps with the orthographic projection of the first region on the substrate.

[0012] In some embodiments, the second height difference between the height of the first planarization layer in the second region and the height in the third region is less than 0.15 micrometers, wherein the height of the first planarization layer is the distance between the surface of the first planarization layer away from the substrate and the substrate.

[0013] In some embodiments, the thickness of the second planarization layer is 1 to 1.7 times the thickness of the first planarization layer.

[0014] In some embodiments, the distance between the side surface of the first planarization layer away from the substrate and the side surface of the first signal line close to the substrate is such that the ratio of the thickness of the second region to the thickness of the third region is less than 1:1 and greater than or equal to 1:1.05.

[0015] In some embodiments, in the second region, the thickness of the first planarization layer decreases sequentially along the direction from the first region to the third region.

[0016] In a second aspect, embodiments of the present invention provide a display device comprising the display substrate described in any one of the first aspects.

[0017] Thirdly, embodiments of the present invention provide a method for manufacturing a display substrate, comprising the following steps:

[0018] Provide a substrate;

[0019] A first signal line is formed on the substrate;

[0020] A first planarization layer is formed on the side of the first signal line away from the substrate, wherein a via is formed in the first planarization layer to expose a portion of the surface of the first signal line away from the substrate.

[0021] A second signal line is formed on the side of the first planarization layer away from the substrate, and the second signal line is electrically connected to the first signal line through the via.

[0022] A second planarization layer is formed on the side of the second signal line away from the substrate. The display substrate includes a first region, a second region, and a third region. The first height difference between the height of the second planarization layer in the second region and the height in the third region is less than 0.3 micrometers.

[0023] Wherein, the first region is the region corresponding to the via, the orthographic projection of the second region on the substrate covers the first orthographic projection, the first orthographic projection is the portion of the orthographic projection of the first signal line and / or the second signal line on the substrate outside the first region, the third region is the region outside the first region and the second region, and the height of the second planarization layer is the distance between the surface of the second planarization layer away from the substrate and the substrate.

[0024] In some embodiments, forming a second planarization layer on the side of the second signal line away from the substrate includes:

[0025] A second planarization layer is formed by a photomask exposure etching process, wherein the exposure intensity varies sequentially in the first region, the second region, and the third region.

[0026] In some embodiments, both the first planarization layer and the second planarization layer are fabricated using an exposure etching process with a photomask. The effective exposure area of ​​the photomask includes a fully transparent area, a semi-transparent area, and an opaque area, wherein the fully transparent area corresponds to the first area, the semi-transparent area corresponds to the second area, and the opaque area corresponds to the third area.

[0027] In some embodiments, the semi-transparent area of ​​the mask includes a plurality of primary sub-regions, each of the primary sub-regions being divided into a plurality of secondary sub-regions, wherein each secondary sub-region within each primary sub-region has a different transmittance.

[0028] In some embodiments, each primary sub-region has a secondary sub-region with the same transmittance.

[0029] By controlling the height difference between the second planarization layer in the second and third regions, the liquid crystal can more easily enter the via region, reducing the obstruction effect that the higher height of the second planarization layer might have on the liquid crystal in the second region. This helps to reduce potential bubble defects and improve the reliability of the display substrate. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of a display substrate in related technologies;

[0032] Figure 2 This is a structural diagram of the via region in related technologies;

[0033] Figure 3 This is a structural diagram of poor bubble formation in related technologies;

[0034] Figure 4 This is a schematic diagram of the structure of a display substrate in one embodiment of the present invention;

[0035] Figure 5A This is another structural schematic diagram of the display substrate in one embodiment of the present invention;

[0036] Figure 5B This is another structural schematic diagram of the display substrate in one embodiment of the present invention;

[0037] Figure 5C This is another structural schematic diagram of the display substrate in one embodiment of the present invention;

[0038] Figure 6 This is a flowchart of a method for manufacturing a display substrate according to an embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the patterned process of the first planarization layer in one embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of an intermediate process for fabricating the first planarization layer in one embodiment of the present invention;

[0041] Figure 9 This is a schematic diagram of the complete substrate structure according to an embodiment of the present invention;

[0042] Figure 10 This is a flowchart of a method for determining the transmittance of a photomask in one embodiment of the present invention;

[0043] Figure 11 This is a schematic diagram illustrating the division of primary and secondary sub-regions in one embodiment of the present invention;

[0044] Figure 12 This is a schematic diagram of the division of a tertiary subregion within a secondary subregion in one embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] The inventors of this application discovered that existing display substrates may have bubble defects. Through investigation, the inventors found that the reason for this phenomenon is that the height of the area surrounding the via is different from other areas. Generally, the height of the area surrounding the via is slightly higher than other areas, with a height difference of approximately 0.6 micrometers to 1 micrometer. Here, the height of the structure refers to the distance between the surface of the structure furthest from the substrate and the substrate.

[0047] It is important to understand that, generally speaking, a planarization layer produced by a planarization process is considered to be basically flat. Here, flatness means that the height of the planarization layer is uniform, that is, the distance between the planarization layer and the substrate is basically equal at different positions on the side of the planarization layer away from the substrate.

[0048] like Figure 1 and Figure 2 As shown, due to the presence of display signal line 101 and touch signal line 102 in the via area, even if a planarization layer is formed for planarization, the height near the via area is relatively higher than other locations. Figure 2 The central area corresponds to the via, and its height is greater than that of the surrounding area. This makes it difficult for liquid crystal to diffuse into the via area where the display signal line 101 and the touch signal line 102 are connected.

[0049] like Figure 3 As shown, even if a pressing process is introduced in subsequent processes such as polarizer (POL) bonding to squeeze the liquid crystal in the surrounding area of ​​the via into the via, it is difficult to replenish the liquid crystal in the surrounding area of ​​the via. This leads to the formation of vacuum bubbles in the surrounding area of ​​the via, resulting in bubble defects.

[0050] This invention provides a display substrate.

[0051] like Figure 4As shown, in one embodiment, the display substrate includes a substrate 401 and a buffer layer 402, a semiconductor layer 403, a gate insulating layer (GI) 404, a dielectric layer (ILD) 405, a first signal line (SD) 406, a first planarization layer (PLN) 407, a first protective layer (PAS) 408, a second signal line (TPM) 409, a first transparent electrode layer (C-ITO) 410, a second planarization layer (TVC) 411, a second protective layer (PVX) 412, and a second transparent electrode layer (P-ITO) 413, which are sequentially disposed along a direction away from the substrate 401.

[0052] Understandable, Figure 4 In the illustrated embodiment, the first transparent electrode layer 440 may be fabricated between the touch signal line 409 and the second planarization layer 411. In other embodiments, the first transparent electrode layer 440 may also be fabricated between the second planarization layer 411 and the second protective layer 412.

[0053] The display substrate includes a first region 400A, a second region 400B, and a third region 400C. The first height difference between the height of the second planarization layer in the second region 400B and the height in the third region 400C is less than 0.3 micrometers. Further, in some embodiments, the first height difference is less than 0.2 micrometers.

[0054] like Figure 4 As shown, in some embodiments, the first region 400A is the region corresponding to the via, which can be understood as the first region 400A forming the via after the Mask process.

[0055] The orthographic projection of the second region 400B on the substrate 401 covers the first orthographic projection. The first orthographic projection is the portion of the orthographic projection of the first signal line 406 and / or the second signal line 409 on the substrate 401 outside the first region 400A. It can be understood that the second region 400B includes the regions corresponding to the first signal line 406 and / or the second signal line 409, excluding the vias.

[0056] It should be understood that the height of the first flattening layer 409 and the second flattening layer 411 is mainly affected by the height of the first signal line 406 and the second signal line 409. Therefore, in this embodiment, the division of each region is based on the distribution of the first signal line 406 and the second signal line 409.

[0057] like Figure 5A As shown, in some embodiments, the range of the first signal line 406 is larger than the range of the second signal line 409. In this case, the second region 400B can be understood as the region corresponding to the first signal line 406.

[0058] like Figure 5BAs shown, in another embodiment, the range of the second signal line 409 is larger than the range of the first signal line 406. In this case, the second region 400B can be understood as the region corresponding to the second signal line 409.

[0059] like Figure 5C As shown, in another embodiment, there is a certain non-overlapping area between the range of the first signal line 406 and the range of the second signal line 409. In this case, the second region 400B includes the region corresponding to the first signal line 406 and the region corresponding to the second signal line 409.

[0060] The third zone 400C is the area outside of the first zone 400A and the second zone 400B.

[0061] The height of each structure refers to the distance between the surface of the structure furthest from the substrate 401 and the substrate 401. For example, the height of the first planarization layer 407 is the distance between the surface of the first planarization layer 407 furthest from the substrate 401. Figure 4 The distance between the upper and middle surfaces of the second planarization layer 411 and the substrate 401, and the height of the second planarization layer 411 is the distance between the upper and middle surfaces of the second planarization layer 411 and the surface of the second planarization layer 411 away from the substrate 401. Figure 4 The distance between the upper and middle surfaces and the substrate 401.

[0062] This invention, by controlling the height difference between the second planarization layer 411 in the second region 400B and the third region 400C, allows liquid crystal to more easily enter the via region. This reduces the obstruction effect that the second planarization layer 411 might have on the liquid crystal in the second region 400B due to its higher height. As a result, the via is already filled with liquid crystal before the pressing process, and vacuum bubbles caused by liquid crystal filling the via will not occur in the subsequent pressing process. This helps to reduce the possibility of bubble defects and improve the reliability of the display substrate.

[0063] In some embodiments, the second height difference between the height of the first planarization layer 407 in the second region 400B and the height in the third region 400C is less than 0.15 micrometers. In some preferred embodiments, the second height difference can be controlled to be less than 0.1 micrometers, which helps to further improve the uniformity of the height of the first planarization layer 407. The height of the first planarization layer 407 is the distance between the surface of the first planarization layer 407 away from the substrate 401 and the substrate 01.

[0064] It should be understood that the height difference of the first planarization layer 407 is mainly caused by the first signal line 406. Therefore, in some embodiments, the thickness of the first planarization layer 407 can be adjusted only for the area of ​​the first signal line 406.

[0065] Obviously, the height of the first signal line 406 can also be adjusted simultaneously for the areas where the first signal line 406 and the second signal line 409 exist. This is equivalent to pre-adjusting the height of the first planarization layer 407 for the position of the second signal line 409. When manufacturing the second signal line 409 and the second planarization layer 411, since the height of the first planarization layer 407 has been adaptively adjusted, the amount of change required to adjust the height of the second planarization layer 411 is reduced, which helps to simplify the process and improve control accuracy.

[0066] In other words, in this embodiment, the uniformity of the height of the second planarization layer 411 can be improved by adjusting only the thickness of the second planarization layer 411 in one adjustment; or the uniformity of the height of the second planarization layer 411 can be improved by controlling the thickness of the first planarization layer 407 and the second planarization layer 411 respectively through two process adjustments.

[0067] In some embodiments, the thickness of the second planarization layer 411 is 1 to 1.7 times the thickness of the first planarization layer 407.

[0068] It should be understood that the greater the thickness of the planarization layer, the better the planarization result. Generally, the thickness of the first planarization layer 407 is greater than the thickness of the second planarization layer 411. In this embodiment, by increasing the thickness of the second planarization layer 411, the planarization effect of the second planarization layer 411 can be improved to a certain extent, reducing the complexity of subsequent adjustments to the height of the second planarization layer 411 and helping to improve the reliability of the display substrate.

[0069] In some embodiments, the thickness of the first planarization layer 407 and the second planarization layer 411 is increased simultaneously to improve the planarization effect.

[0070] Research has shown that increasing the thickness of the second planarization layer 411 yields greater benefits than increasing the thickness of the first planarization layer 407. In one embodiment, the thickness of the first planarization layer 407 is set to 1.8 micrometers and the thickness of the second planarization layer 411 is set to 3.0 micrometers. In another embodiment, the thickness of both the first and second planarization layers is set to 2.3 micrometers, both effectively improving the bubble defect phenomenon.

[0071] like Figure 4 As shown, in some embodiments, the first planarization layer 407 has a first thickness h1 in the second region 400B and a second thickness h2 that is smaller than that in the third region 400C.

[0072] The distance between the side surface of the first planarization layer 407 away from the substrate 401 and the side surface of the first signal line 406 close to the substrate 401 is denoted as the first distance L1. The first distance L1 can also be understood as the distance between the lower surface of the first signal line 406 and the upper surface of the first planarization layer 407.

[0073] It is understandable that in the second region 400B, the first distance L1 includes the thickness of the first planarization layer 407 and the thickness of the first signal line 406, while in the third region 400C, the first distance L1 is mainly the thickness of the first planarization layer 40.

[0074] The ratio of the first distance L1 in the second region 400B and the third region 400C is less than 1:1 and greater than or equal to 1:1.05.

[0075] By reducing the thickness of the first planarization layer 407 in the second region 400B, it helps to reduce the difference between the first distance L1 in the second region 400B and the third region 400C, thereby helping to improve the uniformity of the height of the first planarization layer 407, which in turn helps to improve the uniformity of the height of the subsequently fabricated second planarization layer 411.

[0076] Similarly, in some embodiments, the thickness of the second planarization layer 411 in the second region 400B is less than its thickness in the third region 400C.

[0077] like Figure 4 As shown, in some embodiments, the distance between the side surface of the second planarization layer 411 away from the substrate 401 and the side surface of the first planarization layer 407 away from the substrate 401 is denoted as the second distance L2, based on... Figure 4 In the direction shown, the second distance L2 can be understood as the distance between the upper surface of the second flattening layer 411 and the upper surface of the first flattening layer 407.

[0078] It is understandable that in the second region 400B, the second distance L2 includes the thickness of the second planarization layer 411 and the thickness of the second signal line 409, while in the third region 400C, the second distance L2 includes the thickness of the second planarization layer 411.

[0079] The ratio of the second distance L2 in the second region 400B and the third region 400C is less than 1:1 and greater than or equal to 1:1.05.

[0080] It is understood that in the second region 400B, the presence of the first signal line 406 and / or the second signal line 409 leads to an increase in the height of the second flattening layer 411. In this embodiment, the thickness of the second flattening layer 411 in the second region 400B is reduced, which helps to reduce the difference between the second distance L2 in the second region 400B and the third region 400C. This reduces the increase in the height of the second flattening layer 411 in the second region 400B caused by the presence of the first signal line 406 and / or the second signal line 409, thus helping to improve the height uniformity of the second flattening layer 411 in different regions.

[0081] In some embodiments, in the second region 400B, the thickness of the second planarization layer 411 decreases sequentially along the direction from the first region 400A to the third region 400C. This allows the height of the second planarization layer 411 to also be adjusted; specifically, the height of the second planarization layer 411 can also have a certain decreasing trend along the direction from the first region 400A to the third region 400C. During liquid crystal filling, this makes it easier for the liquid crystal to enter the vias, helping to reduce the possibility of bubble defects.

[0082] In some embodiments, in the second region 400B, the thickness of the first planarization layer 407 decreases sequentially along the direction from the first region 400A to the third region 400C. Similarly, adjusting the height of the first planarization layer 407 helps to improve the convenience of subsequent adjustments to the height of the second planarization layer 411, thereby reducing the possibility of bubble defects.

[0083] In some embodiments, the orthographic projection of the second planarization layer 411 on the substrate 401 overlaps with the orthographic projection of the first region 400A on the substrate 401. This can be understood as a portion of the second planarization layer 411 extending into the via in this embodiment. This reduces the slope angle of the via, thereby helping to reduce the slope angle of other structures subsequently fabricated, such as the second transparent electrode layer 413, and thus helping to improve the reliability of the display substrate.

[0084] Furthermore, in some embodiments, during the cell assembly process, the amount of liquid crystal is appropriately increased. Specifically, the amount of liquid crystal can be increased by a certain percentage based on the existing amount. For example, the amount of liquid crystal can be increased by different values ​​such as 1% or 3%, which also helps to improve the filling effect of vias, timely replenish the liquid crystal filling the surrounding area into the vias, and reduce the possibility of generating bubbles and defects.

[0085] It should be understood that the technical solution of this embodiment can be applied to display substrates manufactured by the 12Mask process, and can also be applied to other similar scenarios to solve the same or similar problems.

[0086] This invention also provides a display device, including any of the above-described display substrates.

[0087] Since the display device in this embodiment includes all the technical solutions of the above-described display substrate embodiments, it can achieve at least all of the above-described technical effects, which will not be repeated here.

[0088] This invention also provides a method for manufacturing a display substrate.

[0089] like Figure 6 As shown, in one embodiment, the method includes the following steps:

[0090] Step 601: Provide a substrate.

[0091] Step 602: Form a first signal line on the substrate.

[0092] like Figure 7 As shown, in this embodiment, a first signal line 406 is first formed on the substrate 401. It can be understood that before forming the first signal line 406, other structures can be formed on the substrate 401 as needed. For example, these may include a buffer layer 402, a semiconductor layer 403, a gate insulating layer 404, a dielectric layer 405, etc.

[0093] It should be noted that the first signal line 406 can refer to... Figure 1 The display signal line 101 in the display substrate shown can also be other signal lines. In this embodiment, the first signal line 106 is used as the display signal line 101 for illustrative purposes. Similarly, the second signal line 109 can be the touch signal line 102.

[0094] Step 603: A first planarization layer is formed on the side of the first signal line away from the substrate, wherein a via is formed in the first planarization layer to expose the surface portion of the first signal line away from the substrate.

[0095] Step 604: A second signal line is formed on the side of the first planarization layer away from the substrate, and the second signal line is electrically connected to the first signal line through the via.

[0096] Please also refer to Figure 4 and Figure 7 In fabricating the first planarization layer 407, a first planarization layer material 407A is first deposited. Then, the deposited first planarization layer material 407A is patterned using a mask process to obtain the first planarization layer 407. The materials used and any process steps not described in detail can be referenced from relevant technologies, and no further limitations are made here.

[0097] After the first planarization layer material 407A is deposited, vias need to be opened through the Mask process to form the first planarization layer 407, so that the surface portion of the first signal line 406 away from the substrate 401 is exposed.

[0098] Step 605: Form a second planarization layer on the side of the second signal line away from the substrate.

[0099] Next, through a process similar to that used to form the first planarization layer 407, the second planarization layer 411 is fabricated using the Mask process. The specific structure of the fabricated second planarization layer 411 can be found in [reference needed]. Figure 4 The embodiments shown are not described in detail here.

[0100] In some embodiments, step 605 above includes:

[0101] A second planarization layer is formed by a photomask exposure etching process, wherein the exposure intensity varies sequentially in the first region, the second region, and the third region.

[0102] In some embodiments, the first planarization layer 407 and the second planarization layer 411 are both fabricated using a mask process.

[0103] In some embodiments, the photoresist used in the Mask process is a positive photoresist, and the exposure intensity of the first region 400A, the second region 400B, and the third region 400C decreases sequentially.

[0104] like Figure 7 As shown, the fabrication process of the first planarization layer 407 is illustrated by way of example. The effective exposure area of ​​the mask 700 includes a fully transparent area 701, a semi-transparent area 702, and an opaque area 703.

[0105] like Figure 7 As shown, the fully transparent area 701 corresponds to the first area 400A, the semi-transparent area 702 corresponds to the second area 400B, and the opaque area 703 corresponds to the third area 400C.

[0106] In some embodiments, the first region 400A corresponds to the transparent region 701 of the mask 700, the second region 400B corresponds to the semi-transparent region 702 of the mask 700, and the third region 400C corresponds to the opaque region 703 of the mask 700. In this way, the first region 400A is fully exposed, the second region 400B is partially exposed, and the third region 400C is not exposed.

[0107] like Figure 7As shown, in the Mask process, photoresist is first coated on the first planarization layer material 407A, and then the mask 700 is aligned, ultraviolet (UV) exposed, developed, etched and other processes are performed. Finally, the remaining photoresist is stripped off.

[0108] Please continue reading. Figure 7 In the Mask process, the first region 400A is fully exposed, and the first planarization layer material 407A corresponding to the first region 400A is removed the most, thus forming a via through the first planarization layer 407 in the first region 400A.

[0109] The second region 400B is partially exposed, and the first planarization layer material 407A of the second region 400B is partially removed, which can be understood as a thinning process being performed on the second region 400B.

[0110] The third region 400C has the lowest exposure intensity, which can be described as unexposed. The first planarization layer material 407A in the third region 400C is completely preserved.

[0111] Because the first planarization layer material 407A is partially removed in the second region 400B, the height of the first planarization layer 407 in the second region 400B is reduced, thereby reducing the height difference between the second region 400B and the third region 400C, and further improving the flatness of the upper surface of the first planarization layer 407. Here, the upper surface refers to the surface of the first planarization layer 407 away from the substrate 401, that is... Figure 4 , Figure 7 and Figure 8 The upper surface in the state shown.

[0112] Please also refer to Figure 7 and Figure 8 Through the Mask process, vias can be created, and the first planarization layer 407 of the second region 400B can be thinned, making the surface height of the first planarization layer 407 more uniform and improving its planarity.

[0113] The fabrication process of the second planarization layer 411 is similar to that of the first planarization layer 407. Specifically, the selected materials, exposure areas, and other process parameters and conditions can be adapted according to the fabrication process of the first planarization layer 407.

[0114] The material of the second planarization layer 411 within the second region 400B is partially removed to compensate for the increased height of the second planarization layer 411 due to the presence of the first signal line 406 and / or the second signal line 409. Here, "upper" and "lower" refer to the height of the second planarization layer 411 based on the presence of the first signal line 406 and / or the second signal line 409. Figure 4 The directions shown are up and down. The resulting second flattening layer 411 has higher flatness, which helps to optimize the structure of the area adjacent to the via and reduces the possibility of bubble defects.

[0115] When using negative photoresist, the process steps and the structure of the photomask can be adjusted accordingly, which will not be elaborated here.

[0116] In some embodiments, an additional patterning process can be added to create a filling structure to fill the vias. This filling structure covers the area outside the opening area and the pad area (wiring area). Because the vias are filled, the possibility of air bubble defects is completely eliminated, which also helps improve problems such as poor printing on the display substrate, light leakage, and localized black spots. Although an additional masking process is added, it helps improve the reliability of the display substrate.

[0117] In some embodiments, the translucent region 702 of the mask 700 includes a plurality of sub-regions, and the transmittance of each sub-region is determined according to the position of the sub-region and its alignment position with the display substrate.

[0118] like Figure 9 As shown, in actual production, the substrate 901 used is relatively large and is usually divided into multiple regions. This embodiment uses four regions as an example. During the fabrication process, in each process step, the same mask is used to perform a masking process in one region, and then the process is moved to the next region for another masking process.

[0119] After completing all the process steps, the obtained whole substrate is cut to obtain multiple display substrates, specifically four in this embodiment.

[0120] Further research by the inventors revealed that, due to the large size of the substrate, the transmittance of different regions varies. This may be affected by factors such as relative position, substrate deformation caused by gravity, and mask deformation. Therefore, the exposure rate corresponding to the same process parameters may differ at different locations.

[0121] This can be understood as follows: due to the deformation of the mask or substrate under gravity, or the influence of light transmittance or other film layer interference factors in different areas of the semi-finished display substrate, the thickness of the first planarization layer material or the second planarization layer material at different positions is different when performing the Mask process based on the same process parameters. In other words, the actual process results corresponding to the same process parameters are different.

[0122] In this embodiment, the display substrate is further divided into multiple sub-regions. Furthermore, the transmittance of the corresponding region is determined based on the position of the different sub-regions in the substrate and their alignment with the display substrate, so as to improve the manufacturing effect.

[0123] This invention provides a method for determining the transmittance of a photomask, used to determine the transmittance of different regions of the aforementioned photomask.

[0124] like Figure 10 As shown, in one embodiment, the method includes the following steps:

[0125] Step 1001: Divide the effective exposure area of ​​the mask into multiple primary sub-regions;

[0126] Step 1002: Divide each of the first-level sub-regions into multiple second-level sub-regions, wherein each second-level sub-region in each first-level sub-region has a different transmittance;

[0127] Step 1003: Adjust the key dimensions of the mask to detect the thinning thickness of each secondary sub-region of each primary sub-region when the key dimensions are different;

[0128] Step 1004: Determine the target transmittance of each sub-region of the mask under the corresponding target key dimensions and target thinning thickness.

[0129] like Figure 11 As shown, in this embodiment, the mask is first divided into multiple primary sub-regions, where each box corresponds to a primary sub-region, in order to determine the difference in light transmittance between different regions.

[0130] Each primary sub-region is further divided into multiple secondary sub-regions, each with a different light transmittance. Figure 11 Each number corresponds to a secondary sub-region, and the number represents the transmittance of that secondary sub-region.

[0131] The technical solution of this embodiment can be understood as follows: to test the differences in transmittance in different regions, the mask is divided into multiple primary sub-regions, each corresponding to a different location, such as the central region, edge region, etc., thereby analyzing the changes in process parameters caused by positional differences based on each primary sub-region. In this way, for each primary sub-region, the actual processing results of the mask process under different transmittances are tested. Based on these actual processing results, the actual process differences in different regions can be determined, allowing for targeted adjustments to the transmittance of that region.

[0132] Each primary sub-region includes multiple secondary sub-regions, and each secondary sub-region corresponds to a transmittance to be measured. This can be understood as one secondary sub-region corresponding to one transmittance. Within different primary sub-regions, there exist secondary sub-regions with the same transmittance. For example... Figure 11Both the primary sub-region in the upper left corner and the primary sub-region in the lower right corner contain secondary sub-regions with a transmittance of 20%. By comparing the process results of these two secondary sub-regions, we can determine the impact of the positional difference between the upper left and lower right corners on the actual process results under the same process parameters.

[0133] In this embodiment, a secondary sub-region with 100% transmittance is set, and the transmittance to be measured is set into 11 secondary sub-regions ranging from 5% to 55% in increments of 5%. Thus, a primary sub-region actually includes 12 secondary sub-regions.

[0134] It is understood that the range of transmittance adjustment is not limited to this. For example, it can be set to different values ​​such as 5% to 75% or 20% to 70%. The transmittance step size can also be set as needed. For example, it can be set to different values ​​such as 3%, 4%, or 6%. The transmittance step size can be fixed or fluctuating. For example, the transmittance can be set to 5%, 8%, 13%, 15%, etc., with the transmittance step size fluctuating and changing between 3% and 5%. In implementation, the range of transmittance and transmittance change compensation can be set as needed, without further limitations here.

[0135] For each secondary sub-region, different critical dimensions (Mask Critical Dimension, abbreviated as Mask CD) are further set to detect the actual process results corresponding to different critical dimensions.

[0136] Mask CD can be understood as the aperture size or minimum linewidth of the mask. Masks with different Mask CDs are required to meet different precision process requirements. When different patterning processes are needed, the mask must have different Mask CDs.

[0137] In order to measure the actual process results corresponding to each Mask CD under different transmittance, this embodiment further divides each secondary sub-region into multiple tertiary sub-regions, wherein each tertiary sub-region corresponds to one Mask CD. In this way, it is possible to measure the actual process results corresponding to different Mask CDs under different transmittance in different regions of the mask.

[0138] Based on the actual process results obtained, the transmittance of different areas of the mask can be further adjusted in a targeted manner according to the actual process requirements, which helps to further improve the flatness of the planarization layer and improve the reliability of the display substrate.

[0139] For example, such as Figure 11As shown, the effective exposure area of ​​the mask used in this embodiment is approximately 880 mm × 716 mm, which is evenly divided into 12 primary sub-regions in a 4*3 pattern. Each primary sub-region is no less than 200 mm × 200 mm in size. Each primary sub-region includes 12 secondary sub-regions with different transmittance, and each secondary sub-region is no less than 50 mm × 50 mm in size.

[0140] like Figure 12 As shown, for each second-level sub-region, 20 third-level sub-regions are set up. Figure 12 Each number corresponds to a tertiary sub-region and represents a Mask CD for that sub-region. The 20 tertiary sub-regions correspond to the openings of the 20 Mask CDs, ensuring that the spacing between each Mask CD is greater than 10 millimeters. This spacing is large enough to avoid interference between test results when testing different Mask CDs.

[0141] In some embodiments, the Mask CD of the mask is adjusted from 3.5 to 7.3 micrometers, and in some embodiments, the adjustment step of the key dimension of the mask is 0.2 micrometers.

[0142] like Figure 12 As shown, in this embodiment, the detection area corresponding to the variation of Mask CD from 3.5 micrometers to 7.3 micrometers is set with a step size of 0.2 micrometers, which can cover most process requirements. In some embodiments, in order to simplify the test results, the range of Mask CD to be tested can also be reduced, for example, it can be set from 4.5 micrometers to 6.0 micrometers. This can simplify the test process and help reduce test costs while meeting certain process requirements.

[0143] During the testing process, referring to the actual production process, for example, according to Figure 9 The substrate shown is used to move the mask to four regions for mask processing. The actual process parameters are then measured. Here, the actual process parameters refer to the actual thinning thickness, specifically including the thinning thickness of each tertiary sub-region, and the correspondence between the thinning thickness and the Mask CD, transmittance, and the position of the primary sub-region.

[0144] Actual process parameters can be statistically analyzed using transmittance and Mask CD. This can be understood as the statistical analysis of actual thinning dimensions corresponding to different Mask CDs at different locations and with varying transmittance.

[0145] By combining the actual process parameters and the target thinning thickness required under the target Mask CD according to the actual process requirements, and considering the location where the thinning process needs to be performed, the corresponding target transmittance can be determined. A mask is fabricated based on the determined target transmittance, and the masking process is performed using this mask. This results in a planarization layer with high flatness, which helps improve the reliability of the display substrate.

[0146] It is understandable that during implementation, the Mask CD of each structure of the product is fixed. Based on the position of each structure in the display substrate and the required thinning thickness, the corresponding transparency data can be determined from the index table. In this way, a mask is made based on the transparency data, and the mask process is carried out using the mask, which can improve the accuracy of the thinning process.

[0147] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display substrate, characterized by, The device includes a substrate, a first signal line, a first planarization layer, a second signal line, and a second planarization layer arranged sequentially in a direction away from the substrate, wherein the second signal line is electrically connected to the first signal line through a via penetrating the first planarization layer. The display substrate includes a first region, a second region, and a third region, wherein the height difference between the second planarization layer in the second region and the height in the third region is less than 0.3 micrometers. Wherein, the first region is the region corresponding to the via, the orthographic projection of the second region on the substrate covers the first orthographic projection, the first orthographic projection is the portion of the orthographic projection of the first signal line and / or the second signal line on the substrate outside the first region, the third region is the region outside the first region and the second region, and the height of the second planarization layer is the distance between the surface of the second planarization layer away from the substrate and the substrate. In the second region, along the direction from the first region to the third region, the thicknesses of the first flattening layer and the second flattening layer decrease sequentially.

2. The display substrate of claim 1, wherein, The first height difference is less than 0.2 micrometers. 3.The display substrate of claim 1 or 2, wherein, The thickness of the second planarization layer in the second region is less than the thickness in the third region.

4. The display substrate of claim 3, wherein, The distance between the side surface of the second flattening layer away from the substrate and the side surface of the first flattening layer away from the substrate is in a ratio of less than 1:1 and greater than or equal to 1:1.05 in the second region and in the third region. 5.The display substrate of claim 3, wherein, The orthographic projection of the second planarization layer on the substrate overlaps with the orthographic projection of the first region on the substrate.

6. The display substrate according to claim 1, characterized in that, The second height difference between the height of the first planarization layer in the second region and the height in the third region is less than 0.15 micrometers, wherein the height of the first planarization layer is the distance between the surface of the first planarization layer away from the substrate and the substrate.

7. The display substrate according to claim 1 or 6, characterized in that, The thickness of the second planarization layer is 1 to 1.7 times the thickness of the first planarization layer. 8.The display substrate of claim 7, wherein, The distance between the side surface of the first planarization layer away from the substrate and the side surface of the first signal line close to the substrate is such that the ratio of the thickness in the second region to the thickness in the third region is less than 1:1 and greater than or equal to 1:1.

05.

9. A display device, characterized by comprising: The display substrate includes any one of claims 1 to 8.

10. A manufacturing method of a display substrate, comprising: Includes the following steps: Provide a substrate; A first signal line is formed on the substrate; A first planarization layer is formed on the side of the first signal line away from the substrate, wherein a via is formed in the first planarization layer to expose a portion of the surface of the first signal line away from the substrate. A second signal line is formed on the side of the first planarization layer away from the substrate, and the second signal line is electrically connected to the first signal line through the via. A second planarization layer is formed on the side of the second signal line away from the substrate. The display substrate includes a first region, a second region, and a third region. The first height difference between the height of the second planarization layer in the second region and the height in the third region is less than 0.3 micrometers. Wherein, the first region is the region corresponding to the via, the orthographic projection of the second region on the substrate covers the first orthographic projection, the first orthographic projection is the portion of the orthographic projection of the first signal line and / or the second signal line on the substrate outside the first region, the third region is the region outside the first region and the second region, and the height of the second planarization layer is the distance between the surface of the second planarization layer away from the substrate and the substrate. In the second region, along the direction from the first region to the third region, the thicknesses of the first flattening layer and the second flattening layer decrease sequentially.

11. The method of claim 10, wherein, The formation of a second planarization layer on the side of the second signal line away from the substrate includes: A second planarization layer is formed by a photomask exposure etching process, wherein the exposure intensity varies sequentially in the first region, the second region, and the third region.

12. The method of claim 11, wherein, Both the first planarization layer and the second planarization layer are fabricated using an exposure etching process with a photomask. The effective exposure area of ​​the photomask includes a fully transparent area, a semi-transparent area, and an opaque area. The fully transparent area corresponds to the first area, the semi-transparent area corresponds to the second area, and the opaque area corresponds to the third area.

13. The method according to claim 12, characterized in that, The semi-transparent area of ​​the mask includes multiple primary sub-regions, each of which is further divided into multiple secondary sub-regions, wherein each secondary sub-region within each primary sub-region has a different transmittance.

14. The method according to claim 13, characterized in that, Each primary subregion has a secondary subregion with the same transmittance.

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