Memory system and non-volatile memory

Abstract

A memory system and a nonvolatile memory that suppress an increase in an amount of data transfer between a memory controller and the nonvolatile memory are provided. According to an embodiment, a memory system includes a nonvolatile memory including a plurality of memory cells each capable of storing at least a first bit, a second bit, and a third bit, and a memory controller that controls the nonvolatile memory. The nonvolatile memory outputs first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data related to the first bit, the second bit, and the third bit to the memory controller. The memory controller performs an error correction process using the first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data.

Description

[0001] [Related Applications]

[0002] This application enjoys priority to Japanese Patent Application No. 2021-191709 (filed on November 26, 2021). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention relate to a memory system and a non-volatile memory. Background Technology

[0004] There is a known memory system that incorporates non-volatile memory such as NAND (Not AND) flash memory. Summary of the Invention

[0005] In one embodiment of the present invention, a memory system and a non-volatile memory are provided that are capable of suppressing the increase in data transfer volume between the memory controller and the non-volatile memory.

[0006] The memory system of the embodiment includes: a non-volatile memory including a plurality of memory cells, each capable of storing at least a first bit, a second bit, and a third bit; and a memory controller that controls the non-volatile memory. The non-volatile memory outputs a first hard bit of data (the first bit), a second hard bit of data (the second bit), a third hard bit of data (the third bit), and a fourth soft bit of data associated with the first, second, and third bits to the memory controller. The memory controller performs error correction processing using the first hard bit of data, the second hard bit of data, the third hard bit of data, and the fourth soft bit of data. Attached Figure Description

[0007] Figure 1 This is a block diagram showing the overall configuration of a data processing apparatus including the memory system of the first embodiment.

[0008] Figure 2 This is a block diagram showing the configuration of the ECC circuit included in the memory system of the first embodiment.

[0009] Figure 3 This is a block diagram showing the configuration of the SB decoding circuit included in the memory system of the first embodiment.

[0010] Figure 4 This is a block diagram illustrating the basic structure of the non-volatile memory in the first embodiment.

[0011] Figure 5This is a circuit diagram of the memory cell array included in the non-volatile memory of the first embodiment.

[0012] Figure 6 This is a block diagram of the data register and sense amplifier included in the non-volatile memory of the first embodiment.

[0013] Figure 7 This is a graph showing the relationship between the threshold voltage distribution and data allocation of the TLC included in the non-volatile memory of the first embodiment.

[0014] Figure 8 This is a diagram illustrating an example of the relationship between the threshold voltage distribution of the "Er" state and the "A" state in the memory system of the first embodiment and the hard bit data and soft bit data.

[0015] Figure 9 This is a graph showing the relationship between the threshold voltage distribution of the TLC in the memory system of the first embodiment and the hard bit data and compressed soft bit data.

[0016] Figure 10 This diagram illustrates the calculation of soft data SB_L, SB_M, and SB_U based on the results of read operations of the lower, middle, and upper pages in the memory system of the first embodiment.

[0017] Figure 11 This diagram illustrates the computational processing of calculating compressed soft data based on the soft data SB_L, SB_M, and SB_U in the memory system of the first embodiment.

[0018] Figure 12 This diagram illustrates the decoding process of soft bit data SB_L, SB_M, and SB_U in the memory system of the first embodiment.

[0019] Figure 13 This is a flowchart of the read operation in the memory system of the first embodiment.

[0020] Figure 14 It is the instruction sequence of the first read mode in the memory system of the first embodiment.

[0021] Figure 15 It is the instruction sequence for the second read mode in the memory system of the first embodiment.

[0022] Figure 16 It is the instruction sequence for the third read mode in the memory system of the first embodiment.

[0023] Figure 17 This is a flowchart of the read operation in the memory system of the second embodiment.

[0024] Figure 18 This is a block diagram of the data register and sense amplifier included in the non-volatile memory of the third embodiment.

[0025] Figure 19 This is a graph showing the relationship between the threshold voltage distribution and the count value of the "Er" state and the "A" state in the memory system of the third embodiment.

[0026] Figure 20 This is a flowchart of the read operation in the memory system of the third embodiment.

[0027] Figure 21 It is the instruction sequence for the read operation in the memory system of the third embodiment.

[0028] Figure 22 This is a graph showing the relationship between the threshold voltage distribution and data allocation of the QLC included in the non-volatile memory of the fourth embodiment.

[0029] Figure 23 This is a graph showing the relationship between the threshold voltage distribution of the QLC in the memory system of the fourth embodiment and the hard bit data and compressed soft bit data.

[0030] Figure 24 This diagram illustrates the decoding process of soft bit data SB_L, SB_M, SB_U, and SB_T in the memory system of the fourth embodiment. Detailed Implementation

[0031] Hereinafter, embodiments will be described with reference to the accompanying drawings. The drawings are schematic diagrams. Furthermore, in the following description, constituent elements having substantially the same function and structure are labeled with the same symbols. The numbers following the text of the reference numerals are used to distinguish elements having the same structure from each other.

[0032] 1. First Implementation Method

[0033] 1.1 Composition

[0034] 1.1.1 Composition of the data processing device

[0035] First, refer to Figure 1 An example of the configuration of a data processing device 1 that includes a memory system will be described. Figure 1 This is a block diagram showing the overall configuration of the data processing device 1. Furthermore, in Figure 1 In the example, the arrows represent part of the connection between the constituent elements, but the connection between the constituent elements is not limited to these.

[0036] like Figure 1As shown, the data processing device 1 includes a host device 2 and a memory system 3. Furthermore, multiple memory systems 3 can be connected to the host device 2.

[0037] Host device 2 is an information processing device (computing device) that accesses memory system 3. Host device 2 controls memory system 3. More specifically, for example, host device 2 requests (commands) write or read data (hereinafter referred to as "user data") from memory system 3.

[0038] The memory system 3 is, for example, an SSD (Solid State Drive). The memory system 3 is connected to the host device 2.

[0039] 1.1.2 Memory System Composition

[0040] Next, refer to Figure 1 An example of the configuration of memory system 3 will be described.

[0041] like Figure 1 As shown, the memory system 3 includes a memory controller 10 and a non-volatile memory 20.

[0042] The memory controller 10 responds to requests (commands) from the host device 2 by instructing the non-volatile memory 20 to perform read, write, and erase operations. Furthermore, the memory controller 10 manages the memory space of the non-volatile memory 20.

[0043] The non-volatile memory 20 is, for example, a NAND flash memory. A NAND flash memory has multiple blocks. A block is, for example, a data erasure unit; data within the same block is erased together. Each block contains multiple memory cell transistors (hereinafter also referred to as "memory cells") that non-volatilely store data. Furthermore, the memory system 3 may include multiple non-volatile memories 20.

[0044] Next, the internal structure of the memory controller 10 will be described. The memory controller 10 includes a host interface circuit (host I / F) 11, a CPU (Central Processing Unit) 12, a ROM (Read Only Memory) 13, a RAM (Random Access Memory) 14, a buffer memory 15, an ECC (Error Checking and Correcting) circuit 16, and a memory interface circuit (memory I / F) 17. These circuits are interconnected, for example, via a bus. Furthermore, the functions of the memory controller 10 can be implemented either by dedicated circuitry or by firmware executed by the CPU 12.

[0045] The host interface circuit 11 is a hardware interface circuit connected to the host device 2. The host interface circuit 11 performs communication according to the interface standard between the host device 2 and the memory controller 10. The host interface circuit 11 sends requests and user data received from the host device 2 to the CPU 12 and the buffer memory 15, respectively. Additionally, in response to commands from the CPU 12, the host interface circuit 11 sends user data from the buffer memory 15 to the host device 2.

[0046] CPU 12 is a processor. CPU 12 controls the overall operation of memory controller 10. For example, based on requests received from host device 2, CPU 12 commands write operations, read operations, and erase operations to non-volatile memory 20.

[0047] In addition, based on the requests received from the host device 2, the CPU 12, besides processing the specific actions commanded by the non-volatile memory 20, also performs various processes in the background to manage the non-volatile memory 20, such as garbage collection, updates, wear leveling, and patrol reads. Furthermore, the CPU 12 performs various operations such as data encryption and randomization.

[0048] Garbage collection is also known as compaction. Because the data erasure unit and data read / write unit in non-volatile memory 20 are different, if overwriting of non-volatile memory 20 progresses, blocks become fragmented due to invalid data. If the number of such fragmented blocks increases, the number of usable blocks decreases. Garbage collection is a process used to increase the number of usable blocks. For example, it involves collecting valid data from multiple valid blocks containing both valid and invalid data, rewriting it into other blocks, and ensuring the availability of free blocks.

[0049] A valid block represents a block that records valid data. A free block represents a block that does not record valid data. A free block can be reused as an erased block after erasure. In this embodiment, a free block includes both the block before erasure without valid data and the erased block. Valid data refers to data that corresponds to a logical address, while invalid data refers to data that does not correspond to a logical address. A erased block becomes a valid block if data is written to it.

[0050] Updates, for example, involve rewriting the data in a block to other blocks when data degradation is detected in a block, such as when the number of correction bits increases during error correction processing using ECC circuit 16.

[0051] Loss leveling is, for example, a process of leveling the number of overwrites of blocks in non-volatile memory 20 by replacing the data stored in blocks with a relatively high number of overwrites or erases with the data stored in blocks with a relatively low number of overwrites or erases.

[0052] The patrol read is used to detect blocks with increasing errors, such as reading data stored in non-volatile memory 20 in specific units, and testing the read data against the error correction results in ECC circuit 16. This testing process, for example, compares the number of error bits in the read data with a threshold, and sets data with more than the threshold as update targets.

[0053] ROM13 is a non-volatile memory. For example, ROM13 is an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory). ROM 13 is a non-transitory storage medium for storing firmware and programs, etc. For example, the operation of the memory controller 10 described below is implemented by the CPU 12 executing the firmware of ROM 13.

[0054] RAM14 is volatile memory. RAM14 can be DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), etc. RAM14 is used as the operating area of ​​CPU12. RAM14 stores firmware or various management tables used to manage non-volatile memory 20.

[0055] Buffer memory 15 is volatile memory. Buffer memory 15 may be DRAM or SRAM, etc. Buffer memory 15 temporarily stores data read by memory controller 10 from non-volatile memory 20 or user data received from host device 2, etc.

[0056] ECC circuit 16 is the circuit that performs ECC processing. ECC processing includes data encoding and decoding. ECC circuit 16 encodes the data written to non-volatile memory 20. Encoding methods include BCH (Bose-Chaudhuri-Hocquenghem), RS (Reed-Solomon), LDPC (Low-Density Parity-Check), etc. ECC circuit 16 decodes the data read from non-volatile memory 20. In other words, ECC circuit 16 performs data error correction. The configuration of ECC circuit 16 will be described below.

[0057] The memory interface circuit 17 is a hardware interface circuit connected to the non-volatile memory 20. The memory interface circuit 17 performs communication according to the interface standard between the memory controller 10 and the non-volatile memory 20. Based on the control of the CPU 12, the memory interface circuit 17 transmits and receives data and various signals with the non-volatile memory 20.

[0058] More specifically, the memory interface circuit 17 and the non-volatile memory 20 transmit and receive, for example, 8-bit signals DQ<7:0> and clock signals DQS and DQSn. Signals DQ<7:0> can be, for example, data, address, and instruction. Hereinafter, without specifying any of the signals DQ<7:0>, it will be referred to as signal DQ. Clock signals DQS and DQSn are clock signals used for data input and output. Clock signal DQSn is the inverted version of clock signal DQS.

[0059] In addition, the memory interface circuit 17 sends a chip enable signal CEn, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn to the non-volatile memory 20. Furthermore, the memory interface circuit 17 sends a ready / busy signal RBn from the non-volatile memory 20.

[0060] The chip enable signal CEn is used to enable the non-volatile memory 20, for example, by being low ("L"). The instruction latch enable signal CLE indicates that the signal DQ is an instruction, for example, by being high ("H"). The address latch enable signal ALE indicates that the signal DQ is an address, for example, by being high ("H").

[0061] The write enable signal WEn is used to fetch received signals into non-volatile memory 20. The timing of instruction and address fetching from non-volatile memory 20 is, for example, activated at an "L" level. Therefore, whenever signal WEn is triggered, instructions and addresses are fetched into non-volatile memory 20.

[0062] The read enable signal REn is used by the memory controller 10 to read data from the non-volatile memory 20. The signal REn is active at, for example, an "L" level. For example, during data output, the non-volatile memory 20 generates signals DQS and DQSn based on the signal REn.

[0063] The ready / busy signal RBn indicates whether the non-volatile memory 20 is unable to receive the signal DQ from the memory controller 10 or is able to receive the signal DQ. For example, the ready / busy signal RBn is set to "L" level when the non-volatile memory 20 is in a busy state.

[0064] 1.1.3 Structure of ECC Circuit

[0065] Next, refer to Figure 2 An example of the configuration of ECC circuit 16 will be explained. Figure 2 This is a block diagram showing the configuration of ECC circuit 16.

[0066] like Figure 2 As shown, the ECC circuit 16 includes an encoding circuit 160, a hard-determining decoding circuit 161, a soft-determining decoding circuit 162, and an SB decoding circuit 163.

[0067] Encoding circuit 160 is a circuit for encoding data. For example, if a write request is received from host device 2, then encoding circuit 160 generates an error correction code (parity check) from the user data for ECC processing. Encoding circuit 160 assigns parity to the user data. This is also described as encoding. Therefore, the written data includes user data and parity.

[0068] The hard-determining decoding circuit 161 is a circuit that performs hard-determining decoding on the read data. Hard-determining decoding involves ECC processing using the hard-determining value received (read) from the non-volatile memory 20. Hereinafter, the hard-determining value will also be referred to as a hard bit. Hard bits will be described below. Hard-bit data is input to the hard-determining decoding circuit 161. The hard-determining decoding circuit 161 decodes the user data based on the hard-bit data.

[0069] The soft-decision decoding circuit 162 is a circuit that performs soft-decision decoding on the read data. Soft-decision decoding is ECC processing using the soft-decision value received (read) from the non-volatile memory 20. Hereinafter, the soft-decision value will also be referred to as a soft bit. The soft bit will be described below. Hard bit data and soft bit data are input to the soft-decision decoding circuit 162. The soft-decision decoding circuit 162 decodes the user data based on the hard bit data and the soft bit data. During decoding, the soft-decision decoding circuit 162 uses a Log-Likelihood Ratio (LLR) table. The LLR table is a table that shows the correspondence between soft bits and the log-likelihood ratio. The LLR table contains log-likelihood ratio values ​​(LLR values). The LLR value is information expressed as a logarithmic ratio of the likelihood when the data is "0" to the likelihood when the data is "1". The LLR value represents the reliability (likelihood) of the data read using a certain read voltage. For example, the LLR table is read from the non-volatile memory 20 to the memory controller 10 and stored in RAM 14 when the memory system 3 is started.

[0070] The SB decoding circuit 163 is a circuit that decodes soft data. In this embodiment, the non-volatile memory 20 sends compressed soft data to the memory controller 10. The compressed soft data is data obtained by compressing multiple soft data segments. The compressed soft data will be described below. The SB decoding circuit 163 uses hard data and compressed soft data to decode the multiple soft data segments.

[0071] An example of decoding soft data will be explained. For example, the memory cell transistor of the non-volatile memory 20 is a TLC (Triple Level Cell) that stores 3 bits of data including a lower bit, a middle bit, and a higher bit. In this case, the non-volatile memory 20 compresses (synthesizes) the 3 bits of soft data corresponding to the lower bit, middle bit, and higher bit to calculate 1 bit of compressed soft data. The SB decoding circuit 163 decodes each bit of soft data in the lower bit, middle bit, and higher bit according to the hard data of the lower bit, middle bit, and higher bit read from the non-volatile memory 20 and the compressed soft data.

[0072] 1.1.4 Structure of the SB Decoding Circuit

[0073] Next, refer to Figure 3 An example of the configuration of the SB decoding circuit 163 will be explained. Figure 3 This is a block diagram showing the configuration of the SB decoding circuit 163. Furthermore, Figure 3 The SB decoding circuit 163 shown corresponds to the case where the memory cell transistor is TLC.

[0074] like Figure 3 As shown, the SB decoding circuit 163 includes a de-multiplexer (DEMUX) 1001, four buffers 1002-1005, and an SB decoder 1006. Furthermore, the number of buffers can be arbitrarily set based on the number of bits that the memory cell transistors can store. For example, if the memory cell transistors can store k bits (k is an integer greater than or equal to 2), the SB decoding circuit 163 may include k+1 buffers.

[0075] DEMUX1001 is a connection circuit. Based on the switching signal received from CPU12, DEMUX1001 electrically connects the input terminal to any one of the four output terminals connected to buffers 1002 to 1005.

[0076] Buffer 1002 is a buffer that temporarily stores the next bit of hard data HB_L. Buffer 1002 receives hard data HB_L from DEMUX 1001. Buffer 1002 may, for example, store hard data HB_L with a length of m bits (m being an integer greater than or equal to 1). Furthermore, the length of data that buffer 1002 can store may be the same as or different from the length of the data processed together by ECC (hereinafter referred to as "ECC frame").

[0077] Buffer 1003 is a buffer that temporarily stores hard data HB_M of a certain length. Buffer 1003 receives hard data HB_M from DEMUX 1001. For example, like buffer 1002, buffer 1003 stores hard data HB_M of a data length of m bits.

[0078] Buffer 1004 is a buffer that temporarily stores the hard data HB_U of the upper bit. Buffer 1004 receives the hard data HB_U from DEMUX 1001. For example, like buffer 1002, buffer 1004 stores hard data HB_U of a data length of m bits.

[0079] Buffer 1005 is a buffer for temporarily storing compressed soft data SB. Buffer 1005 receives compressed soft data SB from MUX 1001. For example, like buffer 1002, buffer 1005 stores compressed soft data SB with a data length of m bits.

[0080] SB decoder 1006 is a decoding circuit for soft data SB. SB decoder 1006 receives hard data HB_L, HB_M, and HB_U, as well as compressed soft data SB. Based on the hard data HB_L, HB_M, and HB_U, and the compressed soft data SB, SB decoder 1006 decodes the lower-order soft data SB_L, the middle-order soft data SB_M, and the upper-order soft data SB_U. For example, SB decoder 1006 sends the soft data SB_L, SB_M, and SB_U to soft-determination decoding circuit 162.

[0081] 1.1.5 Construction of Non-Volatile Memory

[0082] Next, refer to Figure 4 An example of the configuration of the non-volatile memory 20 will be described. Figure 4 This is a block diagram illustrating the basic structure of the non-volatile memory 20. Furthermore, in Figure 4 In the example, arrows are used to indicate a portion of the connection between the constituent elements. However, the connections between the constituent elements are not limited to these.

[0083] like Figure 4As shown, the non-volatile memory 20 is, for example, a NAND flash memory. The non-volatile memory 20 is connected to the memory controller 10. The non-volatile memory 20 operates based on commands from the memory controller 10.

[0084] The non-volatile memory 20 includes input / output circuitry 201, logic control circuitry 202, address register 203, instruction register 204, status register 205, sequence generator 206, ready / busy circuitry 207, voltage generation circuitry 208, and multiple layers of PLN.

[0085] Input / output circuit 201 is a circuit for inputting and outputting signal DQ. Input / output circuit 201 is connected to memory controller 10. Furthermore, input / output circuit 201 is connected to address register 203, instruction register 204, status register 205, and data registers 214 of each level PLN. When the input signal DQ is data DAT, input / output circuit 201 receives the input signal DQ based on clock signals DQS and DQSn. Then, input / output circuit 201 sends data DAT to the data register 214 of the corresponding level PLN. Additionally, input / output circuit 201 outputs data DAT and status information STS together with clock signals DQS and DQSn to memory controller 10. When the input signal DQ is address ADD, input / output circuit 201 sends address ADD to address register 203. When the input signal DQ is instruction CMD, input / output circuit 201 sends instruction CMD to instruction register 204.

[0086] The logic control circuit 202 is a circuit that performs logic control based on control signals. The logic control circuit 202 is connected to the memory controller 10. Additionally, the logic control circuit 202 is connected to the input / output circuit 201 and the sequence generator 206. The logic control circuit 202 receives various control signals from the memory controller 10. Based on the received control signals, the logic control circuit 202 controls the input / output circuit 201 and the sequence generator 206.

[0087] Address register 203 is a register that temporarily stores the address ADD. Address register 203 is connected to the row decoder 212 and column decoder 215 of each PLN layer. The address ADD contains the row address RA and the column address CA. Address register 203 sends the row address RA to the row decoder 212. In addition, address register 203 sends the column address CA to the column decoder 215.

[0088] Instruction register 204 is a register that temporarily stores the instruction CMD. Instruction register 204 is connected to sequence generator 206. Instruction register 204 sends the instruction CMD to sequence generator 206.

[0089] Status register 205 is a register that temporarily stores status information STS. Status register 205 is connected to sequence generator 206. Status register 205 temporarily stores status information STS during write operations, read operations, and erase operations. Status information STS is sent to memory controller 10 via input / output circuit 201.

[0090] The sequence generator 206 controls the overall operation of the non-volatile memory 20. More specifically, the sequence generator 206 controls the ready / busy circuit 207, the voltage generation circuit 208, the row decoder 212, the sense amplifier 213, the data register 214, and the column decoder 215, etc. Based on the instruction CMD, the sequence generator 206 performs write, read, and erase operations. The sequence generator 206 sends the status information STS to the status register 205.

[0091] The ready / busy circuit 207 is a circuit that sends the ready / busy signal RBn. The ready / busy circuit 207 sends the ready / busy signal RBn to the memory controller 10 according to the operation status of the sequence generator 206.

[0092] The voltage generation circuit 208, based on the control of the sequence generator 206, generates various voltages for write, read, and erase operations. The voltage generation circuit 208 supplies voltages to the memory cell array 211, row decoder 212, sense amplifier 213, data register 214, and column decoder 215 of each layer of the PLN.

[0093] The PLN layer is the component that performs data writing and reading operations. Figure 4 In the example, the non-volatile memory 20 includes four layers: PLN0, PLN1, PLN2, and PLN3. However, the number of layers (PLN) is not limited to four. There can be one layer (PLN) or multiple layers (more than four). Layers PLN0 to PLN3 can operate independently of each other. Alternatively, layers PLN0 to PLN3 can operate in parallel.

[0094] Next, the internal structure of the layer PLN will be described. Hereinafter, the case where layers PLN0 to PLN3 have the same structure will be described. However, the structure of each layer PLN may also differ. Hereinafter, without limiting any of layers PLN0 to PLN3, it will be referred to as "layer PLN". The layer PLN includes a memory cell array 211, a row decoder 212, a sense amplifier 213, a data register 214, and a column decoder 215.

[0095] The memory cell array 211 is a collection of multiple arranged memory cell transistors. The memory cell array 211 contains multiple blocks (BLKs). Figure 4 In the example, the memory cell array 211 contains four blocks BLK0, BLK1, BLK2, and BLK3. Furthermore, the number of blocks BLK within the memory cell array 211 is arbitrary. A block BLK is, for example, a collection of multiple memory cell transistors that erase data together. Details regarding the composition of the blocks BLK will be described below.

[0096] The row decoder 212 is the decoding circuit for the row address RA. Based on the decoding result, the row decoder 212 selects any one block BLK within the memory cell array 211. The row decoder 212 applies voltage to the row direction wiring (hereinafter, word lines and select gate lines) of the selected block BLK.

[0097] Sensing amplifier 213 is a circuit for writing and reading data DAT. Sensing amplifier 213 is connected to memory cell array 211. During a read operation, sensing amplifier 213 reads data DAT from memory cell array 211. During a write operation, sensing amplifier 213 supplies a voltage corresponding to the written data DAT to memory cell array 211. Based on the read data, sensing amplifier 213 calculates soft bit data SB. Furthermore, sensing amplifier 213 calculates compressed soft bit data SB from multiple soft bit data SBs. Sequence generator 206 is a control circuit that controls sensing amplifier 213 to calculate soft bit data SB and compressed soft bit data SB.

[0098] Data register 214 is a register that temporarily stores data DAT. Data register 214 is connected to sense amplifier 213. Data register 214 contains multiple latch circuits. Each latch circuit temporarily stores data to be written or read.

[0099] Column decoder 215 is a circuit for decoding column address CA. Column decoder 215 receives column address CA from address register 203. Based on the decoding result of column address CA, column decoder 215 selects the latch circuit in data register 214.

[0100] In addition, sometimes elements of the input / output circuit 201, logic control circuit 202, address register 203, instruction register 204, status register 205, sequence generator 206, ready / busy circuit 207, voltage generation circuit 208, and a portion of the row decoder 212, sense amplifier 213, data register 214, and column decoder 215 contained in each layer of the multi-layer PLN are referred to as control circuits.

[0101] 1.1.6 Circuit Structure of Memory Cell Array

[0102] Next, refer to Figure 5An example of the circuit configuration of the memory cell array 211 will be described. Figure 5 This is a circuit diagram of the memory cell array 211. Furthermore, Figure 5 The example illustrates the circuit configuration of a block BLK.

[0103] A block BLK may contain, for example, four string components SU0 to SU3. Furthermore, the number of string components SU contained in a block BLK can be arbitrary.

[0104] A string component SU is, for example, a collection of multiple NAND strings NS selected together in a write or read operation. A string component SU contains multiple NAND strings NS.

[0105] A NAND string NS is a collection of multiple memory cell transistors MC connected in series. Multiple NAND strings NS within a string assembly SU are connected to any one of the bit lines BL0 to BLn (where n is an integer greater than or equal to 1). A NAND string NS contains multiple memory cell transistors MC, and selection transistors ST1 and ST2. Figure 5 In the example, the NAND string NS contains eight memory cell transistors MC0 to MC7.

[0106] A memory cell transistor (MC) is a non-volatile memory element that stores data. An MC includes a control gate and a charge storage layer. MCs can be either MONOS (Metal-Oxide-Nitride-Oxide-Silicon) or FG (Floating Gate) type. MONOS type transistors use an insulating layer for the charge storage layer, while FG type transistors use a conductive layer.

[0107] Transistors ST1 and ST2 are selected as switching elements. Transistors ST1 and ST2 are used to select the string assembly SU for various operations.

[0108] The current paths of select transistor ST2, memory cell transistors MC0-MC7, and select transistor ST1 within the NAND string NS are connected in series. The drain of select transistor ST1 is connected to bit line BL. The source of select transistor ST2 is connected to source line SL.

[0109] Within the same block BLK, the control gates of memory cell transistors MC0 to MC7 are all connected to word lines WL0 to WL7. More specifically, for example, block BLK contains four string components SU0 to SU3. Moreover, each string component SU contains multiple memory cell transistors MC0. The control gates of the multiple memory cell transistors MC0 within block BLK are all connected to one word line WL0. The same applies to memory cell transistors MC1 to MC7.

[0110] The gates of multiple select transistors ST1 within the string assembly SU are all connected to a single select gate line SGD. More specifically, the gates of multiple select transistors ST1 within the string assembly SU0 are all connected to select gate line SGD0. The gates of multiple select transistors ST1 within the string assembly SU1 are all connected to select gate line SGD1. The gates of multiple select transistors ST1 within the string assembly SU2 are all connected to select gate line SGD2. The gates of multiple select transistors ST1 within the string assembly SU3 are all connected to select gate line SGD3.

[0111] The gates of multiple select transistors ST2 within block BLK are all connected to the select gate line SGS. Furthermore, similar to the select gate line SGD, a different select gate line SGS can be set for each string assembly SU.

[0112] Word lines WL0 to WL7, select gate lines SGD0 to SGD3, and select gate line SGS are respectively connected to the line decoder 212 within the layer PLN.

[0113] Bit lines BL are commonly connected to one NAND string NS within each string component SU of each block BLK. Multiple NAND strings NS connected to one bit line BL are assigned the same column address. Each bit line BL is connected to the sense amplifier 213 within the layer PLN.

[0114] Source lines (SLs) are shared, for example, across multiple block BLKs.

[0115] A collection of multiple memory cell transistors MC connected to a common word line WL within a single string component SU is, for example, described as a "cell group CU". For example, if a memory cell transistor MC stores 1 bit of data, the storage capacity of the cell group CU is defined as "1 page of data". The data length of 1 page of data can be any bit length.

[0116] Furthermore, the CU (Cell Group) can have a storage capacity of more than two pages of data, based on the number of bits of data stored in the memory cell transistor MC (Metal Block Chromatography). For example, in the case of a TLC (Telematics Cell) memory cell transistor MC, the CU can store three pages of data. The data length of one page can be the same as the data length of an ECC frame, or one page can contain multiple ECC frames.

[0117] 1.1.7 Configuration of Data Register and Sensing Amplifier

[0118] Next, refer to Figure 6 An example of the configuration of the data register 214 and the sensing amplifier 213 will be described. Figure 6 This is a block diagram of data register 214 and sensing amplifier 213.

[0119] like Figure 6 As shown, the sense amplifier 213 includes a plurality of sense amplifier components (SAUs) configured for each bit line BL. Furthermore, the data register 214 includes a plurality of latch circuits (XDLs) configured for each sense amplifier component (SAU).

[0120] For example, a sense amplifier assembly (SAU) includes a sense circuit (SA), an arithmetic unit (OP), and latch circuits (SDL, ADL, BDL, CDL, and TDL). The sense circuit (SA) and the latch circuits (SDL, ADL, BDL, CDL, and TDL) are all connected to their respective latch circuits (XDL) via a bus (LBUS). In other words, the latch circuits (XDL, SA, SDL, ADL, BDL, CDL, and TDL) are connected via the LBUS bus in a manner capable of transmitting and receiving data. Furthermore, the number of latch circuits included in the sense amplifier assembly (SAU) can be designed based on the number of bits of data that a single memory cell transistor (MC) can store.

[0121] During a read operation, the sensing circuit SA senses the data read onto the corresponding bit line BL and determines whether the read data is "0" or "1". During a write operation, the sensing circuit SA applies a voltage to the bit line BL based on the write data.

[0122] The arithmetic unit OP performs various logic operations using the data stored in the latch circuits XDL, SDL, ADL, BDL, CDL, and TDL. Alternatively, the sense amplifier 213 can also include additional arithmetic circuitry for performing various logic operations, replacing the arithmetic unit OP.

[0123] The latch circuits SDL, ADL, BDL, CDL, and TDL temporarily store read or write data. For example, in the case of a read operation, the read data is stored in any one of the latch circuits SDL, ADL, BDL, CDL, and TDL. Similarly, in the case of a write operation, the write data of the latch circuit XDL is stored in any one of the latch circuits SDL, ADL, BDL, CDL, and TDL.

[0124] The latch circuit XDL serves as a high-speed buffer for data input / output between the sense amplifier component SAU and the input / output circuit 201. More specifically, write data received from the memory controller 10 is sent via the latch circuit XDL to the latch circuits SDL, ADL, BDL, CDL, and TDL or the sense circuit SA. Additionally, read data stored in the latch circuits SDL, ADL, BDL, CDL, and TDL or the sense circuit SA is sent via the latch circuit XDL to the memory controller 10.

[0125] 1.2 Threshold voltage distribution of memory cell transistors

[0126] Next, the threshold voltage distribution achievable by the memory cell transistor MC will be explained. The following explanation assumes that the memory cell transistor MC is a TLC transistor, but this embodiment can be applied as long as the memory cell transistor MC can store more than 2 bits of data.

[0127] 1.2.1 Relationship between threshold voltage distribution of memory cell transistors and data allocation

[0128] First, refer to Figure 7 An example illustrating the relationship between the threshold voltage distribution of the memory cell transistor MC and the data allocation is presented. Figure 7 This is a graph showing the relationship between the threshold voltage distribution and data allocation in a TLC.

[0129] like Figure 7 As shown, for example, the threshold voltage of each memory cell transistor MC takes a value contained in any one of eight discrete distributions. Hereinafter, the eight distributions are described in order of threshold voltage from low to high as "Er" state, "A" state, "B" state, "C" state, "D" state, "E" state, "F" state, and "G" state.

[0130] The "Er" state is equivalent to the data erasure state. Furthermore, the "A" to "G" states are equivalent to the states where charge is injected into the charge storage layer to write data. During the write operation, the verification voltages corresponding to each threshold voltage distribution are set to VA to VG. Thus, these voltage values ​​are in the relationship VA < VB < VC < VD < VE < VF < VG < VREAD. Voltage VREAD is the voltage applied to the word line WL connected to the cell group CU that is not being read during the read operation. If voltage VREAD is applied to the gate, the memory cell transistor MC is in the ON state regardless of the data stored.

[0131] Furthermore, during the write operation, the verification voltages corresponding to each threshold voltage distribution are set to VA to VG, but the method for determining voltages VA to VG is not limited to this. For example, voltages VA to VG can be written to the ROM fuse of the non-volatile memory 20 (represented as preset voltages). After the memory system 3 is shipped, the CPU 12 can also read voltages VA to VG from the ROM fuse. Alternatively, the CPU 12 can update and store the voltages VA to VG read from the ROM fuse of the non-volatile memory 20 in any block BLK of the non-volatile memory 20. In addition, the CPU 12 can update voltages VA to VG as shift read and tracking operations are performed. For example, the CPU 12 performs shift read and tracking operations during a patrol read.

[0132] Shift read refers to the CPU 12 shifting the read voltage and attempting to read data from the non-volatile memory 20 again. At this time, the CPU 12 can also update the voltages VA to VG by saving the shift amount information from the preset voltage.

[0133] The tracking action refers to the CPU 12 determining the intersection point when adjacent threshold voltage distributions overlap, and calculating the appropriate readout voltage, i.e., the shift amount, based on the obtained intersection point. Alternatively, the tracking action involves exploring the voltage that minimizes the number of faulty bits in the ECC circuit 16, or the voltage at which error correction can be performed using the ECC circuit 16, when the readout voltage changes in place of the intersection point.

[0134] The relationship between each state and voltages VA to VG is described in detail. The threshold voltage included in state "Er" is less than voltage VA. The threshold voltage included in state "A" is above voltage VA and less than voltage VB. The threshold voltage included in state "B" is above voltage VB and less than voltage VC. The threshold voltage included in state "C" is above voltage VC and less than voltage VD. The threshold voltage included in state "D" is above voltage VD and less than voltage VE. The threshold voltage included in state "E" is above voltage VE and less than voltage VF. The threshold voltage included in state "F" is above voltage VF and less than voltage VG. Furthermore, the threshold voltage included in state "G" is above voltage VG and less than voltage VREAD.

[0135] As described above, each memory cell transistor MC has any of eight threshold voltage distributions, enabling it to take on eight states. By assigning these states to "000" to "111" in binary representation, each memory cell transistor MC can store 3 bits of data. Hereinafter, the 3 bits of data will be referred to as the lower bit, middle bit, and upper bit. Furthermore, the set of lower bits written to (or read from) the cell group CU in one go is referred to as the lower page. The set of middle bits is referred to as the middle page. The set of upper bits is referred to as the upper page. In addition, when not specifying any of the lower, middle, or upper pages, it will simply be referred to as a "page".

[0136] For example, in the case of a lower page read operation, the data read by the read voltage VA is stored in the latch circuit TDL. Next, the data read by the read voltage VE is logically processed in the arithmetic unit OP with the data in the latch circuit TDL, and the result is stored in the latch circuit TDL. This stored data is then sent to the memory controller 10 via the latch circuit XDL as the lower page read data.

[0137] In the case of a middle page readout, the data read out at the readout voltage VB is stored, for example, in the latch circuit TDL. Next, the data read out at the readout voltage VD is logically processed in the arithmetic unit OP with the data in the latch circuit TDL, and the result is stored in the latch circuit TDL. Furthermore, the data read out at the readout voltage VF is logically processed in the arithmetic unit OP with the data in the latch circuit TDL, and the result is stored in the latch circuit TDL. This stored data is then sent to the memory controller 10 via the latch circuit XDL as the middle page readout data.

[0138] In the case of a read operation of the upper page, the data read by the read voltage VC is stored, for example, in the latch circuit TDL. Next, the data read by the read voltage VG is logically processed in the arithmetic unit OP with the data in the latch circuit TDL, and the result is stored in the latch circuit TDL. This stored data is then sent to the memory controller 10 via the latch circuit XDL as read data for the upper page.

[0139] exist Figure 7 In the example, for the memory cell transistors MC included in each threshold voltage distribution, the data for "high bit / middle bit / low bit" is assigned as follows.

[0140] "Er" status: "111" data

[0141] Status "A": Data "110"

[0142] "B" status: "100" data

[0143] "C" status: "000" data

[0144] "D" status: "010" data

[0145] "E" status: "011" data

[0146] "F" status: "001" data

[0147] "G" status: "101" data

[0148] When reading data with this allocation, the lower bit is determined by the readout actions corresponding to states "A" and "E". The middle bit is determined by the readout actions corresponding to states "B", "D", and "F". The upper bit is determined by the readout actions corresponding to states "C" and "G". In other words, the values ​​of the lower, middle, and upper bits are determined by readout actions corresponding to 2, 3, and 2 states, respectively. This data allocation will be described below as a "2-3-2 code". However, the allocation of data to states "Er" through "G" is not limited to a 2-3-2 code.

[0149] 1.2.2 Specific Examples of Hard and Soft Data

[0150] Next, refer to Figure 8 Specific examples of hard bit data HB and soft bit data SB will be explained. Figure 8 This is a diagram illustrating an example of the relationship between the threshold voltage distribution in the "Er" and "A" states and the hard bit data HB and soft bit data SB.

[0151] like Figure 8 As shown, due to read disturbances or data retention, the width of the threshold voltage distribution in each state sometimes expands, and the lower part of adjacent threshold voltage distributions overlaps with each other. Figure 8 (The slanted area). In such a case, if a read operation is performed, the memory cell transistor MC corresponding to the overlapping area at the lower end is more likely to become a faulty bit. More specifically, for example, when performing a read operation corresponding to the "A" state at voltage VA, the memory cell transistor MC in the "Er" state with a threshold voltage above voltage VA and the memory cell transistor MC in the "A" state with a threshold voltage below voltage VA become faulty bits. If the number of faulty bits generated exceeds the number of bits that the ECC circuit 16 can erroneously correct, it becomes difficult to read the data correctly.

[0152] Therefore, in this embodiment, during the readout operation of one state, two readout voltages are set in the region that overlaps at the lower end of the threshold voltage distribution. More specifically, for state "A", two readout voltages, VAL and VAH, are set. Voltage VAL is a voltage less than voltage VA. Voltage VAH is a voltage greater than voltage VA. The region where state "Er" overlaps with state "A" is located between voltage VAL and voltage VAH. Furthermore, the voltage difference between voltage VAL and voltage VA can be the same as or different from the voltage difference between voltage VA and voltage VAH.

[0153] For example, in a readout operation using voltage VAL, the data of the memory cell transistor MC with a threshold voltage less than voltage VAL is "1". The data of the memory cell transistor MC with a threshold voltage greater than voltage VAL is "0".

[0154] Furthermore, during the readout operation using voltage VAH, the data of the memory cell transistor MC with a threshold voltage less than voltage VAH is "1". The data of the memory cell transistor MC with a threshold voltage greater than voltage VAH is "0".

[0155] In this embodiment, among the two readout voltages corresponding to one state, the readout data based on the lower readout voltage is defined as hard bit data HB.

[0156] The soft bit data SB is calculated using an XOR operation on the two read data. Figure 8 In the example, the soft bit data SB of the memory cell transistor MC with a threshold voltage less than voltage VAL is "0". The soft bit data SB of the memory cell transistor MC with a threshold voltage greater than voltage VAL and less than voltage VAH is "1". The soft bit data SB of the memory cell transistor MC with a threshold voltage greater than voltage VAH is "0". Furthermore, the calculation of the soft bit data SB is not limited to XOR. The calculation of the soft bit data SB can be set based on the definition of the soft bit data SB. For example, when the soft bit data SB of the memory cell transistor MC with a threshold voltage greater than voltage VAL and less than voltage VAH is defined as "0", the soft bit data SB can also be calculated using XNOR (Exclusive Not Orb) operation.

[0157] Therefore, the soft bit data SB indicates whether the threshold voltage is located near the boundary between two adjacent threshold voltage distributions. By referring to the hard bit data HB and the soft bit data, information can be obtained as to whether the threshold voltage is located in the lower part of the threshold voltage distribution of the object state.

[0158] 1.2.3 Hard displacement and compressed soft displacement in each state

[0159] Next, refer to Figure 9 The hard bit data HB and compressed soft bit data SB for each state are explained. Figure 9 This is a graph showing the relationship between the threshold voltage distribution of TLC and the hard bit data HB and the compressed soft bit data SB.

[0160] like Figure 9As shown, the two read voltages corresponding to state "A" are set as voltage VAL and voltage VAH. The two read voltages corresponding to state "B" are set as voltage VBL and voltage VBH. The two read voltages corresponding to state "C" are set as voltage VCL and voltage VCH. The two read voltages corresponding to state "D" are set as voltage VDL and voltage VDH. The two read voltages corresponding to state "E" are set as voltage VEL and voltage VEH. The two read voltages corresponding to state "F" are set as voltage VFL and voltage VFH. The two read voltages corresponding to state "G" are set as voltage VGL and voltage VGH. These voltages are in the following relationship: VAL < VA < VAH < VBL < VB < VBH < VCL < VC < VCH < VDL < VD < VDH < VEL < VE < VEH < VFL < VF < VFH < VGL < VG < VGH < VREAD. The readout actions using voltages VAL, VAH, VBL, VBH, VCL, VCH, VDL, VDH, VEL, VEH, VFL, VFH, VGL, and VGH are respectively described as ALR read, AHR read, BLR read, BHR read, CLR read, CHR read, DLR read, DHR read, ELR read, EHR read, FLR read, FHR read, GLR read, and GHR read.

[0161] During the lower-level page read operation, four read operations are performed: ALR read, AHR read, ELR read, and EHR read. The hard data HB_L is the data determined by the ALR and ELR reads. The soft data SB_L is based on the hard data HB_L and the data determined by the AHR and EHR reads.

[0162] For example, in the case of reading hard data from the next lower page, the data read by the read voltage VAL is stored in the latch circuit TDL. Then, the data read by the read voltage VEL is logically operated on with the data in the latch circuit TDL in the arithmetic unit OP, and the result is stored in the latch circuit TDL as hard data HB_L.

[0163] Additionally, for example, in the case of reading soft data from the next lower page, the data read by the read voltage VAH is stored, for example, in the latch circuit CDL. Next, the data read by the read voltage VEH is logically operated on with the data in the latch circuit CDL in the arithmetic unit OP, and the result is stored in the latch circuit CDL. Then, the arithmetic unit OP performs an XOR operation between the data stored in the latch circuit TDL and the data stored in the latch circuit CDL, and stores the result as soft data SB_L in, for example, the latch circuit CDL.

[0164] In the middle page read operation, six read operations are performed: BLR read, BHR read, DLR read, DHR read, FLR read, and FHR read. The hard data HB_M is the data determined by the BLR read, DLR read, and FLR read. The soft data SB_M is based on the hard data HB_M and the data determined by the BHR read, DHR read, and FHR read.

[0165] For example, in the case of reading hard data from the middle page, the data read by the read voltage VBL is stored in the latch circuit TDL. Next, the data read by the read voltage VDL is logically operated on with the data in the latch circuit TDL in the arithmetic unit OP, and the result is stored in the latch circuit TDL. Furthermore, the data read by the read voltage VFL is logically operated on with the data in the latch circuit TDL in the arithmetic unit OP, and the result is stored in the latch circuit TDL as hard data HB_M.

[0166] Additionally, for example, in the case of reading soft data from the middle page, the data read by the read voltage VBH is stored, for example, in the latch circuit BDL. Next, the data read by the read voltage VDH is logically operated on with the data in the latch circuit BDL in the arithmetic unit OP, and the result is stored in the latch circuit BDL. Furthermore, the data read by the read voltage VFH is logically operated on with the data in the latch circuit BDL in the arithmetic unit OP, and the result is stored in the latch circuit BDL. Then, the arithmetic unit OP performs an XOR operation between the hard data HB_M stored in the latch circuit TDL and the data stored in the latch circuit BDL, and stores the result as soft data SB_M in, for example, the latch circuit BDL.

[0167] The upper-level page read operation involves four read actions: CLR read, CHR read, GLR read, and GHR read. The hard data HB_U is determined by the CLR and GLR reads. The soft data SB_U is based on the hard data HB_U and the data determined by the CHR and GHR reads.

[0168] For example, in the case of reading hard data from the upper page, the data read by the read voltage VCL is stored in the latch circuit TDL. Then, the data read by the read voltage VGL is logically operated on with the data in the latch circuit TDL in the arithmetic unit OP, and the result is stored in the latch circuit TDL as hard data HB_U.

[0169] Additionally, for example, in the case of reading soft data from the upper page, the data read by the read voltage VCH is stored, for example, in the latch circuit ADL. Next, the data read by the read voltage VGH is logically operated on with the data in the latch circuit ADL in the arithmetic unit OP, and the result is stored in the latch circuit ADL. Then, the arithmetic unit OP performs an XOR operation between the data stored in the latch circuit TDL and the data stored in the latch circuit ADL, and stores the result as soft data SB_U in, for example, the latch circuit ADL.

[0170] The compressed soft bit data SB is the data calculated based on the soft bit data SB_L, SB_M, and SB_U.

[0171] exist Figure 9 In this example, corresponding to the 14 readout voltages, the threshold voltage of the memory cell transistor MC is divided into 15 segments. More specifically, the threshold voltage of segment D1 is less than voltage VAL. The threshold voltage of segment D2 is above voltage VAL and less than voltage VAH. The threshold voltage of segment D3 is above voltage VAH and less than voltage VBL. The threshold voltage of segment D4 is above voltage VBL and less than voltage VBH. The threshold voltage of segment D5 is above voltage VBH and less than voltage VCL. The threshold voltage of segment D6 is above voltage VCL and less than voltage VCH. The threshold voltage of segment D7 is above voltage VCH and less than voltage VDL. The threshold voltage of segment D8 is above voltage VDL and less than voltage VDH. The threshold voltage of segment D9 is above voltage VDH and less than voltage VEL. The threshold voltage of segment D10 is above voltage VEL and less than voltage VEH. The threshold voltage of segment D11 is above voltage VEH and less than voltage VFL. The threshold voltage for distinguishing D12 is above VFL and below VFH. The threshold voltage for distinguishing D13 is above VFH and below VGL. The threshold voltage for distinguishing D14 is above VGL and below VGH. The threshold voltage for distinguishing D15 is above VGH and below VREAD.

[0172] The combinations of "hard data HB_U / HM_M / HB_L" and "compressed soft data SB" for each region are shown below.

[0173] Distinguish between D1 (“Er” state): “111”, “0”

[0174] Distinguish between D2 (“A” state): “110”, “1”

[0175] Distinguish between D3 (“A” state): “110”, “0”

[0176] Distinguish between D4 (“B” state): “100”, “1”

[0177] Distinguish between D5 (“B” states): “100”, “0”

[0178] Distinguish between D6 (“C” state): “000”, “1”

[0179] Distinguish between D7 (“C” state): “000”, “0”

[0180] Distinguish between D8 (“D” state): “010”, “1”

[0181] Distinguish between D9 (“D” states): “010”, “0”

[0182] Distinguish between D10 (“E” state): “011”, “1”

[0183] Distinguish between D11 (“E” state): “011”, “0”

[0184] Distinguish between D12 (“F” state): “001”, “1”

[0185] Distinguish between D13 (“F” state): “001”, “0”

[0186] Distinguish between D14 (“G” state): “101”, “1”

[0187] Distinguish between D15 (“G” state): “101”, “0”.

[0188] 1.3 Compression methods for soft-bit data

[0189] Next, refer to Figure 10 and Figure 11 An example of a compression method for soft bit data (SB) will be explained. Figure 10 This diagram illustrates the calculation of soft data SB_L, SB_M, and SB_U based on the results of reading actions from the lower, middle, and upper pages. Figure 11 This diagram illustrates the computational process of calculating compressed soft data SB based on soft data SB_L, SB_M, and SB_U.

[0190] like Figure 10 As shown, for example, after the readout of the lower page, the sense amplifier 213 performs an XOR operation on the hard data HB_L (ALR / ELR) determined by the ALR and ELR readouts, and the data (AHR / EHR) determined by the AHR and EHR readouts. As a result, the soft data SB_L is calculated. In this case, the distinctions D2 and D10 of the soft data SB_L are "1" data, and the other distinctions D are "0" data.

[0191] Next, after the readout of the middle page, the sense amplifier 213 performs an XOR operation on the hard bit data HB_M (BLR / DLR / FLR) determined by the BLR, DLR, and FLR reads, and the data (BHR / DHR / FHR) determined by the BHR, DHR, and FHR reads. As a result, the soft bit data SB_M is calculated. In this case, the distinctions D4, D8, and D12 of the soft bit data SB_M are "1" data, and the other distinctions D are "0" data.

[0192] Next, after the readout operation of the upper page, the sensing amplifier 213 performs an XOR operation on the hard data HB_U (CLR / GLR) determined by the CLR and GLR readouts, and the data (CHR / GHR) determined by the CHR and GHR readouts. As a result, the soft data SB_U is calculated. Distinctions D6 and D14 of the soft data SB_U are set to "1", while other distinctions D are set to "0".

[0193] like Figure 11 As shown, the threshold voltage distribution (state) for the "1" data of soft bit data SB_L, SB_M, and SB_U to become "1" data are different. Therefore, the distinction D of the existence of "1" data of soft bit data SB_L, SB_M, and SB_U are different. Therefore, the sensing amplifier 213 performs an OR (or gate) operation on the soft bit data SB_L, SB_M, and SB_U. As a result, the compressed soft bit data SB is calculated. That is, through the OR operation, 3 pages of data are compressed into 1 page of data.

[0194] For example, when soft data SB_U is stored in latch circuit ADL, soft data SB_M is stored in latch circuit BDL, and soft data SB_L is stored in latch circuit CDL, the arithmetic unit OP performs an OR operation on the data stored in latch circuit ADL, the data stored in latch circuit BDL, and the data stored in latch circuit CDL, and stores the result as compressed soft data SB in, for example, latch circuit ADL. This stored data as compressed soft data SB is then sent to memory controller 10 via latch circuit XDL.

[0195] 1.4 Decoding Method for Compressed Soft Bits

[0196] Next, refer to Figure 12 An example of a decoding method for compressed soft bit data (SB) will be explained. Figure 12 This is a diagram representing the decoding process of soft bit data SB_L, SB_M, and SB_U.

[0197] The positions (states) generated by the "1" data in soft bit data SB_L, SB_M, and SB_U are mutually exclusive. Furthermore, the combinations of hard bit data HB_L, HB_M, and HB_U and soft bit data SB_L, SB_M, and SB_U can be defined one-to-one. Using these conditions, the soft bit data SB of each page is decoded based on the hard bit data HB_L, HB_M, and HB_U and the compressed soft bit data SB.

[0198] like Figure 12 As shown, the SB decoding circuit 163 receives hard data HB_L, HB_M, and HB_U, as well as compressed soft data SB, from the non-volatile memory 20. When the SB decoder 1006 decodes the soft data SB_L, SB_M, and SB_U, the following operations are performed. Furthermore, in the following expressions, "|" represents an OR operation, and "~" represents inverted data. Also, in the following expressions, the hard data HB_L, HB_M, and HB_U are only represented as "L", "M", and "U".

[0199] SB_L=((~L&M&U)|(L&M&~U))&SB

[0200] SB_M=((~L&~M&U)|(~L&M&~U)|(L&~M&~U))&SB

[0201] SB_U=((~L&~M&~U)|(L&~M&U))&SB

[0202] Through the aforementioned formula, the use of Figure 10 The soft-bit data SB_L, SB_M, and SB_U are described for decoding. Furthermore, the operational formulas can be appropriately modified based on the data allocation in the memory cell transistor MC.

[0203] 1.5 Reading Action

[0204] 1.5.1 Reading Action Flow

[0205] First, refer to Figure 13 The process of reading operations in memory system 3 will be explained. Figure 13 It is a flowchart of the reading action. Furthermore, Figure 13 The example illustrates the case of reading multiple pages of data from a single unit group (CU).

[0206] like Figure 13As shown, if the memory controller 10 receives a read request from the host device 2, it begins the read operation. The non-volatile memory 20, based on the control of the memory controller 10, performs the read operation of multiple pages of data stored in the cell group CU (step S10). For example, when the memory cell transistor MC is TLC, the read operation of the lower page, the read operation of the middle page, and the read operation of the upper page are performed.

[0207] The sensing amplifier 213 compresses the multiple pages of soft bit data SB and calculates the compressed soft bit data SB (step S11). More specifically, the sensing amplifier 213 compresses the soft bit data SB_L, SB_M, and SB_U (OR operation) to calculate the compressed soft bit data SB.

[0208] The memory controller 10 reads multiple pages of hard data HB from the non-volatile memory 20 (step S12). More specifically, for example, the memory controller 10 reads hard data HB_L, HB_M, and HB_U from the non-volatile memory 20. Furthermore, steps S11 and S12 can be performed in parallel at least partially, or step S12 can be performed first.

[0209] The hard-determining decoding circuit 161 performs hard-determining decoding processing (step S13). More specifically, for example, the hard-determining decoding circuit 161 uses hard bit data HB_L, HB_M, and HB_U to perform hard-determining decoding processing for the lower page, middle page, and upper page, respectively.

[0210] If the hard-determined decoding process is successful (step S14_Yes), the memory controller 10 sends the decoded user data to the host device 2, and the read operation ends.

[0211] In the event of a hard-determined decoding failure (step S14_No), the memory controller 10 reads the compressed soft data SB from the non-volatile memory 20 (step S15). Furthermore, the soft data SB_L, SB_M, and SB_U are not read.

[0212] The SB decoding circuit 163 decodes the soft data SB of each page according to the compressed soft data SB (step S16). More specifically, for example, the SB decoding circuit 163 uses hard data HB_L, HB_M, and HB_U to decode the soft data SB_L, SB_M, and SB_U according to the compressed soft data SB.

[0213] The soft-determination decoding circuit 162 performs soft-determination decoding processing (step S17). More specifically, the soft-determination decoding circuit 162 uses hard bit data HB_L, HB_M, and HB_U, soft bit data SB_L, SB_M, and SB_U, and the LLR table to perform soft-determination decoding processing on the lower page data, the middle page data, and the upper page data, respectively.

[0214] 1.5.2 Read Operations in Non-Volatile Memory

[0215] Next, the read operations in the non-volatile memory 20 will be described. The read operations in the non-volatile memory 20 generally include cell read operations and cache read operations. The cell read operation is the operation of reading data from the data register 214, that is, the latch circuit XDL, from the memory cell array 211. The cache read operation is the operation of reading (externally outputting) data from the data register 214 to the memory controller 10 via the input / output circuit 201.

[0216] For example, the non-volatile memory 20 has at least one read mode, including a first read mode, a second read mode, and a third read mode, during a read operation. The non-volatile memory 20 executes any one read mode based on a sequence of instructions received from the memory controller 10.

[0217] Read mode 1 and read mode 2 are operation modes for reading page data by sending instruction sets for each page. Read mode 1 is an operation mode that executes page data read operations (cell read operation and cache read operation) sequentially. In read mode 1, the ready / busy signal RBn is set to "L" level during the execution of the cell read operation. Therefore, cell read operation and cache read operation cannot be executed in parallel.

[0218] The second read mode unit is an operation mode that can perform read operations and cache read operations of other pages in parallel. In the second read mode, even when the execution unit is performing a read operation, if a cache read operation can be performed, that is, if the data of the latch circuit XDL can be output, the ready / busy signal RBn is set to the "H" level.

[0219] The third readout mode is an operation mode that continuously reads out multiple pages of data stored in the unit group (CU) based on a single instruction set.

[0220] 1.5.3 Instruction Sequence for Read Mode 1

[0221] Next, refer to Figure 14 An example of the instruction sequence for the first readout mode will be explained. Figure 14 This is the instruction sequence for the first read mode. In Figure 14 In the example, for simplicity, signals CEn, CLE, ALE, WEn, REn, DQS, and DQSn are omitted, representing signal DQ and the ready / busy signal RBn. In signal DQ, instructions are represented in circles, addresses in quadrilaterals, and data in hexagons.

[0222] Figure 14 The example illustrates the sequential execution of the lower page read operation, the middle page read operation, and the upper page read operation of a unit group CU.

[0223] like Figure 14 As shown, firstly, the memory controller 10 sends a set of instructions to the non-volatile memory 20 for reading the lower page. More specifically, firstly, the memory controller 10 sends the instruction "PFX" to the non-volatile memory 20. The instruction "PFX" is a prefix instruction that notifies the execution of the read operation of hard data HB and the calculation operation of soft data SB. In other words, the instruction "PFX" is an instruction that notifies the execution of two read operations using two read voltages for one status and the execution of the calculation of soft data SB. Next, the memory controller 10 continuously sends the instructions "01h", "00h", address "ADD", and instruction "30h" to the non-volatile memory 20. The instruction "01h" is the instruction that specifies the lower page. The instruction "00h" is the instruction that notifies the execution of the cell read operation. The address "ADD" corresponds to the cell group CU that becomes the object of the read operation. For example, the address "ADD" includes the row address RA and the column address CA, etc. The instruction "30h" is an instruction to execute the unit read action based on the previously sent address "ADD".

[0224] If the non-volatile memory 20 receives the instruction "30h", it sets the ready / busy signal RBn to "L" level and begins the cell read operation of the next page. The result of the cell read operation is, for example, storing hard data HB_L in the latch circuit XDL. For example, storing soft data SB_L as cached data for soft data SB in the latch circuit ADL. Figure 14 (SB high-speed buffer).

[0225] If the read operation of the lower page cell is completed, then the non-volatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0226] If the memory controller 10 confirms the "H" level ready / busy signal RBn, it sends a set of instructions to the non-volatile memory 20 for a cache read operation of the next page (hard data HB_L). More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20. The instruction "05h" is an instruction to notify the execution of a cache read operation. The instruction "E0h" is an instruction to execute a cache read operation based on the previously sent address "ADD".

[0227] The non-volatile memory 20 sends the hard bit data HB_L of the data register 214 to the memory controller 10.

[0228] After reading the hard data HB_L from the non-volatile memory 20, that is, after the cache read operation is completed, the memory controller 10 sends a set of instructions for reading the middle page from the non-volatile memory 20. More specifically, the memory controller 10 continuously sends the instructions "PFX", "02h", "00h", address "ADD", and instruction "30h" to the non-volatile memory 20. The instruction "02h" is the instruction that specifies the middle page.

[0229] If the non-volatile memory 20 receives the instruction "30h", then the ready / busy signal RBn is set to "L" level, and a cell read operation of the middle page is initiated. The result of the cell read operation, for example, is that hard data HB_M is stored in the latch circuit XDL. Soft data SB_M is, for example, ORed with soft data SB_L stored in the latch circuit ADL. For example, the result of the OR operation between soft data SB_L and SB_M is stored in the latch circuit ADL. Figure 14 SB_L|SB_M) is used as the SB high-speed buffer.

[0230] If the cell read operation of the middle page is completed, then the non-volatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0231] If the memory controller 10 acknowledges the "H" level ready / busy signal RBn, it sends a set of instructions to the non-volatile memory 20 for a cache read operation of the middle page (hard data HB_M). More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0232] The non-volatile memory 20 sends the hard bit data HB_M of the data register 214 to the memory controller 10.

[0233] After reading the hard data HB_M from the non-volatile memory 20, the memory controller 10 sends a set of instructions to the non-volatile memory 20 to perform a read operation of the upper-level page. More specifically, the memory controller 10 continuously sends the instructions "PFX", "03h", "00h", address "ADD", and instruction "30h" to the non-volatile memory 20. The instruction "03h" is the instruction that specifies the upper-level page.

[0234] If the non-volatile memory 20 receives the instruction "30h", it sets the ready / busy signal RBn to "L" level and begins the cell read operation of the upper page. The result of the cell read operation, for example, is that the hard data HB_U is stored in the latch circuit XDL. The soft data SB_H is, for example, ORed with the SB cache (SB_L|SB_M) stored in the latch circuit ADL. For example, the latch circuit ADL stores the result of the OR operation between the soft data SB_L, SB_M, and SB_U. Figure 14 The SB_L|SB_M|SB_U) are used as the SB high-speed buffer. That is to say, the compressed soft bit data SB is stored in the latch circuit ADL.

[0235] If the read operation of the upper page cell is completed, then the non-volatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0236] If the memory controller 10 acknowledges the "H" level ready / busy signal RBn, it sends a set of instructions for a cache read operation of the upper page (hard data HB_U) to the non-volatile memory 20. More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0237] The non-volatile memory 20 sends the hard bit data HB_U of the data register 214 to the memory controller 10.

[0238] After reading the hard data HB_U from the non-volatile memory 20, the memory controller 10 sends a set of instructions to the non-volatile memory 20 to read (transfer) the compressed soft data SB to the latch circuit XDL. More specifically, the memory controller 10 continuously sends the instruction "00h", the address "ADD", and the instruction "XXh" to the non-volatile memory 20. The instruction "XXh" is the instruction to transfer the compressed soft data SB to the latch circuit XDL.

[0239] If the non-volatile memory 20 receives the instruction "XXh", then it sets the ready / busy signal RBn to the "L" level, for example, by transferring compressed soft data SB from latch circuit ADL to latch circuit XDL.

[0240] If the transmission of compressed soft data SB is completed, then the non-volatile memory 20 sets the ready / busy signal RBn to "H" level.

[0241] If the memory controller 10 acknowledges the "H" level ready / busy signal RBn, it sends a set of instructions for a cache read operation of compressed soft data SB to the non-volatile memory 20. More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0242] The non-volatile memory 20 sends compressed soft bit data SB of the data register 214 to the memory controller 10.

[0243] 1.5.4 Instruction Sequence for Read Mode 2

[0244] Next, refer to Figure 15 An example of the instruction sequence for the second readout mode will be explained. Figure 15 This is the instruction sequence for the second read mode. Figure 15 In the example, for simplicity, signals CEn, CLE, ALE, WEn, REn, DQS, and DQSn are omitted, representing signal DQ and the ready / busy signal RBn. In signal DQ, instructions are represented in circles, addresses in quadrilaterals, and data in hexagons.

[0245] Figure 15 The example illustrates the sequential execution of the lower page read operation, the middle page read operation, and the upper page read operation of a unit group CU.

[0246] like Figure 15 As shown, firstly, the memory controller 10 sends a set of instructions to the non-volatile memory 20 for reading cells from the next lower page. More specifically, the memory controller 10 continuously sends the instructions "PFX", "01h", "00h", address "ADD", and instruction "30h" to the non-volatile memory 20.

[0247] If the non-volatile memory 20 receives the instruction "30h", it sets the ready / busy signal RBn to "L" level and begins the cell read operation of the next page. The result of the cell read operation is, for example, storing hard data HB_L in the latch circuit XDL. Or, for example, storing soft data SB_L in the latch circuit ADL.

[0248] If the read operation of the lower page cell is completed, the non-volatile memory 20 will set the ready / busy signal to the RBn "H" level.

[0249] If the memory controller 10 confirms the "H" level ready / busy signal RBn, it sends a set of instructions to the non-volatile memory 20 to schedule a cell read operation of a middle page. More specifically, the memory controller 10 continuously sends the instructions "PFX", "02h", "00h", address "ADD", and instruction "31h" to the non-volatile memory 20. Instruction "31h" is an instruction used to schedule the execution of a cell read operation containing instruction "31h" after the ongoing cell read operation has ended.

[0250] If the non-volatile memory 20 receives the instruction "31h", it sets the ready / busy signal RBn to "L" level and schedules the cell read operation of the middle page.

[0251] If the reservation ends, the non-volatile memory 20 sets the ready / busy signal RBn to "H" level. Since the cell read operation of the lower page has ended, the non-volatile memory 20 maintains the ready / busy signal RBn at the "H" level and begins the cell read operation of the middle page.

[0252] If the memory controller 10 acknowledges the "H" level ready / busy signal RBn, it sends a set of instructions to the non-volatile memory 20 for a cache read operation of the next page (hard data HB_L). More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0253] The non-volatile memory 20 performs cell read operations in parallel with the middle page, sending the hard bit data HB_L of the data register 214 to the memory controller 10.

[0254] After reading the hard data HB_L from the non-volatile memory 20, the memory controller 10 sends a set of instructions to the non-volatile memory 20 to schedule the read operation of the upper page. More specifically, the memory controller 10 continuously sends the instructions "PFX", "03h", "00h", address "ADD", and instruction "31h" to the non-volatile memory 20.

[0255] When the read operation of the upper page is scheduled to end but the read operation of the middle page is not yet finished, the non-volatile memory 20 sets the ready / busy signal RBn to "L" level. For example, after the output of hard data HB_L, the hard data HB_M is stored in the latch circuit XDL. In the latch circuit ADL, the OR operation result (SB_L|SB_M) of soft data SB_L and SB_M is stored as the SB cache.

[0256] If the read operation of the middle page is completed, the non-volatile memory 20 sets the ready / busy signal RBn to "H" level. Since the read operation of the middle page is completed, the non-volatile memory 20 maintains the ready / busy signal RBn at the "H" level and begins the read operation of the upper page.

[0257] If the memory controller 10 acknowledges the "H" level ready / busy signal RBn, it sends a set of instructions to the non-volatile memory 20 for a cache read operation of the middle page (hard data HB_M). More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0258] The non-volatile memory 20 performs cell read operations in parallel with the upper page, sending the hard data HB_M of the data register 214 to the memory controller 10.

[0259] If the cache read operation for the middle page (hard data HB_M) is complete, then the memory controller 10 sends the instruction "3Fh" to the non-volatile memory 20. The instruction "3Fh" is for reading the last page (in... Figure 15 In the example, after the read operation of the cell (for the upper page) is completed, an instruction is scheduled to transmit the read data to the latch circuit XDL.

[0260] If the output of hard data HB_M (buffer read operation) ends, and the system becomes capable of transmitting data to the latch circuit XDL, then the non-volatile memory 20 sets the ready / busy signal RBn to "L" level. Furthermore, the non-volatile memory 20 transmits hard data HB_U to the latch circuit XDL. At this time, for example, in the latch circuit ADL, the OR operation result (SB_L|SB_M|SB_U) of soft data SB_L, SB_M, and SB_U is stored as the SB buffer. In other words, the latch circuit ADL stores compressed soft data SB.

[0261] If the transfer of hard data HB_U to latch circuit XDL is completed, then non-volatile memory 20 sets the ready / busy signal RBn to "H" level.

[0262] If the memory controller 10 acknowledges the "H" level ready / busy signal RBn, it sends a set of instructions for a cache read operation of the upper page (hard data HB_U) to the non-volatile memory 20. More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0263] The non-volatile memory 20 sends the hard bit data HB_U of the data register 214 to the memory controller 10.

[0264] The readout action of compressed soft data SB is the same as the first action mode.

[0265] 1.5.5 Instruction Sequence for Read Mode 3

[0266] Next, refer to Figure 16 An example of the instruction sequence for the third readout mode will be explained. Figure 16 This is the instruction sequence for the third read mode. Figure 16 In the example, for simplicity, signals CEn, CLE, ALE, WEn, REn, DQS, and DQSn are omitted, representing signal DQ and the ready / busy signal RBn. In signal DQ, instructions are represented in circles, addresses in quadrilaterals, and data in hexagons.

[0267] Figure 16 The example illustrates the situation where, based on a single instruction set, the read operations of the lower page, the middle page, and the upper page of a single unit group (CU) are executed sequentially.

[0268] like Figure 16 As shown, firstly, the memory controller 10 sends a set of instructions for the read operation of the third read mode to the non-volatile memory 20. More specifically, the memory controller 10 continuously sends the instructions "PFX", "00h", address "ADD", and instruction "30h" to the non-volatile memory 20.

[0269] If the non-volatile memory 20 receives the instruction "30h", then the ready / busy signal RBn is set to "L" level, and first, the cell read operation of the next page begins. As a result of the cell read operation, for example, in latch circuit XDL, hard data HB_L is stored. For example, in latch circuit ADL, soft data SB_L is stored.

[0270] If the read operation of the next page is completed, the non-volatile memory 20 sets the ready / busy signal RBn to "H" level. Alternatively, the non-volatile memory 20 maintains the ready / busy signal RBn at "H" level and begins the read operation of the next page.

[0271] If the memory controller 10 acknowledges the "H" level ready / busy signal RBn, it sends a set of instructions to the non-volatile memory 20 for a cache read operation of the next page (hard data HB_L). More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0272] The non-volatile memory 20 performs cell read operations in parallel with the middle page, sending the hard bit data HB_L of the data register 214 to the memory controller 10.

[0273] After reading the hard data HB_L from the non-volatile memory 20, the memory controller 10 sends a set of instructions to the non-volatile memory 20 to read (transfer) the hard data HB_M to the latch circuit XDL. More specifically, the memory controller 10 continuously sends the instruction "00h", the address "ADD", and the instruction "YYh" to the non-volatile memory 20. The instruction "YYh" is the instruction to transfer the hard data HB_M to the latch circuit XDL.

[0274] If the cell read operation of the middle page is completed and the system becomes ready to transfer data to the latch circuit XDL, then the non-volatile memory 20 sets the ready / busy signal RBn to the "L" level. Then, the non-volatile memory 20 transfers the hard data HB_M to the latch circuit XDL. At this time, for example, in the latch circuit ADL, the result of the OR operation (SB_L|SB_M) of the soft data SB_L and SB_M is stored as the SB buffer.

[0275] After the hard data HB_M to the latch circuit XDL is transferred, the non-volatile memory 20 sets the ready / busy signal RBn to the "H" level. The non-volatile memory 20 maintains the ready / busy signal RBn at the "H" level and begins the read operation of the upper page.

[0276] When the memory controller 10 detects a ready / busy signal RBn at the "H" level, it sends a set of instructions to the non-volatile memory 20 for a cache read operation of the middle page (hard data HB_M). More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0277] In parallel with the cell read operation of the upper page, the non-volatile memory 20 sends the hard bit data HB_M of the data register 214 to the memory controller 10.

[0278] After reading the hard data HB_M from the non-volatile memory 20, the memory controller 10 sends a set of instructions to the non-volatile memory 20 to read (transfer) the hard data HB_U to the latch circuit XDL. More specifically, the memory controller 10 continuously sends the instruction "00h", the address "ADD", and the instruction "ZZh" to the non-volatile memory 20. The instruction "ZZh" is an instruction to transfer the hard data HB_U to the latch circuit XDL.

[0279] If the read operation of the upper page cell is completed and the system becomes capable of transmitting data to the latch circuit XDL, then the non-volatile memory 20 sets the ready / busy signal RBn to the "L" level. Then, the non-volatile memory 20 transmits the hard data HB_U to the latch circuit XDL. At this time, for example, in the latch circuit ADL, the OR operation result (SB_L|SB_M|SB_U) of the soft data SB_L, SB_M, and SB_U is stored as the SB cache. That is, the compressed soft data SB is stored in the latch circuit ADL.

[0280] After the hard data HB_U of the latch circuit XDL is transferred, the non-volatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0281] When the memory controller 10 detects a ready / busy signal RBn at the "H" level, it sends a set of instructions to the non-volatile memory 20 for a cache read operation of the upper page (hard data HB_U). More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0282] The non-volatile memory 20 sends the hard bit data HB_U of the data register 214 to the memory controller 10.

[0283] The readout action of compressed soft data SB is the same as the first action mode.

[0284] 1.6 Effects of this implementation method

[0285] If configured as described in this embodiment, a memory system capable of suppressing the increase in data transfer volume can be provided. This effect will be described in detail.

[0286] For example, in the case of performing soft-decision decoding, at least one soft bit data is required for each page. Therefore, based on the number of pages in the unit group (CU), multiple pages of soft bit data are read from the non-volatile memory to the memory controller. For example, in the case of TLC, at least six pages of page data, totaling six pages of page data (three pages of hard bit data corresponding to the lower, middle, and upper pages, and three pages of soft bit data), are read. Therefore, if memory cell transistors become more multi-valued, the amount of data transferred from non-volatile memory to the memory controller increases. Consequently, data transfer time increases, and the processing capability of the memory system decreases.

[0287] In this embodiment, the non-volatile memory 20 compresses (or processes) the soft bit data SB of multiple pages of cell group CU, and can calculate the compressed soft bit data SB of one page of data. Therefore, it is possible to suppress the increase in data transfer volume. Therefore, it is possible to shorten the data transfer time and improve the processing capability of memory system 3.

[0288] Furthermore, if configured as in this embodiment, the memory controller 10 can decode the soft data SB corresponding to each page based on the hard data HB and the compressed soft data SB.

[0289] 2. Second Implementation Method

[0290] Next, the second embodiment will be described. In the second embodiment, the readout process, which differs from that of the first embodiment, will be explained. Hereinafter, the description will focus on aspects that differ from the first embodiment.

[0291] 2.1 Reading out the action flow

[0292] First, refer to Figure 17 The process of reading operations in memory system 3 will be explained. Figure 17 It is a flowchart of the reading action. Furthermore, Figure 17 The example illustrates the case of reading multiple pages of data from a single unit group (CU).

[0293] like Figure 17 As shown, compared with the first embodiment Figure 13 Unlike the first embodiment, the hard-determined decoding process is omitted (steps S13 and S14). After reading multiple hard-bit data HB from the non-volatile memory 20 (step S12), the memory controller 10 continues to read compressed soft-bit data SB (step S15). Subsequent processes (steps S16 and S17) are the same as in the first embodiment.

[0294] 2.2 Effects of this implementation method

[0295] If this embodiment is configured as described above, then the same effects as in the first embodiment will be obtained.

[0296] 3. Third Implementation Method

[0297] Next, the third embodiment will be described. In the third embodiment, the readout operation that differs from the first and second embodiments will be described. Hereinafter, the description will focus on aspects that differ from the first and second embodiments.

[0298] 3.1 Composition of Data Register and Sensing Amplifier

[0299] First, refer to Figure 18An example of the configuration of the data register 214 and the sensing amplifier 213 will be described. Figure 18 This is a block diagram of data register 214 and sensing amplifier 213.

[0300] like Figure 18 As shown, the sensing amplifier 213 in this embodiment includes a counter CT. Other configurations are the same as in the first embodiment. Figure 6 same.

[0301] Counter CT is a counter that counts the number (bits) of "1" data in one page of compressed soft data SB. Counter CT transmits the counting result to sequence generator 206. For example, sequence generator 206 transmits the counting result to status register 205 as status information STS. Furthermore, the data for counting "1" data by counter CT is not limited to compressed soft data SB. For example, counter CT can also count the number of "1" data in soft data SB_L, SB_M, and SB_U respectively. Additionally, counter CT can also count the number of "0" data. Counter CT counts the number (bits) of logic level data in any of the latch circuits being counted.

[0302] 3.2 Specific examples of the relationship between count values ​​and threshold voltage distribution

[0303] Next, refer to Figure 19 A specific example illustrating the relationship between the count value of the counter CT and the threshold voltage distribution is provided. Figure 19 This is a graph showing the relationship between the threshold voltage distribution and the count value for the "Er" and "A" states.

[0304] like Figure 19 As shown, for example, when the threshold voltage distribution without the "Er" state overlaps with the threshold voltage distribution of the "A" state, the number of memory cell transistors MC whose threshold voltage is between voltage VAL and voltage VAH is relatively small. In other words, the number of memory cell transistors MC whose soft bit data SB becomes "1" data is relatively small. In this case, the count value of the "1" data of the counter CT is relatively small. In contrast, if the overlapping area at the lower end of the threshold voltage distribution becomes larger, the number of memory cell transistors MC whose threshold voltage is between voltage VAL and voltage VAH increases. In other words, the number of memory cell transistors MC whose soft bit data SB becomes "1" data increases. If the overlapping area at the lower end of the threshold voltage distribution becomes larger, the number of failed bits increases, and the probability of hard decision decoding failure increases. Therefore, the difficulty of hard decision decoding can be estimated by compressing the count value of the "1" data of the soft bit data SB.

[0305] 3.3 Reading Action Flow

[0306] Next, refer to Figure 20 The process of reading operations in memory system 3 will be explained. Figure 20 It is a flowchart of the reading action. Furthermore, Figure 20 The example illustrates the case of reading multiple pages of data from a single unit group (CU).

[0307] like Figure 20 As shown, the procedures up to steps S10 to S12 are the same as in the first embodiment.

[0308] After step S12, the memory controller 10 reads the count value of the "1" data of the compressed soft bit data SB from the non-volatile memory 20. Furthermore, the memory controller 10 compares the count value with a preset determination value (step S20). Alternatively, the non-volatile memory 20 can also compare the count value with the determination value. In this case, the memory controller 10 reads the comparison result from the non-volatile memory 20. Additionally, the non-volatile memory 20 can also count the number of "1" data in each of the soft bit data SB_L, SB_M, and SB_U. In this case, the memory controller 10 can also compare each count value with the determination value separately.

[0309] If the count value is less than the determination value (step S21_Yes), the memory controller 10 performs hard determination decoding processing (step S13). In this case, since the probability of success of hard determination decoding processing is relatively high, the memory controller 10 does not perform the reading of compressed soft bit data SB, but directly performs hard determination decoding processing.

[0310] If the count value is above the determination value (step S21 - No), the memory controller 10 performs the operation of steps S15 to S17 in the same manner as in the first embodiment.

[0311] 3.4 Reading the instruction sequence of the action

[0312] Next, refer to Figure 21 An example of a sequence of instructions for reading out actions will be explained. Figure 21 It is the sequence of instructions for the read-out action. Figure 21 In the example, for simplicity, signals CEn, CLE, ALE, WEn, REn, DQS, and DQSn are omitted, representing signal DQ and the ready / busy signal RBn. In signal DQ, instructions are represented in circles, addresses in quadrilaterals, and data in hexagons.

[0313] Figure 21 The example illustrates the case of executing the first readout mode, but this implementation can also be applied to the second or third readout mode.

[0314] like Figure 21 As shown, the instruction set up to the cache read operation of hard data HB_U is the same as that in the first embodiment. Figure 14 same.

[0315] After reading the hard data HB_U from the non-volatile memory 20, the memory controller 10 sends a set of instructions to the non-volatile memory 20 to read (transfer) the compressed soft data SB to the latch circuit XDL. More specifically, the memory controller 10 continuously sends the instruction "00h", the address "ADD", and the instruction "XXh" to the non-volatile memory 20.

[0316] If the non-volatile memory 20 receives the instruction "XXh", it sets the ready / busy signal RBn to "L" level, for example, by transferring compressed soft data SB from latch circuit ADL to latch circuit XDL. At this time, counter CT counts the number of "1" data in the compressed soft data SB. The count value is stored in status register 205.

[0317] If the transmission of compressed soft data SB ends and the count of the number of "1" data ends, then the non-volatile memory 20 sets the ready / busy signal RBn to the "H" level.

[0318] If the memory controller 10 acknowledges the "H" level ready / busy signal RBn, it sends a set of instructions to read the count value. The memory controller 10 reads the count value from the status register 205 as status information STS. More specifically, the memory controller 10 sends the instruction "7Xh" to the non-volatile memory 20. The instruction "7Xh" is the instruction to execute the reading of the status information STS.

[0319] If the non-volatile memory 20 receives the instruction "7Xh", it sends a count value to the memory controller 10. Figure 21 The "1" count is used as the status information STS.

[0320] After receiving the count value information, the memory controller 10 sends a set of instructions to the non-volatile memory 20 for a high-speed buffer read operation of compressed soft bit data SB. More specifically, the memory controller 10 continuously sends the instruction "05h", the address "ADD", and the instruction "E0h" to the non-volatile memory 20.

[0321] The non-volatile memory 20 sends compressed soft bit data SB of the data register 214 to the memory controller 10.

[0322] 3.5 Effects of this implementation method

[0323] If this embodiment is configured as described above, then the same effects as in the first embodiment will be obtained.

[0324] Furthermore, in this embodiment, the non-volatile memory 20 includes a counter CT that counts the number of "1" data points in the compressed soft data SB. By counting the number of "1" data points, the ease or difficulty of the hard-determination decoding process can be determined. If the count value is less than a preset determination value, the memory controller 10 determines that the probability of successful hard-determination decoding is high, and the reading (data transfer) of the compressed soft data SB from the non-volatile memory 20 can be omitted. Therefore, when the probability of successful hard-determination decoding is high, the data transfer of the compressed soft data SB, which is likely to be unused, can be avoided. Thus, the increase in data transfer volume can be suppressed.

[0325] 4. Fourth Implementation Method

[0326] Next, the fourth embodiment will be described. In the fourth embodiment, the memory cell transistor MC is described as a QLC (Quad Level Cell) that stores 4 bits of data, including the lower bit, middle bit, upper bit, and top bit. Hereinafter, the description will focus on aspects that differ from the first to third embodiments.

[0327] 4.1 Relationship between threshold voltage distribution of memory cell transistors and data allocation

[0328] First, refer to Figure 22 An example illustrating the relationship between the threshold voltage distribution of the memory cell transistor MC and the data allocation is presented. Figure 22 This is a graph showing the relationship between the threshold voltage distribution of the QLC and the data allocation.

[0329] like Figure 22 As shown, the threshold voltage of each memory cell transistor MC takes a discrete value from any one of 16 distributions. Hereinafter, the 16 distributions are described in ascending order of threshold voltage as states "S0", "S1", "S2", "S3", "S4", "S5", "S6", "S7", "S8", "S9", "S10", "S11", "S12", "S13", "S14", and "S15".

[0330] The "S0" state is equivalent to the data erasure state. Furthermore, the "S1" to "S15" states are equivalent to injecting charge into the charge storage layer to write data. During the write operation, the verification voltages corresponding to each threshold voltage distribution are set to V1 to V15. Thus, these voltage values ​​are in the relationship V1 < V2 < V3 < V4 < V5 < V6 < V7 < V8 < V9 < V10 < V11 < V12 < V13 < V14 < V15 < Vread.

[0331] More specifically, the threshold voltage included in state "S0" is less than voltage V1. The threshold voltage included in state "S1" is above voltage V1 and less than voltage V2. The threshold voltage included in state "S2" is above voltage V2 and less than voltage V3. The threshold voltage included in state "S3" is above voltage V3 and less than voltage V4. The threshold voltage included in state "S4" is above voltage V4 and less than voltage V5. The threshold voltage included in state "S5" is above voltage V5 and less than voltage V6. The threshold voltage included in state "S6" is above voltage V6 and less than voltage V7. The threshold voltage included in state "S7" is above voltage V7 and less than voltage V8. The threshold voltage included in state "S8" is above voltage V8 and less than voltage V9. The threshold voltage included in state "S9" is above voltage V9 and less than voltage V10. The threshold voltage included in state "S10" is above voltage V10 and less than voltage V11. The threshold voltage included in state “S11” is above voltage V11 and below voltage V12. The threshold voltage included in state “S12” is above voltage V12 and below voltage V13. The threshold voltage included in state “S13” is above voltage V13 and below voltage V14. The threshold voltage included in state “S14” is above voltage V14 and below voltage V15. The threshold voltage included in state “S15” is above voltage V15 and below voltage VREAD.

[0332] As described above, each memory cell transistor MC can take on 16 states through any one of 16 threshold voltage distributions. These states are assigned binary representations from "0000" to "1111", and each memory cell transistor MC can store 4 bits of data. Hereinafter, these 4 bits are referred to as the lower bit, middle bit, upper bit, and top bit. Furthermore, the set of lower bits written to (or read from) the cell group CU in one go is referred to as the lower page. The set of middle bits is referred to as the middle page. The set of upper bits is referred to as the upper page. The set of top bits is referred to as the top page.

[0333] exist Figure 22In the example, for the memory cell transistors MC contained in each threshold voltage distribution, the data for "top bit / upper bit / middle bit / lower bit" is allocated in the following manner.

[0334] "S0" status: "1111" data

[0335] "S1" status: "0111" data

[0336] "S2" status: "0011" data

[0337] "S3" status: "1011" data

[0338] "S4" status: "1001" data

[0339] "S5" status: "1000" data

[0340] "S6" status: "0000" data

[0341] "S7" status: "0001" data

[0342] "S8" status: "0101" data

[0343] "S9" status: "0100" data

[0344] "S10" status: "0110" data

[0345] "S11" Status: "0010" Data

[0346] "S12" status: "1010" data

[0347] "S13" status: "1110" data

[0348] "S14" status: "1100" data

[0349] "S15" Status: "1101" Data

[0350] When reading data with this allocation, the lower bit is determined by the readout actions corresponding to states "S5", "S7", "S9", and "S15". The middle bit is determined by the readout actions corresponding to states "S4", "S10", and "S14". The upper bit is determined by the readout actions corresponding to states "S2", "S8", "S11", and "S13". The top bit is determined by the readout actions corresponding to states "S1", "S3", "S6", and "S12". In other words, the values ​​of the lower, middle, upper, and top bits are determined by readout actions corresponding to 4, 3, 4, and 4 states, respectively. This data allocation will be described as a "4-3-4-4 code". However, the data allocation is not limited to the 4-3-4-4 code.

[0351] 4.2 Hard bit data and compressed soft bit data for each state

[0352] Next, refer to Figure 23 The hard bit data HB and soft bit data SB for each state are explained. Figure 23 This is a graph showing the relationship between the threshold voltage distribution of the QLC and the hard bit data HB and the compressed soft bit data SB.

[0353] like Figure 23 As shown, the two read voltages corresponding to state "S1" are set to voltages V1L and V1H. The two read voltages corresponding to state "S2" are set to voltages V2L and V2H. The two read voltages corresponding to state "S3" are set to voltages V3L and V3H. The two read voltages corresponding to state "S4" are set to voltages V4L and V4H. The two read voltages corresponding to state "S5" are set to voltages V5L and V5H. The two read voltages corresponding to state "S6" are set to voltages V6L and V6H. The two read voltages corresponding to state "S7" are set to voltages V7L and V7H. The two read voltages corresponding to state "S8" are set to voltages V8L and V8H. The two read voltages corresponding to state "S9" are set to voltages V9L and V9H. The two read voltages corresponding to state "S10" are set to voltages V10L and V10H. Set the two read voltages corresponding to state "S11" to voltages V11L and V11H. Set the two read voltages corresponding to state "S12" to voltages V12L and V12H. Set the two read voltages corresponding to state "S13" to voltages V13L and V13H. Set the two read voltages corresponding to state "S14" to voltages V14L and V14H. Set the two read voltages corresponding to state "S15" to voltages V15L and V15H.

[0354] These voltages are in the relationship V1L < V1 < V1H < V2L < V2 < V2H < V3L < V3 < V3H < V4L < V4 < V4H < V5L < V5 < V5H < V6L < V6 < V6H < V7L < V7 < V7H < V8L < V8 < V8H < V9L < V9 < V9H < V10L < V10 < V10H < V11L < V11 < V11H < V12L < V12 < V12H < V13L < V13 < V13H < V14L < V14 < V14H < V15L < V15 < V15H < VREAD.

[0355] The readings of voltages V1L, V1H, V2L, V2H, V3L, V3H, V4L, V4H, V5L, V5H, V6L, V6H, V7L, V7H, V8L, V8H, V9L, V9H, V10L, V10H, V11L, V11H, V12L, V12H, V13L, V13H, V14L, V14H, V15L, and V15H will be used. The actions are described as follows: 1LR read, 1HR read, 2LR read, 2HR read, 3LR read, 3HR read, 4LR read, 4HR read, 5LR read, 5HR read, 6LR read, 6HR read, 7LR read, 7HR read, 8LR read, 8HR read, 9LR read, 9HR read, 10LR read, 10HR read, 11LR read, 11HR read, 12LR read, 12HR read, 13LR read, 13HR read, 14LR read, 14HR read, 15LR read, 15HR read.

[0356] During the lower-level page read operation, eight read operations are performed: 5LR read, 5HR read, 7LR read, 7HR read, 9LR read, 9HR read, 15LR read, and 15HR read. The hard data HB_L is the data determined by the 5LR, 7LR, 9LR, and 15LR reads. The soft data SB_L is based on the XOR operation between the hard data HB_L and the data determined by the 5HR, 7HR, 9HR, and 15HR reads.

[0357] During the middle page read operation, six read operations are performed: 4LR read, 4HR read, 10LR read, 10HR read, 14LR read, and 14HR read. The hard data HB_M is determined by the 5LR, 10LR, and 14LR reads. The soft data SB_M is based on the XOR operation between the hard data HB_M and the data determined by the 4HR, 10HR, and 14HR reads.

[0358] During the upper-level page read operation, eight read operations are performed: 2LR read, 2HR read, 8LR read, 8HR read, 11LR read, 11HR read, 13LR read, and 13HR read. The hard data HB_U is the data determined by the 2LR, 8LR, 11LR, and 13LR reads. The soft data SB_U is based on the XOR operation between the hard data HB_U and the data determined by the 2HR, 8HR, 11HR, and 13HR reads.

[0359] During the top-page read operation, eight read operations are performed: 1LR read, 1HR read, 3LR read, 3HR read, 6LR read, 6HR read, 12LR read, and 12HR read. The hard data HB_T is the data determined by the 1LR, 3LR, 6LR, and 12LR reads. The soft data SB_T is based on the XOR operation between the hard data HB_T and the data determined by the 1HR, 3HR, 6HR, and 12HR reads.

[0360] The compressed soft bit data SB is the data calculated by performing an OR operation on the soft bit data SB_L, SB_M, SB_U, and SB_T.

[0361] exist Figure 23 In this example, corresponding to the 30 readout voltages, the threshold voltage of the memory cell transistor MC is divided into 31 regions. The combination of "hard data HB_T / HB_U / HM_M / HB_L" and "compressed soft data SB" for each region of each state is shown below.

[0362] "S0" state (less than voltage V1L): "1111", "0"

[0363] "S1" state (voltage V1L above but less than voltage V1H): "0111", "1"

[0364] "S1" state (voltage V1H above and voltage V2L): "0111", "0"

[0365] "S2" state (voltage V2L above but less than voltage V2H): "0011", "1"

[0366] "S2" state (voltage V2H above and voltage V3L): "0011", "0"

[0367] "S3" state (voltage V3L above but less than voltage V3H): "1011", "1"

[0368] "S3" state (voltage V3H above and voltage V4L): "1011", "0"

[0369] "S4" state (voltage V4L above but less than voltage V4H): "1001", "1"

[0370] "S4" state (voltage V4H above and voltage V5L): "1001", "0"

[0371] "S5" state (voltage V5L above but less than voltage V5H): "1000", "1"

[0372] "S5" state (voltage V5H above and voltage V6L): "1000", "0"

[0373] "S6" state (voltage V6L above but less than voltage V6H): "0000", "1"

[0374] "S6" state (voltage V6H above and voltage V7L): "0000", "0"

[0375] "S7" state (voltage V7L above but less than voltage V7H): "0001", "1"

[0376] "S7" state (voltage V7H above and voltage V8L): "0001", "0"

[0377] "S8" state (voltage above V8L but below V8H): "0101", "1"

[0378] "S8" state (voltage V8H above and voltage V9L): "0101", "0"

[0379] "S9" state (voltage V9L above and voltage V9H): "0100", "1"

[0380] "S9" state (voltage V9H above and voltage V10L): "0100", "0"

[0381] "S10" state (voltage V10L above but less than voltage V10H): "0110", "1"

[0382] "S10" state (voltage V10H above and voltage V11L): "0110", "0"

[0383] "S11" state (voltage V11L above but less than voltage V11H): "0010", "1"

[0384] "S11" state (voltage V11H above and voltage V12L): "0010", "0"

[0385] "S12" state (voltage V12L above but less than voltage V12H): "1010", "1"

[0386] "S12" state (voltage V12H above and voltage V13L): "1010", "0"

[0387] "S13" state (voltage V13L above but less than voltage V13H): "1110", "1"

[0388] State “S13” (voltage V13H above and voltage V14L): “1110”, “0”

[0389] "S14" state (voltage V14L above but less than voltage V14H): "1100", "1"

[0390] "S14" state (voltage V14H above and voltage V15L): "1100", "0"

[0391] "S15" state (voltage V15L above but less than voltage V15H): "1101", "1"

[0392] "S15" state (voltage V15H above and less than voltage VEAD): "1101", "0"

[0393] 4.3 Decoding Methods for Compressed Soft Bits

[0394] Next, refer to Figure 24 The decoding method for compressed soft bit data (SB) is explained. Figure 24 This is a diagram representing the decoding process of soft bit data SB_L, SB_M, SB_U, and SB_T.

[0395] The positions (states) that can be generated by the "1" data in soft bit data SB_L, SB_M, SB_U, and SB_T are mutually exclusive. Furthermore, the combinations of hard bit data HB_L, HB_M, HB_U, and HB_T can be defined one-to-one with the combinations of soft bit data SB_L, SB_M, SB_U, and SB_T. Using these conditions, the soft bit data SB of each page is decoded based on the hard bit data HB_L, HB_M, HB_U, and HB_T and the compressed soft bit data SB.

[0396] like Figure 24 As shown, the SB decoding circuit 163 receives hard data HB_L, HB_M, HB_U, and HB_T, as well as compressed soft data SB, from the non-volatile memory 20. The SB decoder 1006 performs the following operations when decoding the soft data SB_L, SB_M, SB_U, and SB_T. Furthermore, in the following expressions, "|" represents an OR operation, and "~" represents inverted data. Additionally, in the following expressions, the hard data HB_L, HB_M, HB_U, and HB_T are only represented as "L", "M", "U", and "T".

[0397] SB_L=((~L&~M&~U&T)|(L&~M&~U&~T)|

[0398] (~L&~M&U&~T)|(L&~M&U&T))&SB

[0399] SB_M=((L&~M&~U&T)|(~L&M&U&~T)|

[0400] (~L&~M&U&T))&SB

[0401] SB_U=((L&M&~U&~T)|(L&~M&U&~T)|

[0402] (~L&M&~U&~T)|(~L&M&U&T))&SB

[0403] SB_T=((L&M&U&~T)|(L&M&~U&T)|

[0404] (~L&~M&~U&~T)|(~L&M&~U&T))&SB

[0405] According to the aforementioned formula, the following will be used Figure 24 The soft-bit data SB_L, SB_M, SB_U, and SB_T are described for decoding. Furthermore, the operational formulas can be appropriately modified based on the allocation of data in the memory cell transistor MC.

[0406] 4.4 Effects of this implementation method

[0407] If this embodiment is configured as described above, then the same effects as in the first embodiment will be obtained.

[0408] Furthermore, this embodiment can be combined with the second or third embodiment.

[0409] 5. Other

[0410] According to the embodiment, the memory system includes: a non-volatile memory (20) comprising a plurality of memory cells (MCs) capable of storing at least a first bit (lower bit) and a second bit (middle bit), and calculating a third soft bit data (compressed SB) based on an OR operation using at least a first soft bit data (SB_L) corresponding to the first bit and a second soft bit data (SB_M) corresponding to the second bit; and a memory controller (10) for decoding the first soft bit data and the second soft bit data based on at least a first hard bit data (HB_L) corresponding to the first bit, a second hard bit data (HB_M) corresponding to the second bit, and the third soft bit data.

[0411] By applying the described embodiments, a memory system capable of suppressing the increase in data transfer volume between the memory controller and the non-volatile memory can be provided.

[0412] Furthermore, the implementation method is not limited to the described method and various variations are possible.

[0413] For example, in the third embodiment, a case is shown where either hard decision decoding or soft decision decoding is performed based on the determination result of the count value; however, the action based on the determination result of the count value is not limited to this. For example, if the hard decision decoding process fails, the count value determination may also be performed. In this case, it may also be determined whether or not soft decision decoding is performed based on the determination result.

[0414] For example, in the described embodiment, the case of compressing multiple pages of soft bit data SB of one unit group CU into one page of data has been explained, but it is not limited to this. For example, multiple soft bit data SB of multiple unit groups CU may also be compressed into one page of data.

[0415] Furthermore, the "connection" in the above embodiments also includes a state in which two parts are indirectly connected by other components such as transistors or resistors.

[0416] The embodiments are exemplified, and the scope of the invention is not limited to these.

[0417] [Explanation of Symbols]

[0418] 1: Data processing device

[0419] 2: Main unit

[0420] 3: Memory System

[0421] 10: Memory controller

[0422] 11: Host Interface Circuit

[0423] 12: CPU

[0424] 13: ROM

[0425] 14: RAM

[0426] 15: Buffer memory

[0427] 16: ECC circuit

[0428] 17: Memory Interface Circuit

[0429] 20: Non-volatile memory

[0430] 160: Encoding circuit

[0431] 161: Hard-determined decoding circuit

[0432] 162: Soft-determining decoding circuit

[0433] 163: SB Decoding Circuit

[0434] 201: Input / Output Circuit

[0435] 202: Logic Control Circuit

[0436] 203: Address Register

[0437] 204: Instruction Register

[0438] 205: Status Register

[0439] 206: Sequence Generator

[0440] 207: Ready / Busy Circuit

[0441] 208: Voltage Generation Circuit

[0442] 211: Memory Cell Array

[0443] 212: Line Decoder

[0444] 213: Sensing Amplifier

[0445] 214: Data Register

[0446] 215: Column Decoder

[0447] 1001: Demultiplexer

[0448] 1002~1005: Buffer

[0449] 1006: SB Decoder

[0450] CT: Counter.

Claims

1. A memory system, comprising: Non-volatile memory, comprising multiple memory cells, each capable of storing at least the first, second, and third bits; as well as A memory controller controls the non-volatile memory; The non-volatile memory is: Based on the first soft bit data of the first bit, the second soft bit data of the second bit, and the third soft bit data of the third bit, the fourth soft bit data is generated according to reversible compression; The first hard bit data of the first bit, the second hard bit data of the second bit, the third hard bit data of the third bit, and the fourth soft bit data are output to the memory controller; The memory controller is: Based on the first hard data, the second hard data, the third hard data, and the fourth soft data, the first soft data, the second soft data, and the third soft data are recovered; and Error correction is performed using the first hard data, the second hard data, the third hard data, and the fourth soft data.

2. The memory system according to claim 1, wherein The data size of the first hard data, the second hard data, the third hard data, and the fourth soft data are all the same.

3. The memory system according to claim 1, wherein The non-volatile memory is: The fourth soft bit data is calculated based on an OR operation using the first soft bit data associated with the first bit, the second soft bit data associated with the second bit, and the third soft bit data associated with the third bit.

4. The memory system according to claim 3, wherein The memory controller is: Based on the first hard bit data and the fourth soft bit data, the first soft bit data is recovered. Based on the second hard bit data and the fourth soft bit data, the second soft bit data is recovered. Based on the third hard bit data and the fourth soft bit data, the third soft bit data is recovered.

5. The memory system according to claim 3, wherein The first bit is determined by at least a first readout action based on the first state; The first readout action includes: The second readout action uses the first voltage corresponding to the first state; and The third readout action uses a second voltage that corresponds to the first state and is higher than the first voltage; The first hard bit data is determined at least based on the second readout action; The first soft bit data is calculated based on the first hard bit data and the result of the third readout action.

6. The memory system according to claim 3, wherein The memory controller performs the error correction process based on the first hard data, the second hard data, the third hard data, the first soft data, the second soft data, and the third soft data.

7. The memory system according to claim 3, wherein The non-volatile memory also includes: A counter counts the number of first logic level data of any one of the first soft bit data, the second soft bit data, the third soft bit data, or the fourth soft bit data; The memory controller reads the number of bits, and if the number of bits read is less than a preset determination value, it reads the fourth soft bit data from the non-volatile memory.

8. A non-volatile memory, comprising: Multiple storage units, each capable of storing at least the first, second, and third bits; Word lines are commonly connected to the multiple memory cells; Multiple bit lines are respectively connected to the multiple memory cells; as well as A sensing amplifier, connected to the plurality of bit lines; The sensing amplifier is: Generate the first hard bit data of the first bit; Generate the second hard bit data of the second bit; Generate the third hard bit data of the third bit; and Based on the first soft bit data of the first bit, the second soft bit data of the second bit, and the third soft bit data of the third bit, a fourth soft bit data is generated according to reversible compression; and The first hard bit data, the second hard bit data, the third hard bit data, and the fourth soft bit data are output to an external memory controller.

9. The non-volatile memory according to claim 8, wherein The data size of the first hard data, the second hard data, the third hard data, and the fourth soft data are all the same.

10. The non-volatile memory according to claim 8, wherein The fourth soft bit data is calculated based on an OR operation using the first soft bit data associated with the first bit, the second soft bit data associated with the second bit, and the third soft bit data associated with the third bit.

11. The non-volatile memory according to claim 10, wherein The first bit is determined by at least a first readout action based on the first state. The first readout action includes: The second readout action uses the first voltage corresponding to the first state; and The third readout action uses a second voltage that corresponds to the first state and is higher than the first voltage; The first hard bit data is determined at least based on the second readout action; The first soft bit data is calculated based on the first hard bit data and the result of the third readout action.

12. The non-volatile memory according to claim 10, further comprising: The counter counts the number of first logic level data of any one of the first soft bit data, the second soft bit data, the third soft bit data, or the fourth soft bit data.

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