Local reference voltage generator for non-volatile memory

Abstract

Memory devices including a reference voltage (VREF) generator and methods of operation thereof are disclosed to improve memory sensing margins and extend the operating temperature range and lifetime of the devices. Generally, the devices also include an array of non-volatile memory cells divided into a plurality of blocks, a sensing circuit coupled to the array to receive memory signals from the array and compare them to the VREF to read data from the cells. A local reference voltage generator is configured to provide one of a plurality of reference voltages to the sensing circuit based on which block is being read. The array can be divided based on row and column addresses of the cells in the blocks. Therein, the cells include 1T1C ferroelectric random access memory (F-RAM) cells and the reference voltage is selected based on a lowest P term or a highest U term of the cells in the block being read.

Description

[0001] Cross-references to related applications

[0002] This application is an international application of U.S. Nonprovisional Application No. 17 / 122,284, filed December 15, 2020, and claims priority to U.S. Provisional Patent Application Serial No. 63 / 085,823, filed September 30, 2020, pursuant to 35 U.SC119(e), the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to semiconductor memories, and more specifically to memory devices having an array of non-volatile memory (NVM) cells divided into segments or blocks and including a local reference voltage generator, and methods of operating thereof. Background Technology

[0004] Integrated memory devices using arrays of single-ended sensing non-volatile memory (NVM) cells (e.g., a 1T1C (1 transistor 1 capacitor) architecture) provide high memory density. NVM memory cells store data as charge, for example, in silicon-oxide-nitride-oxide-silicon (SONOS) type charge-trapping NVM cells, or as the polarization state of a ferroelectric capacitor in ferroelectric random access memory (F-RAM) cells. In single-ended sensing / reading, data stored in a cell is read by comparing a reference voltage with a voltage generated on the cell's bit line due to the cell's charge or polarization state. Based on the comparison of the bit line voltage or current with a reference, the NVM cell is considered either programmed or erased. For example, Figure 1 The diagram illustrates a 1T1CF-RAM cell. Cell 100 includes a ferroelectric capacitor 102 having a first plate connected to a plate line (PL) and a second plate coupled to a bit line (BL) via a transistor 104 controlled by a word line (WL). Data is written to the cell by applying an electric field to charge either side of the plates of the ferroelectric capacitor 102, forcing atoms within the capacitor to orient upwards or downwards (depending on the polarity of the charge), thereby storing a P-term or logic "1", or a U-term or logic "0". In another embodiment, the logical / binary states of the "P-term" and "U-term" can be reversed. In single-ended sensing, cell 100 is read by applying a read voltage between the plate line PL and the bit line BL, or by applying a pulse to the plate line and operating the transistor 104. The "P-term" or "U-term" voltage is output via the bit line BL, and then the "P-term" or "U-term" voltage is compared with a reference voltage (V) using a sense amplifier 106 in the memory device. REF (Compare)

[0005] A reference voltage (V) is generated by performing a margin sweep of the array of memory cells to determine the expected bit line voltage by reading the programming cells (P-items) and erasing cells (U-items). REF In one implementation, V REF It can be selected to be located between the highest measured U-term (U0) voltage and the lowest measured P-term (P0) voltage in the entire memory array, such that when the memory cell 100 is read, a bit line voltage higher than the reference is identified as programmed, and a voltage lower than the reference is identified as erased. Figure 1 An example margin scan of an F-RAM memory array is shown, illustrating the statistical changes in bit line voltages (memory signals) obtained by reading P and U terms. The difference between the lowest P term (P0) and the highest U term (U0) represents the total sensing margin (U margin + P margin).

[0006] Figure 2 This is a graph showing the margin scan of memory signals from memory cells in an F-RAM array. It illustrates the statistical variations of the P-term voltage and U-term voltage (bit line voltage) of different cells in the array of cells in the NVM and their impact on the overall sensing margin of the NVM. (Refer to...) Figure 2 It can be seen that a global V applied to all or more cells (e.g., an array of 1T1C F-RAM cells) of the device via a reference bit line (Ref.BL) is used. REF One problem with conventional NVM devices using single-ended sensing is the statistical variation in the P and U terms of each cell. Figure 2 In the diagram, each black dot between 0 and approximately 55 millivolts (mV) represents an unprogrammed term or U term for a cell. The U margin 202 of an NVM device represents V. REF The voltage difference between the highest or worst-case U term (U0) of one or more cells in the NVM device. Similarly, each black dot between approximately 180 and 200 mV represents a programmed term or P term of a cell. The P margin 204 of the NVM device represents V. REF The voltage difference between the lowest or worst-case P term (P0) of the cell in the NVM device. These statistical variations are particularly problematic for the P margin, as holding losses and other time-related factors are observed to cause the P term to degrade more than the U term (P0 shifts downward).

[0007] Another problem with memory devices using 1T1C cells in an F-RAM array stems from the temperature dependence of the P and U terms. Figure 3 This is a graph showing the temperature correlation between the P and U terms of a memory cell, where V REF It is set to be 21mV higher than the worst-case U term (U0), or approximately 83mV. (See reference...) Figure 3 We can see that the P margin (the worst-case P term (P0302)) is related to V. REF The difference between the two values ​​decreases as the temperature of the NVM device increases. For example, at 0°C, the NVM device has a P margin of approximately 57 mV, while at approximately 125°C, the P margin drops to approximately 22 mV. This temperature dependence is exacerbated by time-dependent degradation, where the temperature-dependent P0 transitions from an initially higher voltage to a lower voltage over the lifetime of the NVM device. This time-dependent degradation at a specific temperature... Figure 3 The value is represented by vertical bar 302. For example, during the lifetime of an NVM device, P0 302 at 0°C can decrease from a high value of approximately 155 mV to approximately 128 mV, or from a P margin of approximately 72 mV to approximately 45 mV. This time-related degradation, coupled with temperature dependence, can cause the P margin to practically become zero at higher operating temperatures, leading to premature end of lifetime. When P0 302 at the highest expected operating temperature is compared with V... REF End of lifetime occurs when there is no longer sufficient P margin to reliably determine the state of a memory cell through read operations.

[0008] Refer again Figure 3 It is noted that the worst-case or highest U term (U0 306) is also affected by temperature-dependent and time-dependent degradation. However, it has been observed that these two factors result in less degradation of the U term (U0 306) than that of the P term (P0 302).

[0009] Finally, it will be understood that since the range of P and U terms for each unit is a result of statistical variation, and since larger observed variations are expected for larger arrays, it is therefore necessary to apply a single global V term to the entire array. REF Then, the worst-case margin of the memory cell reduction will limit the size of the array.

[0010] Therefore, there is a need for memory devices and their operation methods that include arrays of 1T1C NVM cells to optimize V REF The margin between the P and U terms allows the memory device to have larger arrays, improved reliability and yield, and extended device lifespan. Summary of the Invention

[0011] A memory device or memory system and its operation method are disclosed. The memory device or memory system includes an array of cells divided into segments or blocks and a reference voltage generator capable of providing local reference voltages for reading different blocks. Typically, in addition to the reference voltage generator and the array of non-volatile memory (NVM) cells divided into multiple blocks, the device also includes sensing circuitry coupled to the array to receive memory signals from the array and compare the memory signals with local reference voltages to read data from the cells. The reference voltage generator is configured to provide one of a plurality of reference voltages to the sensing circuitry based on which block is being read. The NVM cells are arranged in multiple rows and multiple columns, with each row sharing word lines and board lines, each column sharing bit lines, and the array is logically divided into multiple blocks based on the row and column addresses of the NVM cells in each block. The reference voltage generator is configured to provide one of a plurality of reference voltages to the sensing circuitry based on the row and column addresses of the NVM cells in the multiple blocks.

[0012] A method for operating a memory device is also disclosed, the memory device including an array of memory cells divided into multiple blocks and a reference voltage generator capable of providing an optimized local reference voltage to each block. Typically, the method begins by logically dividing the array of memory cells in the memory device into multiple blocks based on the row and column addresses of the cells in each block. Next, multiple margin scans are performed for each block to determine an optimized local reference voltage for each block. A reference reference voltage for the array and an adjusted reference voltage for each block are determined based on the local reference voltage of each block; the adjusted reference voltage is a voltage that can offset the reference reference to provide the local reference voltage for each block. The adjusted reference voltage for each block is stored in a lookup table coupled to the memory device or the reference voltage generator. During a read operation of a memory cell in one of the blocks, a final or local reference voltage is generated by looking up the adjusted reference voltage of that block and combining it with the reference reference voltage; this final or local reference voltage is substantially equal to the optimized local reference voltage of that block. This local reference voltage is applied to a reference bit line input of a sense amplifier coupled to the bit line of the memory cell being read.

[0013] The reference voltage generator and method of this disclosure are particularly useful when the array comprises single-transistor single-capacitor (1T1C) ferroelectric random access memory (F-RAM) cells, and a reference voltage for reading one of the blocks is selected based on the lowest P term (P0) or the highest U term (U0) of the F-RAM cell in the block being read. Attached Figure Description

[0014] Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, in which corresponding reference numerals indicate corresponding parts. Furthermore, the accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the invention and, together with the description, further serve to explain the principles of the invention and enable those skilled in the art to implement and use the invention.

[0015] Figure 1 This is a schematic diagram of a single-transistor single-capacitor (1T1C) ferroelectric random access memory (F-RAM) cell;

[0016] Figure 2 It is a graph showing the margin scan of memory signals from memory cells in an F-RAM array, which shows the statistical changes of the P and U terms and their impact on the overall sensing margin;

[0017] Figure 3 It is a graph showing the temperature-dependent and time-dependent degradation of the P and U terms of memory cells in an F-RAM array;

[0018] Figure 4 It is a block diagram of a system including a memory array and an address-dependent local reference voltage generator;

[0019] Figure 5 It is a block diagram of a memory array divided into multiple blocks for generating address-dependent reference voltages;

[0020] Figure 6A , Figure 6B and Figure 6C It shows that the reference V is included. REF Generation circuit and instantaneous adjustment V REF Schematic diagram and block diagram of the reference voltage generator for the circuit;

[0021] Figure 7 This is a schematic diagram of the sensing circuit and switches that couple the local reference voltage generator in Figure 6 to the memory array in the system.

[0022] Figure 8 Is to Figure 6A , Figure 6B and Figure 6C Timing diagram of the signal of the local reference voltage generator;

[0023] Figure 9A and Figure 9B It is used to retrieve V from a lookup table stored in the monitoring memory based on the memory address. REF A schematic diagram of the local reference voltage selection circuit system for the regulation value;

[0024] Figure 10This is a flowchart of a method for determining a reference voltage and an adjustment voltage for a memory device or system comprising multiple blocks and using address-dependent local reference voltages, and for operating the memory device or system.

[0025] Figure 11A and Figure 11B It is a graph showing the memory margin results for a memory system operating using a single global reference voltage;

[0026] Figure 12A and Figure 12B It is a graph showing the memory margin results for a memory system operating using address-dependent local reference voltages;

[0027] Figure 13 It is used for using local V REF A flowchart illustrating the segmented repair (LVS) method for repairing faulty bits in a memory device; and

[0028] Figure 14 The diagram shows the P-margin of an unrepaired memory device, the same memory device repaired using the global repair method, and a memory device repaired using the LVS repair method. Detailed Implementation

[0029] A memory device or system is provided, comprising an array of cells divided into segments or blocks and a reference voltage generator capable of providing local reference voltages for reading different blocks, as well as a method for operating the memory device or system. This memory device and method improve yield, reliability, and extend the device's operating life and temperature range, and are particularly useful in or in conjunction with single-ended sensing non-volatile memory (NVM) such as 1T1C ferroelectric random access memory (F-RAM).

[0030] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without these specific details. In other instances, well-known structures and techniques have not been shown in detail or illustrated in block diagram form in order to avoid unnecessarily obscuring the understanding of this specification.

[0031] The reference to "one embodiment" or "implementation" in this specification means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing in different places in the specification does not necessarily refer to the same embodiment. The term "coupled" as used herein can include both a direct electrical connection of two or more components or elements and an indirect connection of two or more components or elements via one or more intermediate components.

[0032] In short, the memory device includes an array of non-volatile memory (NVM) cells divided into multiple blocks, and sensing circuitry coupled to the array to receive memory signals from the array and compare the memory signals with a reference voltage to read data from the NVM cells. The memory device also includes a reference voltage generator, or the memory device is coupled to a reference voltage generator to provide a reference voltage to the sensing circuitry. The reference voltage generator is configured to provide one of multiple reference voltages to the sensing circuitry based on which block is being read. The block being read can be identified by one or more addresses of the NVM cells(s) being read.

[0033] Figure 4 This diagram shows a memory device 402 and an address-dependent local reference voltage (V). REF A block diagram of a system 400 with generator 408, the memory device 402 having a memory array 404 divided into multiple segments or blocks 406. (Refer to...) Figure 4 In the illustrated embodiment, the memory device 402 further includes a plurality of sensing circuits 410 coupled between the memory array 404 and the local reference voltage generator 408. The sensing circuits 410 receive address-related local reference voltages from the local reference voltage generator 408, determine the binary or logical state (i.e., programmed or erased) of the memory cells in the block 406 being read, and output the read data via an interface or data path 412. In one embodiment, the memory array 404 may include 1T1C FRAM cells, wherein the P-term voltage or U-term voltage of the FRAM cells is compared with the local reference voltage provided by the local reference voltage generator 408 to determine their binary state (whether programmed with logic 1). In other embodiments, the memory device may include other types of NVM cells employing a single-ended sensing configuration, such as charge-trapped silicon-oxide-nitride-oxide-silicon (SONOS) cells, floating-gate cells, R-RAM cells, M-RAM cells, etc.

[0034] System 400 also includes a reference voltage selection circuitry 414 for operating or controlling the local reference voltage generator 408 to provide an address-dependent reference voltage optimized for the block 406 being read. In the illustrated embodiment, this circuitry includes a configuration circuitry 416 to provide a reference voltage (V0) to the local reference voltage generator 408. REF The settings are common or substantially the same for all blocks 406 in the memory array 404, and these circuits include digital control circuitry 418 to provide an regulated reference V to the local reference voltage generator. REF Adjust V REF The configuration enables the local reference voltage generator 408 to generate an regulated reference voltage in a manner described in more detail below, which is combined with a reference reference voltage or used to offset the reference reference voltage to generate an address-dependent reference voltage optimized for the specific block 406 being read.

[0035] Typically, as shown in the embodiment, system 400 also includes an address buffer 420 coupled to digital control circuitry 418 and a non-volatile monitoring memory 422. The address buffer 420 receives the address of the NVM cell being read and transmits it to digital control circuitry 418 so that digital control circuitry can identify the block 406 being read (the location of the requested NVM cell). Monitoring memory 422 includes one or more lookup tables that store information used by digital control circuitry 418 to generate adjustment reference voltage settings.

[0036] Although Figure 4 The circuitry and components of system 400 described above are shown as separate blocks, but it will be understood that each of these circuitry and components, including memory device 402, may be integrally formed on a single semiconductor substrate or chip, or packaged in a single multi-chip package, together with other components of the memory device or system not shown, and the system may be synonymous with the memory device.

[0037] Now refer to Figure 5 Up to Figure 9 Figure 4 The circuitry and components of System 400 and their operation are described in more detail.

[0038] Figure 5This is a block diagram of a memory array 500 divided into multiple segments or blocks 502 for which address-dependent reference voltages are provided. Each segment or block 502 may be addressed by column address decoders and row address decoders (not shown) in the memory device and identified or defined by the range of column and row addresses of memory cells in the memory array 500. For example, the memory array 500 may include a 4Mb memory array divided into sixteen (16) 256Kb subarrays 504, each subarray including one or more blocks 502. A margin scan is performed on each block 502, and an optimized local reference voltage is determined individually for each block. Based on these local reference voltages, a reference reference voltage is determined for the entire memory array 500 or all blocks 502 in the memory array 500, and an appropriate regulated reference voltage is determined for each block 502.

[0039] Alternatively or alternatively, the memory array 500 may be physically (instead of logically) divided into a plurality of physically separate blocks 502, wherein each individual block is provided with a local reference voltage from one of a plurality of local reference voltage generators coupled to one or a few separate smaller blocks 502.

[0040] Now refer to Figures 6A to 6C The implementation of the reference voltage generator is described in more detail. Figure 6A This is a detailed schematic diagram of a portion of an implementation of a reference voltage generator, which includes a reference voltage (V). REF Generator or generation circuit 602 and instantaneous adjustment V REF Generation circuit 604. Typically, the reference voltage generator includes an array of metal-oxide-semiconductor (MOS) capacitors arranged in binary groups. Each binary group is coupled via multiple first MOS switches 606 to a positive voltage supply or voltage source (Vdd) and a negative supply voltage (Vss) or ground to precharge the capacitors, and is coupled via multiple second MOS switches 608 to a distribution bus 618 to share the reference voltage V. REF The capacitor in circuit 602 generates charge to generate a reference voltage. REF Generation circuit 602 and adjustment V REF The generation circuit 604 is divided among the components. The total number of capacitors will depend on the values ​​of Vdd and Vss, and the amount of incremental voltage between Vdd and Vss selected for the potential reference voltage. Similarly, the reference V... REF Generation circuit 602 and adjustment V REF The number of capacitors included in the generation circuit 604 will depend on the number of incremental voltages between Vdd and Vss selected for the adjustment reference voltage.

[0041] In the illustrated embodiment, reference VREF The generation circuit 602 includes a first array of 225 metal-oxide-semiconductor (MOS) capacitors 603 arranged in binary groups. That is, there is a single capacitor (X1), and there are groups of 2 capacitors (X2), second groups of 4 capacitors (X4), and so on, where the number of capacitors in each consecutive group is doubled. An exception to this arrangement is that the largest set or group (X113) has 113 capacitors instead of 128, with the remaining capacitors included in the adjustment V. REF In the second array of 15 capacitors 605 in the generation circuit 604, for address-related adjustment of the reference voltage as described below.

[0042] Input signals pVdd[0:7] and pVss[0:7] control the reference V REF Switch 606 in generation circuit 602 precharges the capacitor set to Vdd or Vss respectively. The binary arrangement of the MOS capacitors allows for a reference V based on the pVdd[0:7] and pVss[0:7] signals. REF The settings are used to incrementally control the capacitors in steps ranging from 1 to 255. The pVdd[0:7] and pVss[0:7] signals are, for example... Figure 6B The first logic circuit 610 shown and included in the reference voltage generator generates the voltage. (Refer to...) Figure 6B The precharge signal (prch) is provided to the first input of the first AND gate 612 and the second AND gate 614. Next, from the configuration circuit ( Figure 4 The configuration circuit 416 in the middle provides a reference V to the second input terminal of the first AND gate 612. REF A setting signal is provided to the second input terminal of the second AND gate 614 via the first inverter 616, and a reference V is supplied. REF Set signals to generate pVdd[0:7] and pVss[0:7] signals respectively. Although in Figure 6B Only one first logic circuit 610 is shown, but it should be understood that the reference voltage generator includes multiple logic circuits, each for each group of MOS capacitors X1 to X113.

[0043] One advantage of the reference voltage generator design is that it requires some time to reliably precharge the capacitor to Vdd or Vss and prepare it for the next memory cycle. Therefore, the pVdd[0:7] and pVss[0:7] signals cannot be set instantaneously based on the incoming address. In the design shown, these input settings (pVdd[0:7] and pVss[0:7]) are set such that the reference V REFThe generation circuit 602 provides a common or reference voltage for all blocks in the memory array. After the pre-charge step, the reference voltage V is provided by closing switch 608, which is controlled by the share signal. REF All capacitors in the generation circuit 602 are connected to each other (with charge sharing) and connected to the distribution bus 618 outside the reference voltage generator.

[0044] Adjust V REF The generation circuit 604 includes a second array or block of 15 capacitors in two sets, grouped in binary: X1, X2, X4, and X8. These sets or groups of capacitors are pre-charged via a switch 620 controlled by a pre-charge signal (prch). All capacitors in the first set of 15 are pre-charged to Vdd, and all capacitors in the second set are pre-charged to Vss. After the pre-charge step, a switch 622, selectively controlled by the sVdd[0:3] and sVss[0:3] input signals, shares selected groups from these sets of 15 capacitors onto a distribution bus 618. The sVdd[0:3] and sVss[0:3] signals are controlled by a generator such as a reference voltage generator. Figure 6C The second logic circuit 624 shown is generated. (Refer to...) Figure 6C Used to convert the reference V REF The capacitor in generation circuit 602 is coupled to the same share signal of distribution bus 618, which is applied to the first input of third AND gate 626. Next, the adjustment V provided by digital control circuit 418... REF The setting signal is applied to the second input of the third AND gate 626 to generate the sVdd[0:3] signal, and then the second inverter 628 generates the sVss[0:3] signal. Furthermore, although in Figure 6C Only one second logic circuit 624 is shown, but it should be understood that the reference voltage generator includes multiple second logic circuits to generate signals sVdd[0] to sVdd[3] and signals sVss[0] to sVss[3].

[0045] A key feature of this design is that the sVdd[0:3] and sVss[0:3] signals can be changed instantly based on the incoming address, because there is a complete set of 15 capacitors pre-charged to Vdd and Vss, thus ready to be selectively shared to the power distribution bus 618 without delay.

[0046] Figure 7 It shows the method used to... Figures 6A to 6C A schematic diagram of a circuit in which a local reference voltage generator is coupled to a sensing circuit and then coupled to a bit line (BL) in a memory array. (Refer to...) Figure 7Circuit 700 includes a first MOS switch 702 and a second MOS switch 706. A distribution bus 618 from the reference voltage generator is coupled to a bus capacitor 704 via the first MOS switch 702. The bus capacitor is coupled to a cascading capacitor 708 in the sensing circuit 710 via the second MOS switch 706. When a share-to-bus signal is applied to or activated by the first MOS switch 702 and the second MOS switch 706, the charge generated on the capacitor array of the reference voltage generator is shared onto the cascading capacitor 708. The sensing circuit 710 also includes a third switch 712 coupled between the cascading capacitor 708 and a comparator or sensing amplifier (sensing amplifier 714). When a share-to-ref-BL signal is activated, and typically after the share-to-bus signal is deactivated, an address-dependent local reference voltage generated by the charge shared onto the cascading capacitor 708 is applied to the reference bit line (BL) input of the sensing amplifier 714. It should be understood that... Figure 7 The components shown on the left, namely the first MOS switch 702, the second MOS switch 706, and the bus capacitor 704, can be included in the local reference voltage generator or sensing circuit 710.

[0047] although Figure 7 Only one sensing circuit 710 is shown, but it will be understood that memory devices or systems (not shown) typically include multiple sensing circuits from 1 to x, where x is equal to the number of bit lines (BLs) in each block of the memory array to be read.

[0048] Now refer to Figures 6A to 6C and Figure 7 as well as Figure 8 This describes the operation of an implementation of a local reference voltage generator for generating address-dependent local reference voltages. Figure 8 It shows Figures 6A to 6C and Figure 7 The timing diagram of the signal is shown. (Refer to...) Figure 8 The operation begins from t0 to t1 by placing the precharge signal (prch 802) in an active state to regulate V. REF The capacitor in generation circuit 604 is pre-charged. During this period, the reference V... REF Setting or signal (reference V) REF [0:7]804) is static and coupled to logic circuit 610 along with the pre-charge signal to generate signals pVdd[0:7] and pVss[0:7] to the reference V REFThe capacitor in generation circuit 602 is pre-charged. At time t1, the pre-charge signal is set to an invalid state, and between times t1 and t2, V is adjusted based on the address in the block being read. REF Settings (Adjust V) REF [0:3]806) is coupled to the second logic circuit 624 to prepare for selectively adjusting V REF Multiple capacitors in generation circuit 604 share a distribution bus 618. At time t2, the share signal 808 is activated, thereby closing the second switch 608 to set the reference V. REF The charge on the capacitor in generation circuit 602 is shared to distribution bus 618. Almost simultaneously, the share signal applied to the third AND gate 626 in the second logic circuit 624 generates signals sVdd[0:3] and sVss[0:3] to close switch 622, thereby adjusting V REF The charge on the selected capacitor in generation circuit 604 is shared to distribution bus 618. At time t3, the share signal is deactivated, thereby opening switches 608 and 622. From time t4 to time t5, the share-to-bus signal 810 is activated, thereby closing the first switch 702 and the second switch 706, and allowing the charge generated on the capacitor array of the reference voltage generator to be shared to the graded capacitor 708. From time t6 to time t7, the share-to-ref-BL signal 812 is activated, thereby enabling the address-dependent local reference voltage generated by the charge shared to the graded capacitor 708 to be applied to the reference BL input of the sense amplifier 714.

[0049] Now refer to Figure 9A and Figure 9B The schematic diagram is used with or included in the reference voltage selection circuit system 414 to retrieve V from a lookup table based on a memory address. REF A local reference voltage selection circuit system that adjusts the reference voltage in real time or fine-tunes it. (Refer to...) Figure 9AThe selection circuit system 900 receives an adjustment signal 902 as a vector, which contains the adjustment values ​​previously determined for each segment or block of the memory array. Each segment is adjusted using the same number of bits. The vector signal is a concatenation of all adjustment values ​​in the order in which the segment addresses appear in the memory array. The adjustment signal or adjustment vector is coupled to an even-numbered adjustment value lookup table 904 and an odd-numbered adjustment value lookup table 906. The even-numbered adjustment value lookup table 904 stores only a selected subset of the vector for segments whose segment addresses are even. The odd-numbered adjustment value lookup table 906 is a selected subset of the vector used only for segments whose segment addresses are odd. The live_segment_addr signal 908 is received as a vector containing the addresses of the segments being actively accessed. The live_segment_addr signal 908 is only updated when a transaction starts and when a burst transaction crosses the address boundaries between segments. The live_segment_addr signal 908 remains static at the end of a transaction unless it is reset and cleared. The bufer_segment_addr signal 910 is received as a vector signal containing the address of a segment that has not yet been initiated and may not yet be a complete value, because the address is still being transmitted from the address source to the selection circuitry system 900. However, once the selection circuitry system has received the complete value, it is always available and remains static. The first multiplexer 912 is based on... Figure 9B A portion of the selection circuit system shown receives the live_select signal 914, selects between live_segment_addr and buffer_segment_addr, and outputs the selected address. As the burst progresses, the burst transaction naturally increments the address during the data phase. To facilitate burst transactions, the selection circuit system 900 includes an increment / decrement block 916 to calculate the subsequent address of the currently selected address based on the state of the received cr_decrement signal 918. When in an active state, the cr_decrement signal 918 indicates that the subsequent address should be a decrement operation starting from the current address within the burst transaction. The increment / decrement block 916 provides the subsequent address to a second multiplexer 920 coupled to an even-adjustment value lookup table 904 and a third multiplexer 922 coupled to an odd-adjustment value lookup table 906.

[0050] The least significant bit (LSb) of the currently selected address determines whether the segment is considered even or odd. LSb serves as a selector for the second multiplexer 920 and the third multiplexer 922. When LSb is 0, the second multiplexer 920, coupled to the even adjustment lookup table 904, selects the current address and provides the selected address with its LSb truncated as an index to the even adjustment lookup table. When LSb is 1, the second multiplexer 920, coupled to the even adjustment lookup table 904, selects the subsequent address and provides the selected address with its LSb truncated as an index to the even adjustment lookup table 904. The lookup result is provided on the even_Vref vector signal 924. When LSb is 0, the third multiplexer 922, coupled to the odd adjustment value lookup table 906, selects the subsequent address and provides the selected address with its LSb truncated as an index to the odd adjustment value lookup table 906. When LSb is 1, the third multiplexer 922, coupled to the odd adjustment value lookup table 906, is selected, and the selected address with LSb truncated is provided as an index to the odd adjustment value lookup table 906. The lookup result is provided on the odd_Vref vector signal 926.

[0051] The state of the live_select signal 914 is determined by Figure 9B The selection circuit system shown is determined. (Refer to...) Figure 9BThe test_scan_mode signal 928 selects the operating mode for the selection circuit system 900. When the test_scan_mode signal 928 is 1, the mode is test scan mode, in which all flip-flops 930, 932 operate using a synchronous clock signal, and operation of all other elements in the functional path is not expected. When the test_scan_mode signal 928 is 0, the selection circuit system 900 is in operating mode, and the clock signal to the flip-flops 930, 932 can be asynchronous. The first multiplexer 934 selects the clock signal to be passed to the flip-flops 930, 932 and other elements based on the test_scan_mode signal 928. When the test_scan_mode signal 928 is 1, the first multiplexer 934 passes the synchronous clk_tc_ms_tile clock signal 936, where the effective edge of the clock signal is a falling edge. When the test_scan_mode signal 928 is 0, the signal passed through the first multiplexer 934 is the result of a logical NOR 938 of the valid read strobe signals (tc_ms_rd_strb_b1 clock signal 940 and tc_ms_rd_strb_b0 clock signal 942), which indicates the start of the macro read operation. The output of the first multiplexer 934 is passed through an inverter 944 to the clock gate unit (scan_gater 946) enabled by the test_scan_mode signal 928. The output from scan_gater 946 is inverted by an inverter 948 and provided to the scan control / observation flip-flop 930, and the flip-flop is toggled only when the selection circuit system 900 is operating in scan mode.

[0052] Local V REFThe lookup operation is enabled by the local_vref_en signal 950, a control signal provided to generate the live_select signal 914 via the clock signal enabled to the live_select flip-flop 932 through the clock gate unit (rd_gater 952). The rd_gater 952 receives the inverted clock signal passed through the first multiplexer 934. The output of the rd_gater 952 is then inverted by the inverter 954, such that the phase of the output matches the phase of the clock passed through the first multiplexer 934, and the clock to the live_select flip-flop 932 is inverted only when the local_vref_en signal 950 is 1. During the rising edge of the tc_ms_rd_strb_b1 signal 940 or the rising edge of the tc_ms_rd_strb_b0 signal 942, when the local_vref_enable signal 950 is 1, the Q output of the flip-flop 930 operated by the inverter 955 will cause the flip-flop 932 to capture data at its D input, thereby indicating on the live_select signal 914 that the address to be used at this time is the live_segment_address signal 908.

[0053] When a new transaction begins, it is either a read transaction or not; if it is a read transaction, it includes or excludes the address phase. When the current transaction is a read transaction that does not include the address phase, the expected address is address zero, and the tc_ms_opc_rcont signal 956 is received as a pulse lasting one clock cycle, indicating that it will... Figure 9A The starting address, which is zero, is found on the buffer_segment_addr signal 910. When the current transaction is a read transaction that includes an address phase, the tc_ms_addr_ld1 signal 958, which is received as a pulse lasting one clock cycle, indicates that the starting address of the transaction will be found on the buffer_segment_addr signal 910. When the new transaction is not a read transaction, neither the tc_ms_opc_rcont signal 956 nor the tc_ms_addr_ld1 signal 958 are set to an active state, and the starting address of the transaction will be found on the live_segment_addr signal 908.

[0054] The tc_ms_opc_rcont signal 956 and the tc_ms_addr_ld1 signal 958 are combined in a logical OR operation via an OR gate 960 to generate the return_to_buf_adr signal. This return_to_buf_adr signal is inverted by an inverter 962 and combined with a low-active reset signal (rst_tc_ms_tile_n 964) in an AND gate 966. If either the tc_ms_opc_rcont signal 956 or the tc_ms_addr_ld1 signal 958 is received, the resulting logical AND input is fed to a second multiplexer 968, and when selected, the live_select trigger 932 is cleared or reset. The output from the AND gate 966 is also combined with the output from the OR gate 938 in an XOR gate 970 to provide data input to the scan control / observation trigger 930. The data input to the scan control / observation trigger 930 can be logically represented as follows: ((not (return_to_buf_adr)) XOR (tc_ms_rd_strb_b0 or not tc_ms_rd_strb_b1)). As a result, when 900 operates in scan mode, a fixed fault can be observed on any signal used as an input to this circuit. The reset state of the output of the scan control / observation trigger 930 is 0, and when the test_scan_mode signal 928 is 0, the default state of the D input to the live_select trigger 932 (coupled from the Q output of the trigger 930 operated via inverter 955) is 1. When the test_reset_control signal 972 is in an active state, it forces any subsequent low-active reset signals into their high-inactive state. When test_scan_mode is 1, the second multiplexer 968 selects a logical OR of test_reset_control and rst_tc_ms_tile_n 964. When test_scan_mode 928 is 0, the second multiplexer 968 selects a logical AND of rst_tc_ms_tile_n 964 and NOT (return_to_buf_adr) . The output of the second multiplexer 968 is called rst_local_async_n. It provides a low-active reset signal to the live_select flip-flop 932.

[0055] Now refer to Figure 10 The flowchart describes a method for determining a reference voltage and an adjustment voltage, and for operating a memory device or system that uses an address-dependent local reference voltage. (Refer to...) Figure 10Typically, this method begins by dividing an array of memory cells in a memory device into multiple blocks based on the row and column addresses of the cells in each block (1002). As described above, this can include dividing the array logically or physically, such that each individual block is provided with an optimized local reference voltage from one of a plurality of local reference voltage generators coupled to one or a few blocks in a larger memory array. The partitioning can also include logically or physically dividing the larger memory array into multiple subarrays, each comprising one or more blocks.

[0056] Next, multiple margin scans are performed for each block, and an optimized local reference voltage (1004) is determined for each block. The local reference voltage is a voltage that provides a predetermined or predefined minimum margin (U-margin) between the local reference voltage and the highest erased term or U-term in the block. As mentioned above, because erased terms or U-terms are generally less affected by statistical variations and are observed to be more stable with time and temperature, the predefined minimum margin is usually chosen to be substantially less than the margin (P-margin) between the local reference voltage and the lowest programmed term or P-term in the block.

[0057] Margin scan refers to scanning or monotonically increasing or decreasing the reference voltage applied to the memory array or block and repeatedly reading memory cells to determine the bit line signal or voltage by reading programming terms (P terms) and erase terms (U terms). As mentioned above, due to process, voltage, and temperature variations, there are expected statistical variations in the bit line signals obtained by reading different memory cells. In particular, in F-RAM, there are expected statistical variations in the P and U terms due to variations in the size and dielectric constant of the ferroelectric layer in the ferroelectric capacitor.

[0058] To perform a margin scan, the entire array or block is written to a P-term (internal 1), and then the memory is read using a reference voltage set low (below the minimum expected statistical change of the P-term). At this reference voltage, there should be a 100% pass rate, meaning all cells should be correctly read as programmed or P-terms. The reference voltage is gradually increased, and the write and read operations are repeated. At some point, the reference voltage will be higher than the lowest P-term (P0) in the block, and the associated memory cell will fail, meaning it will be incorrectly read as an erased or U-term. As the reference voltage increases, more and more programmed cells will be incorrectly read as erased, i.e., read failures occur (as predicted by the statistical change). A graph can be created showing the P-term bit failure count according to the scan reference voltage. After a predetermined number of increments, or after all or substantially all p-items have failed, this process is repeated by writing the erased or U-items to the entire array or block, scanning the reference voltage from an initial high voltage (above the maximum expected statistical change of the U-items) to a lower voltage, and forming a graph of U-item bit failure counts based on the reference voltage. These two graphs can be as shown above. Figure 2 The combinations are shown below. The interval between the lowest P term (P0) and a specific reference voltage represents the P margin of that reference voltage. The interval between the highest U term (U0) and the reference voltage represents the U margin.

[0059] Then, a reference reference voltage for the entire array is determined based on the local reference voltage found for each block in the previous step, and an adjustment reference voltage offset from the reference reference voltage is determined for each block (1006). In one embodiment, the reference reference voltage is determined or selected by setting the reference reference voltage to a predetermined or predefined amount from the highest internal "0" or U term in the entire array. The adjustment reference voltage can then be determined by calculating a voltage that, for each block, must be used to adjust the reference reference voltage to achieve or obtain a local reference voltage based on that block. This will result in a constant or near-constant margin (U margin) between the address-dependent final or local reference voltage and the highest internal "0" or U term in each block across the entire array. Furthermore, since the margin is substantially lower than the margin (P margin) between the local reference voltage and the lowest programmed term or P term in each block, the P margin will also be maximized.

[0060] Then, the regulated reference voltage for each block is stored in a lookup table in a monitoring memory coupled to the reference voltage generator (1008). Next, during a read operation of a memory cell in one of the blocks, a final or local reference voltage is generated by generating a reference reference voltage, looking up the regulated reference voltage of the block being read, and generating the regulated reference voltage and combining it with the reference reference voltage (1010). Finally, the local reference voltage is coupled to or applied to a reference bit line of a sense amplifier coupled to the bit line of the memory cell being read (1012).

[0061] Now refer to Figure 11A and Figure 11B as well as Figure 12A and Figure 12B The improvement in memory margin of memory devices or systems that operate using address-dependent local reference voltages compared to conventional memory systems that operate using a single global reference voltage is described.

[0062] Figure 11A and Figure 11B This is a graph illustrating the memory margin results for a memory device comprising a 4Mb F-RAM array divided into sixteen 256Kb blocks and operating normally using a single global reference voltage. (See also...) Figure 11A The diagram illustrates curve 1102 for the lowest P-term (P0), curve 1104 for the highest U-term (U0), and a single global reference voltage 1106 used for reading from all blocks in the array for each block. The global reference voltage is selected in a conventional manner by choosing it as a fixed offset from either the highest U-term (U0) or the lowest P-term (P0) in the array. In this example, the global reference voltage is selected with a fixed offset of 19 mV from the highest U-term, as shown in block 10. Figure 11B The resulting P-margin and U-margin are shown for each block in a memory device operating normally using a single global reference voltage 1106. (Refer to...) Figure 11B Line 1108 represents the P-margin, and line 1110 represents the U-margin. The obtained minimum P-margin, minimum U-margin, maximum P-margin, maximum U-margin, average P-margin, and average U-margin are shown in Table 1 below. Note that operation using a single global reference voltage results in a P-margin as low as 18mV, which is problematic and may lead to bit faults or read faults under elevated temperatures, and may also shorten the operating life of the memory device.

[0063] Table 1

[0064] P margin U margin Minimum 18 mV 19mV maximum 53mV 40mV average 36mV 31mV

[0065] Figure 12A and Figure 12BThis is a graph showing the memory margin results for the same memory device operating using address-dependent local reference voltages as described herein. Figure 12A The curves for the lowest P-term (P0) 1202, the highest U-term (U0) 1204, and the sixteen (16) address-related local reference voltages 1206 for each block in the array are shown. As described above, the address-related local reference voltages 1206 are determined using the method described above. That is, the reference reference voltage is determined by setting it at a predefined offset from the highest U-term (U0) in the array (i.e., 19 mV higher than U0 of block 10), thereby determining the adjustment reference voltage for each of the 16 segments or blocks and generating a local reference voltage for each of the 16 segments or blocks. Figure 12B The resulting P-margin 1208 and U-margin 1210 on each block of a memory device operating using an address-dependent local reference voltage are shown. The resulting minimum P-margin and minimum U-margin, maximum P-margin and maximum U-margin, and average P-margin and average U-margin are shown in Table 2 below. Note that the address-dependent local reference voltage results in a substantially constant U-margin across all segments or blocks. It should also be noted that operating using an address-dependent local reference voltage results in a 63% increase in the minimum P-margin and a 33% increase in the average P-margin.

[0066] Table 2

[0067] P margin U margin Minimum 31 mV 19mV maximum 65mV 19mV average 48mV 19mV

[0068] On the other hand, local V was disclosed. REF The segmented level slicing (LVS) repair method is used to repair fault bits in memory devices that have an array of NVM cells divided into multiple blocks and include a local reference voltage generator.

[0069] In conventional global repair methods, the bit or memory cell with the lowest programming term or P term among all memory cells in the array is replaced by a previously unused spare bit or memory cell in the array or manufactured with the array on the die or chip. In short, repair and replacement are typically accomplished before die packaging by disconnecting links to decouple the memory cell to be replaced from the word lines, board lines, and bit lines in the array. This is done by updating the row and column decoders in the memory device so that the bit addressing the faulty memory cell points to a spare memory cell, which is then coupled into the array to replace the faulty memory cell. This spare memory cell, typically configured to be coupled to one or more of the same word lines, board lines, and bit lines as the memory cell being replaced.

[0070] Global repair methods are satisfactory for memory devices with a single large array and / or using a single global reference. However, in memory devices comprising arrays of 1T1C cells divided into multiple blocks and using, for example, the local reference voltage generator described above, the margin between the least significant programming term or P margin is determined by the least significant programming term or P0 in the block or segment, and the local V related to the address. REF The difference between them determines the value. Therefore, the lowest programming term or P0 in the entire array does not necessarily mean that the associated cell or bit has the lowest P margin, because for all local blocks or segments, the local V... REF They are not the same. Therefore, using a global repair method and a local reference voltage generator in a memory device comprising multiple blocks will result in over-repair for some segments with lower reference voltages and over-repair for segments with higher local reference voltages. REF Some sections lack sufficient repair.

[0071] In contrast, the LVS repair method only repairs bits with the lowest programming term or P term (P0) within blocks or segments where the programming term or P margin is below a predefined value. Therefore, by using the LVS repair method, over-repair of strong segments is avoided, under-repair of weak segments is avoided, and the programming term or P margin of the die is maximized.

[0072] Figure 13 This is a flowchart illustrating an implementation of an LVS repair method for repairing faulty bits in a memory device comprising an array of 1T1C NVM cells divided into multiple blocks, and further comprising a local reference voltage generator as described above. (Refer to...) Figure 13 Typically, this method begins by dividing the array of memory cells in the memory device into multiple blocks based on the row and column addresses of the cells in each block (1302). Multiple margin scans are performed on each block, and an optimized local reference voltage is determined for each block (1304). Next, blocks in the block with a margin between the memory cell having the lowest programming term or P0 and the local reference voltage that is lower than a predefined minimum are identified (1306). Then, the block is repaired by decoupling the memory cell having the lowest programming term or P0 in the identified block with a margin lower than the predetermined minimum, and replacing the memory cell with a spare memory cell in that block (1308).

[0073] Now refer to Figure 14 The diagrams shown illustrate the advantages and improvements of the LVS repair method for repairing fault bits in memory devices with arrays of 1T1C cells divided into multiple blocks, compared to conventional global repair methods. Figure 14The chart shows the P-margin of an unrepaired memory device, the same memory device repaired using the 40-bit global repair method, and a memory device repaired using the LVS repair method. Figure 14 The data in the charts shown was obtained using a 4Mb F-RAM array, divided into 16 256Kb segments or blocks, and operated using 16 address-dependent local reference voltages. Bits or memory cells with faulty P-items were then repaired first using a global repair method and an LVS repair method. In both cases, a 3-bit global replacement was used to repair bits with faulty U-items. (Refer to...) Figure 14 Line 1402 shows the P-margin for each block or block of the unrepaired memory device. Line 1404 shows the P-margin for each block or block of the same memory device repaired using the global repair method, and line 1406 shows the P-margin for each block or block of the memory device repaired using the LVS repair method. The average P-margin, minimum P-margin, maximum P-margin, and margin of the resulting memory devices are shown in Table 3 below. Note that all values ​​in Table 3 are expressed in V0 of the local reference voltage. REF The units are given. It should also be noted that the margin of a memory device is determined by the maximum limit P-margin of the blocks in the memory device minus the minimum P-margin, and is substantially equal to it. (See reference...) Figure 14 As can be seen, by applying the LVS repair method, under-repaired segments (indicated by P item 1408) are eliminated, and over-repair (indicated by P item 1410) is essentially minimized. Referring to Table 3, it can be seen that compared to the global repair method, the P-margin of the memory device repaired using the LVS repair method is increased by 11% (from 44 to 49V). REF unit).

[0074] Table 3

[0075] Globally repaired P margin LVS-corrected P margin average 49 49 maximum 55 54 Minimum 44 49 device margin 44 49

[0076] A method for performing LVS repair on a 1T1CF-RAM by independently executing an n-step P-margin binary search in each block or segment will now be described. In this method, each step of the n-step P-margin binary search is performed in all segments before moving to the next step. The final repair solution is obtained in the last step, where there are no under-repaired segments and over-repair of segments is minimized.

[0077] Before performing an LVS repair, the following three values ​​must be determined:

[0078] 1. The highest U term (U0) for each segment. This value will be used as the starting point for each LVS during the repair period and will be used to calculate the P margin.

[0079] 2. Predefined minimum 1T1C margin limit (P0-U0). This is based on reliability and yield assessment. If no repair solution is found for certain parts, those parts will be rejected. The minimum 1T1C margin (P0-U0) limit will guarantee the reliability of qualified parts.

[0080] 3. Predefined P-margin search range. This is based on the statistics of the device's P-margin distribution to include a six-sigma distribution. The search range will determine the number of search steps. For example, performing 2... 5 Or 32 and 2 6 Or 64 V REF The binary search method for the unit's search range will require 5 and 6 search steps respectively.

[0081] Typically, the repair search will start from V REF =U0 + margin constraint + N-step binary search algorithm, starting with the first interval. The first interval will be the midpoint of the binary search algorithm's range. At each time interval, an attempt will be made to repair all segments. A given interval is considered repairable only if all segments are repairable. A 5-step binary search algorithm will be used below for illustrative purposes. In this example, the following values ​​are used for U0 of the 8-segment device:

[0082] LVS U0 0 48 1 44 2 37 3 40 4 45 5 51 6 48 7 36

[0083] The 1T1C margin limit (P0-U0) is either predefined or set to 32 V. REF The unit, and the range of the binary search method is set to 32 V. REF Units. Therefore, this example requires a 5-step binary search. In the first interval, an attempt will be made in V. REF Repair each segment at point U0+32. If successful, the second interval is calculated by adding 8 to the first interval. If unsuccessful, the second interval is calculated by subtracting 8 from the first interval.

[0084] Will try in V REF =U0+32+ Repair each LVS at the second interval. If successful, the third interval is calculated by adding 4 to the second interval. If unsuccessful, the third interval is calculated by subtracting 4 from the second interval. The sequence continues with more than two intervals: + / -2 and + / -1. At the highest repairable V... REF The identified repair solution will be stored in the device.

[0085] The embodiments of the present invention have been described above with the aid of functional block diagrams and schematic block diagrams illustrating the implementation of specified functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are properly executed.

[0086] The foregoing description of specific embodiments so fully reveals the general nature of the invention that others can readily modify such specific embodiments and / or adapt them to various applications without excessive experimentation by applying knowledge of the art, without departing from the overall conception of the invention. Therefore, it is intended that such adaptations and modifications be made within the meaning and scope of equivalents of the disclosed embodiments, based on the teachings and guidance presented herein. It should be understood that the wording or terminology used herein is for descriptive purposes and not for limiting purposes, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on these teachings and guidance.

[0087] It should be understood that the claims are intended to be interpreted using the Detailed Description section rather than the Summary and Abstract section. The Summary and Abstract section may set forth one or more exemplary embodiments of the invention as conceived by the inventors, but not all exemplary embodiments, and therefore is not intended to limit the invention and the appended claims in any way.

[0088] The breadth and scope of this invention should not be limited to any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A ferroelectric random access memory (F-RAM) device, comprising: An array of F-RAM cells, the F-RAM cells being arranged in multiple rows and multiple columns, each row sharing word lines and board lines, each column sharing bit lines, the array being divided into multiple blocks based on the row and column addresses of the F-RAM cells in each block; and A sensing circuit includes a charge-sharing element and at least one comparator, the at least one comparator having a first input coupled to a bit line of one of the plurality of blocks being read to receive a memory signal from the bit line, the charge-sharing element being coupled to a second input of the comparator via at least one switching circuit. The charge-sharing element is also coupled to a reference voltage generator to receive a reference voltage based on an address to one of the plurality of blocks being read. The reference voltage generator includes a reference reference voltage generation circuit and an adjustable reference voltage generation circuit. The reference reference voltage generation circuit provides a reference voltage, and the adjustable reference voltage generation circuit provides an adjustable voltage to offset the reference voltage based on which of the plurality of blocks is being read, so as to generate the reference voltage provided to the sensing circuit.

2. The F-RAM device according to claim 1, wherein, The F-RAM cell includes a single-transistor, single-capacitor 1T1CF-RAM cell, and wherein the reference voltage is selected based on the lowest P term (P0) or the highest U term (U0) of the F-RAM cell in one of the plurality of blocks being read.

3. The F-RAM device according to claim 1, further comprising a control circuit coupled to the reference voltage generator, wherein, The control circuit includes a configuration circuit for controlling the reference voltage generation circuit and an adjustment control circuit for controlling the adjustment reference voltage generation circuit.

4. The F-RAM device of claim 3, further comprising a monitoring memory coupled to the regulating reference voltage generation circuit, the monitoring memory including one or more lookup tables storing information such that the regulating reference voltage generation circuit can be operated to provide the regulating voltage based on which of the plurality of blocks is being read.

5. The F-RAM device according to claim 4, wherein, The reference voltage generation circuit includes a first capacitor array, one or more capacitors in the first capacitor array being coupled to transfer charge to the charge-sharing element in the sensing circuit to provide a reference voltage thereto, and the adjustment reference voltage generation circuit includes a second capacitor array, one or more capacitors in the second capacitor array being coupled to transfer charge to the charge-sharing element to offset the reference voltage to generate the reference voltage provided to the sensing circuit.

6. A memory system, comprising: An array of non-volatile memory (NVM) cells divided into multiple blocks; A sensing circuit coupled to the array to receive a memory signal from the array and compares the memory signal with a reference voltage to read data from the NVM cell; as well as A reference voltage generator is coupled to the sensing circuit to provide a reference voltage to the sensing circuit, the reference voltage generator being configured to provide one of a plurality of reference voltages to the sensing circuit based on which of the plurality of blocks is being read. The reference voltage generator includes a reference reference voltage generation circuit and an adjustment reference voltage generation circuit. The reference reference voltage generation circuit provides a reference voltage, and the adjustment reference voltage generation circuit provides an adjustment voltage to offset the reference voltage based on which of the plurality of blocks is being read, so as to generate one of the plurality of reference voltages provided to the sensing circuit.

7. The memory system according to claim 6, wherein, A first reference voltage provided to the sensing circuit for reading one of the plurality of reference voltages of one of the plurality of blocks is different from a second reference voltage provided for reading another of the plurality of blocks.

8. The memory system according to claim 6, wherein, The NVM cells are arranged in multiple rows and multiple columns, with each row sharing a word line and each column sharing a bit line. The array is logically divided into the multiple blocks based on the row and column addresses of the NVM cells in each of the multiple blocks. The reference voltage generator is configured to provide one of the multiple reference voltages to the sensing circuit based on the row and column addresses of the NVM cells in each of the multiple blocks.

9. The system according to claim 6, wherein, The NVM cell includes a single-transistor, single-capacitor 1T1C memory cell, and one of the plurality of reference voltages is selected based on the lowest programmed or highest erased term of the NVM cell in one of the plurality of blocks being read.

10. The memory system of claim 6, further comprising control circuitry coupled to the reference voltage generator, wherein, The control circuit includes a configuration circuit for controlling the reference voltage generation circuit and an adjustment control circuit for controlling the adjustment reference voltage generation circuit.

11. The memory system of claim 10, further comprising a monitoring memory coupled to the regulating reference voltage generation circuit, the monitoring memory including one or more lookup tables storing information such that the regulating reference voltage generation circuit can be operated to provide the regulating voltage based on which of the plurality of blocks is being read.

12. The memory system according to claim 11, wherein, The NVM cells are arranged in multiple rows and multiple columns, with each row sharing a word line and each column sharing a bit line. The array is logically divided into the multiple blocks based on the row and column addresses of the NVM cells in each block. The system also includes an address buffer coupled to the regulating reference voltage generation circuit to identify which of the multiple blocks is being read.

13. The memory system according to claim 6, wherein, The reference voltage generation circuit includes a first capacitor array, one or more capacitors in the first capacitor array being coupled to transfer charge to a cascaded capacitor in the sensing circuit to provide the reference voltage thereto, and the adjustment reference voltage generation circuit includes a second capacitor array, one or more capacitors in the second capacitor array being coupled to transfer charge to the cascaded capacitor to offset the reference voltage to generate one of the plurality of reference voltages provided to the sensing circuit.

14. A method of operating a memory device, comprising: The array of memory cells in the memory device is logically divided into multiple blocks based on the row and column addresses of the cells in each block; Perform multiple margin scans for each block and determine the local reference voltage for each block; The reference voltage of the array and the adjustment reference voltage of each block are determined based on the local reference voltage of each block; The regulated reference voltage for each block is stored in a lookup table; During a read operation of one of the plurality of blocks, the local reference voltage previously determined for the block being read is generated by finding and generating the regulated reference voltage of the block and combining the regulated reference voltage with the reference reference voltage; as well as The local reference voltage is applied to the reference bit line of a sense amplifier, which is coupled to the bit line of the memory cell being read.

15. The method according to claim 14, wherein, Performing the multiple margin scans for each block includes: The minimum programming term for the block is determined by the following steps: starting from an initial scan reference voltage, write "1" to each memory cell in the block and read all memory cells in the block, incrementally increasing the initial scan reference voltage and repeating the write and read operations until a memory cell fails to be read correctly. The scan reference voltage at which the memory cell fails is recorded as the minimum programming term. The highest internal "0" of the block is determined by the following operation: starting from the initial scan reference voltage, write "0" to each memory cell in the block and read all memory cells in the block, gradually decrease the initial scan reference voltage and repeat the write and read operations until the memory cell fails to be read correctly, and record the scan reference voltage at which the memory cell fails as the highest internal "0".

16. The method according to claim 15, wherein, The local reference voltage is set to a predefined voltage, which is higher than the scan reference voltage when the memory cell with the highest internal '0' fails, and wherein a first margin between the local reference voltage and the scan reference voltage when the memory cell with the highest internal '0' fails is less than a second margin between the local reference voltage and the scan reference voltage when the memory cell with the lowest programming term fails.

17. The method according to claim 15, wherein, The memory cell includes a ferroelectric random access memory (F-RAM) cell, the highest internal '0' is the highest U term, and the local reference voltage is set to a predefined voltage that is higher than the scan reference voltage when the memory cell with the highest U term fails.

18. The method according to claim 14, wherein, Performing the multiple margin scans for each block includes identifying blocks in the block where the margin between the memory cell with the lowest programming term and the local reference voltage is lower than a predefined minimum, and also includes repairing the block by decoupling the memory cell with the lowest programming term in the block and coupling a spare memory cell in the block to replace the memory cell.

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