Display device

Abstract

Embodiments of the present application relate to a display device including a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels, a plurality of light emitting elements disposed on the plurality of sub-pixels, and a plurality of drive transistors configured to drive the plurality of light emitting elements, and each including a drive gate and a control gate disposed opposite the drive gate and electrically connected to a control voltage line, wherein a control voltage of a first level is applied to the control gate of at least one of the plurality of drive transistors in a control period that is a part of a frame period, the at least one of the plurality of drive transistors being turned off in the control period. By control of the control voltage applied to the control gate disposed opposite the drive gate of the drive transistor, the on state and the off state of the drive transistor can be easily controlled and non-light emitting driving can be performed in display driving.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0171145, filed on December 2, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a display device. Background Technology

[0004] The development of the information society has led to an increasing demand for display devices that display images, and various display devices such as liquid crystal displays and organic light-emitting diode displays have been put into use.

[0005] Because organic light-emitting display devices use self-emissive organic light-emitting diodes (OLEDs) to display images, they offer advantages such as fast response speed, high luminous efficiency, high brightness, and wide viewing angle.

[0006] In addition, methods to reduce the video image response time of organic light-emitting display devices have been researched and developed. Summary of the Invention

[0007] Embodiments of the present invention can provide a display device that can improve video response time while reducing changes in the structure and driving method of sub-pixels provided in the display device.

[0008] Embodiments of the present invention may provide a display device, comprising: a display panel including a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels; a plurality of light-emitting elements disposed on the plurality of sub-pixels; and a plurality of driving transistors configured to drive the plurality of light-emitting elements, each of the plurality of driving transistors including a driving gate and a control gate disposed opposite to the driving gate and electrically connected to a control voltage line, wherein during a control period as part of a frame period, a first-level control voltage is applied to the control gate of at least one of the plurality of driving transistors, the at least one driving transistor being turned off during the control period.

[0009] Embodiments of the present invention may provide a display device, comprising: a display panel including a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels; and a plurality of driving transistors, each of the plurality of driving transistors including a driving gate and a control gate disposed opposite to the driving gate and electrically connected to a control voltage line, wherein the level of the control voltage applied to the control gate of at least one of the plurality of driving transistors during a period when a scan signal is applied to a first gate line of the plurality of gate lines is different from the level of the control voltage applied to the control gate of the at least one driving transistor during a period when a scan signal is applied to a second gate line of the plurality of gate lines.

[0010] According to various embodiments of the present invention, since the driving transistor disposed on the sub-pixel is turned off by the control voltage applied to the control gate of the driving transistor during the frame cycle, the structure and driving method of the sub-pixel that can improve the video response time of the display device can be easily realized.

[0011] According to various embodiments of the present invention, by applying a control voltage to a control gate disposed opposite to the drive gate of the drive transistor, the on-state and off-state of the drive transistor can be easily controlled, and non-light-emitting drive can be performed in the display drive. Furthermore, since non-light-emitting drive is performed by applying a control voltage to the control gate of the drive transistor, non-light-emitting drive can be performed independently of the period during which the scan signal is applied, and non-light-emitting drive can be performed without affecting the display drive, thereby improving the video response time of the display device. Attached Figure Description

[0012] The above and other objects, features, and advantages of the invention will become more clearly understood from the following detailed description given in conjunction with the accompanying drawings. In the drawings:

[0013] Figure 1 This is a schematic view illustrating the structure of a display device according to an embodiment of the present invention;

[0014] Figure 2 This is a view illustrating an example of the circuit structure of a sub-pixel included in a display device according to an embodiment of the present invention;

[0015] Figure 3 It is a diagram based on the applied... Figure 2 A view showing an example of the control voltage of the control gate of the driving transistor set on the sub-pixel, and the variation of the threshold voltage of the driving transistor.

[0016] Figures 4A to 4C It is a diagram Figure 2 A view showing an example of the driving method for the sub-pixels;

[0017] Figure 5 This is a view illustrating another example of the circuit structure of a sub-pixel included in a display device according to an embodiment of the present invention;

[0018] Figure 6 It is a diagram based on Figure 5 The view shows an example of the output curve of the first control transistor set on the sub-pixel.

[0019] Figure 7 It is a diagram Figure 5 A view showing an example of the driving method for the sub-pixels;

[0020] Figure 8 This is a view illustrating another example of a circuit structure of a sub-pixel included in a display device according to an embodiment of the present invention, and an example of a driving method thereof;

[0021] Figure 9A and 9B This is a view illustrating an example of a structure in a display device according to an embodiment of the present invention, in which control voltage lines are arranged.

[0022] Figure 10 This is a view illustrating an example of the driving timing of gate lines and control voltage lines provided in a display device according to an embodiment of the present invention;

[0023] Figure 11A It is a diagram based on... Figure 10 The image shows an example of a voltage waveform obtained by driving the sub-pixel driven by the gate line represented by 1001.

[0024] Figure 11B It is a diagram based on... Figure 10 The image shows an example of a voltage waveform obtained by driving the sub-pixel driven by the gate line represented by 1002.

[0025] Figure 12A and 12B This is a view illustrating other driving timing examples of gate lines and control voltage lines provided in a display device according to an embodiment of the present invention. Detailed Implementation

[0026] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are shown by way of example, and the same reference numerals and symbols may be used to refer to the same or similar components, even if shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, a detailed description of well-known functions and components involved herein will be omitted when it is determined that such a detailed description would obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “including,” and “constitute” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.”

[0027] The elements of the present invention may be described herein using terms such as “first,” “second,” “A,” “B,” “(A),” or “(B).” Each of these terms is not intended to define the nature, order, sequence, or number of the elements, but is merely used to distinguish the corresponding element from the others.

[0028] When the first element and the second element are referred to as "connected or coupled" or "overlapping," it should be interpreted that the first element can not only be "directly connected or coupled" or "directly contact or overlap" with the second element, but also that a third element can be inserted between the first element and the second element, or that the first element and the second element can be "connected or coupled" or "overlapping" with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled," "in contact," or "overlapping" with each other.

[0029] When time-relative terms such as “after,” “follow,” “next,” “before,” etc. are used to describe the process or operation of an element or structure, or the flow or steps in an operation, process, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations, unless these terms are used with the terms “directly” or “immediately after.”

[0030] Furthermore, when referring to any dimension, relative size, etc., it should be taken into account that the numerical values ​​or corresponding information of a component or feature (e.g., level, range, etc.) include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.), even if no relevant specification is given. In addition, the term "may" fully encompasses the complete meaning of the term "able to".

[0031] The various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is a schematic view illustrating the structure of a display device 100 according to an embodiment of the present invention.

[0033] Reference Figure 1The display device 100 may include a display panel 110 and a gate driving circuit 120, a data driving circuit 130 and a controller 140 for driving the display panel 110.

[0034] The display panel 110 may include an active area AA in which a plurality of sub-pixels SP are disposed, and a non-active area NA located outside the active area AA.

[0035] Multiple gate lines GL and multiple data lines DL can be arranged on the display panel 110. Multiple sub-pixels SP can be located in the area where the gate lines GL and data lines DL intersect.

[0036] The gate drive circuit 120 is controlled by the controller 140 and sequentially outputs the scan signal to multiple gate lines GL arranged on the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0037] The gate drive circuit 120 may include one or more gate driver integrated circuits (GDICs) and may be located only on one side of the display panel 110, or may be located on both sides of it depending on the driving method.

[0038] Each gate driver integrated circuit (GDIC) can be connected to the bonding pads of the display panel 110 via a tape-on-absence (TAB) method or a chip-on-glass (COG) method. Alternatively, each GDIC can be implemented using an in-panel gate-in-in-particle (GIP) method and then directly disposed on the display panel 110. Alternatively, the GDIC can be integrated and disposed on the display panel 110. Alternatively, each GDIC can be implemented using a chip-on-film (COF) method, wherein the components are mounted on a film connected to the display panel 110.

[0039] The data driving circuit 130 receives image data DATA from the controller 140 and converts the image data DATA into an analog data voltage Vdata. Then, the data driving circuit 130 outputs the data voltage Vdata to each data line DL according to the timing of the scan signal applied via the gate line GL, so that each of the plurality of sub-pixels SP emits light with a brightness corresponding to the image data DATA.

[0040] The data drive circuit 1 30 may include one or more source driver integrated circuits (SDICs).

[0041] Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, output buffer, etc.

[0042] Each source driver integrated circuit (SDIC) can be connected to the bonding pads of the display panel 110 via a tape-on-absent (TAB) method or a chip-on-glass (COG) method. Alternatively, each source driver integrated circuit (SDIC) can be directly disposed on the display panel 110. Alternatively, the gate-source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Alternatively, each source driver integrated circuit (SDIC) can be implemented using a chip-on-film (COF) method. In this case, each source driver integrated circuit (SDIC) can be mounted on a film connected to the display panel 110 and can be electrically connected to the display panel 110 via wires on the film.

[0043] The controller 140 can provide various control signals to the gate drive circuit 120 and the data drive circuit 130, and control the operation of the gate drive circuit 120 and the data drive circuit 130.

[0044] The controller 140 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the gate drive circuit 120 and the data drive circuit 130 via the printed circuit board, flexible printed circuit, etc.

[0045] The controller 140 allows the gate drive circuit 120 to output scan signals according to the timing implemented in each frame. The controller 140 can convert data signals received from the outside into a data signal format that conforms to the data drive circuit 130, and then output the converted image data to the data drive circuit 130.

[0046] The controller 140 can receive image data and various timing signals from outside the display device 100 (e.g., a host system), including vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, input data enable signal DE, clock signal CLK, etc.

[0047] The controller 140 can generate various control signals using various timing signals received from the outside, and can output control signals to the gate drive circuit 120 and the data drive circuit 130.

[0048] For example, in order to control the gate drive circuit 120, the controller 140 may output a gate control signal GCS including a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, etc.

[0049] The gate start pulse (GSP) controls the start timing of operation of one or more gate driver integrated circuits (GDICs) constituting the gate drive circuit 120. The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits (GDICs) and controls the shift timing of the scan signal. The gate output enable signal (GOE) specifies timing information regarding one or more gate driver integrated circuits (GDICs).

[0050] In addition, in order to control the data drive circuit 130, the controller 140 can output various data control signals DCS, including the source start pulse SSP, the source sampling clock SSC, and the source output enable signal SOE.

[0051] The source start pulse SSP controls the data sampling start timing of one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source sampling clock SSC is a clock signal used to control the timing of the sampled data in the corresponding source driver integrated circuit (SDIC). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0052] The display device 100 may further include a power management integrated circuit for providing various voltages or currents to the display panel 110, gate driving circuit 120, data driving circuit 130, etc., or for controlling various voltages or currents to be provided.

[0053] Each subpixel SP is a region defined by the intersection of gate line GL and data line DL, and at least one circuit element including a light-emitting element may be disposed in the subpixel SP.

[0054] For example, in the case where the display device 100 is an organic light-emitting display device, organic light-emitting diodes (OLEDs) and various circuit elements can be disposed on multiple sub-pixels (SPs). Since the current supplied to the organic light-emitting diodes (OLEDs) is controlled by the various circuit elements, each sub-pixel SP can present a brightness corresponding to the image data.

[0055] Optionally, in some cases, light-emitting diodes (LEDs) or micro-LEDs (μLEDs) can be disposed on sub-pixels (SPs).

[0056] Figure 2 This is a view illustrating an example of the circuit structure of a sub-pixel SP included in a display device 100 according to an embodiment of the present invention.

[0057] Reference Figure 2 Each of the plurality of sub-pixels SP may include a light-emitting element ED. The sub-pixel SP may include a driving transistor DRT configured to provide driving current to the light-emitting element ED.

[0058] In addition to the driving transistor DRT and the light-emitting element ED used to drive the sub-pixel SP, the sub-pixel SP may also include at least one circuit element.

[0059] For example, a sub-pixel SP may include a first switching transistor SWT1, a second switching transistor SWT2, and a storage capacitor Cstg.

[0060] Figure 2The illustrated circuit structure example of the sub-pixel SP shows a 3T1C structure including three thin-film transistors and one capacitor in the sub-pixel SP. However, embodiments of the present invention are not limited to this; at least one driving transistor may be disposed on the sub-pixel SP. Furthermore, it is shown... Figure 2 The example shown is an N-type thin-film transistor array on a sub-pixel SP, but at least some of the thin-film transistors included in the sub-pixel SP may be P-type.

[0061] The first switching transistor SWT1 can be electrically connected between the data line DL and the first node N1.

[0062] The first switching transistor SWT1 can be controlled by the gate line GL to which the first scan signal SCAN1 is applied.

[0063] The first switching transistor SWT1 can be controlled to apply the data voltage Vdata provided via the data line DL to the first node N1. The first node N1 can be the gate node of the driving transistor DRT.

[0064] The second switching transistor SWT2 can be electrically connected between the reference voltage line RVL and the second node N2.

[0065] The second switching transistor SWT2 can be controlled by the gate line GL, which is subjected to the first scan signal SCAN1.

[0066] The second switching transistor SWT2 can be controlled by a different gate line GL than the gate line GL used to control the first switching transistor SWT1, but it can also be controlled as follows: Figure 2 As shown in the example, it is controlled by the same gate line GL used to control the first switching transistor SWT1. The number of gate lines GL located on the active region AA can be reduced.

[0067] The second switching transistor SWT2 can be controlled to apply a reference voltage Vref to the second node N2. The second node N2 can be the source node or the drain node of the driving transistor DRT.

[0068] The second switching transistor SWT2 can be driven in the process of sensing the voltage or current of the second node N2 via the reference voltage line RVL.

[0069] Degradation of the driving transistor DRT or light-emitting element ED disposed on the sub-pixel SP can be detected by sensing via a reference voltage line RVL. When compensation is performed based on the degradation detected by sensing, image quality degradation due to sub-pixel SP degradation deviation can be prevented.

[0070] The storage capacitor Cstg can be electrically connected between the first node N1 and the second node N2. The storage capacitor Cstg can maintain the voltage difference between the first node N1 and the second node N2 during a frame.

[0071] The driving transistor DRT can be electrically connected to the driving voltage line DVL that provides the first driving voltage EVDD. The first driving voltage EVDD can be, for example, a high-level driving voltage.

[0072] The driving transistor DRT can be controlled by the data voltage Vdata applied to the first node N1. The driving transistor DRT can output a driving current based on the voltage difference between the first node N1 and the second node N2, and control the driving of the light-emitting element ED.

[0073] The light-emitting element ED can be electrically connected to the second node N2. The light-emitting element ED can also be electrically connected to the voltage line to which the second driving voltage EVSS is applied. The second driving voltage EVSS can, for example, be a low-potential driving voltage.

[0074] The light-emitting element (ED) emits light according to the drive current provided by the driving transistor (DRT) and presents a grayscale-based image.

[0075] The LED (Emitting Diode) does not emit light during certain periods of its normal operating time to improve video response time.

[0076] For example, when the data voltage Vdata corresponding to a black image is supplied via the data line DL, the driving transistor DRT can be turned off, and the light-emitting element ED will not emit light. In this case, it may be necessary to drive the gate line GL and the data line DL to supply the data voltage Vdata to the sub-pixel SP.

[0077] Embodiments of the present invention provide a method for driving gate line GL and data line DL by driving a gate in the gate of a driving transistor DRT that is different from the gate to which the applied data voltage Vdata is applied.

[0078] In the following text, the driving method of controlling the light-emitting element ED to not emit light when driving the sub-pixel SP in order to improve video response time can be referred to as "non-emitting drive". In addition, non-emitting drive can refer to driving the driving transistor DRT and the light-emitting element ED in the off state, but in some cases, it can include the state in which the light-emitting element ED emits light at a very low gray level.

[0079] For example, the driving transistor DRT disposed on the sub-pixel SP may include a driving gate GEd and a control gate GEc. The first control gate of the first driving transistor disposed on the first sub-pixel of the plurality of sub-pixels SP may be electrically connected to the second control gate of the second driving transistor disposed on the second sub-pixel of the plurality of sub-pixels SP.

[0080] The driving gate GEd of the driving transistor DRT can refer to the first node N1 or an electrode electrically connected to the first node N1. The driving gate GEd of the driving transistor DRT can control the driving of the driving transistor DRT according to the data voltage Vdata applied to the first node N1.

[0081] The control gate GEc of the driving transistor DRT can be set relative to the driving gate GEd.

[0082] For example, the control gate GEc and drive gate GEd of the driving transistor DRT can be located on opposite sides of the channel.

[0083] The control gate GEc of the driving transistor DRT can be implemented using a light-shielding layer provided to prevent external light from entering the channel of the driving transistor DRT. Alternatively, the control gate GEc of the driving transistor DRT can be implemented using separately provided electrode layers.

[0084] The control gate GEc of the driving transistor DRT can be implemented using any electrode layer that is positioned opposite the driving gate GEd to which the applied data voltage Vdata is applied.

[0085] The control gate GEc of the driving transistor DRT can be electrically connected to the control voltage line CVL that provides the control voltage Vb.

[0086] The threshold voltage of the driving transistor DRT can be changed according to the control voltage Vb applied to the control gate GEc of the driving transistor DRT.

[0087] Figure 3 It is a diagram based on the applied... Figure 2 The view shows an example of the change in the control voltage Vb of the control gate GEc of the driving transistor DRT set on the sub-pixel SP, and the threshold voltage of the driving transistor DRT.

[0088] Reference Figure 3 An example of the current output based on the voltage applied to the driving transistor DRT is shown.

[0089] For example, if the control voltage Vb applied to the control gate GEc of the driving transistor DRT decreases from 10V to 0V, the threshold voltage of the driving transistor DRT can increase by ΔVth.

[0090] Because the threshold voltage Vth of the driving transistor DRT is increased, the output current can be reduced when the same voltage is applied to the driving transistor DRT.

[0091] The driving state of the light-emitting element (ED) can be changed by reducing the current output by the driving transistor DRT.

[0092] Furthermore, the on and off states of the driving transistor DRT can be changed according to the change in the threshold voltage of the driving transistor DRT.

[0093] Depending on the change in the on and off states of the driving transistor DRT, DRT can be turned off, and the light-emitting element ED can be in a non-emitting state. Since the light-emitting element ED has a non-emitting state during the emission period, non-emitting driving of the sub-pixel SP can be performed, and video response time can be improved.

[0094] Because the above-mentioned non-light-emitting drive is performed by controlling the control voltage Vb applied to the control gate GEC of the driving transistor DRT, the above-mentioned non-light-emitting drive can be performed without affecting the voltages applied to the first node N1 and the second node N2 of the driving transistor DRT.

[0095] It can perform non-light-emitting drives to improve video response time while reducing the impact on the display drive of sub-pixels SP.

[0096] Figures 4A to 4C It is a diagram Figure 2 The view shows an example of the driving method for the subpixel SP.

[0097] Reference Figure 4A The high-level first scan signal SCAN1 can be applied to the gate line GL during the first time period P1 of the frame period FP.

[0098] The first switching transistor SWT1 and the second switching transistor SWT2 can be turned on by the first scan signal SCAN1.

[0099] When the first switching transistor SWT1 is turned on, the data voltage Vdata provided via the data line DL can be applied to the first node N1. When the second switching transistor SWT2 is turned on, the reference voltage Vref provided via the reference voltage line RVL can be applied to the second node N2.

[0100] The voltage used for display driving of sub-pixels SP can be applied to the first node N1 and the second node N2 of the driving transistor DRT during the first time period P1. The first time period P1 can be referred to as the data write time period WP.

[0101] Reference Figure 4BThe low-level first scan signal SCAN1 can be applied to the gate line GL during the second time period P2 of the frame period FP.

[0102] The first switching transistor SWT1 and the second switching transistor SWT2 can be turned off by the first scan signal SCAN1.

[0103] Since the first node N1 and the second node N2 are floating, the voltage levels of the first node N1 and the second node N2 can be increased. Drive current can be provided by the driving transistor DRT, and the light-emitting element ED can emit light with a brightness corresponding to the data voltage Vdata.

[0104] The second time period, P2, can be referred to as the luminescent period, EP.

[0105] Non-light-emitting drive can be performed during the light-emitting period (EP).

[0106] For example, refer to Figure 4C A control period CP may be included in the frame period FP. At least a portion of the control period CP may overlap with the emission period EP of the frame period FP. The control period CP may be a part of the frame period FP. Figure 4C An example is shown where the control period CP is part of the emission period EP, but in some cases, the control period CP may overlap with the data write period WP.

[0107] The control voltage Vb of the first level L1 can be applied to the control gate GEc of the driving transistor DRT during the control period CP.

[0108] The control voltage Vb of the first level L1 can be, for example, a voltage capable of shifting the threshold voltage of the driving transistor DRT to a positive level. In some cases, when the driving transistor DRT is P-type, the control voltage Vb of the first level L1 can be a voltage capable of shifting the threshold voltage of the driving transistor DRT to a negative level.

[0109] The control voltage Vb of the first level L1 can be a voltage that can turn off the driving transistor DRT by changing the threshold voltage of the driving transistor DRT.

[0110] The driving transistor DRT can be turned off by the control voltage Vb of the first level L1. Since the driving transistor DRT is turned off, the light-emitting element ED can be in a non-light-emitting state.

[0111] Non-light-emitting drive can be easily performed in the frame period FP by applying a control voltage Vb to the first level L1 of the control gate GEc of the driving transistor DRT.

[0112] During periods other than the control period CP of the frame period FP, the level of the control voltage Vb applied to the control gate GEC of the driving transistor DRT can be a second level L2, which is different from the first level L1.

[0113] The control voltage Vb of the second level L2 can be a voltage used to drive the driver transistor DRT normally without shifting the threshold voltage of the driver transistor DRT to a positive level.

[0114] Because the level of the control voltage Vb decreases from the second level L2 to the first level L1 at the beginning of the control period CP, the voltages of the first node N1 and the second node N2 can be coupled to the control gate GEc and decrease slightly. Because the level of the control voltage Vb increases from the first level L1 to the second level L2 at the end of the control period CP, the voltages of the first node N1 and the second node N2 can increase slightly. In other words, the voltage level of the driving gate can change during the time when the control voltage Vb at the first level L1 is applied.

[0115] During the control period CP, the voltage level difference between the first node N1 (driving gate) and the second node N2 (source or drain) can remain the same or similar as before the control period CP.

[0116] The control voltage Vb of the second level L2 can be applied to the control gate GEc of the driving transistor DRT during periods other than the control period CP. The current output characteristics of the driving transistor DRT can be stably maintained by the control voltage Vb of the second level L2.

[0117] Furthermore, since the level of the control voltage Vb applied to the control gate GEc of the driving transistor DRT changes from the second level L2 to the first level L1 during the control period CP, non-light-emitting drive of the sub-pixel SP can be easily performed.

[0118] As described above, according to an embodiment of the present invention, by controlling the control voltage Vb applied to the control gate GEc of the driving transistor DRT, the non-light-emitting drive of the sub-pixel SP can be easily performed without affecting the voltage provided for the display drive of the sub-pixel SP.

[0119] Furthermore, since a certain level of control voltage Vb is applied to the control gate GEc of the driving transistor DRT during periods when non-light-emitting drive is not performed, the stability of the current output characteristics of the driving transistor DRT can be improved.

[0120] Furthermore, non-light-emitting drive of sub-pixels SP can be performed in a structure that further improves the stability of the current output characteristics of the driving transistor DRT.

[0121] Figure 5 This is a view illustrating another example of the circuit structure of a sub-pixel SP included in a display device 100 according to an embodiment of the present invention. Figure 6 It is a diagram based on Figure 5 The view shows an example of the output curve of the first control transistor COT1 set on the sub-pixel SP, and the driving transistor DRT. Figure 7 It is a diagram Figure 5 The view shows an example of the driving method for the sub-pixels.

[0122] Reference Figure 5 The sub-pixel SP may include a driving transistor DRT and a light-emitting element ED. The sub-pixel SP may include a first switching transistor SWT1, a second switching transistor SWT2, and a storage capacitor Cstg. The above construction is consistent with reference to... Figure 2 Since the components described are the same, duplicate descriptions will be omitted.

[0123] The sub-pixel SP may include a first control transistor COT1 electrically connected between the second node N2 and the third node N3. The first control transistor COT1 may be disposed on each of the plurality of sub-pixels SP.

[0124] The second node N2 can be the source node (or drain node) of the driving transistor DRT. The third node N3 can be a node connected to the control gate GEC of the driving transistor DRT.

[0125] The first control transistor COT1 can be controlled by the gate line GLb to which the second scan signal SCAN2 is applied. The gate line GLb to which the second scan signal SCAN2 is applied can be different from the gate line GLa to which the first scan signal SCAN1 is applied.

[0126] The sub-pixel SP may include a second control transistor COT2 electrically connected to the third node N3. In some cases, the second control transistor COT2 may be located outside the area where the sub-pixel SP is disposed.

[0127] The second control transistor COT2 can be controlled by the gate line GLc to which the third scan signal SCAN3 is applied. The gate line GLc to which the third scan signal SCAN3 is applied may be different from the gate line GLa to which the first scan signal SCAN1 is applied or the gate line GLb to which the second scan signal SCAN1 is applied.

[0128] The second control transistor COT2 can be electrically connected to the control voltage line CVL. The second control transistor COT2 can be controlled to apply the control voltage Vb to the control gate GEc of the drive transistor DRT.

[0129] When the second control transistor COT2 is located outside the area where the sub-pixel SP is located, the second control transistor COT2 can be electrically connected to one or more control voltage lines CVL, and control the supply of control voltage Vb to the control gate GEc of the drive transistor DRT.

[0130] When the first control transistor COT1 is electrically connected between the second node N2 and the third node N3, the second node N2 and the third node N3 can be electrically connected according to the driving of the first control transistor COT1. The source of the driving transistor DTR and the control gate GEC of the driving transistor DRT can be electrically connected to each other.

[0131] Figure 6 An example curve of the output current (A) based on the voltage (V) applied to the driving transistor DRT is shown.

[0132] Reference Figure 5 and 6 Since the source node and control gate GEC of the driving transistor DRT are electrically connected to each other according to the driving of the first control transistor COT1, the output curve of the driving transistor DRT can be changed from ① to ②. The current output characteristic of the driving transistor DRT can be stabilized.

[0133] The current output characteristics of the driving transistor DRT can be stabilized by the first control transistor COT1 and the second control transistor COT2, and non-light-emitting drive can be performed in the frame period FP.

[0134] Reference Figure 7 The high-level first scan signal SCAN1 can be applied to the gate line GLa during the first time period P1 of the frame period FP. The data voltage Vdata and the reference voltage Vref can each be applied to the first node N1 and the second node N2, respectively.

[0135] A high-level second scan signal SCAN2 can be applied to gate line GLb during the first time period P1. A low-level third scan signal SCAN3 can be applied to gate line GLc during the first time period P1.

[0136] The low-level first scan signal SCAN1 can be applied to the gate line GLa during the second time period P2, and the light-emitting element ED can be in the light-emitting state.

[0137] The second scan signal SCAN2 can be kept high during the first time period P1 and a portion of the second time period P2. When the high-level second scan signal SCAN2 is applied, the first control transistor COT1 can remain in the on state.

[0138] When the third scan signal SCAN3 remains low during the corresponding time period, the second control transistor COT2 can remain in the off state. The control voltage Vb can remain at the second level L2 during the corresponding time period. Alternatively, it can be a state where the control voltage Vb is not provided during the corresponding time period.

[0139] Since the source and control gate GEC of the driving transistor DRT are electrically connected during the display driving period, the current output characteristics of the driving transistor DRT can be stably maintained.

[0140] The low-level second scan signal SCAN2 can be applied to the gate line GLb during the control period CP of the frame period FP. The high-level third scan signal SCAN3 can be applied to the gate line GLc during the control period CP.

[0141] The first control transistor COT1 can be turned off by the low-level second scan signal SCAN2. The second node N2 and the third node N3 are not electrically connected to each other during the control period CP.

[0142] The second control transistor COT2 can be turned on by the high-level third scan signal SCAN3. The control voltage Vb of the first level L1 can be applied to the control gate GEc of the driving transistor DRT during the control period CP. The threshold voltage of the driving transistor DRT can be changed, and the driving transistor DRT can be turned off. The non-emitting drive of the light-emitting element ED can be performed during the control period CP.

[0143] As described above, by connecting the first control transistor COT1 and the second control transistor COT2 to the third node N3, non-light-emitting drive can be easily performed by cutting off the drive transistor DRT while stably maintaining the current output characteristics of the drive transistor DRT.

[0144] Furthermore, according to an embodiment of the present invention, when the above structure is implemented using other types of first control transistor COT1 and second control transistor COT2, a structure capable of performing non-light-emitting drive can be provided while reducing the number of gate lines GL provided on the sub-pixel SP.

[0145] Figure 8 This is a view illustrating another example of the circuit structure of the sub-pixel SP included in the display device 100 according to an embodiment of the present invention, and an example of its driving method.

[0146] Reference Figure 8 The sub-pixel SP may include a first control transistor COT1 electrically connected between the second node N2 and the third node N3. The sub-pixel SP may also include a second control transistor COT2 electrically connected to the third node N3. In some cases, the second control transistor COT2 may be located outside the area where the sub-pixel SP is disposed.

[0147] For example, in such Figure 8 In the example shown, the first control transistor COT1 can be P-type, and the second control transistor COT2 can be N-type.

[0148] Optionally, the first control transistor COT1 can be N-type, and the second control transistor COT2 can be P-type.

[0149] The first control transistor COT1 and the second control transistor COT2 can be controlled by the same gate line GLb. The first control transistor COT1 and the second control transistor COT2 can be controlled by a second scan signal SCAN2 applied to the gate line GLb.

[0150] When the first control transistor COT1 and the second control transistor COT2 are implemented as CMOS, the first control transistor COT1 and the second control transistor COT2 can be controlled by a scan signal.

[0151] For example, a low-level second scan signal SCAN2 can be applied to the gate line GLb during the data writing period WP of the frame period FP and a portion of the light emission period EP.

[0152] During the period when the second scan signal SCAN2 is low, the first control transistor COT1 is turned on, and the second control transistor COT2 is turned off. The second node N2 and the third node N3 are electrically connected. The control voltage Vb is not supplied to the control gate GEc of the drive transistor DRT.

[0153] The high-level second scan signal SCAN2 can be applied to the gate line GLb during the control period CP of the frame period FP.

[0154] During the period when the high-level second scan signal SCAN2 is applied, the first control transistor COT1 can be turned off, and the second control transistor COT2 can be turned on. The second node N2 and the third node N3 are not electrically connected to each other. The control voltage Vb of the first level L1 can be provided to the control gate GEc of the drive transistor DRT.

[0155] While maintaining the stable current output characteristics of the driving transistor DRT in the display driver, non-light-emitting driving can be performed by controlling the voltage Vb. Since the first control transistor COT1 and the second control transistor COT2 are driven by a single gate line GLb, the number of signal lines set on the sub-pixel SP can be reduced.

[0156] As described above, embodiments of the present invention can easily perform non-light-emitting drive of sub-pixels SP by controlling the control voltage Vb applied to the control gate GEc of the driving transistor DRT. The control voltage line CVL providing the control voltage Vb can be arranged in various shapes in the display panel 110. The method of performing non-light-emitting drive can vary depending on the arrangement structure of the control voltage line CVL.

[0157] Figure 9A and 9B This is a view illustrating an example of the structure of a display device 100 according to an embodiment of the present invention, in which a control voltage line (CVL) is provided.

[0158] Reference Figure 9A and 9B The control voltage line CVL can be set to connect to two or more sub-pixels SP set on the active area AA.

[0159] The control voltage line CVL can be electrically connected to the control gate GEc of the driving transistor DRT located on each of two or more sub-pixels SP. The control gates GEc of the driving transistor DRT located on different sub-pixels SP can be electrically connected to each other via the control voltage line CVL.

[0160] The control voltage line CVL can be set in one direction. For example, in Figure 9A In the example shown, the control voltage line CVL can be positioned in a direction intersecting the direction of the gate line GL (or the setting direction of the gate line GL). The control voltage line CVL can be positioned in the direction of the data line DL or the drive voltage line DVL, and can be electrically connected to the sub-pixel SP. In this case, the data line DL, the drive voltage line DVL, the reference voltage line RVL, and the control voltage line CVL can be positioned in the same direction.

[0161] The control voltage line CVL can be electrically connected to the control voltage supply line CVSL, which provides the control voltage Vb, located outside the active region AA.

[0162] In such Figure 9A In the example shown, when setting the control voltage line CVL, the control voltage Vb can be simultaneously supplied to all sub-pixels SP set on the active region AA. Non-emissive driving can be performed simultaneously in all sub-pixels SP during the frame period FP.

[0163] In another example, as Figure 9B In the example shown, the control voltage line CVL can be set in the direction of setting the gate line GL.

[0164] The control voltage line CVL can be electrically connected to the control voltage supply line CVSL located outside the active area AA.

[0165] exist Figure 9B In the structure shown, the control voltage Vb can be supplied to multiple control voltage lines CVL simultaneously, and non-light-emitting drive can be performed.

[0166] Optionally, the control voltage Vb can be sequentially supplied to multiple control voltage lines CVL, and non-light-emitting drive can be performed. Furthermore, non-light-emitting drive can be performed sequentially in groups comprising two or more control voltage lines CVL.

[0167] The sequential non-light-emitting drive performed by the control voltage line CVL can be executed by the gate drive circuit 120 or by a separately configured circuit. When the control voltage line CVL is set in the direction of the gate line GL and the non-light-emitting drive is performed, the non-light-emitting drive can be performed without detecting any image quality abnormalities, even if the non-light-emitting drive is performed sequentially.

[0168] Furthermore, according to an embodiment of the present invention, since non-light-emitting drive is performed by controlling the control voltage line CVL which is electrically connected to the control gate GEc of the driving transistor DRT, non-light-emitting drive can be performed without affecting the display driving timing implemented by the gate line GL and the data line DL.

[0169] Figure 10 This is a view illustrating an example of the driving timing of the gate line GL and the control voltage line CVL provided in a display device 100 according to an embodiment of the present invention.

[0170] Figure 11A It is a diagram based on... Figure 10 The image shows an example of the voltage waveform obtained by driving the sub-pixel SP driven by the gate line GL, represented by 1001. Figure 11B It is a diagram based on... Figure 10 The image shown is a view of an example of the voltage waveform obtained by driving the sub-pixel SP driven by the gate line GL, represented by 1002.

[0171] Reference Figure 10 Scan signals can be applied sequentially from the first gate line GL(1) to the nth gate line GL(n) to execute display driving.

[0172] The control voltage Vb can be maintained at a specific level during the light-emitting period EP. The level of the control voltage Vb can be a level that does not change the threshold voltage of the driving transistor DRT, or a level that does not turn off the driving transistor DRT. Optionally, in some cases, the control voltage Vb may not be provided during the light-emitting period EP.

[0173] The control voltage Vb can be changed to a level that offsets the threshold voltage of the driving transistor DRT. Figure 10The example shown illustrates a scenario where the level of the control voltage Vb decreases during the control period CP, but depending on the type of driving transistor DRT, the level of the control voltage Vb may increase during the control period CP.

[0174] The driving transistor DRT can be turned off by offsetting the threshold voltage of the driving transistor DRT.

[0175] When the driving transistor DRT is turned off, the light-emitting element ED driven by the driving transistor DRT can be in a non-light-emitting state during the control period CP. By controlling the control voltage Vb, non-light-emitting drive can be easily executed during the original light-emitting period, and the video response time based on sub-pixel SP can be improved.

[0176] Furthermore, since the control voltage Vb used for non-light-emitting drive is applied to the control gate GEc of the driving transistor DRT, it does not affect the voltage applied to the first node N1 and the second node N2 of the driving transistor DRT, thus allowing the driving of the sub-pixel SP to be performed independently of the non-light-emitting drive.

[0177] Reference Figure 11A It shows an example of the voltage waveform of the sub-pixel SP driven by the first gate line GL(1).

[0178] A high-level first scan signal SCAN1 can be applied to sub-pixel SP during the data write period WP. The data voltage Vdata is applied to the first node N1, and the reference voltage Vref can be applied to the second node N2.

[0179] When the first scan signal SCAN1 goes low, the voltages of the first node N1 and the second node N2 can rise, and the driving transistor DRT can output a driving current. After the data writing period WP, ​​there can be an emission period EP for the light-emitting element ED to emit light.

[0180] A low-level control voltage Vb can be applied during the control period CP. When the control voltage Vb is applied, the voltage levels of the first node N1 and the second node N2 can be slightly reduced. The difference between the voltage levels of the first node N1 and the second node N2 can remain constant during the control period CP.

[0181] When the threshold voltage of the driving transistor DRT is offset by the control voltage Vb during the control period CP, the driving transistor DRT and the light-emitting element ED can be turned off, and non-light-emitting drive can be performed.

[0182] After the control period CP, the control voltage Vb can become high. When the level of the control voltage Vb changes, the voltage levels of the first node N1 and the second node N2 can increase slightly.

[0183] The threshold voltage of the driving transistor DRT can be changed by varying the level of the control voltage Vb, enabling the driving transistor DRT to conduct. When the voltage level difference between the first node N1 and the second node N2 remains constant, the driving current can be supplied to the light-emitting element ED through the driving transistor DRT, enabling the light-emitting element ED to conduct.

[0184] The application of voltage to the first node N1 and the second node N2 can be performed during the control period CP when a low-level control voltage Vb is applied.

[0185] Reference Figure 11B It shows an example of the voltage waveform of the sub-pixel SP driven by the (n-2)th gate line GL(n-2).

[0186] At least a portion of the data write period WP may overlap with the control period CP. A high-level first scan signal SCAN1 may be provided to the sub-pixel SP during the data write period WP. Simultaneously, a low-level control voltage Vb may be provided to the sub-pixel SP.

[0187] When the control voltage Vb is applied to the control gate GEC of the driving transistor DRT, each of the data voltage Vdata and the reference voltage Vref can be applied to the first node N1 and the second node N2, respectively. Data writing can be performed on the sub-pixel SP during the non-light-emitting driving period.

[0188] The voltages of the first node N1 and the second node N2 may be slightly reduced when the control voltage Vb changes to a low level. The difference between the voltage levels of the first node N1 and the second node N2 may be maintained to be the same as or similar to the difference obtained based on the data voltage Vdata and the reference voltage Vref provided during the data write period WP.

[0189] Since the threshold voltage of the driving transistor DRT is shifted by the low-level control voltage Vb, the driving transistor DRT will not be turned on, and non-light-emitting drive can be performed.

[0190] After the control period CP, a high-level control voltage Vb can be provided to the sub-pixel SP.

[0191] The voltage levels of the first node N1 and the second node N2 can be increased, allowing the driving transistor DRT to conduct. The light-emitting element ED can be turned on according to the driving current provided via the driving transistor DRT, and can be driven.

[0192] As described above, since the non-light-emitting drive can be executed independently of the display drive, the display drive and non-light-emitting drive can be executed without reducing or changing the display drive period based on the non-light-emitting drive.

[0193] Furthermore, the timing of non-light-emitting drive can vary depending on the arrangement of the control voltage line CVL and the drive method.

[0194] Figure 12A and 12B This is a view illustrating other driving timing examples of the gate line GL and control voltage line CVL provided in a display device 100 according to an embodiment of the present invention.

[0195] Reference Figure 12A When the control voltage line CVL is set in the direction of the gate line GL, non-light-emitting drive can be executed sequentially by controlling the control voltage line CVL.

[0196] For example, non-light-emitting driving by the first control voltage line CVL(1) can be performed during the control period CP when the sub-pixel SP is driven by the first gate line GL(1). The level of the control voltage applied to the control gate of at least one of the driving transistors during the period when the scan signal is applied to the first gate line of the plurality of gate lines may be different from the level of the control voltage applied to the control gate of at least one driving transistor during the period when the scan signal is applied to the second gate line of the plurality of gate lines.

[0197] The control voltage line CVL can be set in the direction of the gate line GL, and can sequentially execute display driving and non-light-emitting driving.

[0198] Optionally, even when the control voltage line CVL is set in the direction of the gate line GL, two or more control voltage lines CVL can be driven simultaneously. That is, the control voltage Vb of the first level L1 can be applied simultaneously to the control gate of each of at least two of the multiple driving transistors, and non-light-emitting drive can be performed.

[0199] For example, refer to Figure 12B The gate lines GL can be driven sequentially from the first gate line GL(1) to the fourth gate line GL(4). The low-level control voltage Vb can be provided to the first control voltage line to the fourth control voltage line CVL(1-4) at the same time as the scan signal is provided to the fourth gate line GL(4).

[0200] Since the period during which a low-level control voltage Vb is applied can be independent of the period during which a scan signal is applied, a low-level control voltage Vb can be applied during any of the periods during which a scan signal is applied to the first gate line GL(1) to the fourth gate line GL(4).

[0201] Non-light-emitting drive can be performed in units of groups driven by four control voltage lines (CVL).

[0202] In addition to the methods described above, control voltage Vb can be provided in various time periods independent of the time period in which the scan signal is provided, and non-light-emitting drive can be performed simultaneously or sequentially.

[0203] The embodiments of the present invention described above will be briefly described below.

[0204] A display device 100 according to an embodiment of the present invention may include: a display panel 110, wherein a plurality of gate lines GL, a plurality of data lines DL and a plurality of sub-pixels SP are disposed therein; a plurality of light-emitting elements ED, wherein the light-emitting elements are disposed on each of the plurality of sub-pixels SP; and a plurality of driving transistors DRT, wherein the driving transistors are configured to drive each of the plurality of light-emitting elements ED and include a driving gate GEd and a control gate GEc disposed opposite to the driving gate GEd and electrically connected to a control voltage line CVL.

[0205] During the control period CP, which is part of the frame period FP, a control voltage Vb of the first level L1 can be applied to the control gate GEc of at least one of the plurality of drive transistors DRT, which can be turned off during the control period CP.

[0206] During the control period CP, a scan signal may be applied to the gate line GL of the sub-pixel SP on which at least one driving transistor DRT is disposed.

[0207] During the frame period FP, excluding the control period CP, a control voltage Vb, different from the first level L1 and the second level L2, can be applied to the control gate GEc of the at least one drive transistor DRT.

[0208] At least a portion of the time period during which the control voltage Vb of the second level L2 is applied may overlap with the emission period EP of the frame period FP.

[0209] The control voltage line CVL can be set in the direction of setting the multiple data lines DL, and the control voltage Vb of the first level L1 can be simultaneously applied to the control gate GEc of each of the multiple driving transistors DRT.

[0210] Optionally, the control voltage line CVL can be set in the direction of setting the plurality of gate lines GL, and the control voltage Vb of the first level L1 can be sequentially applied to the control gate GEc of each of the plurality of driving transistors DRT.

[0211] Optionally, the control voltage line CVL can be set in the direction of setting the plurality of gate lines GL, and the control voltage Vb of the first level L1 can be simultaneously applied to the control gate GEc of each of at least two of the plurality of driving transistors DRT.

[0212] The control voltage line CVL can be electrically connected to the control voltage supply line CVSL, which is located outside the area where the plurality of sub-pixels SP are located.

[0213] The first control gate of the first driving transistor disposed on the first sub-pixel of the plurality of sub-pixels SP can be electrically connected to the second control gate of the second driving transistor disposed on the second sub-pixel of the plurality of sub-pixels SP.

[0214] The display device 100 may further include: a first control transistor COT1, configured to be electrically connected between the control gate GEc and the source of each of the plurality of driving transistors DRT; and a second control transistor COT2, configured to be electrically connected to a node between the control gate GEc and the first control transistor COT1, and to control the supply of the control voltage Vb to the control gate GEc.

[0215] The first control transistor COT1 can be in the off state during the period when the second control transistor COT2 is in the on state.

[0216] The second control transistor COT2 can be in the off state during the period when the first control transistor COT1 is in the on state.

[0217] The first control transistor COT1 can be N-type and the second control transistor COT2 can be P-type. Optionally, the first control transistor COT1 can be P-type and the second control transistor COT2 can be N-type.

[0218] The first control transistor COT1 and the second control transistor COT2 can be controlled by the same gate line GL.

[0219] The first control transistor COT1 may be disposed on each of the plurality of sub-pixels SP, and the second control transistor COT2 may be disposed outside the area where the plurality of sub-pixels SP are disposed.

[0220] The voltage level of the driving gate GEd can be changed during the time when the control voltage Vb of the first level L1 is applied.

[0221] The difference between the voltage level of the driving gate GEd of the at least one driving transistor DRT and the voltage level of the source of the at least one driving transistor DRT remains constant during the control period CP.

[0222] A display device 100 according to an embodiment of the present invention may include: a display panel 110, wherein a plurality of gate lines GL, a plurality of data lines DL, and a plurality of sub-pixels SP are disposed therein; and a plurality of driving transistors DRT, wherein each of the plurality of sub-pixels SP includes a driving gate GEd and a control gate GEc disposed opposite to the driving gate GEd and electrically connected to a control voltage line CVL, wherein the level of the control voltage Vb applied to the control gate GEc of at least one of the plurality of driving transistors DRT during the period when a scan signal is applied to a first gate line of the plurality of gate lines GL is different from the level of the control voltage Vb applied to the control gate GEc of the at least one driving transistor DRT during the period when a scan signal is applied to a second gate line of the plurality of gate lines GL.

[0223] According to the above-described embodiments of the present invention, by applying a control voltage Vb to a control gate GEc disposed opposite to the drive gate GEd of the drive transistor DRT, the threshold voltage of the drive transistor DRT can be shifted.

[0224] Therefore, the on and off states of the driving transistor DRT can be easily controlled, non-light-emitting driving can be performed in the display driver, and the video response time of the sub-pixel SP can be improved.

[0225] Furthermore, since non-light-emitting drive is performed by controlling the control voltage Vb of the control gate GEc, which is set separately from the gate node or source node, applied to the driving transistor DRT, non-light-emitting drive can be performed independently of the period during which the scan signal is applied.

[0226] Therefore, according to embodiments of the present invention, a display device 100 that can easily perform non-light-emitting driving without affecting the display driving timing can be provided.

[0227] The above description is provided to enable any person skilled in the art to acquire and use the technical concept of the invention, and the description is provided in the context of a specific application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings are provided for illustrative purposes only, illustrating the technical concept of the invention. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the invention. Therefore, the scope of the invention is not limited to the illustrated embodiments, but is the widest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the appended claims, and all technical concepts within the equivalent scope should be interpreted as being included within the scope of the invention.

Claims

1. A display device, comprising: The display panel includes multiple gate lines, multiple data lines, and multiple sub-pixels; Multiple light-emitting elements are disposed on the multiple sub-pixels; as well as A plurality of driving transistors are configured to drive the plurality of light-emitting elements. Each of the plurality of driving transistors includes a driving gate and a control gate disposed opposite to the driving gate and electrically connected to a control voltage line. During a control period that is part of a frame period, a first-level control voltage is applied to the control gate of at least one of the plurality of driving transistors, wherein the at least one driving transistor is turned off during the control period. At least a portion of the control period overlaps with the emission period of the frame period.

2. The display device according to claim 1, wherein during the control period, a scan signal is applied to a gate line of a sub-pixel of the plurality of sub-pixels on which at least one driving transistor is disposed.

3. The display device according to claim 1, wherein during a period of the frame cycle other than the control period, a control voltage of a second level different from the first level is applied to the control gate of the at least one driving transistor.

4. The display device according to claim 3, wherein at least a portion of the time period during which the control voltage of the second level is applied overlaps with the light emission period of the frame period.

5. The display device according to claim 1, wherein the control voltage line is disposed in the direction of the plurality of data lines, and the first level control voltage is simultaneously applied to the control gate of each of the plurality of driving transistors.

6. The display device according to claim 1, wherein the control voltage line is disposed in the direction in which the plurality of gate lines are disposed, and the first level control voltage is sequentially applied to the control gate of each of the plurality of driving transistors.

7. The display device according to claim 1, wherein the control voltage line is disposed in the direction in which the plurality of gate lines are disposed, and the first level control voltage is simultaneously applied to the control gate of each of at least two of the plurality of driving transistors.

8. The display device according to claim 1, wherein the control voltage line is electrically connected to the control voltage supply line, and the control voltage supply line is disposed outside the region where the plurality of sub-pixels are disposed.

9. The display device according to claim 1, wherein the first control gate of the first driving transistor disposed on a first sub-pixel of the plurality of driving transistors is electrically connected to the second control gate of the second driving transistor disposed on a second sub-pixel of the plurality of driving transistors.

10. The display device according to claim 1, further comprising: A first control transistor is configured to be electrically connected between the control gate and the source of each of the plurality of drive transistors; as well as A second control transistor is configured to be electrically connected to a node between the control gate and the first control transistor, and to control the supply of the control voltage to the control gate.

11. The display device according to claim 10, wherein the first control transistor is in a cut-off state during the period when the second control transistor is in a conducting state.

12. The display device according to claim 10, wherein the second control transistor is in a cut-off state during the period when the first control transistor is in a conducting state.

13. The display device of claim 10, wherein the first control transistor is an N-type transistor and the second control transistor is a P-type transistor, or the first control transistor is a P-type transistor and the second control transistor is an N-type transistor.

14. The display device of claim 13, wherein the first control transistor and the second control transistor are controlled by the same gate line.

15. The display device of claim 10, wherein the first control transistor is disposed on each of the plurality of sub-pixels, and the second control transistor is disposed outside the region on which the plurality of sub-pixels are disposed.

16. The display device according to claim 1, wherein the voltage level of the driving gate changes during the time when the control voltage of the first level is applied.

17. The display device according to claim 1, wherein the difference between the voltage level of the driving gate of the at least one driving transistor and the voltage level of the source of the at least one driving transistor remains constant during the control period.

18. A display device, comprising: The display panel includes multiple gate lines, multiple data lines, and multiple sub-pixels; as well as A plurality of driving transistors are disposed on the plurality of sub-pixels, and each of the plurality of driving transistors includes a driving gate and a control gate disposed opposite to the driving gate and electrically connected to a control voltage line. The level of the control voltage applied to the control gate of at least one of the driving transistors during a control period in which the scan signal is applied to the first gate line of the plurality of gate lines as part of the frame period is different from the level of the control voltage applied to the control gate of the at least one driving transistor during a period in the frame period in which the scan signal is applied to the second gate line of the plurality of gate lines, excluding the control period, and the at least one driving transistor is turned off during the control period. At least a portion of the control period overlaps with the emission period of the frame period.

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