Method, device and system for multi-port data transmission based on FPGA chip

Abstract

This application provides a method, apparatus, and system for multi-port data transmission based on an FPGA chip. The method includes the following steps: receiving a first data packet sent by a target application; determining whether the number of first target receivers corresponding to the first data packet exceeds a preset value; if so, entering an extended mode; allocating at least one message in the first data packet to different queues according to preset rules; and sending at least one message in the first data packet to the corresponding first target receiver through the Ethernet port corresponding to the queue. It can be seen that this application meets the data transmission requirements of industrial cameras by expanding the Ethernet ports of the network card, eliminating the need for a switch and thus reducing industrial costs without compromising data transmission efficiency.

Description

Technical Field

[0001] This application relates to the Internet field, and in particular to methods, apparatus and systems for multi-port data transmission based on FPGA chips. Background Technology

[0002] Industrial cameras are typically used in the most critical stages of product manufacturing processes, such as industrial production lines and logistics management. They not only require real-time control command transmission and result feedback but also the acquisition of large amounts of image and video data in a short period. Therefore, only extremely high network bandwidth and speed can meet actual production demands. GigE Vision is a camera interface standard developed based on the Gigabit Ethernet communication protocol. In industrial machine vision applications, GigE Vision allows users to transmit images quickly over long distances using inexpensive standard cables. With the advancement of industrialization, a single industrial camera is no longer sufficient for production needs. Adding multiple cameras requires an industrial computer with a 4-port network card, which can expand to four GigE Vision cameras. If this is still insufficient, a switch is needed to expand the network to include more Ethernet ports.

[0003] In existing technologies, when an industrial computer connects to more than four GigE Vision cameras, the cameras are connected to two GigE Vision switches via twisted-pair cables. The switches are then connected to the industrial computer's dual-port GigE Ethernet card via twisted-pair cables to form a GigE Ethernet network. This solution is costly, requiring two switches and a dual-port GigE Ethernet card. It is also not very user-friendly, has cumbersome connections, and consumes a significant amount of power. Therefore, providing a simpler method for data transmission from industrial cameras is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a method, apparatus, and system for multi-port data transmission based on an FPGA chip. It can determine whether to expand the Ethernet ports of a network card based on the size of the data to be transmitted, thereby meeting the data transmission requirements of a multi-industrial camera system. Furthermore, since the method in this application directly expands the Ethernet ports of the network card, no switch needs to be configured in the data transmission system, which helps reduce industrial costs.

[0005] In a first aspect, embodiments of this application provide a method for multi-port data transmission based on an FPGA chip, the method comprising the following steps:

[0006] Receive a first data packet sent by the target application, the first data packet including at least one message;

[0007] Determine whether the number of first target receivers corresponding to the first data packet exceeds a preset value;

[0008] If the determination is yes, then enter the extended mode, which is a data transmission mode that adds Ethernet ports. In the extended mode, the FPGA chip is in the working state.

[0009] Distribute at least one message from the first data packet to different queues according to preset rules;

[0010] At least one message from the first data packet is sent to the corresponding first target receiver via the Ethernet port corresponding to the queue.

[0011] In one possible implementation, determining whether the number of first target receivers corresponding to the first data packet exceeds a preset value may include the following steps:

[0012] Determine if a broadcast message exists in the first data packet;

[0013] If the determination is yes, then determine whether the number of first target receivers in the preset network segment exceeds the preset value.

[0014] In another possible implementation, after sending at least one message from the first data packet to the corresponding first target receiver via the queue's Ethernet port, the following steps may also be included:

[0015] Receive a first response message sent by at least one second target terminal, the first response message may include the MAC address and IP address of the second target receiver, the second target receiver being a terminal capable of receiving and / or sending data normally;

[0016] A mapping table is generated based on the MAC address of at least one second target receiver and the queue's working information;

[0017] The mapping table is stored in the FPGA chip.

[0018] In another possible implementation, after storing the mapping table in the FPGA chip, the following steps may also be included:

[0019] Receive a second data packet sent by the target application, the second data packet may include at least one configuration message, each configuration message containing the MAC address of a second target receiver;

[0020] According to the mapping table, the at least one configuration message is assigned to the corresponding queue;

[0021] The configuration message is sent from the Ethernet port of the queue to the corresponding second target receiver.

[0022] In another possible implementation, after sending at least one message from the first data packet to the corresponding first target receiver via the queue's Ethernet port, the following steps may also be included:

[0023] Receive the second response message from the first target receiver;

[0024] Determine if the MAC address in the second response message exists in the mapping table;

[0025] If the determination is negative, the MAC address entry is updated based on the MAC address in the second response message and the queue's working status. This update may refer to establishing a mapping relationship between the queue and the MAC address in the second response message.

[0026] Secondly, embodiments of this application provide a multi-port data transmission device based on an FPGA chip, which may include the following components: a communication module, a judgment module, and a control module;

[0027] The communication module can be used to receive a first data packet sent by a target application, which may include at least one message.

[0028] The judgment module can be used to determine whether the number of first target receivers corresponding to the first data packet exceeds a preset value;

[0029] The control module can be used to control the device to enter an extended mode when the number of first target receivers is greater than a preset value. This extended mode is a data transmission mode that adds Ethernet ports. In the extended mode, the FPGA chip in the device is in working state.

[0030] The control module can also be used to allocate at least one message in the first data packet to different queues according to preset rules;

[0031] The communication module can also be used to send at least one message from the first data packet to the corresponding first target receiver via the Ethernet port corresponding to the queue.

[0032] Thirdly, embodiments of this application provide a multi-port data transmission device based on an FPGA chip, which may include the following components: a processor, a memory, and a bus;

[0033] The processor and memory are connected via a bus, wherein the memory is used to store a set of program code, and the processor is used to call the program code stored in the memory to execute the method described in the first aspect.

[0034] Fourthly, embodiments of this application provide a computer-readable storage medium, comprising:

[0035] The computer-readable storage medium stores instructions that, when executed on a computer, implement the method described in the first aspect.

[0036] Fifthly, embodiments of this application provide a system for multi-port data transmission based on an FPGA chip. The system may include: a control terminal and at least one target receiving end. The control terminal may be configured with a target application and the means for multi-port data transmission based on an FPGA chip as described in the second and third aspects.

[0037] The target application on the control terminal can be used to generate a first data packet, which may include at least one message;

[0038] At least one target receiver can be used to receive at least one message in the first data packet.

[0039] In one possible implementation, the system may include:

[0040] The target application on the control terminal can also be used to generate a second data packet, which may include at least one configuration message, each configuration message may include the MAC address of a target receiver.

[0041] At least one target receiver can also be used to send a first response message and / or a second response message to a device for multi-port data transmission based on an FPGA chip. The first response message and / or the second response message may contain the MAC address and IP address of the target receiver.

[0042] By implementing the method of this application, the Ethernet ports of the network card on the control terminal can be expanded using the FPGA chip, thereby improving the data transmission capability of the network card. Furthermore, the working state of the network card can be flexibly adjusted according to the amount of data to be transmitted (or the number of packets to be transmitted), allowing for the rational selection of scenarios for expanding the network card's Ethernet ports and helping to avoid overkill in network card data transmission performance. Moreover, the method of this application eliminates the need to configure a switch in the data transmission system, which helps reduce industrial costs. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the architecture of a multi-port data transmission system based on an FPGA chip, provided in an embodiment of this application.

[0045] Figure 2 This is a flowchart illustrating a method for multi-port data transmission based on an FPGA chip, as provided in an embodiment of this application.

[0046] Figure 3a This is a schematic diagram of a multi-port data transmission device based on an FPGA chip provided in this application embodiment in a normal mode.

[0047] Figure 3b This is a schematic diagram of a multi-port data transmission device based on an FPGA chip provided in this application embodiment in an extended mode.

[0048] Figure 4 This is a schematic diagram of the composition of a multi-port data transmission device based on an FPGA chip provided in an embodiment of this application;

[0049] Figure 5 This is a schematic diagram of another multi-port data transmission device based on an FPGA chip provided in this application embodiment. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0051] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0052] In this document, the term "embodiment" means that a particular feature, result, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0053] To better understand the technical solutions of the embodiments of this application, a multi-port data transmission system based on an FPGA chip provided in the embodiments of this application will be introduced first. Please refer to... Figure 1 This is a schematic diagram of the architecture of a multi-port data transmission system based on an FPGA chip, provided in an embodiment of this application. The system includes a control terminal 110 and at least one target receiver 120.

[0054] The control terminal 110, also known as a terminal device, access terminal device, UE unit, UE station, mobile station, mobile station, remote station, remote terminal device, mobile device, UE terminal device, mobile terminal, wireless communication device, UE agent, or UE device, etc., can be fixed or mobile. Specific forms include mobile phones, tablets, computers with wireless transceiver capabilities, wearable terminal devices, etc. PC-based terminal devices, such as all-in-one computers, can have operating systems including but not limited to Linux, Unix, Windows series systems (e.g., Windows XP, Windows 7), Mac OS X, etc. Mobile terminal devices, such as smartphones, can have operating systems including but not limited to Android, iOS, Windows, etc. It is equipped with a target application 111 and a multi-port data transmission device 112 based on an FPGA chip. In this embodiment of the application, the target application 111 can be used to generate a first data packet, which may include at least one message; it can also be used to generate a second data packet, which may include at least one configuration message, each configuration message containing the MAC address of a target receiver.

[0055] More specifically, the multi-port data transmission device 112 based on the FPGA chip can take the form of a network interface card (NIC). Classified by the type of computer supported, NICs are mainly divided into standard Ethernet NICs and PCMCIA NICs: standard Ethernet NICs are used for desktop computer networking, while PCMCIA NICs are used for laptops. Classified by the transmission rate supported, NICs are mainly divided into four categories: 10Mbps NICs, 100Mbps NICs, 10 / 100Mbps adaptive NICs, and 1000Mbps NICs. Classified by the bus type supported, NICs can be mainly divided into ISA, EISA, PCI, etc. In this embodiment, the multi-port data transmission device 112 based on the FPGA chip is equipped with an FPGA chip. When the FPGA chip is in an active (or working) state, the number of Ethernet ports of the multi-port data transmission device 112 based on the FPGA chip (such as a gigabit NIC) doubles. Specifically, in this embodiment, the FPGA chip-based multi-port data transmission device 112 can be used to receive a first data packet sent by a target application 111; it can also be used to determine whether the number of first target receivers corresponding to the first data packet exceeds a preset value; it can also be used to control the device to enter an extended mode when the number of first target receivers is greater than the preset value. This extended mode is a data transmission mode that adds Ethernet ports. In the extended mode, the FPGA chip in the device is in a working state; it can also be used to allocate at least one message in the first data packet to different queues according to preset rules; and it can also be used to send at least one message in the first data packet to the corresponding first target receiver through the Ethernet port corresponding to the queue.

[0056] The target receiver 120 can be manifested as an industrial camera. More specifically, industrial cameras can be categorized by chip type (CCD camera, CMOS camera); by sensor structure (line scan camera, area scan camera); by scanning method (interlaced scan camera, progressive scan camera); by resolution (normal resolution camera, high resolution camera); by output signal method (analog camera, digital camera); by output color (monochrome (black and white) camera, color camera); by output signal speed (normal speed camera, high speed camera); and by response frequency range (visible light (normal) camera, infrared camera, ultraviolet camera, etc.). In this embodiment, the target receiver 120 can be used to receive messages from the first data packet sent by the FPGA chip-based multi-port data transmission device 112, and can also be used to send a first response message and / or a second response message to the FPGA chip-based multi-port data transmission device 112. The first response message and / or the second response message may contain the MAC address and IP address of the target receiver 120.

[0057] To better understand the technical solutions of the embodiments of this application, the following will be combined with... Figure 2 The steps described below provide a detailed explanation of a multi-port data transmission method based on an FPGA chip provided in this application embodiment.

[0058] Please see Figure 2 This is a flowchart illustrating a method for multi-port data transmission based on an FPGA chip, as provided in an embodiment of this application. Figure 2 As shown, the method may include the following steps:

[0059] S201, Receive the first data packet sent by the target application.

[0060] It should be noted that the first data packet may include at least one message. More often, one message corresponds to at least one target receiver.

[0061] S202, determine whether the number of first target receivers corresponding to the first data packet exceeds a preset value.

[0062] In one possible implementation, determining whether the number of first target receivers corresponding to the first data packet exceeds a preset value may include the following steps:

[0063] Determine if a broadcast message exists in the first data packet;

[0064] If the determination is yes, then determine whether the number of first target receivers in the preset network segment exceeds the preset value.

[0065] The aforementioned preset network segment can be defined by the first data packet, preset by a technician, or determined based on the network environment (network group, network segment) of the control terminal. It should be noted that the examples of methods for determining the preset network segment described above are for illustrative purposes only and should not be construed as limiting the scope of this application. The specific method for determining the preset network segment can be selected by a technician based on actual circumstances.

[0066] S203, if the determination is yes, then enter extended mode.

[0067] It should be noted that the extended mode is a data transmission mode that adds Ethernet ports. In the extended mode, the FPGA chip is in an active state.

[0068] For example, assuming a preset value of 4, if the first data packet includes 12 messages, where the target receiver corresponding to messages 1 to 3 is receiver 1, the target receiver corresponding to message 4 is receiver 2, the target receiver corresponding to message 5 is receiver 3, the target receiver corresponding to messages 6 to 10 is receiver 4, the target receiver corresponding to message 11 is receiver 5, and the target receiver corresponding to message 12 is receiver 6, then it can be determined that the number of first target receivers corresponding to the first data packet exceeds the preset value. Then, the FPGA chip is controlled to be in an active state (or working state), so that the multi-port data transmission device based on the FPGA chip (such as a gigabit network card) enters the extended mode, thereby obtaining more Ethernet ports.

[0069] More specifically, if the preset value is 4, and the information carried in the first data packet indicates that the preset network segment corresponding to the first preset data packet is network segment 1, and there are 8 target receivers in network segment 1, then it can be determined that the number of the first target receivers corresponding to the first data packet exceeds the preset value. Then, the FPGA chip is controlled to be in an active state (or working state), so that the multi-port data transmission device based on the FPGA chip (such as a gigabit network card) enters the extended mode, thereby obtaining more Ethernet ports.

[0070] Possibly, the method in this application embodiment also allows operators to manually switch the operating mode of the FPGA chip-based multi-port data transmission device. For example, if there are a large number of data transmission tasks (such as a control terminal needing to receive monitoring data sent by multiple target receivers), operators can switch the operating mode of the FPGA chip-based multi-port data transmission device from normal mode to extended mode in advance to handle the subsequent large number of data transmission tasks (such as receiving a large amount of monitoring data sent by target receivers).

[0071] Specifically, when the FPGA-based multi-port data transmission device is in extended mode, the FPGA chip is active, doubling the number of Ethernet ports. For an example, please refer to [link to example]. Figures 3a-3b , Figure 3a This is a schematic diagram illustrating a scenario in normal mode for a multi-port data transmission device based on an FPGA chip provided in an embodiment of this application. Figure 3b This is a schematic diagram illustrating a scenario where a multi-port data transmission device based on an FPGA chip, provided in an embodiment of this application, is in extended mode. Figure 3a In this context, the multi-port data transmission device based on an FPGA chip has physical port 1, physical port 2, physical port 3, physical port 4, Ethernet port 1, Ethernet port 2, Ethernet port 3, and Ethernet port 4, with each physical port corresponding to one Ethernet port; Figure 3bIn the FPGA chip-based multi-port data transmission device, there are physical ports 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, and 8, with each physical port corresponding to two Ethernet ports.

[0072] S204, at least one message in the first data packet is assigned to different queues according to a preset rule.

[0073] The preset rules can be a mapping table stored in the multi-port data transmission device based on the FPGA chip. The mapping table records the mapping relationship between the queue and the MAC address of the target receiver, which helps the multi-port data transmission device based on the FPGA chip (such as a gigabit network card) to select the appropriate queue to send the message according to the MAC address of the target receiver.

[0074] S205, at least one message in the first data packet is sent to the corresponding first target receiver through the Ethernet port corresponding to the queue.

[0075] In one possible implementation, after sending at least one message from the first data packet to the corresponding first target receiver via the Ethernet port corresponding to the queue, the following steps may also be included:

[0076] Receive a first response message sent by at least one second target receiver;

[0077] A mapping table is generated based on the MAC address of at least one second target receiver and the queue's working information;

[0078] The mapping table is stored in the FPGA chip.

[0079] The first response message may include the MAC address and IP address of the second target receiver, which is a terminal capable of receiving and / or sending data normally.

[0080] For example, suppose a multi-port data transmission device based on an FPGA chip sends a request message to receiver 1 to receiver 8. Receiver 1 and receiver 3 are in a fault state and therefore do not respond to the request message sent by the multi-port data transmission device based on an FPGA chip (i.e., receiver 1 and receiver 3 do not send an acknowledgment message to the multi-port data transmission device based on an FPGA chip). Then receiver 2, receiver 4, receiver 5, receiver 6, receiver 7, and receiver 8 are the second target receivers (i.e., terminals that can normally transmit data with the multi-port data transmission device based on an FPGA chip).

[0081] More specifically, queue operation information can refer to the data transmission load of the queue, or the number of MAC addresses mapped to the queue. For example, suppose existing receivers 9 and 10 are the second target receivers (the MAC addresses of receivers 9 and 10 are not mapped to queues in the FPGA-based multi-port data transmission device), and queue 1 has 10 messages to be transmitted, queue 2 has 3 messages to be transmitted, and queue 3 has no messages to be transmitted. Then, a mapping relationship can be established between the MAC address of receiver 9 and queue 3, and between the MAC address of receiver 10 and queue 4. For example, suppose queue 4 is mapped to 2 MAC addresses, queue 5 is mapped to 5 MAC addresses, and queue 6 is mapped to 0 MAC addresses. And existing receivers 11 and 12 are the second target receivers (the MAC addresses of receivers 11 and 12 are not mapped to queues in the FPGA-based multi-port data transmission device). Then, a mapping relationship can be established between the MAC address of receiver 11 and queue 6, and between receiver 12 and queue 4.

[0082] Specifically, the mapping table consists of at least one mapping relationship. After generating the mapping table, it can be stored in the Switch module of the FPGA chip. When a device for multi-port data transmission based on the FPGA chip (such as a gigabit network card) receives a data packet (such as the first data packet) sent by the target application, the Switch module can distribute the packet to the corresponding queue according to the mapping table and the MAC address of the target receiver as described in the packet.

[0083] In another possible implementation, after storing the mapping table in the FPGA chip, the following steps may also be included:

[0084] Receive a second data packet sent by the target application, the second data packet including at least one configuration message, each configuration message containing the MAC address of a second target receiver;

[0085] According to the mapping table, the at least one configuration message is assigned to the corresponding queue;

[0086] The configuration message is sent from the Ethernet port of the queue to the corresponding second target receiver.

[0087] Possibly, the configuration message in the second data packet is generated by the target application based on the information of the second target terminal. The information of the second target receiving terminal may include its type and MAC address, etc. The configuration message may include at least one of the following: the type, quantity, size, or time span of the data the control terminal wants to obtain from the second target receiving terminal. For example, from the perspective of the target receiving terminal, the configuration message could be interpreted as "The control terminal wants to obtain image data from 00:00 on December 23, 2022 to 12:30 on December 25, 2022," or "The control terminal wants to obtain 3GB of image data from the target receiving terminal," or "The control terminal wants to obtain 5,000 image data from the target receiving terminal," or "The control terminal wants to obtain 47MB of audio data from the target receiving terminal," etc. It should be noted that the above examples of configuration messages are only for illustrating the methods of the embodiments of this application in more detail and should not be construed as limiting the embodiments of this application.

[0088] In another possible implementation, after sending at least one message from the first data packet to the corresponding first target receiver via the queue's Ethernet port, the following steps may also be included:

[0089] Receive the second response message from the first target receiver;

[0090] Determine whether the MAC address in the second response message exists in the mapping table;

[0091] If the determination is negative, the MAC address entry is updated based on the MAC address in the second response message and the working status of the queue. The update refers to establishing a mapping relationship between the queue and the MAC address in the second response message.

[0092] For example, if a new receiver 13 is added to a preset network segment, after the control terminal (or the device for multi-port data transmission based on an FPGA chip) sends a request message, the control terminal (or the device for multi-port data transmission based on an FPGA chip) can identify that the MAC address in the response message of receiver 13 does not exist in the mapping table. Therefore, the mapping relationship between the MAC address of receiver 13 and the queue can be established by referring to the steps for establishing the mapping relationship described above. Alternatively, if the control terminal (or the device for multi-port data transmission based on an FPGA chip) sends a request message to receiver 14, and receiver 14 has not previously had a communication connection with the control terminal (or the device for multi-port data transmission based on an FPGA chip), the control terminal (or the device for multi-port data transmission based on an FPGA chip) can identify that the MAC address in the response message of receiver 14 does not exist in the mapping table. Therefore, the mapping relationship between the MAC address of receiver 14 and the queue can be established by referring to the steps for establishing the mapping relationship described above. Alternatively, even if there is a mapping relationship between the MAC address of receiver 15 and the queue, when receiver 15 transmits data to the control terminal (or the device for multi-port data transmission based on FPGA chip) for the first time after changing the network card, the control terminal (or the device for multi-port data transmission based on FPGA chip) can recognize that the MAC address in the (response) message of receiver 15 does not exist in the mapping table. Therefore, the mapping relationship between the MAC address of receiver 15 and the queue can be established by referring to the steps for establishing the mapping relationship above.

[0093] As can be seen, the method of this application embodiment can flexibly adjust the network card's working mode according to the number of target receivers corresponding to the message to be transmitted, enabling the network card to cope with more diverse data transmission scales. Moreover, the data transmission system corresponding to this application embodiment does not require the configuration of a switch, which helps to reduce industrial costs.

[0094] The apparatus involved in the embodiments of this application is described below with reference to the accompanying drawings.

[0095] Please see Figure 4 This is a schematic diagram of a multi-port data transmission device based on an FPGA chip provided in an embodiment of this application. The device may include: a communication module 410, a judgment module 420, and a control module 430.

[0096] Communication module 410 can be used to receive a first data packet sent by a target application, the first data packet may include at least one message;

[0097] The judgment module 420 can be used to determine whether the number of first target receivers corresponding to the first data packet exceeds a preset value;

[0098] The control module 430 can be used to control the device to enter an extended mode when the number of first target receivers is greater than a preset value. This extended mode is a data transmission mode that adds Ethernet ports. In the extended mode, the FPGA chip in the device is in working state.

[0099] The control module 430 can also be used to allocate at least one message in the first data packet to different queues according to preset rules;

[0100] The communication module 410 can also be used to send at least one message in the first data packet to the corresponding first target receiver through the Ethernet port corresponding to the queue.

[0101] In one possible implementation, the device may further include:

[0102] The judgment module 420 can also be used to determine whether a broadcast message exists in the first data packet;

[0103] The judgment module 420 can also be used to determine whether the number of first target receivers in the preset network segment exceeds a preset value when there is a broadcast message in the first data packet.

[0104] In another possible implementation, the device may further include:

[0105] The communication module 410 can also be used to receive a first response message sent by at least one second target terminal. The first response message may include the MAC address and IP address of the second target receiver, which is a terminal that can normally receive and / or send data.

[0106] The control module 430 can also be used to generate a mapping table based on the MAC address of at least one second target receiver and the working information of the queue;

[0107] The control module 430 can also be used to store the mapping table in the FPGA chip.

[0108] In another possible implementation, the device may further include:

[0109] The communication module 410 can also be used to receive a second data packet sent by the target application. The second data packet may include at least one configuration message, and each configuration message contains the MAC address of a second target receiver.

[0110] The control module 430 can also be used to allocate the at least one configuration message to the corresponding queue according to the mapping table;

[0111] The communication module 410 can also be used to send the configuration message from the Ethernet port of the queue to the corresponding second target receiver.

[0112] In another possible implementation, the device may further include:

[0113] The communication module 410 can also be used to receive a second response message from the first target receiver;

[0114] The judgment module 420 can also be used to determine whether the MAC address in the second response message exists in the mapping table;

[0115] The control module 430 can also be used to update the MAC address entry in the mapping table based on the MAC address in the second response message and the working status of the queue when the MAC address in the second message does not exist in the mapping table. This update may refer to establishing a mapping relationship between the queue and the MAC address in the second response message.

[0116] Please see Figure 5 This is a schematic diagram illustrating the composition of another multi-port data transmission device based on an FPGA chip provided in this application embodiment. The device may include:

[0117] The processor 510, memory 520, and I / O interface 530 are communicatively connected. The memory 520 stores instructions, and the processor 510 executes the instructions stored in the memory 520 to achieve the above. Figure 1 The corresponding methods and steps.

[0118] The processor 510 executes the instructions stored in the memory 520 to control the I / O interface 530 to receive and send signals, thus completing the steps in the above method. The memory 520 may be integrated into the processor 510 or may be disposed separately from the processor 510.

[0119] The memory 520 may also include a storage system 521, a cache 522, and RAM 523. The cache 522 is a primary memory located between the RAM 523 and the CPU, composed of static RAM chips (SRAM). It has a relatively small capacity but a much higher speed than main memory, approaching the speed of the CPU. The RAM 523 is an internal memory that directly exchanges data with the CPU. It can be read and written at any time (except during refresh) and is very fast, typically serving as temporary data storage for the operating system or other running programs. The three components combine to realize the function of the memory 520.

[0120] As one implementation approach, the functionality of I / O interface 530 can be implemented using transceiver circuitry or dedicated transceiver chips. Processor 510 can be implemented using dedicated processing chips, processing circuitry, processors, or general-purpose chips.

[0121] As another implementation, the apparatus provided in this application embodiment can be implemented using a general-purpose computer. The program code that implements the functions of processor 510 and I / O interface 530 is stored in memory 520, and the general-purpose processor implements the functions of processor 510 and I / O interface 530 by executing the code in memory 520.

[0122] For the concepts, explanations, detailed descriptions, and other steps related to the technical solutions provided in the embodiments of this application, please refer to the descriptions of the method steps performed by the device in the foregoing method or other embodiments, which will not be repeated here.

[0123] As another implementation of this embodiment, a computer-readable storage medium is provided, on which instructions are stored, which, when executed, perform the methods in the above-described method embodiments.

[0124] As another implementation of this embodiment, a computer program product containing instructions is provided, which, when executed, perform the method in the above method embodiment.

[0125] Those skilled in the art will understand that, for ease of explanation, Figure 5 Only one memory and processor are shown in the illustration. In a real terminal or server, multiple processors and memories may exist. Memory can also be called storage medium or storage device, etc., and this application does not limit this.

[0126] It should be understood that in the embodiments of this application, the processor may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0127] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0128] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor.

[0129] It should be noted that the memories described herein are intended to include, but are not limited to, these and any other suitable types of memories.

[0130] In addition to the data bus, this bus may also include a power bus, a control bus, and a status signal bus. However, for clarity, all buses are labeled "bus" in the diagram.

[0131] It should also be understood that the first, second, third, fourth and various numerical designations used herein are merely for descriptive convenience and are not intended to limit the scope of this application.

[0132] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0133] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0134] In the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0135] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0136] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0138] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0139] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0140] This application also provides a computer storage medium storing a computer program that is executed by a processor to implement some or all of the steps of any of the FPGA chip-based multi-port data transmission methods described in the above method embodiments.

[0141] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the FPGA chip-based multi-port data transmission methods described in the above method embodiments.

[0142] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for multi-port data transmission based on an FPGA chip, characterized in that, The method includes the following steps: Receive a first data packet sent by the target application, the first data packet including at least one message; Determine whether the number of first target receivers corresponding to the first data packet exceeds a preset value; If the determination is yes, then enter the extended mode, which is a data transmission mode that adds Ethernet ports. In the extended mode, the FPGA chip is in the working state. At least one message in the first data packet is assigned to different queues according to preset rules; At least one message in the first data packet is sent to the corresponding first target receiver through the Ethernet port corresponding to the queue. Determining whether the number of first target receivers corresponding to the first data packet exceeds a preset value includes the following steps: Determine whether a broadcast message exists in the first data packet; If the determination is yes, then determine whether the number of the first target receivers in the preset network segment exceeds the preset value.

2. The method according to claim 1, characterized in that, After sending at least one message from the first data packet to the corresponding first target receiver through the Ethernet port of the queue, the method further includes the following steps: Receive a first response message sent by at least one second target receiving end, wherein the first response message includes the MAC address and IP address of the second target receiving end, and the second target receiving end is a terminal that can normally receive and / or send data; A mapping table is generated based on the MAC address of the at least one second target receiving end and the queue's working information; The mapping table is stored in the FPGA chip.

3. The method according to claim 2, characterized in that, After storing the mapping table in the FPGA chip, the following steps are also included: Receive a second data packet sent by the target application, the second data packet including at least one configuration message, each configuration message containing the MAC address of a second target receiver; According to the mapping table, the at least one configuration message is assigned to the corresponding queue; The configuration message is sent from the Ethernet port of the queue to the corresponding second target receiver.

4. The method according to claim 3, characterized in that, After sending at least one message from the first data packet to the corresponding first target receiver through the Ethernet port of the queue, the method further includes the following steps: Receive the second response message from the first target receiver; Determine whether the MAC address in the second response message exists in the mapping table; If the determination is negative, the MAC address entry is updated based on the MAC address in the second response message and the working status of the queue. The update refers to establishing a mapping relationship between the queue and the MAC address in the second response message.

5. A device for multi-port data transmission based on an FPGA chip, characterized in that, The device includes: a communication module, a judgment module, and a control module; The communication module is used to receive a first data packet sent by the target application, the first data packet including at least one message; The judgment module is used to determine whether the number of first target receivers corresponding to the first data packet exceeds a preset value; The control module is used to control the device to enter an extended mode when the number of the first target receivers is greater than the preset value. The extended mode is a data transmission mode that adds Ethernet ports. In the extended mode, the FPGA chip in the device is in a working state. The control module is further configured to allocate at least one message in the first data packet to different queues according to preset rules; The communication module is further configured to send at least one message in the first data packet to the corresponding first target receiving end through the Ethernet port corresponding to the queue; The judgment module is also used to determine whether there is a broadcast message in the first data packet; The judgment module is further configured to determine whether the number of first target receivers in a preset network segment exceeds the preset value when a broadcast message exists in the first data packet.

6. A device for multi-port data transmission based on an FPGA chip, characterized in that, The device includes: A processor, a memory, and a bus, wherein the processor and the memory are connected via the bus, wherein the memory is used to store a set of program code, and the processor is used to call the program code stored in the memory to execute the method as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, include: The computer-readable storage medium stores instructions that, when executed on a computer, implement the method as described in any one of claims 1-4.

8. A multi-port data transmission system based on an FPGA chip, characterized in that, The system includes: a control terminal and at least one target receiving terminal, wherein the control terminal is configured with a target application and a device for multi-port data transmission based on an FPGA chip as described in any one of claims 5-6; The target application on the control terminal is used to generate a first data packet, which includes at least one message. The at least one target receiver is used to receive at least one message in the first data packet.

9. The system according to claim 8, characterized in that, The system includes: The target application on the control terminal is also used to generate a second data packet, the second data packet including at least one configuration message, each configuration message containing the MAC address of a target receiver; The at least one target receiving end is further configured to send a first response message and / or a second response message to the FPGA chip-based multi-port data transmission device, wherein the first response message and / or the second response message contains the MAC address and IP address of the target receiving end.

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