A single-ended SAR ADC circuit with a lockable capacitor array and its operation method

Abstract

The application provides a single-ended SAR ADC circuit with lockable capacitor array and a working method thereof, which comprises a sample and hold circuit, a comparator, a SAR control logic module and a DAC capacitor array with a lock switch. Before starting the analog-digital conversion, it is necessary to determine whether the lock switch in the capacitor array needs to be closed. Therefore, the input signal is compared with a specific voltage first, and according to the comparison result, the off state of the lock switch is judged. If the lock switch is open, the single-ended SAR ADC carries out normal analog-digital conversion. If the lock switch is closed, the capacitor connected with the lock switch in the capacitor array of the single-ended SAR ADC will be locked and kept connected to GND. When the input signal is small, by closing the lock switch, the high-order capacitor is locked, the unnecessary switching of the capacitor array is reduced, and the power consumption of the capacitor array and the switch can be greatly saved at the cost of less hardware overhead.

Description

Technical Field

[0001] This invention is applicable to the field of analog integrated circuit design, and particularly relates to a single-ended SAR ADC circuit and its operating method. Background Technology

[0002] With the rapid development of microelectronics and digital signal processing technologies, analog-to-digital converters (ADCs) have been widely used in various fields and have made significant progress. Summarizing the development process of ADCs, it is easy to see that ADCs are currently developing towards lower power consumption, higher speed, and higher resolution.

[0003] There are many different architectures of ADCs, and each type has its own advantages and disadvantages. SAR ADCs were proposed early on. Their fundamental characteristic is serial operation; the entire process, from sampling the input signal to the completion of the ADC analog-to-digital conversion, continues. Due to this serial operation, SAR ADCs must wait until the entire analog-to-digital conversion process is finished before sampling the input signal again. Typically, compared to Flash ADCs and Pipelined ADCs, SAR ADCs have a lower sampling rate; compared to Σ-Δ ADCs, SAR ADCs have lower accuracy.

[0004] However, with the rapid advancement of semiconductor manufacturing processes, SAR ADCs have seen the greatest improvement. This is because SAR ADCs only have one analog circuit—the comparator—so the limitations imposed on analog circuits by the reduction in semiconductor manufacturing processes have little impact on SAR ADC design. On one hand, the continuous miniaturization of semiconductor manufacturing processes has led to a significant increase in the operating speed of digital circuits, resulting in a substantial improvement in the speed of the switched capacitor circuits in SAR ADCs, thus removing the SAR ADC from the category of low-speed ADCs. On the other hand, the reduction in power supply voltage has further highlighted the low power consumption advantage of SAR ADCs. Moreover, the use of digital correction techniques can also greatly improve the quantization accuracy of SAR ADCs. In summary, optimizing the core modules of SAR ADCs, such as the sampling switch, comparator, SAR logic, and DAC array, is the main method for reducing the figure of merit (FoM) of SAR ADCs.

[0005] Just like the development process of ADCs, as application demands increase, the requirements for the accuracy and speed of SAR ADCs become more and more stringent. The design of SAR ADC circuits also faces many challenges, and it is necessary to continuously develop towards low power consumption, high speed and high resolution, and often a trade-off needs to be made among these three.

[0006] Therefore, this invention proposes a single-ended SAR ADC circuit with a lockable capacitor array. Summary of the Invention

[0007] In view of the above analysis of the development trend of SAR ADCs, the present invention aims to propose a single-ended SAR ADC circuit with a lockable capacitor array to meet the requirements of development.

[0008] The technical solution of the present invention:

[0009] A capacitor array lockable single-ended SAR ADC circuit, comprising:

[0010] The sampling switch circuit includes a sampling switch S1 and a sampling capacitor C. S The first terminal of sampling switch S1 is connected to the input signal VIN, and the second terminal is connected to the sampling capacitor C. S The first terminal, sampling capacitor C S The second terminal is connected to GND.

[0011] A DAC capacitor array with a locking switch, comprising capacitors, a switch, an optional switch, and a locking switch, wherein there are N+1 capacitors, C0, C1, C2...C... N The capacitance value is arranged according to the weighted bits of the binary representation, such as C, 2. 0 C,2 1 C,2 2 C···2 N-1 C, where N<12; the N+1 capacitors C0, C1, C2...C N All the first terminals are connected together, and the second terminal of capacitor C0 is connected to GND. Capacitors C0, C1, C2...C N The second terminal is connected to the optional switches SW1, SW2, ... SW1 respectively. N The first terminal is connected; the optional switches SW1, SW2...SW N The second terminal is connected to VREF, and the third terminal is connected to GND. The optional switches SW1, SW2...SW N Both can be selectively connected to GND or VREF; the first terminal of the locking switch is also connected to the high-level capacitor C. N The second terminal is connected to GND; the second terminal of switch S4 is connected to GND, and the first terminal is connected to N+1 capacitors C0, C1, C2...C N The first terminal is connected to form the output VDAC of the DAC capacitor array.

[0012] The comparator, whose positive input VP is compared with C in the sampling switch circuit. SThe first terminal of switch S2 is connected to the negative input VN of the comparator, and the second terminal of switch S3 is connected to the second terminal of switch S2. The first terminal of switch S2 is connected to the voltage VTH. The first terminal of switch S3 is also connected to the negative input VN of the comparator, and the second terminal is connected to the output VDAC of the DAC capacitor array.

[0013] The SAR control logic module has its input connected to the output of the comparator, and can control the on / off state of the lockout switch and the selectable switches SW1, SW2...SW in the DAC capacitor array with the lockout switch. N The connection status of GND and VREF, and the numeric codes D1, D2, ... D N .

[0014] As described above, the capacitor array lockable single-ended SAR ADC proposed in this invention includes a sample-and-hold circuit, a comparator, a SAR control logic module, and a DAC capacitor array with a lock-in switch. Before starting analog-to-digital conversion, it is necessary to determine whether the lock-in switch in the capacitor array needs to be closed. Therefore, the input signal is first compared with a specific voltage. Based on the comparison result, the off state of the lock-in switch is determined. If the lock-in switch is open, the single-ended SAR ADC performs normal analog-to-digital conversion; if the lock-in switch is closed, the capacitors in the capacitor array of the single-ended SAR ADC connected to the lock-in switch will be locked and remain locked to GND.

[0015] The beneficial effects of this invention are as follows: when the input signal is relatively small, by closing the locking switch to lock the high-level capacitor, unnecessary switching of the capacitor array can be reduced. At the cost of less hardware overhead, the power consumption generated by the capacitor array and the switch can be greatly saved. Attached Figure Description

[0016] Figure 1 This is the basic circuit structure diagram of a single-ended SAR ADC.

[0017] Figure 2 This is a circuit diagram of the single-ended SAR ADC with a lockable capacitor array proposed in this invention.

[0018] Figure 3 This is a circuit diagram of a 4-bit capacitor array lockable single-ended SAR ADC proposed in this invention.

[0019] Figure 4 This is a flowchart illustrating the operation of the single-ended SAR ADC with a lockable capacitor array proposed in this invention.

[0020] Figure 5The following are waveforms of the binary search algorithm for the 4-bit capacitor array lockable single-ended SAR ADC proposed in this invention, with the analog input voltage being relatively small, under two conditions: the lock switch is open and closed. (a) is the algorithm waveform when the lock switch is open, and (b) is the algorithm waveform when the lock switch is closed.

[0021] In the diagram: 1-Sampling switch circuit; 2-Comparator; 3-SAR control logic module; 4-DAC capacitor array with latching switch. Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific examples:

[0023] Figure 1 This is a basic diagram of a single-ended SAR ADC circuit, consisting of a sample-and-hold circuit, a comparator, a DAC binary capacitor array, SAR control logic circuitry, and an N-bit register. The principle of this structure is simple; a brief explanation will follow to illustrate the capacitor array lockable single-ended SAR ADC proposed in this invention.

[0024] The analog input voltage is held by the sample-and-hold circuit. The most significant bit (MSB) of the DAC's binary capacitor array is first set to "1", while the other bits are "0", meaning the DAC output VDAC = VREF / 2. Then, the first comparison is performed, comparing VIN with VDAC to determine if VIN is greater than or less than VDAC. If VIN is greater than VDAC, the comparator outputs a logic level of "1", and the most significant bit (MSB) remains "1". If VIN is less than VDAC, the comparator outputs a logic level of "0", and the most significant bit (MSB) changes to "0". Subsequently, the SAR control logic shifts the second most significant bit and sets it to "1" before performing a second comparison, and so on, until the least significant bit (LSB) is determined, completing the analog-to-digital conversion. This algorithm is called the binary search algorithm.

[0025] Figure 2 This invention presents a single-ended SAR ADC with a lockable capacitor array. It improves upon the most basic single-ended SAR ADC structure. The working principle of this invention's single-ended SAR ADC with a lockable capacitor array is as follows: the positive input VP of the comparator is connected to the sampling switch circuit, and the negative input of the comparator is connected to VTH and the DAC capacitor array respectively through two switches. The DAC capacitor array is connected to the highest-order capacitor C... N A locking switch connected to GND was added at the location. When the locking switch is closed, capacitor C... NThe capacitor will be locked to GND. Before starting the analog-to-digital conversion, it is necessary to determine whether the latching switch in the capacitor array needs to be closed. The analog input voltage VIN is first compared with VTH. Based on the comparison result, it is determined whether the latching switch is closed or open, and then a binary search algorithm is performed to complete the analog-to-digital conversion. When the input signal is relatively small, closing the latching switch to lock the high-order capacitors reduces unnecessary switching of the capacitor array. This significantly reduces the power consumption of the capacitor array and switches with minimal hardware overhead.

[0026] The following specific examples illustrate the implementation of the present invention.

[0027] Figure 3 This is a circuit diagram of a 4-bit capacitor array lockable single-ended SAR ADC proposed in this invention. Figure 4 This is a flowchart illustrating the operation of the capacitor array lockable single-ended SAR ADC proposed in this invention. Wherein, Figure 3 In the 4-bit DAC capacitor array with a latching switch, the capacitors C0, C1, C2, C3, and C4 are distributed according to binary weights, with the capacitance values ​​in the following ratio: C0:C1:C2:C3:C4 = C:2. 0 C:2 1 C:2 2 C:2 3 C = C:C:2C:4C:8C.

[0028] Combination Figure 3 and Figure 4 The following describes the embodiments of the present invention.

[0029] First, the ADC begins sampling the analog input signal. Switch S1 is closed, and the analog input signal VIN is sampled by the sample-and-hold circuit to the sampling capacitor C. S Then, switch S1 is opened, and the analog input signal VIN is held at the positive input VP of the comparator; simultaneously, switch S2 is closed and switch S3 is opened, connecting the negative input VN of the comparator to VTH. Since this locking switch is connected to capacitor C4, the value of VTH is equal to the weight of capacitor C4, VREF / 2, that is, VTH = VREF / 2. At this time, VP = VIN, VN = VTH.

[0030] Then, the comparator compares the values ​​of VP and VN to determine whether the latching switch in the capacitor array needs to be closed. Based on this comparison, it decides whether the latching switch in the DAC capacitor array needs to be closed. If VP is greater than VN, the latching switch is open. If VP is less than VN, the latching switch is closed, and capacitor C4 will be latched and remain connected to GND.

[0031] After determining the closed / closed state of the lockout switches in the capacitor array, switch S2 opens and switch S3 closes, connecting the negative input of the comparator to the output VDAC of the DAC capacitor array. Simultaneously, switch S4 closes, and selectable switches SW1, SW2, SW3, and SW4 are all connected to GND, resetting the entire DAC capacitor array.

[0032] Next, analog-to-digital conversion is performed, which involves the binary search algorithm described above. At this point, due to the different states of the locking switch, the following two situations will occur.

[0033] Scenario 1: The locking switch is in the open state, and capacitor C4 is not locked. In this case, the normal binary search algorithm applies. First, switch S4 is opened, ending the reset state. The SAR control logic module controls the optional switch SW4, which connects to the highest-order MSB capacitor C4 in the DAC capacitor array, to VREF. At this time, the output of the DAC capacitor array VDAC = VREF / 2, which means the negative input of the comparator VN = VDAC = VREF / 2. The positive input of the comparator VP = VIN. The first comparison of the analog-to-digital conversion begins; the comparator operates, comparing the magnitudes of VP and VN. If VP is greater than VN, the SAR control logic module outputs the highest bit D1 = 1. The optional switch SW4, connected to the highest bit MSB capacitor C4, remains connected to VREF, and the optional switch SW3, connected to the second highest bit capacitor C3, is connected to VREF. The value of VDAC will become VREF*3 / 4. If VP is less than VN, the SAR control logic module outputs D1 = 0. The optional switch SW4, connected to the highest bit MSB capacitor C4, switches to GND, and the optional switch SW3, connected to the second highest bit capacitor C3, is connected to VREF. The value of VDAC will become VREF*1 / 4. Then, a second comparison is performed for the analog-to-digital conversion. The comparator works, comparing the magnitudes of VP and VN again to determine the magnitude of the second highest bit D2. This process continues until the lowest bit D4 is determined, completing the entire analog-to-digital conversion process.

[0034] Scenario 2: The locking switch is closed, and capacitor C4 is locked. This differs slightly from the binary search algorithm described above. First, switch S4 is opened, ending the reset state. Since the locking switch is closed, capacitor C4 is locked, and the SAR control logic module outputs the highest bit D1 = 0. It's important to note that this result is locked, skipping the first comparison in the binary algorithm. The SAR control logic module does not change the connection state of the optional switch SW4 connected to capacitor C4 (MSB). Next, the binary search algorithm is performed again. The SAR control logic module directly controls the optional switch SW3 connected to capacitor C3 (second highest bit) to connect to VREF, and the value of VDAC will become VREF*1 / 4. Then, the first comparison for analog-to-digital conversion is performed. The comparator works, comparing the magnitudes of VP and VN to determine the magnitude of the second most significant bit D2 and whether the optional switch SW3 should remain connected to VREF. If VP is greater than VN, the SAR control logic module controls the output of the most significant bit D2 = 1, the optional switch SW3 connected to the second most significant bit capacitor C3 remains connected to VREF, and the optional switch SW2 connected to capacitor C2 is connected to VREF. The value of VDAC will become VREF*3 / 8. If VP is less than VN, the SAR control logic module controls the output of D2 = 0, the optional switch SW3 connected to the second most significant bit capacitor C3 switches to GND, and the optional switch SW2 connected to capacitor C2 is connected to VREF. The value of VDAC will become VREF*1 / 8. Then, the second comparison for analog-to-digital conversion is performed. The comparator works again, comparing the magnitudes of VP and VN to determine the magnitude of D3, and so on until the least significant bit D4 is determined. The entire analog-to-digital conversion process is then complete.

[0035] Figure 5 This invention presents the binary search algorithm waveforms for a 4-bit capacitor array lockable single-ended SAR ADC, with the lock switch open and closed when the analog input voltage is relatively small. Figure 5 (a) in the diagram is the algorithm waveform when the locking switch is open. Figure 5 (b) in the figure shows the algorithm waveform when the locking switch is closed; it can be seen that when VIN is less than VTH = VREF / 2, it is obvious that when the locking switch is closed, during the analog-to-digital conversion, one unnecessary switching of the capacitor array is reduced, thereby reducing power consumption.

[0036] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Similarly, a locking switch can be added to the second-highest capacitor, or even to all capacitors.

[0037] According to the binary search algorithm described above, when a single-ended SAR ADC performs analog-to-digital conversion, determining the Nth bit requires connecting the corresponding capacitor to VREF. Then, based on the comparison result, it's determined whether the capacitor for that bit should remain connected to VREF. If the comparison result is "1", the capacitor remains connected to VREF, avoiding unnecessary charging and discharging consumption. If the comparison result is "0", the capacitor switches to GND, resulting in unnecessary charging and discharging consumption. If the highest-order capacitor is locked by closing the lockout switch when the analog input voltage VIN is low, this most energy-intensive and unnecessary switching can be reduced during the binary search algorithm, significantly decreasing power consumption during analog-to-digital conversion.

[0038] In summary, this invention proposes a single-ended SAR ADC circuit with a lockable capacitor array, including a sample-and-hold circuit, a comparator, a SAR control logic module, and a DAC capacitor array with a locking switch. Before starting analog-to-digital conversion, it is necessary to determine whether the locking switch in the capacitor array needs to be closed. Therefore, the input signal is first compared with a specific voltage. Based on the comparison result, the off state of the locking switch is determined. If the locking switch is open, the single-ended SAR ADC performs normal analog-to-digital conversion; if the locking switch is closed, the capacitors in the capacitor array of the single-ended SAR ADC connected to the locking switch will be locked, maintaining a locked connection to GND. When the input signal is relatively small, locking the higher-order capacitors by closing the locking switch can reduce unnecessary switching of the capacitor array, significantly saving power consumption generated by the capacitor array and switches with minimal hardware overhead.

Claims

1. A single-ended SAR ADC circuit with a lockable capacitor array, characterized in that, include: The sampling switch circuit includes a sampling switch S1 and a sampling capacitor C. S The first terminal of sampling switch S1 is connected to the input signal VIN, and the second terminal is connected to the sampling capacitor C. S The first terminal, sampling capacitor C S The second terminal is connected to GND; A DAC capacitor array with a locking switch, comprising capacitors, a switch, an optional switch, and a locking switch; the array has N+1 capacitors, C0, C1, C2, ..., C1. N The capacitance values ​​are arranged according to the binary weight bits, where N < 12; the N+1 capacitors C0, C1, C2...C N All the first terminals are connected together, and the second terminal of capacitor C0 is connected to GND. Capacitors C0, C1, C2...C N The second terminal is connected to the optional switches SW1, SW2, ... SW1 respectively. N The first terminal is connected; the optional switches SW1, SW2...SW N The second terminal is connected to VREF, and the third terminal is connected to GND. The optional switches SW1, SW2...SW N Both can be selectively connected to GND or VREF; the first terminal of the locking switch is also connected to the high-level capacitor C. N The second terminal is connected to GND; the second terminal of switch S4 is connected to GND, and the first terminal is connected to N+1 capacitors C0, C1, C2...C N The first terminal is connected to form the output VDAC of the DAC capacitor array; The comparator, whose positive input VP is compared with C in the sampling switch circuit. S The first terminal of switch S2 is connected to the negative input VN of the comparator, and the second terminal of switch S3 is connected to the second terminal of switch S2. The first terminal of switch S2 is connected to the voltage VTH. The first terminal of switch S3 is also connected to the negative input VN of the comparator, and the second terminal is connected to the output VDAC of the DAC capacitor array. The SAR control logic module has its input connected to the output of the comparator, and can control the on / off state of the lockout switch and the selectable switches SW1, SW2...SW in the DAC capacitor array with the lockout switch. N The connection status of GND and VREF, and the numeric codes D1, D2, ... D N .

2. The single-ended SAR ADC circuit with a lockable capacitor array according to claim 1, characterized in that, In a DAC capacitor array with a latching switch: not only in the highest bit capacitor C N Add a locking switch, or add a locking switch to the second-highest capacitor or add a locking switch to all capacitors; the first terminal of the locking switch is connected to the corresponding capacitor C. i The second terminal is connected to GND, and i = 0 to N.

3. The method of operating a single-ended SAR ADC circuit with a lockable capacitor array as described in claim 1 or 2, characterized in that, The positive input VP of the comparator is connected to the sampling switch circuit, and the negative input of the comparator is connected to VTH and the DAC capacitor array respectively through two switches. The DAC capacitor array has a capacitor C at the highest bit. N When the locking switch at the location is closed, capacitor C N It will be locked to GND; before starting the analog-to-digital conversion, it is necessary to determine whether the lockout switch in the capacitor array needs to be closed; let the analog input voltage VIN be compared with VTH first, and decide whether the lockout switch is closed or open based on the comparison result, and then perform the binary search algorithm to complete the analog-to-digital conversion; When the input signal is relatively small, the high-level capacitor is locked by closing the lock switch, thus reducing the switching of the capacitor array.

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