Semiconductor device

Abstract

Provided is a semiconductor device capable of suppressing a decrease in signal quality. The semiconductor device of the present embodiment includes: a substrate having a first surface and a first pad and a second pad provided on the first surface; a chip stack in which a plurality of first semiconductor chips are stacked, the first semiconductor chips each having a second surface facing the first surface, a third surface on the opposite side of the second surface, and a third pad and a fourth pad provided on the third surface; a first wire group including a plurality of first wires electrically connecting the first pad and the third pad of each of the first semiconductor chips; a second wire electrically connecting the second pad and the fourth pad of the first semiconductor chip closest to the substrate among the plurality of first semiconductor chips; and a third wire electrically connecting the fourth pads of the plurality of first semiconductor chips.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2021-201023 (filed on December 10, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor device. Background Technology

[0004] Semiconductor devices may have a semiconductor controller chip and multiple stacked semiconductor memory chips on a wiring substrate. Signals are transmitted using lines that electrically connect the signal pads of the semiconductor controller chip and the signal pads of the semiconductor memory chips. In semiconductor devices, it is desirable, for example, that the signals transmitted between the semiconductor controller chip and the semiconductor memory chips have high waveform quality. Summary of the Invention

[0005] Provide semiconductor devices that can suppress signal quality degradation.

[0006] The semiconductor device of this embodiment includes: a substrate having a first surface and a first pad and a second pad provided on the first surface; a chip stack having a plurality of first semiconductor chips stacked thereon, each first semiconductor chip having a second surface facing the first surface, a third surface opposite to the second surface, and a third pad and a fourth pad provided on the third surface; a first line group including a plurality of first lines electrically connecting the first pads to the third pads of each of the first semiconductor chips; a second line electrically connecting the second pads to the fourth pad of the first semiconductor chip closest to the substrate among the plurality of first semiconductor chips; and a third line electrically connecting the fourth pads of each of the plurality of first semiconductor chips. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a top view showing an example of the structure of the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a schematic diagram illustrating an example of the connection relationship between the semiconductor controller chip and the semiconductor memory chip in the first embodiment.

[0010] Figure 4 This is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 5 It continues Figure 4 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0012] Figure 6 It continues Figure 5 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0013] Figure 7 It continues Figure 6 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0014] Figure 8 It continues Figure 7 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0015] Figure 9 It continues Figure 8 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0016] Figure 10 This is a schematic diagram illustrating an example of the connection relationship between a semiconductor controller chip and a semiconductor memory chip in a comparative example.

[0017] Figure 11 This is a cross-sectional view showing an example of the structure of a semiconductor device according to a modified example of the first embodiment.

[0018] Figure 12 This is a top view showing an example of the structure of a semiconductor device according to a variation of the first embodiment.

[0019] Figure 13 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the second embodiment.

[0020] Figure 14 This is a top view showing an example of the structure of the semiconductor device according to the second embodiment.

[0021] Figure 15 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the third embodiment.

[0022] Figure 16 This is a top view showing an example of the structure of the semiconductor device according to the third embodiment.

[0023] Figure 17 This is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the third embodiment.

[0024] Figure 18 It continues Figure 16A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0025] Figure 19 It continues Figure 17 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0026] Figure 20 It continues Figure 18 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0027] Figure 21 It continues Figure 19 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0028] Figure 22 It continues Figure 20 A diagram illustrating an example of a method for manufacturing a semiconductor device.

[0029] Figure 23 This is a cross-sectional view showing an example of the structure of the semiconductor device according to the fourth embodiment.

[0030] Figure 24 This is a top view showing an example of the structure of the semiconductor device according to the fourth embodiment.

[0031] Explanation of reference numerals in the attached figures

[0032] 1 Semiconductor device, 2 Wiring substrate, 3 Semiconductor controller chip, 4a-4d Semiconductor memory chip, 4aS-4dS edge, 5a electrode pad, 5b electrode pad, 6 electrode pad, 8-17 electrode pad, 18-24 line, 26 electrode pad, 27-30 line, C connecting conductor, C1 electrode pad, C2 wiring, C3 line, F1-F5 surface, WG1 line group, WG2 line group. Detailed Implementation

[0033] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. In the following embodiments, the vertical direction of the wiring substrate refers to the relative direction with the surface where the semiconductor chip is disposed facing upwards, and may sometimes differ from the vertical direction along the acceleration due to gravity. The drawings are schematic or conceptual, and the proportions of the parts may not be identical to reality. In the specification and drawings, elements identical to those described in the previously existing drawings are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0034] (First Implementation)

[0035] Figure 1This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a wiring board 2, a semiconductor chip (semiconductor controller chip) 3, semiconductor chips (semiconductor memory chips) 4a to 4d, wires 18 to 24, an insulating seal 25, and external connection terminals 7.

[0036] The wiring substrate 2 is, for example, a printed circuit board or other substrate. The wiring substrate 2 can be connected to the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d via lines 18 to 24. The wiring substrate 2 has a wiring layer (not shown).

[0037] Semiconductor controller chip 3 and semiconductor memory chips 4a-4d are disposed above surface F1 of wiring substrate 2, for example, by an adhesive layer (not shown). The adhesive layer is, for example, a film-like resin (DAF, Die Attach Film).

[0038] Semiconductor memory chips 4a-4d are, for example, NAND chips. Semiconductor memory chips 4a-4d include, for example, semiconductor elements. These semiconductor elements are, for example, memory cell arrays or CMOS (Complementary Metal Oxide Semiconductor) circuits. Semiconductor memory chips 4a-4d are bonded to the wiring substrate 2 and other semiconductor memory chips 4a-4d by an adhesive layer (not shown). The adhesive layer is, for example, a film-like resin. Figure 1 In the example shown, semiconductor memory chips 4a-4d are stacked in four layers longitudinally via an adhesive layer. The longitudinal direction is approximately perpendicular to the upper surface F1 of the wiring substrate 2. The stacked semiconductor memory chips 4a-4d are, for example, memory chips with the same structure. Furthermore, the number of layers of semiconductor memory chips 4a-4d is not limited to four and can be arbitrarily changed. The number of layers of semiconductor memory chips 4a-4d is set according to the required storage capacity. Additionally, as... Figure 1 As shown, semiconductor memory chips 4a-4d are stacked in a stepped, staggered manner. This prevents other semiconductor memory chips 4a-4d from overlapping on the electrode pads 10-17 of the semiconductor memory chips 4a-4d, and allows lines 19, 21-24 to connect to the electrode pads 10-17 of the semiconductor memory chips 4a-4d.

[0039] Semiconductor controller chip 3, for example, includes CMOS circuitry. Semiconductor controller chip 3 is electrically connected to semiconductor memory chips 4a-4d and controls the operation of semiconductor memory chips 4a-4d. Figure 1As shown, the semiconductor controller chip 3 is disposed adjacent to the semiconductor memory chips 4a-4d, and is bonded to the wiring substrate 2 by an adhesive layer (not shown). The adhesive layer is, for example, a film-like resin. Alternatively, the semiconductor controller chip 3 may be disposed above the semiconductor memory chips 4a-4d.

[0040] Lines 18 and 20 electrically connect the wiring substrate 2 to the semiconductor controller chip 3. The materials of lines 18 and 20 are conductive metals such as gold, silver, or copper.

[0041] Lines 19, 21-24 electrically connect the wiring substrate 2 to the semiconductor memory chips 4a-4d. The material of lines 19, 21-24 is, for example, a conductive metal such as gold, silver, or copper.

[0042] The insulating seal 25 is, for example, a resin such as epoxy resin. The insulating seal 25 seals the semiconductor controller chip 3, the semiconductor memory chips 4a-4d, and the wires 18-24 on the upper surface of the wiring substrate 2. Thus, the insulating seal 25 protects the semiconductor controller chip 3, the semiconductor memory chips 4a-4d, and the wires 18-24 from external impacts or the influence of external gases.

[0043] The external connection terminal 7 is, for example, a metal bump such as a solder ball. In this case, the semiconductor device 1 has a BGA (Ball Grid Array) package structure. The external connection terminal 7 electrically connects the semiconductor device 1 to an external mounting substrate (not shown). The material of the external connection terminal 7 is a conductive metal such as solder. The external connection terminal 7 is provided on the lower surface of the wiring board 2. That is, the external connection terminal 7 is provided on the side of the wiring board 2 opposite to the surface F1 where the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d are disposed.

[0044] Next, the structure of the wiring board 2 will be described.

[0045] The wiring substrate 2 has a surface F1 and electrode pads 5a, 5b, and 6. The electrode pads 5a, 5b, and 6 are disposed on the surface F1.

[0046] Next, the structure of semiconductor controller chip 3 will be explained.

[0047] The semiconductor controller chip 3 has surfaces F4 and F5, and electrode pads 8 and 9. Surface F4 is the surface opposite to surface F1 of the wiring substrate 2. Surface F5 is the surface opposite to surface F4. Electrode pads 8 and 9 are disposed on surface F5.

[0048] Next, the structure of semiconductor memory chips 4a to 4d will be described.

[0049] Semiconductor memory chip 4a has surfaces F2 and F3 and electrode pads 10 and 11. Semiconductor memory chip 4b has surfaces F2 and F3 and electrode pads 12 and 13. Semiconductor memory chip 4c has surfaces F2 and F3 and electrode pads 14 and 15. Semiconductor memory chip 4d has surfaces F2 and F3 and electrode pads 16 and 17. Surface F2 is the surface opposite to surface F1 of wiring substrate 2. Surface F3 is the surface opposite to surface F2. Electrode pads 10 to 17 are provided on surface F3 of the corresponding semiconductor memory chips 4a to 4d.

[0050] Next, the details of the configuration of electrode pads 5a, 5b, 6, 8-17 and lines 18-24 will be explained.

[0051] Figure 2 This is a top view showing an example of the structure of the semiconductor device 1 according to the first embodiment. Figure 2 The AA line represents the cross-sectional view, i.e. Figure 1 The corresponding cross-section. Furthermore, in Figure 1 In the middle, lines 18 to 24 are also represented as side views.

[0052] Electrode pads 5a and 5b are, for example, electrode pads for power supply or grounding voltage supply. Electrode pad 5a is disposed on surface F1 near the semiconductor controller chip 3. Electrode pad 5b is disposed on surface F1 near the semiconductor memory chips 4a to 4d.

[0053] Electrode pad 6 is, for example, an electrode pad used for signal transmission. Electrode pad 6 is disposed on surface F1 between semiconductor controller chip 3 and semiconductor memory chips 4a to 4d.

[0054] The outer edge of the semiconductor controller chip 3, as observed from the normal direction of the substrate surface of the wiring substrate 2, is approximately rectangular.

[0055] Electrode pad 8 is, for example, an electrode pad for supplying a reference voltage for power or ground. Electrode pad 9 is, for example, an electrode pad for signal transmission. Electrode pads 8 and 9 are arranged alternately on surface F5 along one side (side 3S) of semiconductor controller chip 3.

[0056] The outer edge shape of the semiconductor memory chips 4a to 4d, as observed from the normal direction of the substrate surface of the wiring substrate 2, is approximately rectangular.

[0057] Semiconductor memory chips 4a to 4d are stacked in a manner that constitutes a chip stack. The semiconductor memory chips 4a to 4d are stacked in a staggered manner along the X direction. As a result, electrode pads 10 to 17 are exposed from the semiconductor memory chips 4a to 4d stacked above them, thus enabling connection to lines 19, 21 to 24. The semiconductor memory chips 4a to 4d are also stacked in a staggered manner along the Y direction. As will be explained later, this is to facilitate direct connection of the semiconductor memory chips 4a to 4d to the electrode pads 6, respectively. That is, the semiconductor memory chips 4a to 4d are electrically connected to the electrode pads 6 of the wiring substrate 2 without passing through other semiconductor memory chips 4a to 4d.

[0058] That is, multiple semiconductor memory chips 4a-4d are stacked in a staggered manner in the X direction (first direction), which is the direction from each edge 4aS-4dS of the semiconductor memory chips 4a-4d towards the edge opposite to the edge 4aS-4dS. The multiple semiconductor memory chips 4a-4d are also stacked in a staggered manner along the Y direction, which is perpendicular to both the X and Z directions (stacking directions). Figure 2 In the example shown, multiple semiconductor memory chips 4a to 4d are stacked from the bottom layer to the top layer in a staggered manner in the -Y direction.

[0059] Electrode pad 10 is, for example, an electrode pad for supplying a reference voltage for power or ground. Electrode pad 11 is, for example, an electrode pad for signal transmission. Electrode pads 10 and 11 are arranged alternately along one side (side 4aS) of the semiconductor memory chip 4a on surface F3. In this case, the electrode pads can also be arranged in the order of electrode pads for power supply, electrode pads for signals, electrode pads for ground, electrode pads for signals, and electrode pads for power supply.

[0060] Electrode pad 12 is, for example, an electrode pad for supplying a reference voltage for power or ground. Electrode pad 13 is, for example, an electrode pad for signal transmission. Electrode pads 12 and 13 are arranged alternately along one side of the semiconductor memory chip 4b on surface F3. In this case, the electrode pads can also be arranged in the order of power supply electrode pad, signal electrode pad, ground electrode pad, signal electrode pad, and power supply electrode pad.

[0061] Electrode pad 14 is, for example, an electrode pad for supplying a reference voltage for power or ground. Electrode pad 15 is, for example, an electrode pad for signal transmission. Electrode pads 14 and 15 are arranged alternately along one side of the semiconductor memory chip 4c on surface F3. In this case, the electrode pads can also be arranged in the order of power supply electrode pad, signal electrode pad, ground electrode pad, signal electrode pad, and power supply electrode pad.

[0062] Electrode pad 16 is, for example, an electrode pad for supplying a reference voltage for power or ground. Electrode pad 17 is, for example, an electrode pad for signal transmission. Electrode pads 16 and 17 are arranged alternately along one side (side 4dS) of the semiconductor memory chip 4d on surface F3. In this case, the electrode pads can also be arranged in the order of electrode pads for power supply, electrode pads for signals, electrode pads for ground, electrode pads for signals, and electrode pads for power supply.

[0063] Line 18 is, for example, a line for supplying a reference voltage for power or ground. Line 18 electrically connects the electrode pads 5a of the wiring board 2 to the electrode pads 8 of the semiconductor controller chip 3.

[0064] Multiple lines 19 are, for example, lines for supplying reference voltage for power or ground. Lines 19 electrically connect the electrode pads 5b of the wiring substrate 2 to the electrode pads 10, 12, 14, and 16 of the semiconductor memory chips 4a-4d that are closest to the wiring substrate 2 among the stacked semiconductor memory chips. In addition, other lines 19 electrically connect the electrode pads 10, 12, 14, and 16 of adjacent semiconductor memory chips 4a-4d among the stacked semiconductor memory chips.

[0065] Line 19 electrically connects the electrode pad 5b of the wiring substrate 2 to the electrode pad 10 of the semiconductor memory chip 4a. Additionally, line 19 electrically connects the electrode pad 10 of the semiconductor memory chip 4a to the electrode pad 12 of the semiconductor memory chip 4b. Furthermore, line 19 electrically connects the electrode pad 12 of the semiconductor memory chip 4b to the electrode pad 14 of the semiconductor memory chip 4c. Finally, line 19 electrically connects the electrode pad 14 of the semiconductor memory chip 4c to the electrode pad 16 of the semiconductor memory chip 4d.

[0066] Lines 19 are arranged layer by layer according to the number of semiconductor memory chips 4a to 4d. Therefore, lines 19 are configured to connect the electrode pads 5b of the wiring substrate 2 and the electrode pads 10, 12, 14, and 16 of the semiconductor memory chips 4a to 4d in a single, continuous line. Furthermore, lines 19 are arranged with the loop height as low as possible. This allows for the connection of the wiring substrate 2 to the semiconductor memory chips 4a to 4d with shorter lines 19.

[0067] Line 20 is, for example, a signal transmission line. Line 20 electrically connects the electrode pads 6 of the wiring board 2 to the electrode pads 9 of the semiconductor controller chip 3. Furthermore, line 20 is sometimes also referred to as the connecting conductor C.

[0068] Line 21 is, for example, a signal transmission line. Line 21 electrically connects the electrode pads 6 of the wiring board 2 to the electrode pads 11 of the semiconductor memory chip 4a.

[0069] Line 22 is, for example, a signal transmission line. Line 22 electrically connects the electrode pads 6 of the wiring board 2 to the electrode pads 13 of the semiconductor memory chip 4b.

[0070] Line 23 is, for example, a signal transmission line. Line 23 electrically connects the electrode pads 6 of the wiring board 2 to the electrode pads 15 of the semiconductor memory chip 4c.

[0071] Line 24 is, for example, a signal transmission line. Line 24 electrically connects the electrode pads 6 of the wiring board 2 to the electrode pads 17 of the semiconductor memory chip 4d.

[0072] That is, multiple lines 21 to 24 electrically connect the electrode pads 6 of the wiring substrate 2 to the electrode pads 11, 13, 15, and 17 of the semiconductor memory chips 4a to 4d respectively.

[0073] Lines 21-24 are sometimes collectively referred to as line group WG1. Figure 2 In the example shown, the wiring board 2 has two electrode pads 6. Additionally, two wire groups WG1 are provided.

[0074] The signals transmitted (transmit and receive) between the semiconductor memory chips 4a to 4c and the semiconductor controller chip 3 are transmitted through electrode pads 6, 11, 13, 15, 17, 9, lines 21 to 24 and line 20 (connecting conductor C).

[0075] exist Figure 2 In the example shown, semiconductor memory chips 4a-4d are stacked in a staggered manner along the Y direction and are directly connected to electrode pads 6. Figure 2 In the top view shown, electrode pads 9, 11, 13, 15, and 17 are arranged at approximately equal intervals around electrode pad 6. Figure 2 In the top view shown, lines 20 to 24 are set to approximately the same length. Therefore, as shown in the reference... Figure 3 As explained, it can suppress signal quality degradation.

[0076] Figure 3 This is a schematic diagram illustrating an example of the connection relationship between the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d in the first embodiment. Figure 3 This example illustrates a scenario where semiconductor memory chip 4d transmits signals and semiconductor controller chip 3 receives signals. Therefore, electrode pad 17 of semiconductor memory chip 4d is the transmitting end, and electrode pad 9 of semiconductor controller chip 3 is the receiving end.

[0077] Signals transmitted from electrode pad 17 are transmitted, for example, via electrode pad 6 to electrode pads 9, 11, 13, and 15. The signals are reflected, for example, at electrode pads 9, 11, 13, 15, and 17 (semiconductor controller chip 3 and semiconductor memory chips 4a-4d). The signal waveform received at the receiving end, i.e., electrode pad 9, is formed, for example, by combining the signals incident on electrode pads 9, 11, 13, 15, and 17 with the signals reflected from electrode pads 9, 11, 13, 15, and 17.

[0078] Here, with the transmission delay (delay time) from the central electrode pad 6 to electrode pads 9, 11, 13, 15, and 17 being approximately the same, the timing of signal reflection is approximately consistent, thus canceling out the effects of reflection. This suppresses the degradation of the synthesized signal waveform's quality. As a result, the semiconductor controller chip 3 can receive signals more appropriately.

[0079] Transmission delay can be calculated, for example, using the electrical characteristics (signal transmission characteristics) of lines 20-24 and electrode pads 9, 11, 13, 15, and 17. The signal transmission characteristics of lines 20-24 are determined, for example, by their thickness and length. The signal transmission characteristics of electrode pads 9, 11, 13, 15, and 17 are determined, for example, by their capacitance.

[0080] Therefore, preferably, the signal transmission characteristics from electrode pad 6 to each semiconductor memory chip 4a-4d are approximately the same as the signal transmission characteristics from electrode pad 6 to semiconductor controller chip 3. That is, electrode pads 11, 13, 15, 17, electrode pad 9, line group WG1 (lines 21-24), and line 20 (connecting conductor C) are arranged in such a way that the signal transmission characteristics (delay time) from electrode pad 6 to each semiconductor memory chip 4a-4d are approximately the same as the signal transmission characteristics from electrode pad 6 to semiconductor controller chip 3.

[0081] When semiconductor memory chips 4a to 4d are sliced ​​from a single wafer, they are formed in the same process. Therefore, the capacitances of the electrode pads 11, 13, 15, and 17 of each of the semiconductor memory chips 4a to 4d are generally approximately the same. On the other hand, the capacitance of the electrode pad 9 of the semiconductor controller chip 3 is sometimes different from the capacitances of the electrode pads 11, 13, 15, and 17 of the semiconductor memory chips 4a to 4d.

[0082] Lines 20 to 24 are usually formed using the same method, and their thicknesses are approximately the same. The length of line 20 is sometimes set differently from that of lines 21 to 24, depending on the difference between the capacitance of the electrode pad 9 of the semiconductor controller chip 3 and the capacitance of the electrode pads 11, 13, 15, and 17 of the semiconductor memory chips 4a to 4d.

[0083] Furthermore, if we are concerned with the connection between electrode pads 6 and semiconductor memory chips 4a-4d, we need to ensure that the signal transmission characteristics of lines 21-24 are approximately the same. That is, the deviation of the signal transmission characteristics of lines 21-24 should be below a specified value. More specifically, the deviation of the signal transmission characteristics of lines 21-24 relative to the average value should be less than 10%.

[0084] The thickness and length of lines 21 to 24 are preferably approximately the same. That is, the deviation in thickness and length of lines 21 to 24 is preferably below a specified value (e.g., less than 10% relative to the average value). Lines 21 to 24 are typically formed by the same method, and the thickness of lines 21 to 24 is approximately the same. Therefore, lines 21 to 24 are preferably arranged in a manner that makes them approximately the same length.

[0085] In addition, Figure 2 In the diagram, lines 21 through 24, viewed from above, are represented as having approximately the same length. On the other hand, in... Figure 1 In this diagram, due to the difference in the height of the rings, the lengths of lines 21 to 24 are represented differently. To make the lengths of lines 21 to 24 approximately the same, for example, the lengths of lines 21 to 24 when viewed from above can be made different according to the difference in the height of the rings. For example, the maximum height of the rings could gradually decrease as it changes from line 24 to line 21.

[0086] Next, the connection method of lines 19 and 21 to 24 connected to semiconductor memory chips 4a to 4d will be described.

[0087] Figures 4-9 This is a diagram illustrating an example of a method for manufacturing the semiconductor device 1 according to the first embodiment. Figures 4-9 The image above shows cross-sectional views of semiconductor memory chips 4a to 4d. Figures 4-9 The following figure shows a top view of semiconductor memory chips 4a to 4d.

[0088] First, such as Figure 4 As shown, semiconductor memory chips 4a-4d are mounted on wiring substrate 2. The semiconductor memory chips 4a-4d are stacked in a staggered manner in the X and Y directions.

[0089] Next, as Figure 5 As shown, multiple lines 19 are formed. Next, as... Figure 6 As shown, line 21 is formed. Next, as... Figure 7 As shown, line 22 is formed. Next, as... Figure 8 As shown, line 23 is formed. Next, as... Figure 9 As shown, line 24 is formed.

[0090] like Figures 5-9As shown, in order to easily form lines 21 to 24, they are formed sequentially starting from the line with the lower ring height.

[0091] As described above, according to the first embodiment, the deviation of the signal transmission characteristics (transmission delay) of each of lines 21 to 24 is below a predetermined value. Therefore, signal quality degradation can be suppressed. As a result, the semiconductor controller chip 3 can receive signals more appropriately.

[0092] Next, as a comparative example, we will explain the case where lines 21 to 24 are connected in a single stroke, just like multiple lines 19 supplying the reference voltage.

[0093] Figure 10 This is a schematic diagram illustrating an example of the connection relationship between the semiconductor controller chip 3 and the semiconductor memory chips 4a to 4d in the comparative example. Figure 10 This example illustrates a scenario where semiconductor memory chip 4a transmits signals and semiconductor controller chip 3 receives signals. Therefore, electrode pad 11 of semiconductor memory chip 4a is the transmitting end, and electrode pad 9 of semiconductor controller chip 3 is the receiving end.

[0094] The signal sent from electrode pad 11 is transmitted to electrode pad 6 and electrode pad 13. The signal is reflected at electrode pad 17 (semiconductor memory chip 4d). This reflection causes a degradation in the waveform quality of the synthesized signal. Additionally, at least a portion of the signal is also reflected, for example, at electrode pads 13 and 15 (semiconductor memory chips 4b and 4c). This reflection also causes a degradation in the waveform quality of the synthesized signal. Furthermore, the higher the signal speed, the more likely a waveform quality degradation will occur.

[0095] In contrast, in the first embodiment, such as Figure 3 As shown, electrode pads 9, 11, 13, 15, and 17 of the semiconductor controller chip 3 and semiconductor memory chips 4a-4d are connected to electrode pad 6, respectively. By making the transmission delays of the semiconductor chips approximately the same with electrode pad 6 as the center, the waveform quality degradation caused by signal reflection can be suppressed. Therefore, the waveform quality of the waveform received by the semiconductor controller chip 3 can be improved.

[0096] Furthermore, the signal transmission characteristics are such that the influence of the lines is sometimes greater than that of the electrode pads. In this case, the deviation of the signal transmission characteristics of each of the multiple lines 21-24 and line 20 can also be below a specified value (e.g., 10% relative to the average value).

[0097] Furthermore, the semiconductor controller chip 3 is not limited to a controller chip, but can also be other semiconductor chips. Similarly, the semiconductor memory chips 4a-4d are not limited to memory chips, but can also be other semiconductor chips.

[0098] Furthermore, the number of 4a to 4d electrodes in a semiconductor memory chip is not limited to four. The number of lines (line groups) and electrode pads is also not limited to... Figure 1 and Figure 2 The example shown.

[0099] (A variation of the first embodiment)

[0100] Figure 11 This is a cross-sectional view showing an example of the structure of a semiconductor device 1, a modified example of the first embodiment. Figure 12 This is a top view showing an example of the structure of a semiconductor device 1 according to a modified example of the first embodiment. The modified example of the first embodiment differs from the first embodiment in the structure of the connecting conductor C.

[0101] The connecting conductor C includes electrode pads C1, wiring C2, and wire C3. Furthermore, in a variation of the first embodiment, wire 20 is not provided.

[0102] Electrode pad C1 is, for example, an electrode pad for signal transmission. Electrode pad C1 is disposed on surface F1 of wiring board 2.

[0103] Wiring C2 is, for example, a signal transmission wiring. Wiring C2 is disposed on wiring substrate 2, electrically connecting electrode pad 6 of wiring substrate 2 to electrode pad C1 of wiring substrate 2. In addition, wiring C2 may also include columnar electrodes (Via) within wiring substrate 2.

[0104] Line C3 is, for example, a signal transmission line. Line C3 electrically connects the electrode pads 9 of the semiconductor controller chip 3 to the electrode pads C1 of the wiring substrate 2.

[0105] The signal transmission characteristics (transmission delay) are adjusted in the same manner as in the first embodiment, regardless of the structure of the connecting conductor C. That is, the electrode pads 11, 13, 15, 17, electrode pad 9, wire group WG1 (wires 21 to 24), electrode pad C1, wiring C2, and wire C3 are arranged in such a way that the signal transmission characteristics from the electrode pad 6 to each semiconductor memory chip 4a to 4d are approximately the same as the signal transmission characteristics from the electrode pad 6 to the semiconductor controller chip 3.

[0106] Since the other structures of the semiconductor device 1 in the modified example of the first embodiment are the same as the corresponding structures of the semiconductor device 1 in the first embodiment, detailed descriptions of them are omitted.

[0107] The structure of the connecting conductor C can also be changed as in the variation of the first embodiment. The semiconductor device 1 of the variation of the first embodiment can achieve the same effect as the first embodiment.

[0108] (Second Implementation)

[0109] Figure 13 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the second embodiment. Figure 14 This is a top view showing an example of the structure of the semiconductor device 1 according to the second embodiment. Figure 14 CC line representation and cross-sectional view Figure 13 The corresponding cross-section.

[0110] The second embodiment differs from the first embodiment in that it also includes lines 27 to 30.

[0111] The wiring substrate 2 has multiple electrode pads 6. Figure 14 In the example shown, the wiring board 2 has two electrode pads 6.

[0112] The wiring board 2 also has electrode pads 26 disposed between adjacent electrode pads 6. The electrode pads 26 are, for example, electrode pads for power supply or ground voltage supply.

[0113] The semiconductor memory chip 4a has multiple electrode pads 11. Figure 14 In the example shown, the semiconductor memory chip 4a has two electrode pads 11. The adjacent electrode pads 11 are configured to sandwich the electrode pad 10 in the middle.

[0114] The semiconductor memory chip 4b has multiple electrode pads 13. Figure 14 In the example shown, the semiconductor memory chip 4b has two electrode pads 13. The adjacent electrode pads 13 are configured to sandwich the electrode pad 12 in the middle.

[0115] The semiconductor memory chip 4c has multiple electrode pads 15. Figure 14 In the example shown, the semiconductor memory chip 4c has two electrode pads 15. The adjacent electrode pads 15 are configured to sandwich the electrode pad 14 in the middle.

[0116] The semiconductor memory chip 4d has multiple electrode pads 17. Figure 14 In the example shown, the semiconductor memory chip 4d has two electrode pads 17. The adjacent electrode pads 17 are configured to sandwich the electrode pad 16 in the middle.

[0117] Semiconductor device 1 includes multiple line groups WG1 corresponding to multiple electrode pads 6, multiple electrode pads 11, multiple electrode pads 13, multiple electrode pads 15, and multiple electrode pads 17. Figure 14 In the example shown, semiconductor device 1 has two wire groups WG1.

[0118] Here, when the two wire groups WG1 are configured close together, the signal quality may be reduced due to crosstalk between the wire groups WG1.

[0119] Therefore, the semiconductor device 1 also includes a line group WG2 disposed between adjacent line groups WG1.

[0120] Line group WG2 contains multiple lines 27 to 30.

[0121] Line 27 is, for example, a line for supplying a reference voltage for power or ground. Line 27 electrically connects the electrode pads 26 of the wiring board 2 to the electrode pads 10 of the semiconductor memory chip 4a. As described above, the electrode pads 10 connected to line 27 are arranged between adjacent electrode pads 11.

[0122] Furthermore, the line 27 connected to the semiconductor memory chip 4a is positioned between the two lines 21 connected to the semiconductor memory chip 4a within each adjacent line group WG1. For example... Figure 13 As shown, line 27 has a loop shape that is approximately the same as that of line 21 when viewed from the Y direction.

[0123] Line 28 is, for example, a reference voltage supply for power or ground. Line 28 electrically connects the electrode pads 26 of the wiring board 2 to the electrode pads 12 of the semiconductor memory chip 4b. As described above, the electrode pads 12 connected to line 28 are arranged between adjacent electrode pads 13.

[0124] Additionally, the line 28 connected to the semiconductor memory chip 4b is positioned between the two lines 22 connected to the semiconductor memory chip 4b within each adjacent line group WG1. For example... Figure 13 As shown, line 28 has a loop shape that is approximately the same as that of line 22 when viewed from the Y direction.

[0125] Line 29 is, for example, a line for supplying a reference voltage for power or ground. Line 29 electrically connects the electrode pads 26 of the wiring board 2 to the electrode pads 14 of the semiconductor memory chip 4c. As described above, the electrode pads 14 connected to line 29 are arranged between adjacent electrode pads 15.

[0126] Additionally, the line 29 connected to the semiconductor memory chip 4c is positioned between the two lines 23 connected to the semiconductor memory chip 4c within each adjacent line group WG1. For example... Figure 13 As shown, line 29 has a loop shape that is approximately the same as that of line 23 when viewed from the Y direction.

[0127] Line 30 is, for example, a line for supplying a reference voltage for power or ground. Line 30 electrically connects the electrode pads 26 of the wiring board 2 to the electrode pads 16 of the semiconductor memory chip 4d. As described above, the electrode pads 16 connected to line 30 are arranged between adjacent electrode pads 17.

[0128] Additionally, the line 30 connected to the semiconductor memory chip 4d is positioned between the two lines 24 connected to the semiconductor memory chip 4d within each adjacent line group WG1. For example... Figure 13 As shown, line 30 has a loop shape that is approximately the same as that of line 24 when viewed from the Y direction.

[0129] By using lines 27-30 (line group WG2), crosstalk between adjacent line groups WG1 can be suppressed. As a result, signal quality degradation can be suppressed.

[0130] Since the other structures of the semiconductor device 1 in the second embodiment are the same as the corresponding structures of the semiconductor device 1 in the first embodiment, detailed descriptions of them are omitted.

[0131] As in the second embodiment, lines 27 to 30 may also be provided. The semiconductor device 1 of the second embodiment can achieve the same effects as the first embodiment. In addition, variations of the first embodiment may be combined into the second embodiment.

[0132] (Third Implementation)

[0133] Figure 15 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the third embodiment. Figure 16 This is a top view showing an example of the structure of the semiconductor device 1 according to the third embodiment. Figure 16 The DD line representation and cross-sectional view are... Figure 15 The corresponding cross-section.

[0134] The third embodiment differs from the first embodiment in the stacked structure of the semiconductor memory chips 4a to 4d.

[0135] exist Figure 16 In the example shown, the stacked structure of semiconductor memory chips 4a to 4d is alternately misaligned in the Y direction. That is, semiconductor memory chip 4b is stacked in a misaligned position relative to semiconductor memory chip 4a in the -Y direction. Semiconductor memory chip 4c is stacked in a misaligned position relative to semiconductor memory chip 4b in the +Y direction. Semiconductor memory chip 4d is stacked in a misaligned position relative to semiconductor memory chip 4c in the -Y direction.

[0136] That is, multiple semiconductor memory chips 4a-4d are stacked in a staggered manner along the Z direction, alternating between the Y direction (perpendicular to the X direction and the Z direction, e.g., the +Y direction) and the opposite direction of the Y direction (e.g., the -Y direction). This allows the semiconductor memory chips 4a-4d to be stacked in a staggered manner along the Y direction, so that lines 21-24 do not intersect when viewed from above in the Z direction. Furthermore, compared with the reference... Figure 2Compared with the first embodiment described, the arrangement area of ​​semiconductor memory chips 4a to 4d in the Y direction can be suppressed.

[0137] Furthermore, the misalignment amount in the Y direction of each of the semiconductor memory chips 4a to 4d can be changed within a range that prevents lines 21 to 24 from overlapping when viewed from above.

[0138] like Figure 15 As shown, the heights of the loops of lines 21 to 24 differ depending on the distance between electrode pad 6 and electrode pads 11, 13, 15, and 17. For example, the loop of line 21 connected to the semiconductor memory chip 4a closest to electrode pad 6 is the tallest. The loop of line 24 connected to the semiconductor memory chip 4d furthest from electrode pad 6 is the shortest. That is, the maximum height of the loop of line 24 connected to the electrode pad 17 of the semiconductor memory chip 4d furthest from the wiring substrate 2 is lower than the maximum height of the loop of line 21 connected to the electrode pad 11 of the semiconductor memory chip 4a closest to the wiring substrate 2.

[0139] Thus, in the second embodiment, by adjusting the height of the ring, the lengths of lines 21 to 24 are adjusted to be approximately the same.

[0140] Since the other structures of the semiconductor device 1 in the third embodiment are the same as the corresponding structures of the semiconductor device 1 in the first embodiment, detailed descriptions of them are omitted.

[0141] Next, the connection method of lines 19 and 21 to 24 connected to semiconductor memory chips 4a to 4d will be described.

[0142] Figures 17-22 This is a diagram illustrating an example of a method for manufacturing the semiconductor device 1 according to the third embodiment. Figures 17-22 The image above shows cross-sectional views of semiconductor memory chips 4a to 4d. Figures 17-22 The following figure shows a top view of semiconductor memory chips 4a to 4d.

[0143] First, such as Figure 17 As shown, semiconductor memory chips 4a-4d are mounted on wiring substrate 2. The semiconductor memory chips 4a-4d are stacked in a staggered manner in the X and Y directions.

[0144] Next, as Figure 18 As shown, multiple lines 19 are formed. Next, as... Figure 19 As shown, line 24 is formed. Next, as... Figure 20 As shown, line 23 is formed. Next, as... Figure 21 As shown, line 22 is formed. Next, as... Figure 22 As shown, line 21 is formed.

[0145] like Figures 17-22 As shown, in order to easily form lines 21 to 24, they are formed sequentially starting from the line with the lower ring height.

[0146] As in the third embodiment, the stacking structure of the semiconductor memory chips 4a to 4d can be changed within the range of connectable lines 19, 21 to 24. The semiconductor device 1 of the third embodiment can achieve the same effects as the first embodiment. In addition, variations of the first embodiment can be combined into the third embodiment.

[0147] (Fourth Implementation)

[0148] Figure 23 This is a cross-sectional view showing an example of the structure of the semiconductor device 1 according to the fourth embodiment. Figure 24 This is a top view showing an example of the structure of the semiconductor device 1 according to the fourth embodiment. Figure 24 The EE line representation and cross-sectional view are as follows: Figure 23 The corresponding cross-section.

[0149] The fourth embodiment differs from the third embodiment in that it also includes lines 27-30. That is, the fourth embodiment is a combination of the second and third embodiments.

[0150] As described in the second embodiment, crosstalk between adjacent line groups WG1 can be suppressed by using lines 27-30 (line group WG2). As a result, signal quality degradation can be suppressed.

[0151] As in the fourth embodiment, lines 27 to 30 may also be provided. The semiconductor device 1 of the fourth embodiment can achieve the same effect as the third embodiment. In addition, variations of the first embodiment may be combined into the fourth embodiment.

[0152] Some embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, characterized in that, have: A substrate having a first surface and a first pad and a second pad disposed on the first surface; A chip stack having multiple first semiconductor chips stacked thereon, each first semiconductor chip having a second surface facing the first surface, a third surface opposite to the second surface, and a third pad and a fourth pad disposed on the third surface. A first line group includes a plurality of first lines that electrically connect the first pad to the third pad of each of the first semiconductor chip; The second line electrically connects the second pad to the fourth pad of the first semiconductor chip that is closest to the substrate among a plurality of first semiconductor chips. as well as The third line electrically connects the fourth pads of each of the plurality of first semiconductor chips. The third pad and the fourth pad are arranged on the third surface along the first edge of the first semiconductor chip. Multiple first semiconductor chips are stacked in a staggered manner in a first direction, which is a direction from the first edge of each first semiconductor chip toward a second edge on the opposite side of the first edge. The first pad is an electrode pad for signal transmission, the second pad is an electrode pad for power supply or ground voltage supply, the third pad is an electrode pad for signal transmission, and the fourth pad is an electrode pad for power supply or ground reference voltage supply.

2. The semiconductor device according to claim 1, characterized in that, The maximum height of the loop of the first line connected to the third pad of the first semiconductor chip furthest from the substrate is lower than the maximum height of the loop of the first line connected to the third pad of the first semiconductor chip closest to the substrate.

3. The semiconductor device according to claim 1, characterized in that, The substrate also has a fifth pad disposed on the first surface. The plurality of the first semiconductor chips also have a sixth pad disposed on the third surface. The semiconductor device also includes: The fourth line electrically connects the fifth pad to the sixth pad of the first semiconductor chip that is closest to the substrate among a plurality of the first semiconductor chips. as well as The fifth line electrically connects the sixth pads of each of the plurality of first semiconductor chips; The fourth pad, the third pad, and the sixth pad are arranged sequentially in one direction.

4. The semiconductor device according to claim 3, characterized in that, When the fourth pad is a pad to which either a power supply voltage or a ground voltage is applied, the sixth pad is a pad to which either a power supply voltage or a ground voltage is applied, and the third pad is a pad to which an input signal is received.

5. The semiconductor device according to claim 1, characterized in that, The deviations in thickness and length of the first lines are less than 10% relative to the average value.

6. The semiconductor device according to claim 1, characterized in that, It also has: A second semiconductor chip has a fourth surface facing the first surface, a fifth surface opposite the fourth surface, and a seventh pad disposed on the fifth surface; and A connecting conductor electrically connects the first pad to the seventh pad.

7. The semiconductor device according to claim 1, characterized in that, Multiple first semiconductor chips are stacked in a staggered manner in a second direction, which is perpendicular to the first direction and the stacking direction.

8. The semiconductor device according to claim 1, characterized in that, Multiple first semiconductor chips are stacked along the stacking direction in an alternating manner towards a second direction and the opposite direction of the second direction, the second direction being perpendicular to the first direction and the stacking direction.

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