An FPGA communication signal automatic calibration system

Abstract

This invention provides an automatic calibration system for FPGA communication signals, comprising: a multi-channel high-speed signal acquisition and processing module configured with multiple signal channels, performing synchronous sampling and preprocessing of multi-channel signals; a communication high-dimensional extraction and evaluation module, performing time-frequency feature analysis and signal quality analysis on the signals output by the multi-channel high-speed signal acquisition and processing module, and providing feedback on signal status and distortion parameters; and an intelligent signal correction and dynamic compensation module, comprising: a multi-protocol calibration strategy management and switching module, which identifies the current communication protocol type, detects signal environment quality, and evaluates device resource status, and generates calibration strategy instructions based on a comprehensive decision based on protocol type, signal environment quality, and device resource status; and an intelligent signal correction and dynamic compensation module, which adjusts the amplitude, phase, and frequency offset parameters of the signal based on the calibration strategy instructions, the signal status, and the distortion parameters.

Description

Technical Field

[0001] This invention relates to the technical field of signal calibration, and more particularly to an automatic calibration system for FPGA communication signals. Background Technology

[0002] With its advantages such as hardware reconfigurability and strong parallel processing capabilities, FPGA (Field-Programmable Gate Array) has become the core processing component in signal calibration systems of modern wireless communication base stations, satellite terminals, and military electronic warfare equipment. By dynamically reconfiguring logic resources, FPGA can achieve real-time acquisition and dynamic adaptation of multi-band and multi-standard communication signals, meeting the stringent requirements for signal processing flexibility and real-time performance in complex electromagnetic environments.

[0003] Currently, existing FPGA communication signal calibration schemes are static compensation methods based on preset calibration tables. This scheme first uses instruments such as spectrum analyzers and vector network analyzers to perform offline calibration of the link to be calibrated, extracting amplitude and phase error coefficients at different frequencies and temperatures to form a preset calibration table. Then, a digital signal processor (DSP) module is integrated within the FPGA to retrieve the preset coefficients via a lookup table, and combined with a finite impulse response (FIR) filter to achieve channel equalization and phase correction. Some improved schemes also introduce an analog-to-digital conversion sampling architecture based on a fixed clock allocation strategy and employ a general-purpose FIR filter for out-of-band noise suppression.

[0004] However, as communication scenarios evolve towards high-density heterogeneous networks, ultra-low latency industrial IoT, and dynamic spectrum sharing systems, the aforementioned static calibration scheme suffers from the following technical problems: 1. Insufficient sampling clock adaptation capability: Traditional analog-to-digital conversion sampling uses a fixed clock allocation strategy, which cannot dynamically adapt to the switching requirements of Nyquist sampling rate for multi-band signals. In communication scenarios where LTE and millimeter-wave bands coexist, a fixed sampling clock results in a sampling synchronization error exceeding 1.2 nanoseconds, severely deteriorating the phase consistency of multi-channel signals.

[0005] 2. Lack of targeted interference suppression: Existing technical solutions rely on general-purpose FIR filters for noise suppression, without designing nonlinear interference suppression algorithms for specific communication protocols (such as 5G NR, tactical data links, etc.). When power amplifier nonlinear distortion or strong out-of-band interference exists, the out-of-band spurious power increases significantly, reducing the receiver's dynamic range and sensitivity.

[0006] 3. Fixed calibration strategy, lacking real-time sensing capability: Calibration thresholds, compensation coefficients, and other parameters are pre-defined in the FPGA configuration file, making dynamic adjustments impossible based on internal FPGA resource usage (such as lookup table utilization and block random access memory availability) and external environmental parameters (such as temperature, voltage, and interference intensity). In scenarios involving sudden strong interference or drastic environmental changes, the calibration system's response latency increases significantly, and calibration may even fail.

[0007] 4. Limited protocol identification capability: Existing protocol identification modules only support matching of a limited number of known modulation standards (such as QPSK, 16QAM, etc.), and cannot analyze the unknown signal characteristics that appear in dynamic spectrum access systems or cognitive radio networks, resulting in an increased signal type misjudgment rate, which in turn triggers incorrect calibration paths.

[0008] 5. Weak security protection mechanisms: The integrity protection of calibration parameters relies solely on Cyclic Redundancy Check (CRC), without embedded adversarial sample detection or parameter anomaly monitoring mechanisms. Malicious attackers can tamper with the calibration table or inject forged synchronization sequences, causing calibration parameters to drift, leading to degraded or even interrupted communication link performance, posing a serious security risk.

[0009] In summary, existing FPGA communication signal calibration technologies struggle to simultaneously meet the multi-dimensional requirements of high dynamic response, multi-channel synchronization, nonlinear suppression, protocol adaptation, and security and reliability. Therefore, there is an urgent need for an automatic FPGA communication signal calibration system capable of real-time sensing of system status and environmental changes, adaptively adjusting calibration strategies, and possessing robust security protection capabilities. Summary of the Invention

[0010] This invention provides an automatic calibration system for FPGA communication signals that can simultaneously meet the multi-dimensional requirements of high dynamic response, multi-channel synchronization, nonlinear suppression, protocol adaptation, and security and reliability.

[0011] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.

[0012] To achieve one, some, or all of the above objectives or other objectives, the present invention provides an automatic calibration system for FPGA communication signals, comprising: a multi-channel high-speed signal acquisition and processing module configured with multiple signal channels, performing synchronous sampling and preprocessing of multi-channel signals; a communication high-dimensional extraction and evaluation module, performing time-frequency feature analysis and signal quality analysis on the signals output by the multi-channel high-speed signal acquisition and processing module, and providing feedback on signal status and distortion parameters; an intelligent signal correction and dynamic compensation module, comprising: a multi-protocol calibration strategy management and switching module, identifying the current communication protocol type, detecting signal environment quality, and evaluating device resource status, and generating calibration strategy instructions based on a comprehensive decision based on protocol type, signal environment quality, and device resource status; an intelligent signal correction and dynamic compensation module, adjusting the amplitude, phase, and frequency offset parameters of the signal based on the calibration strategy instructions, the signal status, and the distortion parameters; and a data interaction intelligent integration management module, providing a data transmission interface for communication with external communication modules, and the data interaction intelligent integration management module is also used for the management of internal logic resources of the FPGA.

[0013] The multi-channel high-speed signal acquisition and processing module includes a high-precision analog-to-digital conversion sampling module for sampling input analog communication signals and performing analog-to-digital conversion on the analog communication signals; a multi-channel synchronous sampling coordination module that distributes a common reference clock to all channels to ensure that the communication signals of all channels are consistent in time, and sets the same trigger signal to align the sampling start signal, synchronizing the sampling results of multiple signal channels. After completing the signal synchronization processing, the multi-channel synchronous sampling coordination module injects a signal with a known frequency and phase into all channels for phase alignment calibration; a digital filtering noise suppression module that performs filtering processing on the synchronized sampled signal based on a configurable digital filtering algorithm; a dynamic amplitude normalization processing module that adaptively adjusts the amplitude of the filtered signal to the optimal receiving range of the FPGA processor to achieve pre-equalization of the signal amplitude; and a clock recovery sampling synchronization control module that uses clock data recovery technology to ensure the synchronization of the sampling clock and the signal clock, reducing clock drift.

[0014] The clock recovery sampling synchronization control module includes a phase detector that compares the phase difference between the input signal clock and the locally recovered clock; a loop filter that smooths the phase difference signal output by the phase detector; a charge pump calibration circuit that receives the output of the loop filter and dynamically adjusts the delay line taps of the digitally controllable delay line to control the phase difference within 50 ps; a temperature sensor and a temperature-polarization model. The temperature sensor monitors the internal temperature of the FPGA, and the temperature-polarization model calculates the frequency offset of the crystal oscillator caused by temperature changes, thereby monitoring the sampling clock offset. Based on the sampling clock offset result, the delay line parameters are dynamically adjusted by the logic units inside the FPGA until the synchronization accuracy meets the requirements.

[0015] The dynamic amplitude normalization processing module includes a peak detector, a gain controller, and a digital attenuator. The peak detector detects the peak value based on the overflow flag of the ADC chip in the high-precision analog-to-digital conversion sampling module. The detected peak value is used as the reference for error calculation and compared with the target amplitude to calculate the error value. The gain controller calculates the amount of attenuation to be adjusted based on the error value using a PID control algorithm. The digital attenuator adjusts the amplitude of the signal based on the attenuation amount output by the gain controller. The adjusted amplitude of the signal is then sampled and adjusted again by the dynamic amplitude normalization processing module until the signal amplitude stabilizes near the target value.

[0016] The communication high-dimensional feature extraction and evaluation module includes: a time-domain statistical feature analysis module, which extracts the time-domain features of the signal, including at least instantaneous amplitude, power, level, and pulse width; a frequency-domain analysis distortion detection module, which receives the time-domain features output by the time-domain statistical feature analysis module and extracts the frequency-domain features of the signal based on the FPGA's built-in FFT IP core or an IP core that executes wavelet transform algorithms, including at least spectral distribution, bandwidth, and harmonic distortion; a format identification performance bit error rate evaluation module, which receives the frequency-domain features output by the frequency-domain analysis distortion detection module, performs constellation diagram analysis on the signal, and estimates the bit error rate and signal error; and a nonlinear interference feature separation module, which receives the bit error rate and signal error output by the format identification performance bit error rate evaluation module, separates intermodulation distortion and external interference in the signal based on higher-order statistics and independent component analysis algorithms, performs centering and whitening processing on the signal, and performs FastICA... The algorithm iteratively calculates the separation matrix and outputs the interference components and the clean signal; the key parameter monitoring module of the operating environment collects and monitors the temperature, power supply voltage, and oscillator frequency offset parameters of each module in the communication high-dimensional feature extraction and evaluation module during operation; the distortion parameters fed back by the communication high-dimensional feature extraction and evaluation module include at least harmonic distortion and the interference components output by the nonlinear interference feature separation module; the signal state fed back by the communication high-dimensional feature extraction and evaluation module includes at least instantaneous amplitude, power, level, pulse width, spectral distribution, bandwidth, bit error rate, signal error, and oscillator frequency offset parameters.

[0017] The intelligent signal correction dynamic compensation module includes a multi-parameter joint optimization adjustment module and a machine learning parameter prediction decision module. The intelligent signal correction dynamic compensation module selects to activate the multi-parameter joint optimization adjustment module and / or the machine learning parameter prediction decision module based on the calibration strategy instruction. The multi-parameter joint optimization adjustment module adjusts the amplitude, phase, and frequency offset parameters of the signal based on the signal state and the distortion parameters. The machine learning parameter prediction decision module predicts the optimal calibration parameters based on the signal state, the distortion parameters, and the current adjustment state information fed back by the multi-parameter joint optimization adjustment module. The optimal calibration parameters include at least signal amplitude compensation and signal phase compensation. The current adjustment state information fed back by the multi-parameter joint optimization adjustment module includes at least the gain coefficient of each channel, the filter tap value, and the current error vector. The current adjustment state information indicates the current operating node of the system. The multi-parameter joint optimization adjustment module, in conjunction with the machine learning parameter prediction decision module, performs signal correction.

[0018] The intelligent signal correction dynamic compensation module further includes: a real-time closed-loop error feedback control module, which outputs feedback results based on the response changes of the corrected signal feedback control module; the multi-parameter joint optimization adjustment module adjusts the signal based on the feedback results; the machine learning parameter prediction decision module trains the model based on the feedback results; and an abnormal behavior identification security protection unit, which is connected to the multi-protocol calibration strategy management switching module, the machine learning parameter prediction decision module, the multi-parameter joint optimization adjustment module, and the real-time closed-loop error feedback control module, respectively, to monitor the operating status of each module in the intelligent signal correction dynamic compensation module, and triggers strategy rollback or alarm protection when an abnormal state is detected.

[0019] The multi-protocol calibration strategy management and switching module includes: a protocol type identification unit for identifying whether the communication protocol is LTE, 5G NR, Wi-Fi, Zigbee, low-power protocol, Ethernet protocol, or a custom protocol; a signal environment detection subunit for collecting environmental interference type, signal quality, and noise level; a device capability resource evaluation unit for evaluating FPGA resources, storage resources, and computing power; a calibration strategy determination unit for generating a calibration strategy based on the comprehensive status of protocol type, signal environment, and device capabilities; and a decision result output module for outputting calibration strategy instructions to the multi-parameter joint optimization and adjustment module and the machine learning reference prediction decision module based on the generated calibration strategy.

[0020] The judgment logic of the calibration strategy determination unit is as follows: If the protocol type is 5G communication protocol, the environmental interference is strong, and the equipment resources are sufficient, the calibration strategy determination unit generates a highly complex and fine calibration strategy. The FPGA scheduling dynamic reconfiguration management module loads the highly complex and fine calibration strategy module, which uses multi-parameter joint optimization and machine learning algorithms to perform fine signal correction. If the protocol is a low-power protocol and the equipment resources are limited, the calibration strategy determination unit generates a lightweight calibration strategy. The FPGA scheduling dynamic reconfiguration management module loads the lightweight calibration strategy module, which uses simplified algorithms to quickly adjust core parameters. If protocol identification fails or the identified protocol is an unknown protocol, the calibration strategy determination unit generates a conservative correction strategy. The FPGA scheduling dynamic reconfiguration management module loads a conservative and downgraded strategy module, which reduces the correction frequency. If the environmental quality is poor, the calibration strategy determination unit generates a downgraded correction strategy. The FPGA scheduling dynamic reconfiguration management module loads a conservative and downgraded strategy module, which controls the signal correction dynamic compensation module to operate in a downgraded manner, limiting the change in calibration amplitude. Poor environmental quality refers to high environmental noise and severe multipath fading.

[0021] The FPGA scheduling dynamic reconfiguration management module configures multiple hardware acceleration IP cores based on the type of calibration strategy module. Each hardware acceleration IP core integrates a highly complex and fine calibration strategy module, a lightweight calibration strategy module, and a conservative and degraded strategy module. The FPGA scheduling dynamic reconfiguration management module uses Xilinx PartialReconfiguration technology to load the selected IP core into the reconfigurable region of the FPGA and completes the switching of IP cores and executes the corresponding calibration strategy through custom instructions.

[0022] The intelligent integrated management module for data interaction includes: a high-speed external data communication interface module for high-speed data exchange, receiving external remote commands and outputting system operation data; a remote control and configuration management module connected to the high-speed external data communication interface module, receiving system operation data and generating parameter configuration commands; an FPGA scheduling dynamic reconfiguration management module connected to the remote control and configuration management module, receiving the parameter configuration commands, performing time scheduling and logic reconfiguration, and outputting module operating status signals; a system operation diagnostic log storage module connected to the FPGA scheduling dynamic reconfiguration management module, receiving the module operating status signals, storing system operation records, calibration history records, and fault records, and generating system health status data; and an intelligent power monitoring and heat dissipation management module connected to the system operation diagnostic log storage module, receiving the system health status data and performing power regulation and heat dissipation regulation.

[0023] Compared with existing technologies, the beneficial effects of this invention mainly include: 1. By combining a clock recovery synchronization module and a dynamic amplitude normalization module with real-time closed-loop error feedback control, high-speed closed-loop correction of signal sampling synchronization, amplitude, phase, and frequency offset is achieved, significantly improving calibration accuracy and response speed, and meeting the low-latency communication requirements of 5G NR and other technologies. 2. The multi-protocol calibration strategy management and switching module automatically identifies protocols such as LTE / 5G / Wi-Fi / Zigbee / Ethernet, and dynamically selects fine calibration (through machine learning and multi-parameter joint optimization adjustment), lightweight calibration, or conservative degradation mode based on signal environment quality and FPGA resource status. This avoids fixed algorithm failure or resource waste, and greatly improves adaptability to different communication standards and complex environments. 3. An integrated machine learning parameter prediction decision module predicts the optimal compensation value (amplitude, phase, frequency offset) based on historical signal status and distortion parameters, and achieves self-evolving calibration through real-time closed-loop feedback online model training. Compared with traditional lookup table or fixed coefficient methods, it has stronger nonlinear tracking capabilities and long-term stability. 4. The abnormal behavior identification and security protection unit monitors the operating status of each module in real time and triggers policy rollback or alarm when an abnormality occurs; the FPGA scheduling dynamic reconfiguration management module uses Partial Reconfiguration technology to load calibration algorithms of different complexities on demand, realizes time-division multiplexing of hardware resources, reduces power consumption and improves system robustness.

[0024] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This invention provides a system architecture diagram for an automatic calibration system for FPGA communication signals.

[0027] Figure 2 This is an architecture diagram of the multi-channel high-speed signal acquisition and processing module of the present invention.

[0028] Figure 3 This is an architecture diagram of the dynamic amplitude normalization processing module and the clock recovery sampling synchronization module in the multi-channel high-speed signal acquisition and processing module of the present invention.

[0029] Figure 4 This is an architecture diagram of the communication high-dimensional extraction and evaluation module of the present invention.

[0030] Figure 5 This is a diagram of the architecture of the intelligent signal correction and compensation module of the present invention.

[0031] Figure 6 This is an architecture diagram of the data interaction intelligent integration management module of the present invention. Detailed Implementation

[0032] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0033] Example 1 Example 1 provides an automatic calibration system for FPGA communication signals, such as Figure 1 As shown, it includes a multi-channel high-speed signal acquisition and processing module, which is configured with multiple signal channels to perform synchronous sampling and preprocessing of multi-channel signals; The communication high-dimensional extraction and evaluation module performs time-frequency feature analysis (time domain feature analysis and frequency domain feature analysis) and signal quality analysis on the signal output by the multi-channel high-speed signal acquisition and processing module, and provides feedback on signal status and distortion parameters. The intelligent signal correction and dynamic compensation module includes a multi-protocol calibration strategy management and switching module, which identifies the current communication protocol type, detects the signal environment quality, and assesses the device resource status. Based on the protocol type, signal environment quality, and device resource status, it makes a comprehensive decision to generate calibration strategy instructions. The intelligent signal correction and dynamic compensation module adjusts the amplitude, phase, and frequency offset parameters of the signal based on the calibration strategy command, the signal state, and the distortion parameters. The data interaction intelligent integration management module provides a data transmission interface to communicate with external communication modules. The data interaction intelligent integration management module is also used for the management of FPGA internal logic resources.

[0034] The FPGA communication signal automatic calibration system provided in Example 1 can simultaneously achieve the advantages of high-precision multi-channel synchronous calibration, adaptive intelligent compensation, flexible multi-protocol strategy management, efficient resource integration and external interaction, closed-loop feedback and real-time parameter adjustment, effectively making up for the shortcomings of the prior art.

[0035] The following will be combined with the appendix Figure 2-6 The automatic calibration system for FPGA communication signals provided in Embodiment 1 will be explained in detail.

[0036] like Figure 1As shown, the FPGA communication signal automatic calibration system provided in Embodiment 1 includes a multi-channel high-speed signal acquisition and processing module, a communication high-dimensional extraction and evaluation module, an intelligent signal correction and dynamic compensation module, and a data interaction intelligent integration management module.

[0037] like Figure 2 As shown, the multi-channel high-speed signal acquisition and processing module includes a high-precision analog-to-digital conversion sampling module for performing synchronous data sampling, a multi-channel synchronous sampling coordination module, a digital filtering noise suppression module for performing data preprocessing, a dynamic amplitude normalization processing module, and a clock recovery sampling synchronization module.

[0038] The high-precision analog-to-digital converter (ADC) sampling module integrates a 16-bit or higher high-precision ADC chip. It receives external input signals (e.g., analog signals conditioned by the RF front-end) via a differential input interface. The sampling rate supports dynamic configuration (up to 2 GSPS for the highest bit) to adapt to different frequency band requirements. The FPGA controls the ADC's sampling clock, converting the analog signal into a digital code stream, which is then output to the subsequent multi-channel synchronous sampling coordination module. This high-precision ADC sampling module has multiple sampling channels.

[0039] The multi-channel synchronous sampling coordination module ensures that the communication signals of all channels are synchronized in time by distributing a common reference clock to all channels. It also sets the same trigger signal to align the sampling start signal, thereby synchronizing the sampling results of multiple signal channels. After signal synchronization, the module injects a signal of known frequency and phase into all channels for phase alignment calibration. For example, a sinusoidal reference signal with an initial phase of 0° can be injected into all channels. The intensity of the calibration signal is at the standard reference level, and the duration of the calibration signal is 10 complete sinusoidal cycles. Each channel simultaneously acquires the standard signal, and the phase difference between each channel's signal and the reference signal is analyzed using FFT. Based on the calculated phase difference, a phase correction value is obtained, and the phase is then adjusted in real time using a DAC or digital delay unit to complete the phase calibration within each channel.

[0040] The digital filtering noise suppression module performs filtering processing on the synchronously processed sampled signal based on configurable digital filtering algorithms (such as FIR low-pass / medium-pass filtering algorithm, median filtering algorithm, wavelet transform algorithm, etc.) to remove noise and interference in the signal.

[0041] Because the signal amplitude difference between different communication protocols (such as 5G and LoRa) can reach 40dB, directly inputting the signal into the FPGA can lead to quantization accuracy loss or saturation. A dynamic amplitude normalization module is implemented to adaptively adjust the amplitude of the filtered signal to the optimal receiving range of the FPGA processor, achieving pre-equalization of the signal amplitude. Figure 3 As shown, the dynamic amplitude normalization processing module includes a peak detector, a gain controller, and a digital attenuator. The peak detector detects the peak value based on the overflow flag of the ADC chip in the high-precision analog-to-digital conversion sampling module. The detected peak value is used as the reference for error calculation and compared with the target amplitude to calculate the error value. The gain controller uses a PID control algorithm to calculate the attenuation amount of the digital attenuator that needs to be adjusted based on the error value. The digital attenuator (e.g., HMC472) adjusts the signal amplitude based on the attenuation amount output by the gain controller, normalizing the signal amplitude to the optimal quantization range of the FPGA (e.g., 0.5V-2.5V).

[0042] The adjusted signal amplitude value is then sampled again by the peak detector in the dynamic amplitude normalization processing module and adjusted by subsequent modules. Through iterative control, the signal amplitude stabilizes near the target value.

[0043] The clock recovery sampling synchronization control module uses clock data recovery technology to ensure synchronization between the sampling clock and the signal clock, reducing clock drift. For example... Figure 3 As shown, the clock recovery sampling synchronization control module includes a phase detector, which compares the phase difference between the input signal clock (the signal clock output after processing by the dynamic amplitude normalization module) and the locally recovered clock; a loop filter, which smooths the phase difference signal output by the phase detector; and a charge pump calibration circuit, which receives the output of the loop filter and dynamically adjusts the delay line taps of the digitally controllable delay line to control the phase difference within 50ps.

[0044] Meanwhile, temperature changes within the FPGA can affect the frequency offset of the crystal oscillator. To mitigate this impact, a temperature sensor is integrated within the FPGA to monitor its internal temperature. This is based on a temperature-polarization model (a fitting model of the crystal oscillator frequency versus temperature characteristics, with the core formula: Δf / f0 = α1·ΔT + α2·ΔT). 2 +α3·ΔT 3In the above formula, Δf / f0 represents the normalized frequency, Δf is the difference between the frequency and the frequency f0 at the current temperature, the frequency f0 represents the standard frequency, ΔT is the temperature change, and α1, α2, and α3 are calculated based on the physical characteristics of the crystal oscillator itself (α1 affects the linear drift of the frequency with temperature, α2 affects the parabolic drift of the frequency with temperature, and α3 affects the S-curve drift of the frequency with temperature). This calculates the frequency offset of the crystal oscillator caused by the temperature change, thereby monitoring the sampling clock offset. Based on the offset result of the sampling clock, the delay line parameters are dynamically adjusted by the logic unit inside the FPGA (such as the logic unit IDELAYE2 of Xilinx). The charge pump calibration circuit adjusts the delay line taps of the controllable delay line based on these delay line parameters, and then adjusts the phase difference until the accuracy meets the requirements.

[0045] The multi-channel high-speed signal acquisition and processing module of this application performs data preprocessing, including signal filtering, amplitude normalization, and clock and signal synchronization.

[0046] like Figure 4 As shown, the communication high-dimensional feature extraction and evaluation module includes: a time-domain statistical feature analysis module, which extracts the time-domain features of the signal, including at least instantaneous amplitude, power, level, and pulse width; a frequency-domain analysis distortion detection module, which receives the time-domain features output by the time-domain statistical feature analysis module, and extracts the frequency-domain features of the signal based on the FPGA's built-in FFT IP core or an IP core that executes wavelet transform algorithms, including at least spectral distribution, bandwidth, and harmonic distortion; and a format identification performance bit error rate evaluation module, which receives the frequency-domain features output by the frequency-domain analysis distortion detection module, performs constellation diagram analysis on the signal, and estimates the bit error rate and signal error.

[0047] The aforementioned time-domain statistical feature analysis module, frequency-domain distortion detection module, and format identification performance bit error rate assessment module constitute the feature analysis layer, used to analyze signal characteristics. The output of the feature analysis layer enters the signal separation layer for signal separation and output. The signal separation layer includes a nonlinear interference feature separation module, receives the bit error rate and signal error output from the format identification performance bit error rate assessment module, and, based on higher-order statistics and independent component analysis algorithms, separates intermodulation distortion and external interference in the signal. It then performs signal centering and whitening processing, iteratively calculates the separation matrix using the FastICA algorithm (an efficient and fast ICA algorithm using fixed-point iterative optimization), and outputs the interference components and the clean signal.

[0048] The processing flow of the nonlinear interference feature separation module includes: Step 1: Data preprocessing.

[0049] The multi-channel sampled signals are denoted as the observation matrix X = [x1, x2, ..., x...]. m ]ᵀ, where xj ∈Rᴺ represents the N-point sampling sequence of the j-th channel.

[0050] Step 2: Centralized processing.

[0051] The observed signal is centered by subtracting the mean of each channel signal, so that the mean of the processed signal is zero.

[0052] The centered signal matrix is ​​denoted as .

[0053] Step 3: Whitening treatment.

[0054] The centered signal is whitened to remove the correlation between channels. The whitening transformation is achieved through eigenvalue decomposition of the covariance matrix.

[0055] Where E is the eigenvector matrix, and D = diag(λ1, λ2, ..., λ3). m E is an eigenvalue diagonal matrix. T This represents the transpose of the eigenvector matrix, where N is the number of sampling points. This represents the centered observation signal matrix.

[0056] The whitening matrix W is calculated using the following formula: The signal after whitening is: Step 4: Extraction of higher-order statistical features.

[0057] Step 4-1: Skewness Calculation: Skewness measures the asymmetry of a signal's probability distribution, reflecting the degree to which the signal deviates from a normal distribution. The skewness of the j-th channel signal is defined as follows: Where, μ j σ is the mean. j The standard deviation is S. A skewness value S>0 indicates a right-skewed distribution, a skewness value S<0 indicates a left-skewed distribution, and a skewness value S=0 indicates a symmetrical distribution.

[0058] Step 4-2: Kurtosis Calculation: The subtraction of 3 is to make the kurtosis of the normal distribution zero. A positive kurtosis (K>0) indicates a sharper normal distribution, while a negative kurtosis indicates a flatter normal distribution.

[0059] Step 4-3: Mutual information calculation: The mutual information between signals in each channel is calculated based on entropy theory, which is used to quantify the non-Gaussianity of the signal.

[0060] The smaller the mutual information, the more independent the signals of each channel are.

[0061] In addition to using higher-order statistics for feature extraction, step 4 can also use independent component analysis (ICA) to extract features.

[0062] After extracting high-order statistical features, the FastICA algorithm is used for iterative computation. The input is a whitened signal matrix Z, with m independent components. The FastICA algorithm uses a non-Gaussianity metric, a linear mixture model, and Newton's iterative algorithm to batch update the weight vector.

[0063] The main steps include setting the iteration threshold, setting the maximum number of iterations, and initializing the separation matrix. After initializing the separation matrix, a loop is performed to conduct fixed-point iterative calculations until the convergence criteria are met, and the separation matrix W is output. The FastICA algorithm is an existing technology, and will not be described in detail in this application.

[0064] After the FastICA algorithm has processed the separation matrix, signal separation and output are performed, specifically including: Step 1: Separation matrix calculation.

[0065] Based on the iterative calculation results of the FastICA algorithm, the separation matrix W is obtained, and the output signal Y is calculated as follows: Y=W T Z (8); Among them W T This represents the transpose of the separation matrix.

[0066] Step 2: Signal reconstruction.

[0067] The separation result in the whitened space is inversely transformed back to the original signal space: S is the separated signal matrix, with each row corresponding to an independent signal source.

[0068] For the separated signal matrix S, the separated signal components are classified based on the statistical characteristics of the higher-order statistical analysis results.

[0069] Statistical characteristics include skewness (interference components are significantly non-zero), kurtosis (interference components have large absolute values), spectral purity (interference components contain a large number of harmonics), and correlation with the reference signal (interference components have low correlation with the reference signal). Based on the above statistical characteristics, after identifying the interference component signal, it is separated and output.

[0070] The key parameter monitoring module for the operating environment collects and monitors the temperature, power supply voltage, and oscillator frequency offset parameters of each module in the communication high-dimensional feature extraction and evaluation module during operation.

[0071] The distortion parameters fed back by the communication high-dimensional feature extraction and evaluation module include at least harmonic distortion and interference components output by the nonlinear interference feature separation module.

[0072] The signal state fed back by the communication high-dimensional feature extraction and evaluation module includes at least instantaneous amplitude, power, level, pulse width, spectral distribution, bandwidth, bit error rate, signal error, and oscillator frequency offset parameters.

[0073] The intelligent signal correction and dynamic compensation module includes a multi-protocol calibration strategy management and switching module, a multi-parameter joint optimization and adjustment module, a machine learning parameter prediction and decision-making module, a closed-loop error feedback implementation module, and an abnormal behavior recognition and security protection module.

[0074] like Figure 5 As shown, the multi-protocol calibration strategy management switching module includes: a protocol type identification unit, used to identify whether the communication protocol is LTE, 5G NR, Wi-Fi, Zigbee, low-power protocol, Ethernet protocol, or a custom protocol; a signal environment detection subunit, used to collect environmental interference type, signal quality, and noise level; a device capability resource evaluation unit, used to evaluate FPGA resources, storage resources, and computing power; a calibration strategy determination unit, used to generate a calibration strategy based on the comprehensive status of protocol type, signal environment, and device capabilities; and a decision result output module, used to output calibration strategy instructions to the multi-parameter joint optimization adjustment module and the machine learning reference prediction decision module based on the generated calibration strategy.

[0075] The judgment logic of the calibration strategy determination unit is as follows: If the protocol type is 5G communication protocol, the environmental interference is strong and the equipment resources are sufficient, the calibration strategy determination unit generates a highly complex and fine calibration strategy, the FPGA scheduling dynamic reconfiguration management module loads the highly complex and fine calibration strategy module, and the highly complex and fine calibration strategy module enables multi-parameter joint optimization and machine learning algorithms to perform fine correction of the signal.

[0076] If the protocol is a low-power protocol and the device resources are limited, the calibration strategy determination unit generates a lightweight calibration strategy, the FPGA scheduling dynamic reconfiguration management module loads the lightweight calibration strategy module, and the lightweight calibration strategy module enables a simplified algorithm to quickly adjust the core parameters.

[0077] If protocol identification fails or the identified protocol is an unknown protocol, the calibration strategy determination unit generates a conservative correction strategy, the FPGA scheduling dynamic reconfiguration management module loads the conservative and downgraded strategy module, and the conservative and downgraded strategy module reduces the correction frequency.

[0078] As an optional implementation, the FPGA scheduling dynamic reconfiguration management module configures multiple hardware acceleration IP cores based on the type of calibration strategy module. Each of the multiple hardware acceleration IP cores integrates a highly complex and fine calibration strategy module, a lightweight calibration strategy module, and a conservative and degraded strategy module. The FPGA scheduling dynamic reconfiguration management module uses Xilinx Partial Reconfiguration technology to load the selected IP core into the reconfigurable area of ​​the FPGA and completes the switching of IP cores and executes the corresponding calibration strategy through custom instructions (such as custom instruction sets based on RISC-V for instruction extension).

[0079] If the environmental quality is poor, the calibration strategy determination unit generates a downgrade correction strategy, the FPGA scheduling dynamic reconfiguration management module loads the conservative and downgrade strategy module, and the conservative and downgrade strategy module controls the signal correction dynamic compensation module to operate in a downgraded manner to limit the change in calibration amplitude; poor environmental quality refers to high environmental noise and severe multipath fading.

[0080] The intelligent signal correction and dynamic compensation module selects and activates the multi-parameter joint optimization adjustment module and / or the machine learning parameter prediction and decision module based on calibration strategy instructions (highly complex fine calibration strategy, lightweight calibration strategy, conservative correction strategy, and degraded correction strategy). The multi-parameter joint optimization adjustment module adjusts the amplitude, phase, and frequency offset parameters of the signal based on the signal state and distortion parameters. The machine learning parameter prediction and decision module predicts the optimal calibration parameters based on the signal state, distortion parameters, and the current adjustment state information fed back by the multi-parameter joint optimization adjustment module. The optimal calibration parameters include at least signal amplitude compensation and signal phase compensation. The generated optimal calibration parameters are input to the multi-parameter joint optimization adjustment module for signal correction.

[0081] As an alternative implementation, the machine learning parameter prediction decision module can use a lightweight neural network, such as a 2-layer CNN architecture. During model training, the constructed dataset contains historical data samples, and labels are added to these historical data samples to form labeled data. These added labels include interference type, compensation parameters, signal quality level, etc. During training, the signal distortion parameters are used as the loss function, and the model weights are optimized by descent until the prediction amplitude error is less than 0.1 dB and the prediction phase error is less than 0.5°.

[0082] The current adjustment status information fed back by the multi-parameter joint optimization adjustment module includes at least the gain coefficient of each channel, the filter tap value, and the current error vector. The current adjustment status information indicates the current working node of the system. The multi-parameter joint optimization adjustment module, together with the machine learning parameter prediction decision module, performs signal correction.

[0083] The real-time closed-loop error feedback control module outputs feedback results based on the response changes of the feedback control module after correction. The multi-parameter joint optimization adjustment module adjusts the signal based on the feedback results. The machine learning parameter prediction decision module trains the model based on the feedback results.

[0084] The abnormal behavior recognition security protection unit is connected to the multi-protocol calibration strategy management and switching module, the machine learning parameter prediction and decision module, the multi-parameter joint optimization and adjustment module, and the real-time closed-loop error feedback control module, respectively. It monitors the operating status of each module in the intelligent signal correction dynamic compensation module and triggers strategy rollback or alarm protection when an abnormal state is detected.

[0085] like Figure 6 As shown, the data interaction intelligent integration management module includes: a high-speed external data communication interface module, which is used for high-speed data exchange, receiving external remote commands and outputting system operation data.

[0086] The remote control and configuration management module connects to the high-speed external data communication interface module, receives system operation data, and generates parameter configuration instructions.

[0087] The FPGA scheduling dynamic reconfiguration management module is connected to the remote control and configuration management module. It receives the parameter configuration instructions, performs time scheduling and logic reconfiguration, and manages and loads IP cores based on the calibration strategy, and outputs the module working status signal.

[0088] The system operation diagnostic log storage module is connected to the FPGA scheduling dynamic reconfiguration management module. It receives module working status signals, stores system operation records, calibration history records and fault records, and generates system health status data.

[0089] The generated system health status data is also used for the management of internal logic resources of the FPGA. Specifically, the aforementioned system health status data is transmitted to the internal resource management module of the FPGA, which performs logic unit management, storage resource allocation, and computing power scheduling based on the health status of the system.

[0090] The intelligent power monitoring and heat dissipation management module is connected to the system operation diagnostic log storage module. It is used to receive the system health status data and perform power regulation and heat dissipation regulation.

[0091] The above provides a detailed description of the FPGA communication signal automatic calibration system provided by this invention. Specific examples have been used to illustrate the structure and working principle of this invention. The descriptions of the embodiments are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this invention.

Claims

1. An automatic calibration system for FPGA communication signals, characterized in that, It includes a multi-channel high-speed signal acquisition and processing module, which is configured with multiple signal channels to perform synchronous sampling and preprocessing of multi-channel signals; The communication high-dimensional extraction and evaluation module performs time-frequency feature analysis and signal quality analysis on the signal output by the multi-channel high-speed signal acquisition and processing module, and provides feedback on signal status and distortion parameters. The intelligent signal correction and dynamic compensation module includes a multi-protocol calibration strategy management and switching module, which identifies the current communication protocol type, detects the signal environment quality, and assesses the device resource status. Based on the protocol type, signal environment quality, and device resource status, it makes a comprehensive decision to generate calibration strategy instructions. The intelligent signal correction and dynamic compensation module adjusts the amplitude, phase, and frequency offset parameters of the signal based on the calibration strategy command, the signal state, and the distortion parameters. The data interaction intelligent integration management module provides a data transmission interface to communicate with external communication modules. The data interaction intelligent integration management module is also used for the management of FPGA internal logic resources.

2. The FPGA communication signal automatic calibration system according to claim 1, characterized in that, The multi-channel high-speed signal acquisition and processing module includes a high-precision analog-to-digital conversion sampling module, used to sample the input analog communication signal and perform analog-to-digital conversion on the analog communication signal; The multi-channel synchronous sampling coordination module ensures that the communication signals of all channels are consistent in time by distributing a common reference clock to all channels. At the same time, it sets the same trigger signal, aligns the sampling start signal, and synchronizes the sampling results of multiple signal channels. After the signal synchronization is completed, the multi-channel synchronous sampling coordination module injects a signal with a known frequency and phase into all channels to perform phase alignment calibration. The digital filtering noise suppression module performs filtering processing on the synchronously processed sampled signal based on a configurable digital filtering algorithm. The dynamic amplitude normalization processing module adaptively adjusts the amplitude of the filtered signal to the optimal receiving range of the FPGA processor, thereby achieving pre-equalization of the signal amplitude. The clock recovery sampling synchronization control module uses clock data recovery technology to ensure the synchronization of the sampling clock and the signal clock, reducing clock drift.

3. The FPGA communication signal automatic calibration system according to claim 2, characterized in that, The clock recovery sampling synchronization control module includes a phase detector, which compares the phase difference between the input signal clock and the locally recovered clock. A loop filter smooths the phase difference signal output by the phase detector. The charge pump calibration circuit receives the output of the loop filter and dynamically adjusts the delay line taps of the digitally controllable delay line to control the phase difference within 50 ps. A temperature sensor and a temperature-polarization model are used. The temperature sensor monitors the internal temperature of the FPGA, and the temperature-polarization model is used to calculate the frequency offset of the crystal oscillator caused by temperature changes, thereby monitoring the sampling clock offset. Based on the offset result of the sampling clock, the delay line parameters are dynamically adjusted by the logic unit inside the FPGA until the synchronization accuracy meets the requirements.

4. The FPGA communication signal automatic calibration system according to claim 2, characterized in that, The dynamic amplitude normalization processing module includes a peak detector, a gain controller, and a digital attenuator. The peak detector detects the overflow flag bit built into the ADC chip in the high-precision analog-to-digital conversion sampling module. The detected peak value is used as the benchmark for error calculation and is compared with the target amplitude to calculate the error value. The gain controller is based on a PID control algorithm and calculates the amount of attenuation that needs to be adjusted according to the error value. The digital attenuator adjusts the amplitude of the signal based on the attenuation amount output by the gain controller; The adjusted amplitude value of the signal is then sampled and adjusted again by the dynamic amplitude normalization processing module until the signal amplitude stabilizes near the target value.

5. The FPGA communication signal automatic calibration system according to claim 1, characterized in that, The communication high-dimensional feature extraction and evaluation module includes: The time-domain statistical feature analysis module extracts the time-domain features of the signal, which include at least instantaneous amplitude, power, level, and pulse width. The frequency domain analysis distortion detection module receives the time domain features output by the time domain statistical feature analysis module, and extracts the frequency domain features of the signal based on the FPGA's built-in FFT IP core or the IP core that executes the wavelet transform algorithm. The frequency domain features include at least the spectrum distribution, bandwidth, and harmonic distortion. The format identification performance bit error assessment module receives the frequency domain characteristics output by the frequency domain analysis distortion detection module, performs constellation diagram analysis on the signal, and estimates the bit error rate and signal error. The nonlinear interference feature separation module receives the bit error rate and signal error output by the format identification performance bit error evaluation module, and separates the intermodulation distortion and external interference in the signal based on higher-order statistics and independent component analysis algorithm. The signal is centered and whitened, and the separation matrix is ​​iteratively calculated through the FastICA algorithm to output the interference component and the clean signal. The key parameter monitoring module for the operating environment collects and monitors the temperature, power supply voltage, and oscillator frequency offset parameters of each module in the communication high-dimensional feature extraction and evaluation module during operation. The distortion parameters fed back by the high-dimensional feature extraction and evaluation module for communication include at least harmonic distortion and interference components output by the nonlinear interference feature separation module; The signal state fed back by the high-dimensional feature extraction and evaluation module of the communication includes at least instantaneous amplitude, power, level, pulse width, spectral distribution, bandwidth, bit error rate, signal error, and oscillator frequency offset parameters.

6. The FPGA communication signal automatic calibration system according to claim 1, characterized in that, The intelligent signal correction dynamic compensation module includes a multi-parameter joint optimization adjustment module and a machine learning parameter prediction decision module. The intelligent signal correction dynamic compensation module selects to enable the multi-parameter joint optimization adjustment module and / or the machine learning parameter prediction decision module based on the calibration strategy instruction. The multi-parameter joint optimization adjustment module adjusts the amplitude, phase, and frequency offset parameters of the signal based on the signal state and the distortion parameters. The machine learning parameter prediction and decision-making module predicts the optimal calibration parameters based on the signal state, the distortion parameters, and the current adjustment state information fed back by the multi-parameter joint optimization adjustment module. The optimal calibration parameters include at least signal amplitude compensation and signal phase compensation. The current adjustment status information fed back by the multi-parameter joint optimization adjustment module includes at least the gain coefficient of each channel, the filter tap value, and the current error vector. The current adjustment status information indicates the current working node of the system. The multi-parameter joint optimization and adjustment module, together with the machine learning parameter prediction and decision-making module, performs signal correction.

7. The FPGA communication signal automatic calibration system according to claim 1, characterized in that, The intelligent signal correction and dynamic compensation module also includes: The real-time closed-loop error feedback control module outputs feedback results based on the response changes of the feedback control module after correction; the multi-parameter joint optimization adjustment module adjusts the signal based on the feedback results; and the machine learning parameter prediction decision module trains the model based on the feedback results. The abnormal behavior identification and security protection unit is connected to the multi-protocol calibration strategy management and switching module, the machine learning parameter prediction and decision module, the multi-parameter joint optimization and adjustment module, and the real-time closed-loop error feedback control module, respectively. It monitors the operating status of each module in the intelligent signal correction dynamic compensation module and triggers strategy rollback or alarm protection when an abnormal status is detected.

8. The FPGA communication signal automatic calibration system according to claim 1, characterized in that, The multi-protocol calibration strategy management and switching module includes: The protocol type identification unit is used to identify whether the communication protocol is LTE, 5G NR, Wi-Fi, Zigbee, low power protocol, Ethernet protocol or custom protocol; The signal environment detection subunit collects information on environmental interference types, signal quality, and noise levels. The equipment capability resource assessment unit is used to assess FPGA resources, storage resources, and computing capabilities. The calibration strategy determination unit generates a calibration strategy based on the overall status of the protocol type, signal environment, and equipment capabilities. The decision result output module, based on the generated calibration strategy, outputs calibration strategy instructions to the multi-parameter joint optimization adjustment module and the machine learning reference prediction decision module.

9. The FPGA communication signal automatic calibration system according to claim 8, characterized in that, The judgment logic of the calibration strategy determination unit is as follows: If the protocol type is 5G communication protocol, the environmental interference is strong and the equipment resources are sufficient, the calibration strategy determination unit generates a highly complex and fine calibration strategy, the FPGA scheduling dynamic reconfiguration management module loads the highly complex and fine calibration strategy module, and the highly complex and fine calibration strategy module enables multi-parameter joint optimization and machine learning algorithms to perform fine correction of the signal; If the protocol is a low-power protocol and the device resources are limited, the calibration strategy determination unit generates a lightweight calibration strategy, the FPGA scheduling dynamic reconfiguration management module loads the lightweight calibration strategy module, and the lightweight calibration strategy module enables a simplified algorithm to quickly adjust the core parameters; If protocol identification fails or the identified protocol is an unknown protocol, the calibration strategy determination unit generates a conservative correction strategy, the FPGA scheduling dynamic reconfiguration management module loads the conservative and degradation strategy module, and the conservative and degradation strategy module reduces the correction frequency. If the environmental quality is poor, the calibration strategy determination unit generates a downgrade correction strategy, the FPGA scheduling dynamic reconfiguration management module loads the conservative and downgrade strategy module, and the conservative and downgrade strategy module controls the signal correction dynamic compensation module to operate in a downgraded manner to limit the change in calibration amplitude. Poor environmental quality refers to high noise levels and severe multipath fading.

10. An automatic calibration system for FPGA communication signals according to claim 9, characterized in that, The FPGA scheduling dynamic reconfiguration management module configures multiple hardware acceleration IP cores based on the type of calibration strategy module. Each hardware acceleration IP core integrates a highly complex and fine calibration strategy module, a lightweight calibration strategy module, and a conservative and degraded strategy module. The FPGA scheduling dynamic reconfiguration management module utilizes Xilinx Partial Reconfiguration technology to load the selected IP core into the reconfigurable region of the FPGA and completes the switching of IP cores and executes the corresponding calibration strategy through custom instructions.

11. An automatic calibration system for FPGA communication signals according to claim 9, characterized in that, The data interaction intelligent integration management module includes: The high-speed external data communication interface module is used for high-speed data exchange, receiving external remote commands and outputting system operation data; The remote control and configuration management module is connected to the high-speed external data communication interface module, receives system operation data, and generates parameter configuration instructions. The FPGA scheduling dynamic reconfiguration management module is connected to the remote control and configuration management module, receives the parameter configuration instructions, performs time scheduling and logic reconfiguration, and outputs the module working status signal. The system operation diagnostic log storage module is connected to the FPGA scheduling dynamic reconfiguration management module, receives the module's working status signal, stores system operation records, calibration history records and fault records, and generates system health status data. The intelligent power monitoring and heat dissipation management module is connected to the system operation diagnostic log storage module and is used to receive the system health status data and perform power regulation and heat dissipation regulation.

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