Electroluminescent display device and driving apparatus thereof
By partitioning the display panel of the electroluminescent display device and using memory and timing controller for compensation, the problem of driving characteristic deviation under large screen and high resolution is solved, and uniform image quality on the screen is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LG DISPLAY CO LTD
- Filing Date
- 2022-08-26
- Publication Date
- 2026-07-24
AI Technical Summary
In electroluminescent display devices, when used with large screens and high resolutions, the temporal variation of pixels and deviations in driving characteristics make it difficult to achieve uniform image quality across the entire screen.
By dividing the display panel into multiple display areas and setting up a memory and timing controller in each area, the compensation values of the pixels are stored and corrected. Internal and external compensation methods are used to drive the pixels uniformly, including internal compensation circuits and external sensing circuits to compensate for changes in driving characteristics.
It achieves uniform image quality on high-resolution and large-screen electroluminescent display devices, reduces visual steps near boundary lines, and improves the uniformity and stability of image quality.
Smart Images
Figure CN116266450B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to an electroluminescent display device and its driving device. Background Technology
[0002] With advancements in display processing and driving circuit technologies, the market for large-screen, high-resolution displays is expanding. To achieve high-quality images, display devices are being developed to enable high resolution, extended color depth, and high-speed driving.
[0003] Electroluminescent displays offer fast response times, excellent luminous efficiency, superior brightness, and wide viewing angles, resulting in high usability. However, as screen size and resolution increase, the temporal variation and driving characteristic deviations of each pixel increase based on screen position. Therefore, achieving high resolution and large screens to maintain uniform image quality across the entire screen can be challenging in electroluminescent displays. Summary of the Invention
[0004] To overcome the aforementioned limitations of the related technologies, this disclosure provides an electroluminescent display device and a driving device for the electroluminescent display device, the electroluminescent display device having high resolution and a large screen to achieve uniform image quality across the entire screen.
[0005] To achieve these objectives and other advantages, and in accordance with the purposes of this disclosure, as implemented and broadly described herein, an electroluminescent display device includes: a display panel including a first display area configured to display first image data and a second display area configured to display second image data; a first memory configured to store a first master compensation value and a first boundary compensation value corresponding to a first pixel in the first display area; a second memory configured to store a second master compensation value and a second boundary compensation value corresponding to a second pixel in the second display area; a first timing controller configured to correct the first image data based on the first master compensation value, the first boundary compensation value, and the second boundary compensation value; and a second timing controller configured to correct the second image data based on the second master compensation value, the second boundary compensation value, and the first boundary compensation value.
[0006] In another aspect of this disclosure, a driving device for an electroluminescent display apparatus is provided. The electroluminescent display apparatus includes: a first display area of a display panel, the first display area including a first pixel and displaying first image data; and a second display area of the display panel, the second display area including a second pixel and displaying second image data. The driving device may include: a first memory configured to store a first master compensation value and a first boundary compensation value corresponding to the first pixel; a second memory configured to store a second master compensation value and a second boundary compensation value corresponding to the second pixel; a first timing controller configured to correct the first image data based on the first master compensation value, the first boundary compensation value, and the second boundary compensation value; and a second timing controller configured to correct the second image data based on the second master compensation value, the second boundary compensation value, and the first boundary compensation value. Attached Figure Description
[0007] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:
[0008] Figure 1 This is a schematic diagram illustrating an electroluminescent display device according to one embodiment of the present disclosure;
[0009] Figure 2 It is a schematic diagram illustrating the pixel array, pixel circuitry included in the pixel array, and panel driving circuitry of an electroluminescent display device;
[0010] Figure 3 It is a front view viewed from the forward area relative to the electroluminescent display device;
[0011] Figure 4 This is a rear view viewed from the rear area relative to the electroluminescent display device;
[0012] Figure 5 This is a diagram illustrating an example of an electroluminescent display device whose display panel is divided into a first display area and a second display area and is driven by partitioning relative to the boundary line;
[0013] Figure 6 This is a diagram illustrating the connection configuration between the memory and timing controller used for partition driving;
[0014] Figure 7 This is a diagram illustrating the comparison result obtained by comparing the image display states where the boundary compensation values are shared with the image display states where the boundary compensation values are not shared; and
[0015] Figure 8 and Figure 9 This is a diagram illustrating the drive sequence between the memory and the timing controller used for partitioning. Detailed Implementation
[0016] In the following description of the electroluminescent display device according to embodiments of the present disclosure, organic light-emitting display devices will be primarily described, but the inventive concept is not limited thereto. Each pixel of the organic light-emitting display device according to embodiments of the present disclosure may include a driving element that controls the current flowing in the organic light-emitting diode (OLED) of each pixel. The driving element may be implemented as a transistor. The driving characteristics of the pixel, such as threshold voltage and mobility, may be designed to be equal across all pixels; however, due to non-uniformity in the manufacturing process and the driving environment, the electrical characteristics of the driving element are non-uniform.
[0017] In OLEDs and driving elements, the stress applied to them can increase with increasing driving time, and stress differences can occur due to data voltage. The electrical characteristics of the driving elements may be adversely affected by stress. With increasing driving time, pixels may degrade, and the degree of degradation between pixels may differ, thus resulting in image quality degradation that may be displayed on the screen.
[0018] Therefore, organic light-emitting display devices can compensate for the degradation of pixel driving characteristics and achieve uniform driving characteristics by using internal and external compensation methods.
[0019] Internal compensation methods can automatically compensate for threshold voltage deviations between driving elements in pixel circuits. To perform internal compensation, an internal compensation circuit can be added to each pixel. This circuit compensates for the data voltage using the threshold voltages of the OLED and driving elements, ensuring that the current flowing in the OLED is unaffected by these threshold voltages.
[0020] The external compensation method can sense the driving characteristics (threshold voltage, mobility, etc.) of each pixel and modulate the input video data of the external compensation circuit outside the display panel based on the sensing results to compensate for the changes in the driving characteristics of each pixel.
[0021] External compensation methods can sense the voltage or current of pixels by connecting sensing circuits to the pixels in the display panel, convert the sensing results into digital data using an analog-to-digital converter (ADC), and transmit the digital data to a timing controller. The timing controller can then modulate the digital video data of the input video based on the pixel sensing results to compensate for variations in the pixel's driving characteristics.
[0022] In the following embodiments, an example is shown where the pixel circuit is connected to a sensing circuit for external compensation; however, this disclosure is not limited thereto. For example, the pixel circuit according to this disclosure may also include an internal compensation circuit.
[0023] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.
[0024] The shapes, dimensions, ratios, angles, quantities, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary and are not intended to limit the disclosure. The same reference numerals consistently denote the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms “comprising,” “having,” “including,” etc., imply that additional parts may be added, unless the term “only” is used. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
[0025] Even without explicit statement, the elements in the various embodiments of this disclosure should be interpreted as including tolerance ranges.
[0026] When describing positional relationships, for example, when the positional relationship between two components is described as "above", "over", "below", and "next to", one or more other components may be placed between the two components, unless "exactly" or "directly" is used.
[0027] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.
[0028] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this description, detailed descriptions of known functions or configurations will be omitted where it is determined that such descriptions unnecessarily obscure the essential points of the present disclosure. In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
[0029] Figure 1This is a schematic diagram illustrating an electroluminescent display device according to one embodiment of the present disclosure. All components of the electroluminescent display device are operatively connected and configured. Furthermore, Figure 2 It is a schematic diagram illustrating the pixel array, pixel circuitry included in the pixel array, and panel driving circuitry of an electroluminescent display device.
[0030] Reference Figure 1 and Figure 2 An electroluminescent display device according to one embodiment of the present disclosure may include a display panel PNL, panel driving circuits SDRV and GDRV for driving the display panel PNL, a timing controller TCON for controlling the operation of the panel driving circuits SDRV and GDRV, and a memory MEM.
[0031] A pixel array, comprising multiple pixels arranged in a matrix, can be set in a display panel (PNL). The pixel array can be a display area for displaying input image data (DATA).
[0032] Multiple pixels can be arranged in the display area, and signal lines for transmitting drive voltages to the multiple pixels can also be arranged in the display area. The signal lines may include multiple data lines DL for transmitting data voltage Vdata, multiple gating lines GL for transmitting gating signals SCAN and SEN, and multiple readout lines RL for transmitting reference voltage VREF and sensing pixel drive characteristics. The signal lines arranged in the display area may also include drive voltage lines for transmitting high-level pixel voltage EVDD. In the display area, the data lines DL and readout lines RL may be arranged to extend in a first direction, and the gating lines GL may be arranged to extend in a second direction intersecting the first direction. The signal lines can be connected to the pixel circuitry of each pixel and can also be connected to the panel driving circuitry. Furthermore, a low-level pixel voltage EVSS can be provided to the display area. Here, the low-level pixel voltage EVSS may be a common voltage applied to all pixels. The low-level pixel voltage EVSS applied in a sensing mode for detecting drive characteristics may be higher than the low-level pixel voltage EVSS applied in a display mode for applying an image.
[0033] Multiple pixels can constitute a single unit pixel. For example, red (R), white (W), green (G), and blue (B) pixels adjacent to each other in the X direction can constitute a single unit pixel. However, R, G, and B pixels can constitute a single unit pixel, and in this case, the W sub-pixel can be omitted from the pixel array. The R, W, G, and B pixels can simply include different light-emitting materials included in the light-emitting device, and can be substantially the same in other configurations of the pixel circuitry. But this disclosure is not limited thereto. For example, it is also possible to include a single unit pixel comprising pixels of other color combinations.
[0034] like Figure 2 As shown, a pixel may include a light-emitting device (OLED), a driving thin-film transistor (TFT) DT, switching TFTs ST1 and ST2, and a storage capacitor Cst. The driving TFT DT and the switching TFTs ST1 and ST2 may each be implemented as NMOS transistors, but are not limited thereto. For example, at least one of the driving TFT DT and the switching TFTs ST1 and ST2 may be implemented as a PMOS transistor.
[0035] An OLED (Optical Display Cell) is a light-emitting device that emits light with an intensity corresponding to the pixel current input from the driving TFT DT. An OLED can be implemented as an OLED including an organic light-emitting layer, or as an inorganic light-emitting diode including an inorganic light-emitting layer. The anode electrode of the OLED can be connected to a second node N2, and its cathode can be connected to the input terminal of a low-level pixel voltage EVSS.
[0036] The driving TFT DT can be a driving element that generates pixel current based on the gate-source voltage. The gate electrode of the driving TFT DT can be connected to the first node N1, its first electrode (drain electrode) can be connected to the input terminal of the high-level pixel voltage EVDD, and its second electrode (source electrode) can be connected to the second node N2.
[0037] Switching TFTs (e.g., a first TFT and a second switching TFT) ST1 and ST2 can be switching elements that set the gate-source voltage of the driving TFT DT and connect the second electrode of the driving TFT DT to the readout line RL.
[0038] A first switch TFT ST1 can be connected between the data line DL and the first node N1, and can be turned on based on a first strobe signal SCAN from the first strobe line GL1. When the first switch TFT ST1 is turned on, a display or sensing data voltage VDATA can be applied to the first node N1. The gate electrode of the first switch TFT ST1 can be connected to the first strobe line GL1, its first electrode can be connected to the data line DL, and its second electrode can be connected to the first node N1.
[0039] The second switch TFT ST2 can be connected between the readout line RL and the second node N2, and can be turned on based on the second gating signal SEN from the second gating line GL2. The second switch TFT ST2 can be turned on during the setting (establishment) in both the display mode and the sensing mode, and can apply a reference voltage VREF to the second node N2. Furthermore, the second switch TFT ST2 can be turned on when performing a sensing operation after the setting in the sensing mode, and can transfer the source node voltage (or source voltage) driving the TFT DT to the readout line RL. Therefore, the sensing voltage Vsen corresponding to the source voltage can be stored in the parasitic capacitor Cp of the readout line RL. The gate electrode of the second switch TFT ST2 can be connected to the second gating line GL2, its first electrode can be connected to the readout line RL, and its second electrode can be connected to the second node N2.
[0040] The storage capacitor Cst can be connected between the first node N1 and the second node N2, and can maintain the gate-source voltage of the driving TFT DT for a specific duration. In display mode, the gate-source voltage of the driving TFT DT can be set to the voltage difference between the display data voltage VDATA and the reference voltage VREF, and in sensing mode, the gate-source voltage of the driving TFT DT can be set to the voltage difference between the sensing data voltage VDATA and the reference voltage VREF.
[0041] In display mode, the pixel current corresponding to the gate-source voltage of the driving TFT DT can flow in the driving TFT DT, and the OLED can emit light using the pixel current. In sensing mode, the pixel current corresponding to the gate-source voltage of the driving TFT DT can flow in the driving TFT DT, and the source node voltage of the driving TFT DT can be changed by the pixel current. Because the source node voltage changes based on the driving characteristics of the driving TFT DT, changes in the driving characteristics of the driving TFT DT can be detected based on the sensing voltage Vsen corresponding to the source node voltage. Furthermore, in sensing mode, because the low-level pixel voltage EVSS is applied at a level higher than the operating point voltage of the OLED, the pixel current of the driving TFT DT can flow only to the readout line RL instead of to the OLED. Therefore, the source node voltage can be reflected in the sensing node in a short time, thereby increasing sensing reliability.
[0042] This pixel configuration and operation may be just one implementation method, and the inventive concept is not limited thereto. For example, the first strobe signal SCAN and the second strobe signal SEN, as well as the first strobe line GL1 and the second strobe line GL2, can be implemented as a single unit. Furthermore, the pixel configuration can be designed based on a double-rate driving scheme.
[0043] The pixel driving circuit may include a data driver SDRV that provides a data voltage VDATA to the data line DL and a gating driver GDRV that provides gating signals SCAN and SEN synchronized with the data voltage VDATA to the gating lines GL of the pixel array.
[0044] The data driver SDRV may include a digital-to-analog converter (DAC) for generating a data voltage VDATA, a sensing circuit (SENU), and an analog-to-digital converter (ADC). In display mode, the DAC can convert image data DATA provided by the timing controller TCON into a display data voltage VDATA based on a source timing control signal, and can provide the display data voltage VDATA to the data line DL. In sensing mode, the DAC can generate a sensing data voltage VDATA, and can provide the sensing data voltage VDATA to the data line DL.
[0045] In display mode, the sensing circuit SENU can provide a reference voltage VREF to the readout line RL. In sensing mode, the sensing circuit SENU can provide a reference voltage VREF to the readout line RL and sample the sensing voltage Vsen charged into the readout line RL. The sensing circuit SENU may include a reference voltage switch SPRE connected between the readout line RL and the reference voltage VREF input terminal, and a sampling switch SAM connected between the readout line RL and the analog-to-digital converter ADC. The reference voltage switch SPRE may be turned on only during the setup cycle of display mode / sensing mode, and the sampling switch SAM may be turned on only during the sampling cycle of sensing mode.
[0046] In sensing mode, the analog-to-digital converter (ADC) can digitally process the sampled voltage generated when the sampling switch (SAM) is turned on, thereby outputting sensing result data (SDATA).
[0047] The gating driver GDRV can receive operating voltage and gating timing control signals through the data driver SDRV. The gating driver GDRV can be embedded in the non-display area outside the display area of the display panel PNL. The gating driver GDRV can generate a first gating signal SCAN and a second gating signal SEN based on the gating timing control signals, and can provide the first gating signal SCAN and the second gating signal SEN to the first gating line GL1 and the second gating line GL2. The first gating signal SCAN and the second gating signal SEN can select the pixel rows to which display data voltage VDATA will be applied in display mode, and can also select the pixel rows to which sensing data voltage VDATA will be applied in sensing mode. Here, a pixel row can represent a group of signal lines and pixels adjacent to each other in the X direction.
[0048] The memory MEM can store compensation values used to compensate for changes in the driving characteristics of pixels. The pixel compensation values stored in the memory MEM can be updated whenever the sensing mode is repeated. The memory MEM can be implemented as a flash memory.
[0049] When the system is powered on, the timing controller TCON can access the memory MEM and read pixel compensation values from the memory MEM. The timing controller TCON may include external compensation circuitry that corrects the video data based on the pixel compensation values to compensate for variations in pixel driving characteristics.
[0050] In accordance with this embodiment, including Figure 1 and Figure 2 The electroluminescent display device shown herein comprises a display area, panel driving circuits SDRV and GDRV, timing controller TCON, and memory MEM disposed on a display panel substrate. A display device with high resolution and a large screen can be realized by a combination of two or more of these components.
[0051] Figure 3 This is a front view viewed from the forward area relative to the electroluminescent display device. Figure 4 This is a rear view viewed from the area behind the electroluminescent display device. Figure 5 This is an illustration of an electroluminescent display device whose display panel is divided into a first display area and a second display area and is partitioned and driven relative to the boundary line.
[0052] Reference Figures 3 to 5 The display panel PNL's screen can be divided into two display areas (e.g., a first display area and a second display area), LS and RS. The first display area LS can be located on the left side of the screen and can be controlled by a first timing controller TCON1. The second display area RS can be located on the right side of the screen and can be controlled by a second timing controller TCON2.
[0053] The data driver SDRV can be integrated into the source driver integrated circuit (IC) SiC and can be connected to the data line DL and the read line RL. The gating driver GDRV can be directly mounted on the substrate of the display panel PNL. Figure 3 In this context, the gate inside the panel (GIP) can refer to the gate driver GDRV that is directly disposed on the substrate of the display panel PNL.
[0054] exist Figure 3In this context, "LRB" can represent the boundary line between the first display area LS and the second display area RS. The boundary line LRB can represent the boundary line controlled by the first timing controller TCON1 and the second timing controller TCON2 at different timings. The boundary line LRB may not represent the physical division of the substrate of the display panel PNL, but is not limited to this.
[0055] The chip-on-film (COF) layer on which the source driver IC (SiC) is mounted can be connected between the display panel PNL and the source printed circuit board (PCB). The gating drive voltage and gating timing control signals used to control the gating drivers GIP1 and GIP2 can be transmitted to the gating drivers GIP1 and GIP2 of the display panel PNL through the COF.
[0056] The first timing controller TCON1 and the second timing controller TCON2 can be mounted on the control board CPCB together with the memories MEM1 and MEM2. The first timing controller TCON1 and the second timing controller TCON2 can each be implemented as an application-specific integrated circuit (ASIC), but are not limited thereto.
[0057] The first timing controller TCON1 and the second timing controller TCON2 can receive high-resolution input video from the host system 300. The first timing controller TCON1 and the second timing controller TCON2 can respectively control the driving of the first display area LS and the second display area RS. The first timing controller TCON1 can divide the high-resolution input video into first video data to be applied to the first display area LS, and the second timing controller TCON2 can divide the high-resolution input video into second video data to be applied to the second display area RS.
[0058] The memories MEM1 and MEM2 may include a first memory MEM1 storing a first compensation value corresponding to a pixel in the first display area LS and a second memory MEM2 storing a second compensation value corresponding to a pixel in the second display area RS. The first compensation value of the first memory MEM1 may include a first main compensation value and a first boundary compensation value, and the second compensation value of the second memory MEM2 may include a second main compensation value and a second boundary compensation value.
[0059] The first timing controller TCON1 and the second timing controller TCON2 can share the boundary compensation value Edata stored in memories MEM1 and MEM2. The first timing controller TCON1 can access the first memory MEM1 to read a first compensation value (main compensation value + boundary compensation value) and can access the second memory MEM2 to read a second boundary compensation value. The first timing controller TCON1 can correct the first video data based on the read compensation values. The second timing controller TCON2 can access the second memory MEM2 to read the second compensation value (main compensation value + boundary compensation value) and can access the first memory MEM1 to read the first boundary compensation value. The second timing controller TCON2 can correct the second video data based on the read compensation values. Because each of the first timing controller TCON1 and the second timing controller TCON2 references both the first and second boundary compensation values to correct the video data, the possibility of visual staircases appearing near the boundary line LRB can be minimized.
[0060] The motherboard of the host system 300 may include a user input device for receiving user commands, a communication module for communicating with peripheral devices, a communication module for connecting to a communication network such as the Internet, and a graphics processing module for connecting to an electroluminescent display device. The motherboard may be connected to a power source that generates electricity. The power source may provide commercial alternating current (AC) power or battery power to the motherboard and panel driver circuitry. The host system 300 may be a system that requires a display device, such as a television system or a computer system.
[0061] Level shifters and power management integrated circuits (PMICs) can also be mounted on the control board (CPCB). The PMIC can receive a direct current (DC) input voltage using a DC-DC converter to output various DC voltages required to drive the display panel, such as EVDD, EVSS, gate high voltage (VGH), gate low voltage (VGL), and gamma reference voltage.
[0062] A level shifter can shift the voltage level of the gating timing control signals received from the first timing controller TCON1 and the second timing controller TCON2 to generate a voltage that swings between VGH and VGL. Scan pulses output from gating drivers GIP1 and GIP2 can swing between VGH and VGL. The gating high voltage (VGH) can be the gating on-state voltage for the switching TFT used to turn on the pixel circuit. The gating low voltage (VGL) can be the gating off-state voltage for the switching TFT used to turn off the pixel circuit. However, this disclosure is not limited thereto. When the switching TFT is implemented as a PMOS transistor, the gating high voltage (VGH) can also be the gating off-state voltage for the switching TFT used to turn off the pixel circuit.
[0063] Each of the first timing controller TCON1 and the second timing controller TCON2 can transmit the corrected image data to the source driver IC SIC controlled by it. Furthermore, each of the first timing controller TCON1 and the second timing controller TCON2 can transmit control data and clock along with the corrected image data to the source driver IC SIC controlled by it.
[0064] The control board CPCB can be connected to the source PCB SPCB via a flexible flat cable (FFC), and can also be connected to the motherboard of the host system 300 via an FFC.
[0065] The gate line GL can cross the boundary line LRB between the first display area LS and the second display area RS, and is set in horizontally adjacent display areas without being broken. For example... Figure 5 As shown, gating drivers GIP1 and GIP2 can be connected to both sides of gating line GL. Scan pulses can be simultaneously applied to both sides of the same gating line through gating drivers GIP1 and GIP2 connected to both ends of gating line GL.
[0066] The data lines DL and RL in the first display area LS of the display panel PNL can be connected to the source driver IC SIC1 that drives the first display area LS. The data lines DL and RL in the second display area RS of the display panel PNL can be connected to the source driver IC SIC2 that drives the second display area RS.
[0067] The first timing controller TCON1 can transmit the corrected image data of the first display area LS to the source driver IC SIC1 in the first drive circuit SIC1 and GIP1. Figure 5 As shown, the first timing controller TCON1 can control the operating timing of the first driving circuits SIC1 and GIP1 used to drive the pixels of the first display area LS.
[0068] The second timing controller TCON2 can transmit the corrected image data of the second display area RS to the source driver IC SIC2 in the second drive circuit SIC2 and GIP2. For example... Figure 5 As shown, the second timing controller TCON2 can control the operating timing of the second driving circuits SIC2 and GIP2 used to drive the pixels of the second display area RS.
[0069] The first timing controller TCON1 and the second timing controller TCON2 can also execute image quality enhancement algorithms based on the data calculation results of the boundary surface between the display areas LS and RS.
[0070] Figure 6This is a diagram showing the connection configuration between the memory and the timing controller used for partition driving. Figure 7 This is a diagram showing the comparison results obtained by comparing the image display state with the image display state without the shared boundary compensation value.
[0071] Reference Figure 6 When the system power is on, the timing controllers (e.g., the first timing controller and the second timing controller) TCON1 and TCON2 can access the memories (e.g., the first memory and the second memory) MEM1 and MEM2. The access time of each of the timing controllers TCON1 and TCON2 can be controlled by the control signal Csig.
[0072] The first memory MEM1 may include a first main region MAIN1 storing a first main compensation value Mdata1 and a first sub-region SUB1 storing a first boundary compensation value Edata1. The second memory MEM2 may include a second main region MAIN2 storing a second main compensation value Mdata2 and a second sub-region SUB2 storing a second boundary compensation value Edata2.
[0073] The first boundary compensation value Edata1 can be a common compensation value, used to compensate for both the driving characteristic deviation of the first pixel located near the boundary line of the screen in the first display area and the driving characteristic deviation of the second pixel located near the boundary line in the second display area. Similarly, the second boundary compensation value Edata2 can be a common compensation value, used to compensate for both the driving characteristic deviation of the first pixel located near the boundary line of the screen in the first display area and the driving characteristic deviation of the second pixel located near the boundary line in the second display area. The expression "near the boundary line" means that the distance to the boundary line is less than half the width of the screen, for example, less than 1080 pixels, less than 540 pixels, less than 10 pixels, less than 5 pixels, or even less than 3 pixels.
[0074] The first primary compensation value Mdata1 may include compensation values for compensating for driving characteristic deviations of pixels in the first display area other than the first pixel. Furthermore, the second primary compensation value Mdata2 may include compensation values for compensating for driving characteristic deviations of pixels in the second display area other than the second pixel.
[0075] Driving characteristic deviations may include one or more of the threshold voltage deviation of the driving TFT included in the pixel, the electron mobility deviation of the driving TFT, and the threshold voltage deviation of the light-emitting device. The sensed values representing the driving characteristic deviations can be periodically updated in the sensing mode, and whenever a new sensed value is obtained, the compensation values Mdata1, 2 and Edata1, 2 can be updated and stored in memories MEM1 and MEM2. When the system power is on, the first timing controller TCON1 can exclusively occupy (or control) the first main area MAIN1 of the first memory MEM1 and can read the first main compensation value Mdata1 from the first main area MAIN1 of the first memory MEM1. When the system power is on, the second timing controller TCON2 can exclusively occupy (or control) the second main area MAIN2 of the second memory MEM2 and can read the second main compensation value Mdata2 from the second main area MAIN2.
[0076] When the system power is turned on, the timing controllers TCON1 and TCON2 can share the first sub-region SUB1 and the second sub-region SUB2 of the first memory MEM1 and the second memory MEM2, read the first boundary compensation value Edata1 from the first sub-region SUB1, and read the second boundary compensation value Edata2 from the second sub-region SUB2.
[0077] The first timing controller TCON1 can correct the first video data DATA1 based on a first main compensation value Mdata1, a first boundary compensation value Edata1, and a second boundary compensation value Edata2. For example, the first timing controller TCON1 can apply the first main compensation value Mdata1, the first boundary compensation value Edata1, and the second boundary compensation value Edata2 to a predetermined compensation algorithm to calculate a first data correction offset and a first data correction gain, and can correct the first video data DATA1 by adding the first data correction offset to the first video data DATA1 and multiplying the first video data DATA1 by the first data correction gain.
[0078] The second timing controller TCON2 can correct the second video data DATA2 based on the second main compensation value Mdata2, the first boundary compensation value Edata1, and the second boundary compensation value Edata2. For example, the second timing controller TCON2 can apply the second main compensation value Mdata2, the first boundary compensation value Edata1, and the second boundary compensation value Edata2 to a predetermined compensation algorithm to calculate the second data correction offset and the second data correction gain, and can correct the second video data DATA2 by adding the second data correction offset to the second video data DATA2 and multiplying the second video data DATA2 by the second data correction gain.
[0079] When the first boundary compensation value Edata1 and the second boundary compensation value Edata2 are applied to the compensation algorithm, the first timing controller TCON1 and the second timing controller TCON2 can use the average of the first boundary compensation value Edata1 and the second boundary compensation value Edata2. However, this disclosure is not limited to this, and other algorithms are also possible. For example, the first timing controller TCON1 and the second timing controller TCON2 can use the root mean square of the first boundary compensation value Edata1 and the second boundary compensation value Edata2. The first timing controller TCON1 and the second timing controller TCON2 can perform image data correction processing on pixels near the boundary line based on the correlation between the shared first boundary compensation value Edata1 and the second boundary compensation value Edata2, thus greatly reducing the possibility of visual steps appearing near the boundary line.
[0080] like Figure 7 As shown, it can be seen that the visual steps near the boundary line LRB are reduced more in the image display state with shared boundary compensation values than in the image display state without shared boundary compensation values. Distortion of the input image near the boundary line LRB can be minimized when the first boundary compensation value Edata1 and the second boundary compensation value Edata2 are correlated in the image processing (i.e., compensation processing) operation.
[0081] Furthermore, the first timing controller TCON1 and the second timing controller TCON2 can associate the shared first boundary compensation value Edata1 with the shared second boundary compensation value Edata2 and can perform image processing, thereby enhancing the accuracy and reliability of compensation for time variations of the display panel.
[0082] Figure 8 and Figure 9 This is a diagram illustrating the drive sequence between the memory and the timing controller used for partitioning.
[0083] Reference Figure 8 and Figure 9 When the system power is turned on, a reset signal can be generated. Subsequently, the timing controllers TCON1 and TCON2 can read the global compensation parameters (e.g., first global compensation parameter and second global compensation parameter) PARA1 and PARA2 from separate registers. The global compensation parameters PARA1 and PARA2 can be parameters applied to the image quality compensation algorithm. The first global compensation parameter PARA1 can be applied to the first image data of the pixels to be applied to the first display area, and the second global compensation parameter PARA2 can be applied to the second image data of the pixels to be applied to the second display area.
[0084] When the read operations on global compensation parameters PARA1 and PARA2 are completed, timing controllers TCON1 and TCON2 can simultaneously access memories (e.g., a first memory and a second memory) MEM1 and MEM2, and can read compensation values from them. In other words, in response to the first control signal Csig1, the first timing controller TCON1 can access the first main region MAIN1 and the first sub-region SUB1 of the first memory MEM1, and can read the first main compensation value and the first boundary compensation value. At this time, in response to the second control signal Csig2, the second timing controller TCON2 can access the second main region MAIN2 and the second sub-region SUB2 of the second memory MEM2, and can read the second main compensation value and the second boundary compensation value. In the first timing, both the first control signal Csig1 and the second control signal Csig2 can be activated.
[0085] Subsequently, at a second timing different from the first timing, in response to the first control signal Csig1, the first timing controller TCON1 can access the second sub-region SUB2 of the second memory MEM2 and can read the second boundary compensation value. At the second timing, in response to the second control signal Csig2, the second timing controller TCON2 can be in a Hi-Z state, thus preventing access conflicts between timing controllers TCON1 and TCON2. At the second timing, the first control signal Csig1 can be activated, and the second control signal Csig2 can be deactivated.
[0086] Subsequently, at a third timing, different from the first and second timings, in response to the second control signal Csig2, the second timing controller TCON2 can access the first sub-region SUB1 of the first memory MEM1 and can read the first boundary compensation value. In the third timing, in response to the first control signal Csig1, the first timing controller TCON1 can be in a Hi-Z state, thus preventing access conflicts between timing controllers TCON1 and TCON2. In the third timing, the second control signal Csig2 can be activated, and the first control signal Csig1 can be deactivated.
[0087] This implementation method can achieve the following effects.
[0088] In this embodiment, the display panel screen can be divided into multiple display areas and driven. Because the timing controller used to control the partition driving of the display areas performs image processing based on shared boundary compensation values, the possibility of visual staircases appearing near the boundary lines between display areas can be greatly reduced.
[0089] Therefore, this embodiment can provide a display device with high resolution and a large screen to achieve uniform image quality across the entire screen.
[0090] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.
[0091] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of this disclosure as defined by the appended claims.
[0092] Intersection of related applications
[0093] This application claims priority to Korean Patent Application No. 10-2021-0180764, filed in Korea on December 16, 2021, the entire contents of which are expressly incorporated herein by reference.
Claims
1. An electroluminescent display device, the electroluminescent display device comprising: The display panel includes a first display area configured to display first image data and a second display area configured to display second image data; A first memory, configured to store a first master compensation value and a first boundary compensation value corresponding to a first pixel in the first display area; A second memory is configured to store a second main compensation value and a second boundary compensation value corresponding to a second pixel in the second display area; A first timing controller is configured to control the first image data based on the first master compensation value, the first boundary compensation value, and the second boundary compensation value. as well as A second timing controller is configured to control the second image data based on the second master compensation value, the second boundary compensation value, and the first boundary compensation value. The first timing controller and the second timing controller are configured to associate the first boundary compensation value with the second boundary compensation value to perform image processing.
2. The electroluminescent display device according to claim 1, further comprising: A first driving circuit is configured to apply corrected first image data to the first pixel based on the control of the first timing controller. as well as A second driving circuit, configured to apply corrected second image data to the second pixel based on the control of the second timing controller.
3. The electroluminescent display device according to claim 1, wherein, The first memory includes a first main region configured to store the first main compensation value and a first sub-region configured to store the first boundary compensation value, and The second memory includes a second main region configured to store the second main compensation value and a second sub-region configured to store the second boundary compensation value.
4. The electroluminescent display device according to claim 3, wherein, The first timing controller exclusively occupies the first main area of the first memory. The second timing controller exclusively occupies the second main region of the second memory, and The first timing controller and the second timing controller share the first sub-region of the first memory and the second sub-region of the second memory.
5. The electroluminescent display device according to claim 4, wherein, The first timing controller accesses the first main region and the first sub-region of the first memory at a first timing interval, and The second timing controller accesses the second main region and the second sub-region of the second memory at the first timing.
6. The electroluminescent display device according to claim 5, wherein, The first timing controller accesses the second sub-region of the second memory at a second timing different from the first timing, and The second timing controller accesses the first sub-region of the first memory at a third timing, different from the first and second timings.
7. The electroluminescent display device according to claim 1, wherein, The first display area and the second display area are divided along the direction of the gate lines of the display panel.
8. The electroluminescent display device according to claim 7, wherein, The selection line is set across the boundary line between the first display area and the second display area without being broken.
9. The electroluminescent display device according to claim 7, wherein, The first boundary compensation value is a common compensation value used to compensate for the driving characteristic deviation of pixels located near the boundary line in both the first display area and the second display area. The second boundary compensation value is a common compensation value used to compensate for the driving characteristic deviation of pixels located near the boundary line in both the first display area and the second display area.
10. The electroluminescent display device according to claim 9, wherein, The first main compensation value includes a compensation value for compensating for the driving characteristic deviation of pixels in the first display area other than those disposed near the boundary line, and The second main compensation value includes a compensation value used to compensate for the driving characteristic deviation of pixels in the second display area other than the pixels located near the boundary line.
11. The electroluminescent display device according to claim 9, wherein, The drive characteristic deviation includes one or more of the following: Threshold voltage deviation of the driving thin-film transistor TFT included in the pixel. The electron mobility deviation of the driving TFT, and Threshold voltage deviation of light-emitting devices.
12. The electroluminescent display device according to claim 1, wherein, The first timing controller controls the first image data based on the average of the first boundary compensation value and the second boundary compensation value, and the first master compensation value. The second timing controller controls the second image data based on the average of the first boundary compensation value and the second boundary compensation value and the second main compensation value.
13. A driving device for an electroluminescent display device, the electroluminescent display device comprising: A first display area of a display panel, the first display area including a first pixel; and a second display area of the display panel, the second display area including a second pixel, the first display area being configured to display first image data, and the second display area being configured to display second image data, the driving device comprising: A first memory, configured to store a first master compensation value and a first boundary compensation value corresponding to a first pixel in the first display area; A second memory is configured to store a second main compensation value and a second boundary compensation value corresponding to a second pixel in the second display area; A first timing controller, configured to correct the first image data based on a first master compensation value, a first boundary compensation value, and a second boundary compensation value; and A second timing controller is configured to correct the second image data based on the second master compensation value, the second boundary compensation value, and the first boundary compensation value. The first timing controller and the second timing controller are configured to associate the first boundary compensation value with the second boundary compensation value to perform image processing.
14. The driving device according to claim 13, further comprising: A first driving circuit is configured to apply corrected first image data to the first pixel based on the control of the first timing controller. as well as A second driving circuit, configured to apply corrected second image data to the second pixel based on the control of the second timing controller.
15. The driving device according to claim 13, wherein, The first memory includes a first main region configured to store the first main compensation value and a first sub-region configured to store the first boundary compensation value, and The second memory includes a second main region configured to store the second main compensation value and a second sub-region configured to store the second boundary compensation value.
16. The driving device according to claim 15, wherein, The first timing controller exclusively occupies the first main area of the first memory. The second timing controller exclusively occupies the second main region of the second memory, and The first timing controller and the second timing controller share the first sub-region of the first memory and the second sub-region of the second memory.
17. The driving device according to claim 16, wherein, The first timing controller accesses the first main region and the first sub-region of the first memory at a first timing interval, and The second timing controller accesses the second main region and the second sub-region of the second memory at the first timing.
18. The driving device according to claim 17, wherein, The first timing controller accesses the second sub-region of the second memory at a second timing different from the first timing, and The second timing controller accesses the first sub-region of the first memory at a third timing, different from the first and second timings.