Memory system and semiconductor memory device

Abstract

This invention provides a memory system and a semiconductor memory device capable of better control of a semiconductor memory device. The memory system includes a memory controller and a semiconductor memory device. The memory device includes a first plurality of memory cells and a first word line connected to the first plurality of memory cells. The controller sends a first write instruction to the memory device when data is written to the first plurality of memory cells. In response to the first write instruction, the memory device executes a program action and generates a first index based on the number of repetitions of a program loop in the program action, wherein the program action involves repeatedly executing the program loop, including applying a write voltage to the first word line, until a first condition is met. The controller reads the first index from the memory device and, based on the read first index, determines whether to perform a first read verification of data read from the first plurality of memory cells.

Description

[0001] [Related Applications]

[0002] This application enjoys priority to Japanese Patent Application No. 2021-204259 (filed on December 16, 2021). This application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a memory system and a semiconductor memory device. Background Technology

[0004] A memory system is known, comprising: a memory controller, and a semiconductor storage device that performs program operations in response to write instructions received from the memory controller. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a memory system and a semiconductor memory device that can better control a semiconductor memory device.

[0006] The memory system of the embodiment includes a memory controller and a semiconductor memory device. The semiconductor memory device includes a first plurality of memory cells and a first word line connected to the first plurality of memory cells. The memory controller sends a first write instruction to the semiconductor memory device when data is written to the first plurality of memory cells. In response to the first write instruction, the semiconductor memory device executes a program operation and generates a first index based on the number of repetitions of a program loop in the program operation, wherein the program operation involves repeatedly executing the program loop, including applying a write voltage to the first word line, until a first condition is met. The memory controller reads the first index from the semiconductor memory device and, based on the read first index, determines whether to perform a first read verification of reading data from the first plurality of memory cells. Attached Figure Description

[0007] Figure 1 This is a block diagram showing the configuration of the memory system in the first embodiment.

[0008] Figure 2 This is a block diagram illustrating the configuration of the semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a diagram showing the circuit configuration included in the memory cell array of the first embodiment.

[0010] Figure 4 This is a diagram illustrating the distribution of the threshold voltage of the memory cell in the first embodiment.

[0011] Figure 5 This is a diagram used to illustrate the data writing operation of the first embodiment.

[0012] Figure 6 This is a diagram used to illustrate the read verification of the first embodiment.

[0013] Figure 7 This is a graph used to illustrate the deviation of the threshold distribution of the storage cells in the first embodiment.

[0014] Figure 8 This is a diagram illustrating an example of the VPS range counting table in the first embodiment.

[0015] Figure 9 This is a flowchart illustrating the processing flow of the semiconductor memory device according to the first embodiment.

[0016] Figure 10 This is a flowchart illustrating an example of the processing of the memory controller in the first embodiment.

[0017] Figure 11 (a) to (c) are diagrams showing an example of the VPS range counting table in the second embodiment.

[0018] Figure 12 (a) to (b) are diagrams showing an example of the VPS range counting table in the third embodiment.

[0019] Figure 13 This is a block diagram illustrating the configuration of the semiconductor memory device according to the fourth embodiment. Detailed Implementation

[0020] Hereinafter, the memory system and semiconductor memory device according to embodiments will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions will be labeled with the same symbols. Furthermore, repeated descriptions of these components are sometimes omitted. The term "based on XX" means "at least based on XX," and may include cases based on another element besides XX. Furthermore, "based on XX" is not limited to the direct use of XX, and may also include cases based on operations or processing of XX. "XX" is any element (e.g., any information). The term "connection" is not limited to mechanical connections, and may also include electrical connections. That is, the term "connection" is not limited to direct connection to an object, and may also include cases where another element is interposed therebetween for connection.

[0021] (First Embodiment)

[0022] (1. Overall Structure of the Memory System)

[0023] Figure 1This is a block diagram illustrating the configuration of the memory system 1 according to the first embodiment. The memory system 1 is, for example, a storage device such as an SSD (Solid State Drive). The memory system 1 communicates with an external host device 2 and performs various actions according to requests from the host device 2.

[0024] The memory system 1 may include, for example, a memory controller 10, one or more semiconductor storage devices 20, and one or more DRAM (Dynamic Random Access Memory) 30.

[0025] (Memory controller)

[0026] The memory controller 10 is a controller that controls the memory system 1. For example, the memory controller 10 controls the data writing, reading, and erasing operations of the semiconductor memory device 20 according to requests from the host device 2.

[0027] The memory controller 10 includes, for example, a host interface circuit (hereinafter referred to as "host I / F") 11, RAM (Random Access Memory) 12, ROM (Read Only Memory) 13, CPU (Central Processing Unit) 14, ECC (Error Check and Correct) circuitry 15, NAND (Not AND) interface circuitry (hereinafter referred to as "NAND I / F") 16, and DRAM interface circuitry (hereinafter referred to as "DRAM I / F") 17. These components are interconnected via a bus 18. The memory controller 10 is, for example, a SoC (System on a Chip) in which these components are integrated into a single chip. A portion of these components may be located externally to the memory controller 10.

[0028] The host I / F 11 is connected to the host device 2. Under the control of the CPU 14, the host I / F 11 performs data transfer between the host device 2 and the memory controller 10. The RAM 12 is a volatile storage unit. The RAM 12 provides a working area to the CPU 14. When the memory system 1 operates, the firmware (program) is loaded from the ROM 13 into the RAM 12. The CPU 14 is an example of a hardware processor. The CPU 14 controls the operation of the memory controller 10 by executing the firmware loaded into the RAM 12.

[0029] ECC circuit 15 encodes the data to be written to semiconductor memory device 20 (hereinafter referred to as "write data") for error correction. If the data read from semiconductor memory device 20 (hereinafter referred to as "read data") contains errors, ECC circuit 15 performs error correction on the read data based on the error correction code assigned during the write operation.

[0030] NAND1 / F16 is connected to semiconductor memory device 20. Under the control of CPU 14, NAND1 / F16 performs data transfer between memory controller 10 and semiconductor memory device 20. DRAM1 / F17 is connected to DRAM 30. Under the control of CPU 14, DRAM1 / F17 performs data transfer between memory controller 10 and DRAM 30.

[0031] (Semiconductor memory device)

[0032] Semiconductor memory device 20 is a non-volatile semiconductor memory device. Semiconductor memory device 20 is, for example, a NAND flash memory. Semiconductor memory device 20 will be described in detail below.

[0033] (DRAM)

[0034] DRAM 30 is a volatile semiconductor memory device. DRAM 30 functions as a data buffer for data transfer between host device 2 and semiconductor memory device 20. For example, DRAM 30 temporarily stores write data received from host device 2. DRAM 30 may be integrated into memory controller 10.

[0035] (2. Composition of semiconductor memory devices)

[0036] (2.1 Overall Structure of Semiconductor Memory Devices)

[0037] Next, the semiconductor memory device 20 will be described.

[0038] Figure 2 This is a block diagram illustrating the configuration of a semiconductor memory device 20. The semiconductor memory device 20 includes, for example, an input / output circuit 101, a logic control circuit 102, a status register 103, an address register 104, an instruction register 105, a control circuit (sequencer) 106, a threshold storage unit 107, a voltage generation circuit 108, a memory cell array 109, a row address buffer 110, a row decoder 111, a column address buffer 112, a column decoder 113, a data register 114, and a sense amplifier 115.

[0039] Input / output circuit 101 controls the input and output of data signal DQ between memory controller 10 and semiconductor memory device 20. Input / output circuit 101 includes, for example, input circuitry and output circuitry. Input circuitry receives data DAT (e.g., write data WD), address ADD, and instruction CMD from memory controller 10 in the form of data signal DQ. Input circuitry outputs the received data DAT to data register 114, the received address ADD to address register 104, and the received instruction CMD to instruction register 105. Output circuitry outputs status information STS received from status register 103 and data DAT received from data register 114 (e.g., read data RD) to memory controller 10 in the form of data signal DQ.

[0040] The logic control circuit 102 receives various control signals CS from the memory controller 10. The logic control circuit 102 controls the input / output circuit 101 and the control circuit 106 according to the received control signals CS.

[0041] Status register 103 stores status information STS set by control circuit 106. Status information STS indicates the status of semiconductor memory device 20. For example, status information STS indicates whether a write operation, read operation, or erase operation of data DAT in semiconductor memory device 20 has been completed normally. When a status retrieval command is received from memory controller 10, the status information STS stored in status register 103 is sent to memory controller 10 via input / output circuit 101.

[0042] In this embodiment, the status register 103 includes a register 103a that stores an indicator representing the reliability of a write operation (hereinafter referred to as the "write reliability indicator"). For distinction, register 103a will be referred to as the "FDI (Fine Data Information) register 103a". The write reliability indicator stored in the FDI register 103a is sent to the memory controller 10 via the input / output circuit 101 upon receiving a status retrieval instruction corresponding to the write reliability indicator from the memory controller 10. The write reliability indicator will be described in detail below.

[0043] Address register 104 temporarily stores the address ADD received from memory controller 10 via input / output circuit 101. Address register 104 transfers the row address RA contained in the stored address ADD to row address buffer 110, and transfers the column address CA contained in the stored address ADD to column address buffer 112.

[0044] Instruction register 105 temporarily stores the instruction CMD received from memory controller 10 via input / output circuit 101. Instruction register 105 then transmits the stored instruction CMD to control circuit 106.

[0045] The control circuit 106 controls the overall operation of the semiconductor memory device 20. For example, the control circuit 106 controls the status register 103, voltage generation circuit 108, row decoder 111, column decoder 113, data register 114, and sense amplifier 115 according to the instruction CMD stored in the instruction register 105. Thus, the control circuit 106 performs write, read, or erase operations in the semiconductor memory device 20. When the processing of the instruction CMD is complete, the control circuit 106 controls the standby / busy signal R / Bn and notifies the memory controller 10 that processing is complete. Additionally, when the processing of the instruction CMD is complete, the control circuit 106 sets status information STS indicating the processing result in the status register 103. In this embodiment, the control circuit 106 has an index generation unit 106a that generates a write reliability index. The index generation unit 106a will be described in detail below.

[0046] The threshold storage unit 107 stores threshold information (e.g., a set of thresholds) used to generate write reliability metrics. The threshold storage unit 107 may be provided separately from the memory cell array 109, or it may be provided as part of the memory cell array 109. The threshold storage unit 107 will be described in detail below.

[0047] The voltage generation circuit 108 generates the voltage required for write, read, or erase operations according to the control circuit 106. The voltage generation circuit 108 supplies the generated voltage to the memory cell array 109, the line decoder 111, and the sense amplifier 115.

[0048] The storage cell array 109 has multiple blocks BLK (BLK0, BLK1, ..., BLK(L-1) (L is an integer greater than or equal to 1)). Each block BLK contains multiple non-volatile storage cells MT that correspond to rows and columns. Each block BLK stores data DAT non-volatilely by means of voltage applied by the row decoder 111.

[0049] The row address buffer 110 temporarily stores the row address RA received from the address register 104. The row decoder 111 selects the memory cell MT included in the memory cell array 109 based on the decoding result of the row address RA. The row decoder 111 applies the required voltage to the selected memory cell MT.

[0050] Column address buffer 112 temporarily stores the column address CA received from address register 104. Column decoder 113 selects the latch circuit in data register 114 based on the decoding result of column address CA.

[0051] Data register 114 includes multiple latching circuits. Each latching circuit temporarily stores write data WD or read data RD. During a write operation, data register 114 temporarily stores the write data WD received from input / output circuit 101 and outputs the stored write data WD to sense amplifier 115. During a read operation, data register 114 temporarily stores the read data RD received from sense amplifier 115 and outputs the stored read data RD to input / output circuit 101.

[0052] During a write operation, the sense amplifier 115 stores the write data WD received from the data register 114 into the memory cell array 109. During a read operation, the sense amplifier 115 senses the state of the plurality of memory cells MT contained in the memory cell array 109 and generates read data RD based on the sensed state. The sense amplifier 115 stores the generated read data RD into the data register 114.

[0053] (2.2 Composition of the memory cell array)

[0054] Next, the configuration of the storage cell array 109 will be explained.

[0055] Figure 3 This is a diagram showing the circuitry contained in the memory cell array 109, and it selectively represents one block BLK out of the multiple blocks BLK contained in the memory cell array 109. For example, a block BLK contains four serial cells SU0 to SU3.

[0056] Each string cell SU contains multiple NAND strings NS associated with bit lines BL0 to BL(M-1) (where M is an integer greater than or equal to 1). Hereinafter, without distinguishing between bit lines BL0 to BL(M-1), they will be simply referred to as "bit lines BL". Each NAND string NS includes, for example, memory cells MT0 to MT(N-1) (where N is an integer greater than or equal to 1), a first selection transistor ST1, and a second selection transistor ST2. Each memory cell MT is a memory cell transistor that includes a control gate and a charge accumulation layer and non-volatilely stores data. The first selection transistor ST1 and the second selection transistor ST2 are used to select the NAND string NS for various operations.

[0057] In each NAND string NS, memory cells MT0 to MT(N-1) are connected in series. The drain of the first select transistor ST1 is connected to the bit line BL corresponding to the NAND string NS. The source of the select transistor ST1 is connected to one end of the series-connected memory cells MT0 to MT(N-1). The drain of the second select transistor ST2 is connected to the other end of the series-connected memory cells MT0 to MT(N-1). The source of the select transistor ST2 is connected to the source line SL.

[0058] Within the same block BLK, the control gates of memory cells MT0 to MT(N-1) are all connected to word lines WL0 to WL(N-1). The gates of the first selection transistor ST1 within serial cells SU0 to SU3 are all connected to selection gate lines SGD0 to SGD3. The gates of the second selection transistor ST2 within serial cells SU0 to SU3 are all connected to selection gate lines SGS0 to SGS3.

[0059] A collection of multiple storage units MT connected to a common word line WL within a single string unit SU is called a cell assembly CU. For example, the storage capacity of a cell assembly CU containing multiple storage units MT that each store 1 bit of data is defined as "1 page of data". A cell assembly CU may have a storage capacity of 2 pages or more, corresponding to the number of bits of data stored in the storage units MT.

[0060] (3. Basic Operations of Semiconductor Memory Devices)

[0061] (3.1 Distribution of threshold voltage in memory cells)

[0062] Figure 4 This is a graph used to illustrate the distribution of the threshold voltage of the memory cell MT. In Figure 4 In the diagram, the horizontal axis represents the threshold voltage of the memory cell MT, and the vertical axis represents the number of memory cells MT that present a certain bit value (data value). Here, for clarity, the example is given where each memory cell MT is a multi-level cell (MLC) capable of storing 2 bits of data. However, this embodiment can also be applied to cases where the memory cell MT is a three-level cell (TLC) capable of storing 3 bits of data, or a four-level cell (QLC) capable of storing 4 bits of data.

[0063] When each memory cell MT is a multi-level cell (MLC), the distribution of the threshold voltage of the memory cell MT is as follows: Figure 4The diagram shows four large objects (Lobs). The threshold voltage of each memory cell MT is controlled to belong to any one of the four large objects: distribution Er, distribution A, distribution B, and distribution C. Each memory cell MT can store four-valued data "xy" defined by data "x" belonging to the previous page and data "y" belonging to the next page. The values ​​of data "x" and data "y" are either code "0" or code "1". The correspondence between the above four distributions and the data values ​​of the four-valued data "xy" is preset. Hereinafter, without distinguishing between distribution Er, distribution A, distribution B, and distribution C, it is referred to as the "threshold distribution". In addition, the level of the threshold voltage corresponding to distribution A is referred to as "level A", the level of the threshold voltage corresponding to distribution B is referred to as "level B", and the level of the threshold voltage corresponding to distribution C is referred to as "level C".

[0064] Furthermore, the data is randomized and written in such a way that the number of memory cells MT belonging to distributions Er, A, B, and C becomes approximately equal. Randomization refers to generating randomized data by adding random values ​​to the original data sequence and then writing the randomized data to the semiconductor memory device 20. Various known methods can be used for randomization.

[0065] (3.2 Data writing action)

[0066] Next, the data writing action (program action) will be explained.

[0067] Figure 5 This diagram illustrates the data writing process. The data writing process is performed by repeatedly looping a program until a specific condition is met. This program loop includes applying the write voltage Vpgm, program verification, and voltage change operations that increase the set value of the write voltage Vpgm.

[0068] The write voltage Vpgm is applied to the word line WL (hereinafter referred to as "select word line WL") connected to one or more memory cells MT (hereinafter referred to as "select memory cells MT") to be written, causing the threshold voltage of the select memory cell MT to rise toward the threshold voltage corresponding to the desired data value. The write voltage Vpgm is applied, for example, when the potential of the bit line BL connected to the select memory cell MT is set to 0 volts by the sense amplifier 115.

[0069] Program verification verifies whether the threshold voltage of the selected memory cell MT has reached the threshold voltage corresponding to the expected data value; that is, whether the expected data value has been written to the selected memory cell MT. In program verification, program verification voltages VA, VB, or VC are used to determine whether the write operation is complete. The voltage values ​​of program verification voltages VA, VB, and VC are different from each other (see reference). Figure 4 ).

[0070] The program verification voltage VA is the verification voltage corresponding to level A. If the voltage written to the selected memory cell MT at level A is a threshold voltage greater than or equal to the program verification voltage VA, then the write to that selected memory cell MT is considered complete. The program verification voltage VB is the verification voltage corresponding to level B. The voltage value of the program verification voltage VB is greater than the program verification voltage VA. If the voltage written to the selected memory cell MT at level B is a threshold voltage greater than or equal to the program verification voltage VB, then the write to that selected memory cell MT is considered complete. The program verification voltage VC is the verification voltage corresponding to level C. The voltage value of the program verification voltage VC is greater than the program verification voltage VB. If the voltage written to the selected memory cell MT at level C is a threshold voltage greater than or equal to the program verification voltage VC, then the write to that selected memory cell MT is considered complete. The program verification voltage VA is an example of the "first verification voltage". The program verification voltage VB is an example of the "second verification voltage".

[0071] During program verification, a voltage Vread is applied to word lines other than the select word line WL (hereinafter referred to as "non-select word lines WL"), and a program verification voltage VA, VB, or VC is applied to the select word line WL. The voltage Vread is set to be higher than the threshold voltage of any memory cell MT. Furthermore, if no current flows in a specific cell, it is determined that the write to the selected memory cell MT has been completed.

[0072] The voltage change action is an action that increases the set value of the write voltage Vpgm by a specific amount when the threshold voltage of the selected memory cell MT does not reach the threshold voltage corresponding to the expected data value during program verification (in the case of program verification failure). For example, as a voltage change action, the row address decoder 3 increases the write voltage Vpgm applied to the select word line WL by ΔVpgm each time the program loop is repeated. Thus, with each execution of the program loop, the threshold voltage of the selected memory cell MT connected to the select word line WL increases by approximately ΔVpgm.

[0073] As the threshold voltage of the selected memory cell MT gradually increases, during program verification, the threshold voltage of the selected memory cell MT gradually approaches the threshold voltage corresponding to the expected data value, and eventually reaches the threshold voltage corresponding to the expected data value. When the threshold voltage of the selected memory cell MT reaches the threshold voltage corresponding to the expected data value, the program verification is passed. When the program verification is passed, the writing to the selected memory cell MT ends, and the bit line BL corresponding to the selected memory cell MT is set to a non-selected state (write is disabled). For example, by increasing and fixing the voltage applied to the bit line BL, the bit line BL becomes a non-selected state.

[0074] like Figure 5 As shown, the above-mentioned program verification, corresponding to the loop number of the program loop, includes program verification for one or more of levels A, B, and C. That is, multiple program verifications with different verification voltages can be performed on the application of a single write voltage Vpgm. For example, when the loop number of the program loop is small, there are no memory cells MT whose threshold voltage rises to level C; therefore, program verification for levels A and B is performed. On the other hand, when the loop number of the program loop is large, all memory cells MT written to level A have already passed program verification; therefore, program verification for level A is not performed.

[0075] The data writing operation described above is performed by the control circuit 106, the line decoder 111, and the sensing amplifier 115. The data writing operation is performed, for example, in the order of word lines WL0, WL1, WL2, ..., WL(N-1).

[0076] During the write operation on each word line WL, if the program verification of all selected memory units MT connected to that word line WL passes, the control circuit 106 determines that the write operation is successful. Upon determining that the write operation is successful, the control circuit 106 sets the status information STS corresponding to the successful write operation in the status register 103.

[0077] On the other hand, if the program verification fails even after reaching the preset maximum value of the program loop, the control circuit 106 determines that the write operation has failed. Upon determining that the write operation has failed, the control circuit 106 stores the status information STS corresponding to the write operation failure (Program Status Fail: PSF) in the status register 103.

[0078] (3.3 Data Reading Action)

[0079] During the data readout operation, the sense amplifier 115 precharges the bit line BL with the power supply potential Vcc. The line decoder 111 applies a transmission potential to the non-select word line WL, setting the memory cell MT belonging to the non-select word line WL to the on state. Then, the line decoder 111 applies a readout voltage to the word line WL (select word line WL) connected to one or more memory cells MT to be read out. As the readout voltage, multiple readout potentials AR, BR, or CR corresponding to the threshold distribution (distribution Er, distribution A, distribution B, or distribution C) of each data value are sequentially applied (see reference). Figure 4 Then, the sense amplifier 115 determines the data value stored in the memory cell MT to be read by detecting which readout potential AR, BR, or CR the charge accumulated by pre-charging flows out to the source line SL when it is applied.

[0080] For example, when the read voltage AR is set between distribution Er and distribution A, the memory cell MT with a threshold voltage below the read voltage AR is determined to be in distribution Er. When the read voltage BR is set between distribution A and distribution B, the memory cell MT with a threshold voltage below the read voltage BR is determined to be in distribution A. Similarly, when the read voltage is set between two adjacent distributions, the memory cell MT with a threshold voltage below that read voltage is determined to be in the distribution with the lower threshold voltage of the two distributions.

[0081] (4. Read verification)

[0082] In this embodiment, when the write operation is completed through program verification, the control circuit 106 can perform an action to verify whether the written data in the write operation can be read normally. In this application, this verification action is referred to as "read verification".

[0083] Figure 6 This is a diagram used to illustrate the read verification process. For example... Figure 6 As shown, even if the write operation is determined to be successful and a write failure (PSF) does not occur, the data may still not be read correctly when the actual read operation is attempted. For example, Figure 6 The area indicated by the dashed line F represents a situation where, even if the write operation in the semiconductor memory device 20 is successful, the number of memory cells MT where the data value is determined to be incorrect (the number of error bits) exceeds the allowable limit during the data read operation, resulting in data read failure. The term "number of error bits exceeding the allowable limit" refers to, for example, the number of error bits exceeding the error correction capability of the ECC circuit 15.

[0084] Figure 7 This is a graph used to illustrate the deviation of the threshold distribution of the memory cell MT. Figure 7The dashed lines in the diagram represent multiple threshold distributions under ideal (normal) conditions of the semiconductor memory device 20. On the other hand, Figure 7 The solid lines in the graph represent multiple threshold distributions under the deterioration (abnormal) state of the semiconductor memory device 20. For example... Figure 7 As shown by the solid lines, for example, when the characteristics of the storage cell MT change, the threshold distributions expand, and the ends of multiple threshold distributions partially overlap. The area where multiple threshold distributions overlap is a region where the probability of errors occurring during data read operations is high, even if the write operation is determined to be successful.

[0085] Read verification is a pre-emptive verification action performed to suppress read failures of data as described above. Read verification, in response to the completion of a write operation, performs read operations on multiple (e.g., all) memory cells MT connected to the word line WL to be written, verifying whether the data written to the word line WL can be read normally.

[0086] For example, in read verification, a read command is sent from memory controller 10 to semiconductor memory device 20 to read data from multiple (e.g., all) memory cells MT connected to the word line WL to be written to memory controller 10. Then, in memory controller 10, the number of error bits contained in the read data is counted. If the counted number of error bits is below a certain value, the data is considered to have been read normally, thus passing the read verification. Read verification can be performed in response to the completion of a write operation on one word line WL, or in response to the completion of a write operation on multiple word lines WL.

[0087] Here, in a typical read operation (a read operation that reads data according to a request from the host device 2), the memory controller 10 sends a read instruction to the semiconductor memory device 20 according to the read request from the host device 2. The semiconductor memory device 20 performs the read operation in response to the read instruction, that is, reads data from multiple memory cells MT and sends the read data to the memory controller 10.

[0088] In this embodiment, the read verification operation is the same as the read operation performed according to the read request from the host device 2. That is, the read verification operation includes: similar to the read operation performed according to the read request from the host device 2, sequentially applying multiple read voltages AR, BR, or CR to the word line WL of the data to be read, and reading the data values ​​corresponding to the distributions Er, A, B, or C from multiple memory cells MT connected to the word line WL of the data to be read.

[0089] (5. Efficiency related to write operations)

[0090] (5.1 Write reliability metrics)

[0091] Performing the aforementioned read verification for every data write operation may hinder the improvement of the processing speed of the memory system 1. Therefore, in this embodiment, the memory controller 10 evaluates the reliability of a data write operation based on specific metrics. Then, if the memory controller 10 determines that the reliability of the write operation is high, it skips the read verification; if it determines that the reliability of the write operation is low, it performs the read verification. This will be explained in detail below.

[0092] like Figure 2 As shown, the control circuit 106 includes an index generation unit 106a. The index generation unit 106a generates an index (write reliability index) representing the reliability of a write operation, for example, based on information obtained from the write progress of data values ​​in a program operation. In this embodiment, the index generation unit 106a generates the write reliability index based on first information obtained from the write progress of data values ​​(first data values) corresponding to level A in a program operation, second information obtained from the write progress of data values ​​(second data values) corresponding to level B in a program operation, and third information obtained from the write progress of data values ​​(third data values) corresponding to level C in a program operation.

[0093] The first information includes, for example, at least one of the following: information indicating the number of program loops executed before the first specific condition was met, and information indicating the number of memory cells MTs that were written before the first specific condition was met. Here, the first specific condition, for example, means that all selected memory cells MTs with the first data value written to them among a plurality of memory cells MTs connected to a select word line WL have passed program verification. The term "number of memory cells MTs that were written before the first specific condition was met" may also include the number of memory cells MTs that completed the writing of the second or third data value during the repeated execution of the program loop accompanied by the program verification voltage VA. This definition is also the same for the second or third specific conditions described below.

[0094] The second information includes, for example, at least one of the following: information indicating the number of program loops executed before the second specific condition is met, and information indicating the number of memory cells MT that have been written before the second specific condition is met. Here, the second specific condition, for example, means that all selected memory cells MTs among the plurality of memory cells MTs connected to a select word line WL, to which the second data value has been written, have passed program verification.

[0095] Similarly, the third information may include, for example, at least one of the following: information indicating the number of program loops executed before the third specific condition is met, and information indicating the number of memory cells MT that have been written before the third specific condition is met. Here, the third specific condition may, for example, mean that all selected memory cells MTs among the plurality of memory cells MTs connected to a select word line WL, for which the third data value has been written, have passed program verification.

[0096] From one perspective, the first and second information are information obtained during the program operation for a select word line WL. For example, the first information is obtained when the write operation corresponding to level A is completed. The second information is obtained when the write operation corresponding to level B is completed.

[0097] Furthermore, from another perspective, the first, second, and third pieces of information represent deviations between the progress of the data write operation and the design ideal value. For example, the first piece of information represents the deviation between the progress of the write operation corresponding to level A and the design ideal value. The second piece of information represents the deviation between the progress of the write operation corresponding to level B and the design ideal value. The third piece of information represents the deviation between the progress of the write operation corresponding to level C and the design ideal value.

[0098] The index generation unit 106a of this embodiment includes a range comparison unit 201 and a count comparison unit 202 (see reference). Figure 2 For ease of explanation, the range comparison unit 201 will be referred to as the "VPS (Verify Pass Stage) range comparison unit 201". The count comparison unit 202 will be referred to as the "VPS count comparison unit 202". The threshold storage unit 107 stores the VPS range count table T1.

[0099] Figure 8 This is a diagram representing an example of VPS range count table T1. Figure 8 In this context, "VPS range" refers to the threshold value of the ideal number of program loops to be executed before the write operation corresponding to each of the three levels (Level A, Level B, and Level C) is completed. The "Minimum (Min)" of the "VPS range" represents the lower limit of the ideal number of program loops. The "Maximum (Max)" of the "VPS range" represents the upper limit of the ideal number of program loops.

[0100] For example, if the number of program loops executed before the write operation corresponding to level A is 3 or 4, the write operation is determined to be reliable. Similarly, if the number of program loops executed before the write operation corresponding to level B is 5 or 6, the write operation is determined to be reliable. If the number of program loops executed before the write operation corresponding to level C is 7 or 8, the write operation is determined to be reliable. On the other hand, if the number of program loops executed before the write operation at each level deviates from the range of the design ideal value contained in the VPS range count table T1, the write operation is determined to be unreliable (risky). In this embodiment, these determinations regarding the number of program loops are performed by the VPS range comparison unit 201 comparing the number of program loops actually detected during the write operation with the threshold number of program loops contained in the VPS range count table T1.

[0101] Figure 8 In this context, "VPS count" refers to the upper limit of the ideal value of the number of memory cells MT that are written before the write action of each level (level A, level B, and level C) is completed.

[0102] For example, if the number of memory cells MT that have completed writing the desired data value (data value at any of levels A, B, or C) before the write operation corresponding to level A is completed is 6000 or less, the write operation is considered reliable. Similarly, if the number of memory cells MT that have completed writing the desired data value (data value at any of levels A, B, or C) before the write operation corresponding to level B is completed is 12000 or less, the write operation is considered reliable. If the number of memory cells MT that have completed writing the desired data value (data value at any of levels A, B, or C) before the write operation corresponding to level C is completed is 18000 or less, the write operation is considered reliable. On the other hand, if the number of memory cells MT that have completed writing before the write operation at each level is completed exceeds the upper limit included in the VPS range count table T1, the write operation is considered unreliable (risky). In this embodiment, the determination of the number of storage units MT is performed by the VPS count comparison unit 202 comparing the number of storage units MT that actually completed the writing of the expected data value during the write operation with a threshold of the number of storage units MT included in the VPS range count table T1.

[0103] The setting value of VPS range counter table T1 can be determined during the manufacturing of semiconductor memory device 20, or it can be set based on a request from host device 2, and the indication value from host device 2 can be set.

[0104] In this embodiment, the write reliability index is set to "1" when the index generation unit 106a determines that the write operation is reliable, and set to "0" when the index generation unit 106a determines that the write operation is risky. In this embodiment, when the index generation unit 106a determines that the write operation is reliable based on both the determination by the VPS range comparison unit 201 and the determination by the VPS count comparison unit 202, it sets "1" as the write reliability index value and stores the set write reliability index value in the FDI register 103a. On the other hand, when the index generation unit 106a determines that the write operation is risky based on at least one of the determinations by the VPS range comparison unit 201 and the VPS count comparison unit 202, it sets "0" as the write reliability index value and stores the set write reliability index value in the FDI register 103a.

[0105] As described above, the value of the write reliability index stored in the FDI register 103a can be read out by a dedicated instruction from the memory controller 10. When a dedicated instruction is issued from the memory controller 10, the value of the write reliability index is sent from the FDI register 103a to the input / output circuit 101 and then transmitted to the memory controller 10. The value of the write reliability index stored in the FDI register 103a is updated each time a new write reliability index is set in the control circuit 106.

[0106] (5.2 Processing Flow)

[0107] Next, the processing flow related to the data writing operation will be explained.

[0108] Figure 9 This is a flowchart illustrating the processing flow of the semiconductor memory device 20. Figure 9 The series of processes shown are in response to the sending of a write instruction (program instruction) from the memory controller 10 to the semiconductor memory device 20, representing the processing related to one select word line WL in response to the write instruction. Hereinafter, the control unit will be described as the control circuit 106, which performs the processing in appropriate combination with other components (such as the line decoder 111 or the sense amplifier 115). Furthermore, Figure 9 The “State” in this context refers to the threshold distribution of the aforementioned storage unit MT.

[0109] First, when the semiconductor memory device 20 receives a write command sent from the memory controller 10, the control circuit 106 initializes the write reliability index stored in the FDI register 103a (S101). For example, the control circuit 106 initializes the value of the write reliability index stored in the FDI register 103a to "1", which corresponds to a reliable write operation. Next, the control circuit 106 repeats the processes described below in S102 to S108 for write operations corresponding to levels A, B, and C, respectively.

[0110] For example, the control circuit 106 first applies a write voltage Vpgm to the select word line WL (S102) as a write operation corresponding to level A, and performs program verification corresponding to level A (S103). Then, the control circuit 106 determines whether the program verification corresponding to level A has passed (S104).

[0111] If the program verification fails (S104: No), the control circuit 106 determines whether the number of executed program loops has reached its maximum value (S105). If the control circuit 106 determines that the number of program loops has not reached its maximum value (S105: No), it performs a voltage change operation, that is, it increments the program loop count by 1 and increases the set value of the write voltage Vpgm by a specific amount (ΔVpgm), and then returns to the processing in S102. Thus, each time the control circuit 106 repeats the program loop, it increases the write voltage Vpgm applied to the select word line WL by ΔVpgm.

[0112] If the program verification corresponding to level A passes during repeated program loops (S104: Yes), the indicator generation unit 106a determines whether the count of the number of program loops executed before the write operation of level A is completed is within the first specific range (e.g., 3 to 4 times) included in the VPS range count table T1 (S106).

[0113] If the count of the number of program loops being executed is within the first specific range (S106: Yes), the indicator generation unit 106a then determines whether the number of memory cells MT that have completed the data value writing before the write operation of level A is completed is less than or equal to the first specific amount contained in the VPS range count table T1 (e.g., less than 6000) (S107).

[0114] If the count of the number of program loops executed before the write operation at level A is completed is not within the first specific range (S106: No), or if the number of memory cells MT that have completed data value writing before the write operation at level A is completed is not less than the first specific amount (S107: No), the indicator generation unit 106a sets "0" corresponding to the write operation being unreliable (risky) as the value of the write reliability indicator, and stores the set value of the write reliability indicator in the FDI register 103a (S108).

[0115] On the other hand, when the count of the number of executed program loops is within the first specific range (S106: Yes) and the number of memory cells MT that have completed data value writing is less than the first specific amount (S107: Yes), the index generation unit 106a maintains the value of the write reliability index at the initial value. Then, the control circuit 106 also repeats the above-described processing of S102 to S108 for the write operation corresponding to level B. Regarding the details of the processing in this case, simply change "level A" to "level B" in the relevant description of writing level A, change "within the first specific range (e.g., 3 to 4 times)" to "within the second specific range (e.g., 5 to 6 times)", and change "less than the first specific amount (less than 6000)" to "less than the second specific amount (less than 12000)".

[0116] Then, if the count of the number of program loops executed by the index generation unit 106a before the write operation of level B is completed is within the second specific range (S106: Yes), and the number of memory cells MT that have completed data value writing before the write operation of level B is completed is less than the second specific amount (S107: Yes), the value of the write reliability index is maintained at the initial value. Then, the control circuit 106 also repeats the above-described processing of S102 to S108 for the write operation corresponding to level C. Regarding the details of the processing in this case, simply change "level A" to "level C" in the relevant description of writing level A, change "within the first specific range (e.g., 3 to 4 times)" to "within the third specific range (e.g., 7 to 8 times)", and change "less than the first specific amount (less than 6000)" to "less than the third specific amount (less than 18000)".

[0117] Then, if the control circuit 106 completes the write operation corresponding to level C during the repeated program loop, it determines that the write operation is successful (S111). If the write operation is successful, the control circuit 106 stores the status information STS corresponding to the successful write operation in the status register 103 (S112) and outputs the standby / busy signal R / Bn indicating that the write operation corresponding to the write instruction has ended.

[0118] On the other hand, if the control circuit 106 determines that the count of the program loop number has reached its maximum value during the repeated program loop (S105: Yes), it determines that the write operation has failed (S113). If the control circuit 106 determines that the write operation has failed, it stores the status information STS corresponding to the write operation failure (Program Status Fail: PSF) in the status register 103 (S114) and outputs a standby / busy signal R / Bn indicating that the write operation corresponding to the write instruction has ended.

[0119] Figure 10 This is a flowchart illustrating an example of the processing of the memory controller 10. The processing flow described below is an example of the write order of a block BLK in the semiconductor memory device 20. In the processing described below, it is an example of determining whether to perform read verification for each write operation to a word line WL.

[0120] The memory controller 10 sequentially performs the processes described below, S201 to S208, for each of the plurality of word lines WL.

[0121] First, the memory controller 10 generates a write command for the select word line WL to be written and sends the generated write command to the semiconductor memory device 20 (S201). Thus, in the semiconductor memory device 20, [the process is as follows]. Figure 9 The processing steps S101 to S114 are shown.

[0122] First, when the standby / busy signal R / Bn output from the semiconductor memory device 20 indicates that the write operation has ended, the memory controller 10 obtains the status information STS (S202) indicating whether the write operation was successful from the semiconductor memory device 20. For example, the memory controller 10 obtains the status information STS by sending a status acquisition instruction to the semiconductor memory device 20 to read the status information STS stored in the status register 103.

[0123] Next, the memory controller 10 determines whether the acquired status information STS indicates that the write operation was successful (S203). If the status information STS indicates that the write operation failed (S203: No), the memory controller 10 ensures that another block BLK is executed and performs the write operation again (S204). In this case, it returns to S201 to process again.

[0124] When the status information STS indicates that the write operation was successful (S203: Yes), the memory controller 10 obtains the write reliability index from the semiconductor memory device 20 (S205). For example, the memory controller 10 obtains the write reliability index by sending a status acquisition instruction to the semiconductor memory device 20 for reading the write reliability index stored in the FDI register 103a.

[0125] Next, the memory controller 10 determines whether the value of the write reliability index is "1", which corresponds to the write operation having high reliability (S206). In this embodiment, if the value of the write reliability index is "1" (S206: Yes), the memory controller 10 considers the reliability of the program operation to be high enough and skips the read verification. In this case, the memory controller 10 ends the processing of the word line WL that has undergone read verification, and starts processing the next word line WL to be written from S201.

[0126] On the other hand, if the value of the write reliability index is not "1" (S206: No), the memory controller 10 does not skip the read verification and performs read verification (S207). That is, it determines whether data can be read normally from the multiple memory cells MT connected to the select word line WL (S208). For example, the memory controller 10 determines whether the number of error bits contained in the read data is below a specific value.

[0127] If the memory controller 10 can read the data normally according to the read verification (S208: Yes), it ends the relevant processing of the word line WL that has been read verified, and starts processing the next word line WL to be written from S201.

[0128] On the other hand, if the memory controller 10 fails to read data normally according to the read verification (S208: No), it determines that the write operation has failed, ensures that another block BLK is executed, and performs the write operation again (S204). In this case, it returns to S201 to process again.

[0129] After processing all word lines WL to be written as described above in S201 to S208, the memory controller 10 determines that the write operation is successful (S209) and completes a series of processes.

[0130] (6. Advantages)

[0131] In the semiconductor memory device 20, a write operation is considered successful when all data values ​​are written before the program loop count reaches its maximum value. However, the success or failure of a write operation in the semiconductor memory device 20 only indicates whether the write operation has ended normally; it does not determine whether the written data can be read correctly. Therefore, it is ideal to perform read verification through the memory controller 10 to verify whether the written data can be read normally. However, if read verification is performed on all write operations, the processing time of each write operation will increase, and the data write throughput may decrease.

[0132] Therefore, in this embodiment, the memory system 1 includes a memory controller 10 and a semiconductor memory device 20. The semiconductor memory device 20 includes word lines WL connected to a plurality of memory cells MT. When writing data to the plurality of memory cells MT, the memory controller 10 sends a write command to the semiconductor memory device 20. In response to the write command, the semiconductor memory device 20 executes a program operation, that is, executes a program loop until a first specific condition is met. The program loop includes: performing program verification, that is, applying a write voltage to the word line WL, applying a first verification voltage to the word line WL to determine whether to write a first data value contained in the data; increasing the set value of the write voltage if it is determined that the writing of the first data value is not completed; and generating a write reliability index based on the first information obtained according to the writing progress of the first data value in the program operation. The memory controller 10 determines whether to perform a read verification of reading data from the plurality of memory cells MT based on the write reliability index.

[0133] Based on this configuration, read verification is performed to check whether the written data can be read normally when the reliability of the write operation is insufficient, and the number of read verifications can be reduced compared to performing read verification for all write operations. This improves the throughput of data writes. Consequently, better control of the semiconductor memory device 20 is achieved.

[0134] Furthermore, if the success of a write operation cannot be determined before the read verification is complete, the written data needs to remain in DRAM30 until the read verification is complete to allow for recovery in case of errors. In this case, the release of DRAM30 will be delayed. As a result, the data buffer storing the written data is effectively reduced, and the data write time becomes longer. On the other hand, when the decision to perform read verification is based on write reliability indicators, the execution of the write reliability indicator status retrieval instruction is only the reading and transfer of register values ​​within the semiconductor memory device 20, and the execution time is extremely short. Therefore, write time can be reduced by reducing read verification.

[0135] During a write operation, if the number of program loops during the writing of each threshold distribution exceeds the upper limit of the VPS range, there are a certain number of memory cells (MTs) where writing is more difficult than the design ideal. Conversely, if the number of program loops during the writing of each threshold distribution is less than the lower limit of the VPS range, there are a certain number of memory cells (MTs) where writing is easier than the design ideal. These factors are the main causes of threshold voltage deviation. Therefore, in this embodiment, the first information includes information indicating the number of program loops executed before a first specific condition is met. With this configuration, the write reliability index can reflect the existence of memory cells (MTs) where writing is difficult or easy.

[0136] During a write operation, if the number of memory cells (MTs) that have completed writing at each threshold distribution exceeds the VPS count, there are a certain number of memory cells (MTs) whose write progress exceeds the design ideal value. This occurs when the threshold voltage of the memory cell (MT) is biased towards the high potential side, and becomes a major cause of threshold voltage deviation. Therefore, in this embodiment, the first information includes information indicating the number of memory cells (MTs) that completed writing before meeting the first specific condition. With this configuration, the write reliability metric can reflect the existence of memory cells (MTs) whose write progress exceeds the design ideal value.

[0137] (Second Implementation)

[0138] Next, the second embodiment will be described. The difference between the second embodiment and the first embodiment is that multiple VPS range counter tables T2A, T2B, and T2C corresponding to the depletion level of the semiconductor memory device 20 are used. The configuration other than that described below is the same as that of the first embodiment.

[0139] Figure 11Figures (a) to (c) illustrate an example of the VPS range count tables T2A, T2B, and T2C in the second embodiment. In this embodiment, multiple VPS range count tables T2A, T2B, and T2C are used, each corresponding to the depletion level of the semiconductor memory device 20. For example, VPS range count table T2A corresponds to the semiconductor memory device 20 at the first depletion level. The first depletion level is a relatively low depletion level, for example, the write-erase count (W / E) corresponds to 0 to 300 times. VPS range count table T2B corresponds to the semiconductor memory device 20 at the second depletion level. The second depletion level is a moderate depletion level, for example, the write-erase count (W / E) corresponds to 301 to 1500 times. VPS range count table T2C corresponds to the semiconductor memory device 20 at the third depletion level. The third depletion level is a relatively high depletion level, for example, the write-erase count (W / E) corresponds to more than 1501 times. Write / erase count (W / E) is, for example, the average (or representative) number of write / erase operations performed on each block BLK of the semiconductor memory device 20. Hereinafter, without distinguishing between VPS range count tables T2A, T2B, and T2C, it will be referred to as VPS range count table T2.

[0140] like Figure 11 As shown, the values ​​of "VPS Range" and "VPS Count" set for the second exhaustion level are higher than those set for the first exhaustion level. The values ​​of "VPS Range" and "VPS Count" set for the third exhaustion level are higher than those set for the second exhaustion level. The values ​​of "VPS Range" and "VPS Count" are an example of the "First Threshold".

[0141] In this embodiment, the depletion level (e.g., write-erase count) of the semiconductor memory device 20 is managed by the memory controller 10. The memory controller 10 notifies the semiconductor memory device 20 of information indicating the depletion level of the semiconductor memory device 20. The control circuit 106 of the semiconductor memory device 20 determines the depletion level of the semiconductor memory device 20 based on the information notified by the memory controller 10.

[0142] Then, the control circuit 106 determines the values ​​of the "VPS range" and "VPS count" to be used based on the determined depletion level of the semiconductor memory device 20. For example, the control circuit 106 selects VPS range count table T2 from VPS range count tables T2A, T2B, and T2C that corresponds to the determined depletion level of the semiconductor memory device 20. Then, the control circuit 106 uses the values ​​of "VPS range" and "VPS count" contained in the selected VPS range count table T2 to generate write reliability metrics.

[0143] As described above, in this embodiment, the semiconductor memory device 20 generates write reliability metrics based on thresholds that vary according to the depletion level of the semiconductor memory device 20. Here, if the depletion level of the semiconductor memory device 20 progresses, the number of program loops during writing or the number of memory cells (MT) that complete the write operation may become skewed upwards. Therefore, if the threshold set (the values ​​of "VPS range" and "VPS count") is singular, fewer read verifications will be reduced as the semiconductor memory device 20 progresses through depletion, potentially decreasing the effectiveness of read verification reduction. Therefore, by preparing a threshold set for each depletion level of the semiconductor memory device 20 and changing the threshold set to be referenced according to the depletion level, the effectiveness of read verification reduction can be improved.

[0144] (Third Implementation)

[0145] Next, the third embodiment will be described. The difference between the third embodiment and the first embodiment is that multiple VPS range count tables T3A and T3B corresponding to the positions of the word lines WL to be written are used. The configuration other than that described below is the same as that of the first embodiment.

[0146] Figure 12 Figures (a) to (b) illustrate an example of the VPS range count tables T3A and T3B of the third embodiment. In this embodiment, multiple VPS range count tables T3A and T3B are used, corresponding to the positions of the word line WL to be written relative to the multiple word lines WL included in the memory cell array 109. For example, VPS range count table T3A is a table corresponding to word lines WL for which the ease of writing to the memory cell MT (ease of rising threshold voltage) is a first reference. The word lines WL corresponding to the first reference are, for example, the word lines WL (WL(1-94)) among the multiple word lines WL included in the memory cell array 109, excluding the word lines WL at both ends. VPS range count table T3B is a table corresponding to word lines WL for which the ease of writing to the memory cell MT (ease of rising threshold voltage) is a second reference. The word lines WL corresponding to the second reference are, for example, the word lines WL at both ends among the multiple word lines WL included in the memory cell array 109 (WL(0, 95)). Compared to the first benchmark, the second benchmark is easier to write to the memory cell MT (the threshold voltage is easier to rise). Hereinafter, without distinguishing between VPS range count tables T3A and T3B, it will be referred to as VPS range count table T3.

[0147] like Figure 12 As shown, the values ​​of "VPS Range" and "VPS Count" set for the second benchmark are higher than the values ​​of "VPS Range" and "VPS Count" set for the first benchmark. The values ​​of "VPS Range" and "VPS Count" are an example of the "Second Threshold".

[0148] In this embodiment, the control circuit 106 of the semiconductor memory device 20 determines the values ​​of the "VPS range" and "VPS count" based on the position of the word line WL to be written relative to the plurality of word lines WL included in the memory cell array 109. For example, the control circuit 106 selects the VPS range count table T3 corresponding to the position of the word line WL to be written based on the write destination address information representing the word line WL to be written. Then, the control circuit 106 uses the values ​​of the "VPS range" and "VPS count" included in the selected VPS range count table T3 to generate a write reliability index.

[0149] As described above, in this embodiment, the semiconductor memory device 20 generates a write reliability index based on a threshold according to the position of the selected word line WL relative to multiple word lines WL. Here, the semiconductor memory device 20 may have characteristics that differ depending on the word line WL, resulting in different program loop counts or the number of memory cells MT completed during the write operation for each word line WL. Therefore, when the threshold set is singular, the number of read verification reductions among word lines WL with different characteristics decreases, potentially reducing the read verification reduction effect. Therefore, by preparing multiple threshold sets corresponding to the positions of the word lines WL and changing the reference threshold set according to the position of the word line WL, the read verification reduction effect can be improved.

[0150] (Fourth implementation)

[0151] Next, the fourth embodiment will be described. The difference between the fourth embodiment and the first embodiment is that the determination of whether to perform read verification is performed in the semiconductor memory device 20. The configuration other than that described below is the same as that of the first embodiment.

[0152] Figure 13 This is a block diagram illustrating the configuration of the semiconductor memory device 20A according to the fourth embodiment. In this embodiment, the control circuit 106 includes a read verification management unit 121. The index generation unit 106a outputs the generated reliability index to the read verification management unit 121. The read verification management unit 121 performs the verification process as described in the first embodiment. Figure 11 The processing described in S201 to S208 is as follows: When the write reliability index is "1", the read verification management unit 121 skips read verification. On the other hand, when the write reliability index is "0", the read verification management unit 121 performs read verification to check whether the written data can be read normally. If the read verification management unit 121 determines that the write operation is successful, it sets the status information STS indicating the success of the write operation in the status register 103.

[0153] With this configuration, it is not necessary to determine whether to perform read verification through the memory controller 10, which can reduce the signal transmission and reception between the memory controller 10 and the semiconductor memory device 20.

[0154] Several implementation methods have been described above. However, the implementation methods are not limited to the examples described above. For example, two or more implementation methods described above can be combined with each other. For example, the write reliability index is not limited to the two values ​​"0" and "1", but can also be multiple values. For example, the program loop can end after only one iteration.

[0155] According to at least one of the embodiments described above, in response to a write instruction from the memory controller, the semiconductor memory device executes a program operation, namely, executes a program loop. This program loop includes: performing program verification, namely, applying a write voltage to the word line, determining whether to write a first data value, increasing the set value of the write voltage if the writing of the first data value is not complete, and generating an indicator based on first information obtained from the writing progress of the first data value in the program operation. Based on the aforementioned indicator, the memory controller determines whether to perform a read verification to read data from multiple memory cells. With this configuration, the semiconductor memory device can be better controlled.

[0156] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and likewise included in the scope of the invention as described in the claims and their equivalents.

[0157] [Explanation of Symbols]

[0158] 1. Memory System

[0159] 10. Memory Controller

[0160] 20 Semiconductor memory devices

[0161] 101 Input / Output Circuit

[0162] 102 Logic Control Circuit

[0163] 103 Status Register

[0164] 103a FDI Register

[0165] 104 Address Register

[0166] 105 Instruction Register

[0167] 106 Control Circuit

[0168] 106a Indicator Generation Department

[0169] 107 Threshold Storage Unit

[0170] 108 Voltage Generation Circuit

[0171] 109-cell memory array

[0172] 110 line address buffer

[0173] 111-line decoder

[0174] 112 Column Address Buffer

[0175] 113-column decoder

[0176] 114 Data Register

[0177] 115 Sensing Amplifier

[0178] 201 VPS Range Comparison Department

[0179] 202 VPS Count Comparison Department

[0180] MT memory unit

[0181] WL lettering.

Claims

1. A memory system, comprising: Memory controller; as well as A semiconductor memory device, comprising: multiple memory cells; The memory controller is configured to send write instructions to the semiconductor memory device when data is written to the plurality of memory cells. Regarding the write command, The semiconductor memory device is configured as follows: Execute program actions, the program actions including executing a first program loop until a first specific condition is met, the first program loop including: applying a write voltage to the word line, applying a first verification voltage to the word line to perform program verification for performing a write determination of a first data value provided in the data, and increasing the set value of the write voltage if it is determined that the write of the first data value is not completed. An indicator is generated based on first information obtained according to the progress of writing the first data value in the program action, and the memory controller is configured to issue a first instruction to obtain the indicator. The semiconductor memory device is configured to issue the indicator in response to the first instruction. The memory controller is configured to receive the indicator from the semiconductor memory device and, based on the received indicator, determine whether to perform a read verification to read data from the plurality of memory cells.

2. The memory system according to claim 1, wherein The memory controller is configured to send a read instruction to the semiconductor memory device based on a read request from an external host device that uses data from the plurality of memory cells as the read target. The semiconductor memory device is configured to, in response to the read instruction, perform a read operation: read the data from the plurality of memory cells and send the read data to the memory controller.

3. The memory system according to claim 2, wherein If, based on the received metrics, it is determined that the read verification to read data from the plurality of memory cells should be performed, the memory controller is configured to send the read instruction to the semiconductor memory device. The semiconductor memory device is configured to perform the read operation in response to the read instruction.

4. The memory system according to claim 1, wherein The first information includes information indicating the number of times the first program loop is executed until the first specific condition is met.

5. The memory system according to claim 1, wherein The first information includes information indicating the number of the plurality of storage cells that were written before the first specific condition was met.

6. The memory system according to claim 1, wherein The program actions include executing a second program loop until a second specific condition is satisfied, the second program loop including: The write voltage is applied to the word line, and a second verification voltage with a different value than the first verification voltage is applied to the word line to perform a program verification for determining the write of a second data value provided in the data. If it is determined that the write of the second data value is incomplete, the set value of the write voltage is increased. The semiconductor memory device is configured to generate an index based on the first information and the second information, the second information being obtained according to the progress of writing the second data value in the program action.

7. The memory system according to claim 6, wherein The second information includes information indicating the number of times the second program loop is executed until the second specific condition is met.

8. The memory system according to claim 6, wherein The second information includes information indicating the number of the plurality of storage cells that were written before the second specific condition was met.

9. The memory system according to claim 1, wherein The semiconductor memory device is configured to generate the index based on the first information and the first threshold. The first threshold is determined based on the depletion level of the semiconductor memory device.

10. The memory system of claim 1, wherein The semiconductor storage device includes: Multiple character lines, wherein the multiple character lines include the character lines; The semiconductor memory device is configured to generate the index based on the first information and the second threshold. The second threshold is determined based on the position of the multiple word lines.

11. The memory system of claim 9, wherein The memory controller is configured to determine the depletion level of the semiconductor memory device and send the depletion level of the semiconductor memory device to the semiconductor memory device.

12. The memory system of claim 11, wherein The depletion of the semiconductor memory device is the number of write-erase cycles of the semiconductor memory device.

13. The memory system of claim 12, wherein The first threshold when the count of write-erase events in the semiconductor memory device is greater than the first value is higher than the first threshold when the count of write-erase events in the semiconductor memory device is equal to or less than the first value.

14. The memory system of claim 13, wherein The first information includes information indicating the number of times the first program loop is executed until the first specific condition is met.

15. The memory system of claim 13, wherein The first information includes information indicating the number of the plurality of storage cells that were written before the first specific condition was met.

16. The memory system of claim 10, wherein The value of the second threshold when the memory cell connected to the word line for the plurality of word lines is connected to the selection transistor is higher than the value of the second threshold when the memory cell connected to the word line for the plurality of word lines is not connected to the selection transistor.

17. The memory system of claim 16, wherein The first information includes information indicating the number of times the first program loop is executed until the first specific condition is met.

18. The memory system of claim 16, wherein The first information includes information indicating the number of the plurality of storage cells that were written before the first specific condition was met.

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