Method for implementing ARM64-bit floating point emulator on Linux system

Abstract

This invention proposes a method for implementing an ARM64-bit floating-point simulator on a Linux system, comprising: running ARM64-bit instructions on the Linux system; determining whether the ARM64-bit instruction is an ARM64-bit floating-point instruction by applying an instruction classifier to a first feature code in the machine code pointed to by the ARM64-bit instruction; and, in response to the event that the ARM64-bit instruction is an ARM64-bit floating-point instruction, identifying the ARM64-bit floating-point instruction as a specific ARM64-bit floating-point instruction by applying the instruction classifier to a second feature code in the machine code pointed to by the ARM64-bit instruction.

Description

Technical Field

[0001] This invention relates to a method for implementing an ARM64-bit floating-point simulator on a Linux system. Background Technology

[0002] The ARM (Advanced RISC Machine) architecture is widely used in embedded systems. ARM's support for floating-point operations includes the following:

[0003] The first type of support is a hardware-implemented floating-point coprocessor. The compiler directly compiles the code into instructions that the floating-point coprocessor can recognize. When executing these instructions, the ARM core directly hands them over to the floating-point coprocessor. The floating-point coprocessor typically has an additional set of registers to handle floating-point parameter passing and calculations. The new generation ARM64 is a 64-bit extension of the ARM architecture. To support floating-point operations, it adds a floating-point coprocessor and defines a floating-point instruction set. However, if actual hardware is lacking, the instructions will be intercepted and executed by a floating-point emulator.

[0004] The second type of support is software-implemented soft floating-point libraries. Soft floating-point library support is a feature provided by cross-toolchains and is independent of the Linux kernel. When compiling floating-point operations using a cross-toolchain, the compiler replaces the floating-point operations with inline soft floating-point libraries. The resulting machine code contains no floating-point pointers (4EE4), yet it can correctly perform floating-point operations. However, none of the well-known mainstream cross-toolchains provide corresponding ARM64 soft floating-point libraries.

[0005] The third type of support is a software-implemented floating-point emulator. In the early days, ARM lacked a coprocessor, and floating-point operations were simulated by software through the CPU, i.e., a floating-point emulator, primarily implemented using an undefined instruction handler. However, this resulted in extremely frequent exceptions, significantly increasing interrupt latency and reducing system real-time performance. Furthermore, the well-known Linux kernel does not support 64-bit ARM floating-point emulators.

[0006] Currently, Linux only has a 32-bit ARM floating-point emulator, but not a 64-bit ARM floating-point emulator.

[0007] Generally, embedded systems require floating-point operations. However, since the Linux kernel does not typically support ARM64-bit floating-point emulators, the functionality of the ARM64-bit floating-point coprocessor is limited, rendering it unable to perform floating-point operations. In such cases, ARM64 must be downgraded to ARM32. Therefore, there is an urgent need to propose a method for implementing ARM64 floating-point operations on a Linux system to solve this problem. Summary of the Invention

[0008] In view of this, the present invention proposes a method for implementing an ARM64-bit floating-point simulator on a Linux system, comprising: running ARM64-bit instructions on the Linux system; determining whether the ARM64-bit instruction is an ARM64-bit floating-point instruction by applying an instruction classifier to a first feature code in the machine code pointed to by the ARM64-bit instruction; and, in response to the event that the ARM64-bit instruction is an ARM64-bit floating-point instruction, identifying the ARM64-bit floating-point instruction as a specific ARM64-bit floating-point instruction by applying the instruction classifier to a second feature code in the machine code pointed to by the ARM64-bit instruction.

[0009] Optionally, or preferably, when the ARM64-bit instruction is an ARM64-bit floating-point instruction, an ARM64-bit exception is entered, wherein when the ARM64-bit exception is entered, the ARM64-bit exception context is saved and the ARM64-bit floating-point instruction is processed; and after the ARM64-bit floating-point instruction is processed, the ARM64-bit exception is exited.

[0010] Optionally, or preferably, the process of processing the ARM64-bit floating-point instruction further includes: defining a floating-point register and a status structure to store one or more data during the floating-point operation process of processing the ARM64-bit floating-point instruction.

[0011] Optionally, or preferably, the instruction classifier is configured to perform single-layer or layer-by-layer parsing according to the ARM64 encoding rules for floating-point instructions to determine the category of the ARM64-bit floating-point instruction and the specific ARM64-bit floating-point instruction.

[0012] Optionally, or preferably, the instruction classifier is configured to represent the ARM64-bit floating-point instruction as a binary representation of 32 bits, with the most significant bit to the least significant bit defined as bits 31 to 0 in sequence.

[0013] Optionally, or preferably, the instruction classifier is configured to define the 31st bit of the binary representation as tag sf, the 29th bit as tag S, the 22nd and 23rd bits as tag type, the 19th and 20th bits as tag rmode, and the 16th and 18th bits as tag opcode, according to the ARM64 encoding rules for floating-point instructions, and to determine the category of the ARM64-bit floating-point instruction based on the value of type, rmode, or opcode.

[0014] Optionally, or preferably, the ARM64-bit floating-point instructions are classified into conversion instructions, comparison instructions, or arithmetic instructions.

[0015] Optionally, or preferably, the layer-by-layer parsing includes, in one of the multiple classifications, using the label type as the second feature code, and classifying the ARM64-bit floating-point instructions into conversion instructions, comparison instructions, or arithmetic instructions based on the label type.

[0016] Optionally, or preferably, the processing of the ARM64-bit floating-point instruction further includes: dispatching a corresponding floating-point library function to perform the floating-point operation of processing the ARM64-bit floating-point instruction according to the category of the ARM64-bit floating-point instruction determined by the instruction classifier and the specific ARM64-bit floating-point instruction.

[0017] Optionally, or preferably, the method for implementing an ARM64-bit floating-point simulator on a Linux system according to the present invention further includes, after processing the ARM64-bit floating-point instruction and before exiting the ARM64-bit exception, determining whether the next ARM64-bit instruction is another ARM64-bit floating-point instruction; if the next ARM64-bit instruction is determined to be another ARM64-bit floating-point instruction, then the ARM64-bit exception is not exited, and the next ARM64-bit instruction is processed; if the next ARM64-bit instruction is determined not to be another ARM64-bit floating-point instruction, then the ARM64-bit exception is exited.

[0018] The other objects, advantages and novel features of the present invention will become more apparent from the following detailed description with reference to the drawings. Attached Figure Description

[0019] Figure 1 A flowchart illustrating an embodiment of the present invention shows a method for implementing an ARM64-bit floating-point simulator on a Linux system.

[0020] Figure 2A , Figure 2B , Figure 2C and Figure 2DThis invention demonstrates a specific example of the instruction classifier performing layer-by-layer classification.

[0021] Figure 3 A flowchart showing another embodiment of the present invention illustrates a method for optimizing a floating-point emulator for ARM64 based on SEMI.

[0022] [Explanation of Labels in the Attached Image]

[0023] SA1 - Steps to run the code;

[0024] SA2 - Steps to fall into an ARM64-bit exception;

[0025] SA3 - Steps for processing ARM 64-bit floating-point instructions;

[0026] SA31 - Steps for executing the instruction classifier;

[0027] SA32 - Steps for executing floating-point library functions;

[0028] SA4 - Steps to exit ARM64-bit exception;

[0029] TA1 - Steps to determine if it is an ARM64-bit floating-point instruction;

[0030] TB2 - The steps to determine whether the next instruction is still an ARM64-bit floating-point instruction;

[0031] SB1 - Steps to run the code;

[0032] SB2 - Steps to fall into an ARM64-bit exception;

[0033] SB3 - Steps for processing ARM 64-bit floating-point instructions;

[0034] SB4 - Steps to exit an ARM64-bit exception;

[0035] TA1 - Steps to determine if it is an ARM64-bit floating-point instruction;

[0036] TB1 - Steps to determine if it is an ARM64-bit floating-point instruction;

[0037] TB2 - The steps to determine whether the next instruction is still an ARM64-bit floating-point instruction. Detailed Implementation

[0038] The following provides different embodiments of the present invention. These embodiments are used to illustrate the technical content of the present invention and are not intended to limit the scope of the invention. A feature of one embodiment can be applied to other embodiments through suitable modifications, substitutions, combinations, or separations.

[0039] It should be noted that, unless otherwise specified, the term "one" in this document is not limited to having a single component, but may include one or more of the components.

[0040] Furthermore, unless otherwise specified, the ordinal numbers such as "first," "second," etc., used in this document are merely for distinguishing multiple components with the same name and do not indicate any hierarchy, order of execution, or process sequence among them. A "first" component and a "second" component may appear together in the same component or separately in different components. The presence of a component with a higher ordinal number does not necessarily indicate the presence of another component with a lower ordinal number.

[0041] The terms "including," "containing," "having," and "containing" refer to, but are not limited to, these.

[0042] One existing implementation uses a floating-point coprocessor to determine whether an ARM64-bit instruction is an ARM64-bit floating-point instruction, and performs floating-point operations only after confirmation. Without a floating-point coprocessor, this determination is impossible, preventing subsequent floating-point operations. A possible alternative is to use a floating-point emulator. However, Linux lacks a floating-point emulator for ARM architecture processors (ARM64). Therefore, this invention proposes a method to perform simulated floating-point operations even in the absence of a floating-point coprocessor and a floating-point emulator.

[0043] (Methods for implementing an ARM64-bit floating-point emulator on a Linux system)

[0044] Figure 1 This flowchart illustrates a method for implementing an ARM64-bit floating-point emulator on a Linux system according to an embodiment of the present invention. This method can be implemented by software, a computer program, a computer-readable storage medium, or a computer program product. The method includes the following steps:

[0045] This method begins with step SA1: running low-level code, such as machine code, on a Linux system. One machine code corresponds to one assembly code and represents a 64-bit ARM instruction. Machine code is implemented based on ARM encoding rules, such as 1e220000, 52876c81, 72a824a1, 1e270021, 1e212800, 1e380000, and d65f03c0. The corresponding assembly codes for these machine codes are, for example, scvtf, mov, movk, fmov, fadd, fcvtzs, and ret.

[0046] The determination mechanism TA1 executes the instruction classifier to apply it to the machine code. The instruction classifier determines whether the ARM64-bit instruction specified by the running machine code is an ARM64-bit floating-point instruction. If the determination mechanism TA1 determines that the running ARM64-bit instruction is not an ARM64-bit floating-point instruction, the method returns to step SA1 to continue executing the next ARM64-bit instruction. Conversely, if the determination mechanism TA1 determines that the running ARM64-bit instruction is an ARM64-bit floating-point instruction, the method must first save the ARM64-bit exception context and proceed to step SA2.

[0047] Step SA2 involves falling into an ARM64-bit exception. It's worth noting that there are many types of exceptions, but this invention specifically focuses on the ARM64-bit "undefined instruction" exception because it aims to address the problem caused by the well-known lack of support for ARM64-bit floating-point emulators in the Linux kernel.

[0048] After step SA2, proceed to step SA3: process ARM64-bit floating-point instructions. In step SA3, floating-point registers and status structures can be defined to store one or more data (e.g., intermediate results) during the floating-point operation. Step SA3 may also include two sub-steps SA31 and SA32.

[0049] Step SA31 executes the instruction classifier. The instruction classifier is configured to parse ARM64-bit floating-point instructions. Preferably, it parses the instructions layer by layer according to the ARM64 encoding rules for floating-point instructions, first determining the type of ARM64-bit floating-point instruction, and then determining the specific ARM64-bit floating-point instruction.

[0050] Specifically, each ARM64-bit instruction corresponds to a unique machine code. Through layer-by-layer matching by the instruction classifier, it is possible to distinguish whether an ARM64-bit instruction is an ARM64-bit floating-point instruction. Next, to distinguish between ARM64-bit instructions and ARM64-bit floating-point instructions, since all ARM64-bit floating-point instructions have corresponding categories, the instruction classifier can classify ARM64-bit instructions hierarchically according to the instruction encoding format. Among these, ARM64-bit floating-point instructions include several categories: The first category is "conversion instructions," including conversion between floating-point and fixed-point, and between floating-point and integer, but not limited to these; the second category is "comparison instructions," including comparison instructions and conditional comparison instructions, but not limited to these; the third category is "arithmetic instructions," including addition, subtraction, multiplication, division, multiplication-addition (multiplication-addition means multiplication before addition, for example, for four parameters Rd, Rn, Rm, Ra, the instruction FMADD Rd,Rn,Rm,Ra performs the operation Rd = Ra + Rn * Rm), and multiplication-subtraction (multiplication-subtraction means multiplication before subtraction, for example, for four parameters Rd, Rn, Rm, Ra, FMSUB... The instruction Rd,Rn,Rm,Ra performs an operation like Rd = Ra - Rn * Rm, but it is not limited to this. In this way, the instruction classifier can categorize ARM64-bit instructions and match them to a specific, unique ARM64-bit floating-point instruction.

[0051] Step SA32 involves executing floating-point library functions. Since each ARM64-bit floating-point instruction defines a corresponding floating-point library function, the instruction classifier can dispatch different floating-point library functions according to different ARM64 instructions to perform ARM64-bit floating-point simulation operations. For example, if floating-point conversion is required, the floating-point conversion function needs to be called; if floating-point addition and subtraction are required, the floating-point arithmetic function needs to be called. Floating-point operations may require obtaining multiple intermediate results before performing calculations to obtain the final result. These intermediate results can be stored in a floating-point register and read from the register when needed for computation.

[0052] Step SA3 involves returning from the floating-point library function after processing the ARM64-bit floating-point instructions; if there is a final result, it is stored in the corresponding floating-point register.

[0053] In this way, we can proceed to step SA4, exit the ARM64 bit exception, and restore the ARM64 bit exception context that was saved when the judgment mechanism TA1 detected the ARM64 bit exception, so as to continue running the assembly code. That is, we return to step SA1 to continue executing the next ARM64 bit instruction.

[0054] Figure 2A , Figure 2B, Figure 2C and Figure 2D The figure shows a specific example of the instruction classifier of the present invention performing layer-by-layer classification. The example in Figure 2 is merely exemplary. The method of the present invention can also be used to process different ARM64-bit floating-point instructions.

[0055] first, Figure 2A This displays the contents of the C code fp_test for this example:

[0056] int fp_test(int_y)

[0057] {float xx; xx=10.327; return xx+y;}

[0058] The C code above indicates that the function `fp_test` is defined as an integer function, `y` is defined as an integer, and `xx` is defined as a floating-point number with the value of `xx` given as 10.327. The function `fp_test` is configured to perform an addition operation between `xx` and `y`. Since `xx` is a floating-point number, the above operation is a floating-point operation. The above code is just an example. After the C code `fp_test` is input to the compiler, the compiler outputs... Figure 2B The seven ARM64-bit instructions are represented in hexadecimal, 52876c81, 72a824a1, 1e270021, 1e212800, 1e380000, and d65f03c0. For ease of identification, the machine code is represented in hexadecimal, but the actual operation is performed in binary.

[0059] Reference Figure 2B The machine code that displays the above code consists of seven ARM64-bit instructions: 1e220000, 52876c81, 72a824a1, 1e270021, 1e212800, 1e380000, and d65f03c0. The machine code of the first ARM64-bit instruction is represented as 1e220000 in hexadecimal and 00011110001000100000000000000000, which is 32 bits. The bits from the most significant bit (leftmost bit) to the least significant bit (rightmost bit) are defined as bits 31 to 0, respectively. For ease of explanation, the most significant bit can be described as Bit31, the second most significant bit as Bit30, the least significant bit as Bit0, and so on. When running the Linux operating system on an ARM64 processor, the code executed is machine code.

[0060] Secondly Figure 2CThe machine code of the first ARM64 instruction is represented in binary as 00011110001000100000000000000000, and is parsed by the instruction classifier of this invention. The instruction classifier of this invention is configured to define the following tags according to the ARM64 encoding rules for floating-point instructions: bit 31 is the tag sf, bit 29 is the tag S, bits 22 and 23 are the tag type, bits 19 and 20 are the tag rmode, bits 16 and 18 are the tag opcode, bits 5 to 9 are the tag Rn, and bits 0 to 4 are the tag Rd, as shown below. Figure 2C As shown. Based on the values ​​of sf, S, type, rmode, and opcode, the first instruction can be classified and further analyzed to determine which specific ARM64-bit floating-point instruction it is. In one embodiment, the instruction classifier determines whether the instruction is an ARM64-bit floating-point instruction based on the value of the first 8 bits (Bit31, Bit30, Bit29, Bit28, Bit27, Bit26, Bit25, and Bit24), and these 8 bits of machine code can be considered as the first characteristic code. These 8 bits are only one example; in other embodiments, other numbers or other bits of bits can be used to determine whether an ARM64-bit instruction is an ARM64-bit floating-point instruction.

[0061] at last, Figure 2D The machine code of the first instruction is represented in binary as 0001111000100010000000000000000, which is then parsed by the instruction classifier of this invention.

[0062] After determining that it belongs to an ARM64-bit floating-point instruction, the first classification is performed. In this embodiment, the first classification is based on the label "type," specifically the values ​​of Bits 23 and 22. These two bits of machine code can be referred to as the second characteristic code. Using the label "type" for the first classification is just one example; in other embodiments, other labels can be used for the first classification. For example, when the value of the label "type" is 00, the category is "conversion instructions," which involve conversions between floating-point numbers and integers. In some embodiments, "conversion instructions" include the floating-point instructions scvtf, ucvtf, fcvtzs, and fcvtzu. Which of the instructions scvtf, ucvtf, fcvtzs, and fcvtzu the ARM64-bit floating-point instruction belongs to will be determined in subsequent classifications.

[0063] After the first classification is completed, the second classification begins. In this embodiment, the second classification is based on the label rmode, i.e., the values ​​of Bits 20 and 19. These two bits of machine code can be referred to as the third feature code. Using the label rmode for the second classification is just one example; in other embodiments, other labels can be used for the second classification.

[0064] After the second classification is completed, the third classification begins. In this embodiment, the third classification is based on the opcode, specifically the values ​​of Bits 18, 17, and 16. These three bits of machine code can be referred to as the fourth feature code. Using the opcode for the third classification is just one example; in other embodiments, other opcodes can be used for the third classification.

[0065] After completing the third classification, it becomes possible to determine which specific ARM64-bit floating-point instruction it is, for example, the floating-point instruction scvtf. This layer-by-layer classification helps to speed up the identification of specific ARM64-bit floating-point instructions.

[0066] In other embodiments, the hierarchical classification can be performed multiple times, for example, twice or more; alternatively, it may be considered to determine the specific ARM64-bit floating-point instruction directly based on type, rmode, and opcode, without hierarchical classification.

[0067] exist Figure 2D In this embodiment, according to the ARM64 encoding rules for floating-point instructions, the values ​​of sf, S, type, and rmode are extracted as 0, and opcode is 010. Then, following the above classification method, the specific ARM64 floating-point instruction is determined based on the values ​​of various tags. Therefore, it is determined that its category is "conversion instruction," which involves the conversion between floating-point numbers and integers, and its specific ARM64 floating-point instruction is scvtf. Among them, scvtf(scalar, integer) converts a 32-bit integer (integer) into a single-precision floating-point number (scalar).

[0068] After learning that the first ARM64 instruction is a "conversion instruction" and the specific ARM64 floating-point instruction is scvtf, the corresponding floating-point library function int_to_float() is dispatched to perform ARM64 floating-point simulation operations. The int_to_float() function can convert integers into floating-point numbers.

[0069] The above is for Figure 2BThe first ARM64-bit instruction shown indicates the parsing and processing of machine code 1e220000. However, for example, regarding... Figure 2B The machine code 1e212800, which is indicated by the fifth ARM64 instruction shown, can also be parsed and processed in a similar way, as explained in words below.

[0070] Similarly, the machine code 1e212800 of the fifth ARM64 instruction is represented in binary as 00011110001000010010100000000000. The instruction classifier of this invention parses this data. According to the ARM64 encoding rules for floating-point instructions, it extracts the values ​​of sf (0), S (0), type (00), rmode (00), and opcode (001). Then, following the above classification method, it determines the specific ARM64 floating-point instruction based on the values ​​of various tags. Therefore, it is determined that its category is "arithmetic instruction," involving the addition of two floating-point numbers. The specific ARM64 floating-point instruction is fadd, and the corresponding floating-point library function float_add() is then dispatched to perform the ARM64 floating-point simulation operation. The function float_add() can add two floating-point numbers.

[0071] Other ARM64-bit floating-point instructions are also classified and processed in the same way.

[0072] (A method for optimizing a floating-point emulator for ARM64 based on SEMI)

[0073] Figure 3 A flowchart showing another embodiment of the present invention illustrates a method for optimizing a floating-point emulator for ARM64 based on SEMI.

[0074] SEMI (Single Exception for Multiple Instructions) refers to trapping into a single exception to handle multiple ARM64 floating-point instructions. For consecutive ARM64 floating-point instructions, SEMI saves the overhead of trapping into multiple exceptions. Quantitatively speaking, when encountering an ARM64 floating-point instruction, the total time spent from trapping into an exception to performing the ARM64 floating-point instruction simulation and exiting the exception accounts for about 10% of the total time, while the simulation itself accounts for 90%. Therefore, using SEMI can save nearly 10% of the overhead.

[0075] The method for optimizing a floating-point emulator for ARM64 based on SEMI of the present invention can be implemented by software, a computer program, a computer-readable storage medium, or a computer program product. The method includes the following steps:

[0076] This method begins with step SB1: running low-level code, such as machine code, on a Linux system. Step SB1 is similar to... Figure 1 Step SA1 will not be repeated here.

[0077] The determination mechanism TB1 is used to determine whether the running ARM64-bit instruction in the code is an ARM64-bit floating-point instruction. If the determination mechanism TB1 determines that the running ARM64-bit instruction is not an ARM64-bit floating-point instruction, this method returns to step SB1 to continue executing the next ARM64-bit instruction. Conversely, if the determination mechanism TB1 determines that the running ARM64-bit instruction is an ARM64-bit floating-point instruction, this method must first save the ARM64-bit exception context and proceed to step SB2: trapping into an ARM64-bit exception.

[0078] After step SB2, proceed to step SB3: process ARM64-bit floating-point instructions. In step SB3, floating-point registers and status structures must be defined to store data during floating-point operations (e.g., intermediate results). Step SB3 may also include two sub-steps: executing the instruction classifier and executing floating-point library functions. For details on executing the instruction classifier, please refer to step SA31 of the embodiment in Figure 2; for details on executing the floating-point library functions, please refer to step SA32 of the embodiment in Figure 2. These details will not be repeated here. Step SA3 returns from the floating-point library function after processing the ARM64-bit floating-point instructions; simultaneously, if there is a final result, the final result is stored in the corresponding floating-point register.

[0079] The judgment mechanism TB2 is used to determine whether the next ARM64-bit instruction is still an ARM64-bit floating-point instruction. This determination can be referred to the relevant description of step SA31 in the embodiment of Figure 2. The instruction classifier of this invention performs layer-by-layer parsing according to the ARM64 encoding rules for floating-point instructions to quickly determine whether the next ARM64-bit instruction is still an ARM64-bit floating-point instruction. If the judgment mechanism TB2 determines that the next ARM64-bit instruction is still an ARM64-bit floating-point instruction, it is not necessary to exit the ARM64-bit exception; instead, the next ARM64-bit instruction is sent to step SB3 for processing. This is the SEMI mechanism, which saves the overhead of trapping multiple exceptions. Conversely, if the judgment mechanism TB2 determines that the next ARM64-bit instruction is not an ARM64-bit floating-point instruction, it proceeds to step SB4. For example, recalling... Figure 2BFor example, after assigning the corresponding floating-point library function to the fourth machine code 1e270021, the ARM64 instruction following the fourth machine code 1e270021 (the fifth machine code 1e212800) is also an ARM64 floating-point instruction. Therefore, it is not necessary to exit the ARM64 exception, but to send the next ARM64 instruction to step SB3 for processing.

[0080] Step SB4 exits the ARM64 exception and restores the ARM64 exception context saved when the ARM64 exception was detected in the judgment mechanism TB1, so that the code can continue to run. That is, it returns to step SB1 to continue executing the next ARM64 instruction. It should be noted that the next ARM64 instruction here is not an ARM64 floating-point instruction, because consecutive ARM64 floating-point instructions will be processed continuously in the SEMI mechanism.

[0081] In summary, this invention proposes a method for implementing an ARM64-bit floating-point emulator on a Linux system. Furthermore, this invention also proposes a method based on SEMI to optimize the ARM64 floating-point emulator, avoiding frequent exceptions, significantly reducing interrupt latency, and improving system real-time performance.

[0082] Although the invention has been described through various embodiments, it should be understood that many other possible modifications and variations may be made without departing from the spirit of the invention and the claims.

Claims

1. A method for implementing an ARM64-bit floating-point simulator on a Linux system, characterized in that, include: Running ARM64-bit instructions on the Linux system; By applying an instruction classifier to the first feature code in the machine code pointed to by the ARM64-bit instruction, it is determined whether the ARM64-bit instruction is an ARM64-bit floating-point instruction; In response to the event that the ARM64-bit instruction is an ARM64-bit floating-point instruction, the instruction classifier is applied to the second feature code in the machine code pointed to by the ARM64-bit instruction to identify the ARM64-bit floating-point instruction as a specific ARM64-bit floating-point instruction; and The ARM64-bit floating-point instructions are processed to perform floating-point operations.

2. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 1, characterized in that, When the ARM64-bit instruction is an ARM64-bit floating-point instruction, an ARM64-bit exception is entered. When the ARM64-bit exception is entered, the ARM64-bit exception context is saved and the ARM64-bit floating-point instruction is processed. After the ARM64-bit floating-point instruction is processed, the ARM64-bit exception is exited.

3. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 2, characterized in that, The process of processing the ARM64-bit floating-point instruction further includes: defining a floating-point register and a status structure to store one or more data during the floating-point operation process of processing the ARM64-bit floating-point instruction.

4. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 1, characterized in that, The instruction classifier is configured to perform single-layer or layer-by-layer parsing according to the ARM64 encoding rules for floating-point instructions, in order to determine the category of the ARM64-bit floating-point instruction and the specific ARM64-bit floating-point instruction.

5. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 4, characterized in that, The instruction classifier is configured to represent the ARM64-bit floating-point instructions as binary representations, totaling 32 bits, with the most significant bit to the least significant bit defined as bits 31 to 0 in sequence.

6. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 5, characterized in that, The instruction classifier is configured to define the 31st bit of the binary representation as tag sf, the 29th bit as tag S, the 22nd and 23rd bits as tag type, the 19th and 20th bits as tag rmode, and the 16th and 18th bits as tag opcode, according to the ARM64 encoding rules for floating-point instructions. The class of the ARM64-bit floating-point instruction is determined based on the value of type, rmode, or opcode.

7. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 6, characterized in that, The ARM64-bit floating-point instructions are classified into conversion instructions, comparison instructions, or arithmetic instructions.

8. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 6, characterized in that, The layer-by-layer parsing includes, in one of the multiple classifications, using the label type as the second feature code, and classifying the ARM64-bit floating-point instructions into conversion instructions, comparison instructions, or arithmetic instructions based on the label type.

9. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 2, characterized in that, The processing of the ARM64-bit floating-point instructions further includes: assigning corresponding floating-point library functions to perform floating-point operations on the ARM64-bit floating-point instructions according to the category of the ARM64-bit floating-point instructions determined by the instruction classifier and the specific ARM64-bit floating-point instructions.

10. The method for implementing an ARM64-bit floating-point emulator on a Linux system according to claim 2, characterized in that, The method also includes, after processing the ARM64-bit floating-point instruction and before exiting the ARM64-bit exception, determining whether the next ARM64-bit instruction is another ARM64-bit floating-point instruction; if the next ARM64-bit instruction is still another ARM64-bit floating-point instruction, then the ARM64-bit exception is not exited, and the next ARM64-bit instruction is processed; if the next ARM64-bit instruction is not another ARM64-bit floating-point instruction, then the ARM64-bit exception is exited.

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