Thin film transistor, preparation method thereof, display panel and display device

Abstract

The application discloses a thin film transistor and a preparation method thereof, a display panel and a display device, and relates to the technical field of display. The thin film transistor comprises a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer and an electrode layer. The potential of the signal transmitted by the first electrode pattern in the electrode layer is different from the potential of the signal transmitted by the target part of the shielding layer, so that the surface of the semiconductor layer generates a carrier channel under the action of the electric field generated by the first electrode pattern and the target part, the impedance of the semiconductor layer is reduced, and the on-state current of the thin film transistor is improved. Moreover, the improvement of the on-state current of the thin film transistor can improve the refresh rate of the display device, ensure the display quality and smoothness of the display device, and the display effect of the display device is better.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a thin-film transistor and its fabrication method, a display panel, and a display device. Background Technology

[0002] Thin film transistors (TFTs) are devices mounted on a substrate in display devices to drive pixels to emit light.

[0003] In related technologies, a TFT generally includes a semiconductor layer, a gate insulating layer, a gate layer, and a source / drain layer connected to the active layer, sequentially disposed on a substrate. The portion of the semiconductor layer overlapping the gate layer forms the channel of the TFT. To ensure the display quality and smoothness of the display device, a high refresh rate is typically required. Generally, the on-state current of the TFT is positively correlated with the refresh rate of the display device; therefore, to achieve a high refresh rate, the on-state current of the TFT needs to be increased.

[0004] However, due to the influence of the gate layer on the semiconductor layer, it is impossible to effectively conduct the semiconductor layer, which leads to a large impedance of the semiconductor layer, a small on-state current of the TFT, and a poor display effect of the display device. Summary of the Invention

[0005] This application provides a thin-film transistor (TFT) and its fabrication method, a display panel, and a display device, which can solve the problem of poor display effect caused by the small on-state current of TFTs in related technologies. The technical solution is as follows:

[0006] On one hand, a thin-film transistor is provided, the thin-film transistor comprising:

[0007] A shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer are sequentially stacked on a substrate and along the side away from the substrate.

[0008] The electrode layer includes a first electrode pattern, a second electrode pattern, and a third electrode pattern. The third electrode pattern is located between the first electrode pattern and the second electrode pattern, and is spaced from both the first electrode pattern and the second electrode pattern.

[0009] The orthographic projection of the first electrode pattern on the substrate overlaps at least partially with the orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the target portion of the shielding layer on the substrate. The first electrode pattern and the semiconductor layer are electrically connected through a first via in the second insulating layer. The potential of the signal transmitted by the first electrode pattern is different from the potential of the signal transmitted by the target portion.

[0010] The orthographic projection of the second electrode pattern on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate, and the second electrode pattern and the semiconductor layer are electrically connected through a second via in the second insulating layer.

[0011] Optionally, the shielding layer has a first shielding structure and a second shielding structure, wherein the first shielding structure and the second shielding structure are intersecting and are an integral structure;

[0012] The orthographic projection of the first shielding structure on the substrate covers the channel region of the thin film transistor, the channel region of the thin film transistor being the overlapping area of ​​the orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the semiconductor layer on the substrate, and the first shielding structure being the target portion;

[0013] The orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the third electrode pattern on the substrate, and the second shielding structure and the third electrode pattern are electrically connected through a third via in the first insulating layer and a fourth via in the second insulating layer.

[0014] Optionally, the semiconductor layer includes a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure arranged along a first direction and forming a single integral structure;

[0015] The orthogonal projection of the first semiconductor structure on the substrate covers the orthogonal projection of the first via on the substrate.

[0016] The orthographic projection of the second semiconductor structure on the substrate is located within the orthographic projection of the first shielding structure on the substrate;

[0017] The orthogonal projection of the third semiconductor structure onto the substrate covers the orthogonal projection of the second via onto the substrate.

[0018] Optionally, the first shielding structure is a strip-shaped structure extending along the first direction, and the second shielding structure is a strip-shaped structure extending along the second direction, wherein the first direction and the second direction are perpendicular; the first shielding structure has a first target boundary and a second target boundary extending along the second direction and disposed opposite to each other, wherein the first target boundary is closer to the first semiconductor structure relative to the second target boundary, and the second target boundary is closer to the third semiconductor structure relative to the first target boundary;

[0019] The first semiconductor structure has a first boundary and a second boundary extending along a first direction, and a third boundary extending along a second direction; the distance between the first boundary and the second boundary is greater than the length of the first shielding structure along the second direction; in the first direction, the third boundary is further away from the third semiconductor structure relative to the first target boundary;

[0020] The third semiconductor structure has a fourth boundary and a fifth boundary extending along the first direction, and a sixth boundary extending along the second direction; the distance between the fourth boundary and the fifth boundary is greater than the length of the first shielding structure along the second direction; in the first direction, the sixth boundary is further away from the first semiconductor structure relative to the second target boundary;

[0021] The length of the second semiconductor structure along the second direction is less than the length of the first shielding structure along the second direction.

[0022] Optionally, the third electrode pattern is a strip-shaped structure extending along the second direction;

[0023] The portion of the third electrode pattern located in the channel region has a length along the first direction that is less than or equal to the length of the second semiconductor structure along the first direction.

[0024] Optionally, the orthographic projection of the second shielding structure on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate.

[0025] Optionally, the orthographic projection of the first via on the substrate includes: a first hole region that overlaps with the orthographic projection of the first electrode pattern on the substrate, and a second hole region that does not overlap with the orthographic projection of the first electrode pattern on the substrate, wherein the second hole region is used to expose at least a portion of the first semiconductor structure.

[0026] The orthographic projection of the second via on the substrate includes: a third via region that overlaps with the orthographic projection of the second electrode pattern on the substrate, and a fourth via region that does not overlap with the orthographic projection of the second electrode pattern on the substrate, the fourth via region being used to expose at least a portion of the third semiconductor structure.

[0027] Optionally, the first insulating layer also has a fifth via;

[0028] The orthographic projection of the fifth via on the substrate and the orthographic projection of the first via on the substrate at least partially overlap, and the first electrode pattern and the target portion are electrically connected through the first via and the fifth via.

[0029] Optionally, the shielding layer has a third shielding structure, a fourth shielding structure, and a fifth shielding structure arranged at intervals between each other;

[0030] The orthographic projection of the third shielding structure on the substrate covers the orthographic projection of the first via on the substrate, and the third shielding structure is the target portion;

[0031] The orthographic projection of the fourth shielding structure on the substrate covers the channel region of the thin-film transistor, the channel region of the thin-film transistor being the overlapping region of the orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the semiconductor layer on the substrate; the orthographic projection of the fourth shielding structure on the substrate at least partially overlaps with the orthographic projection of the third electrode pattern on the substrate, and the fourth shielding structure and the third electrode pattern are electrically connected through a third via in the first insulating layer and a fourth via in the second insulating layer;

[0032] The orthogonal projection of the fifth shielding structure on the substrate covers the orthogonal projection of the second via on the substrate.

[0033] Optionally, the first insulating layer also has a sixth through-hole;

[0034] The orthographic projection of the sixth via on the substrate and the orthographic projection of the second via on the substrate at least partially overlap, and the second electrode pattern and the fifth shielding structure are electrically connected through the second via and the sixth via.

[0035] Optionally, the third, fourth, and fifth shielding structures are arranged along a third direction; the semiconductor layer includes a fourth, fifth, and sixth semiconductor structures that are arranged along the third direction and are integrally formed.

[0036] The orthographic projection of the fourth semiconductor structure on the substrate and the orthographic projection of the third shielding structure on the substrate partially overlap; the orthographic projection of the fifth semiconductor structure on the substrate and the orthographic projection of the fourth shielding structure on the substrate partially overlap; the orthographic projection of the sixth semiconductor structure on the substrate and the orthographic projection of the fifth shielding structure on the substrate partially overlap.

[0037] Wherein, the length of the fifth semiconductor structure along the fourth direction is less than the length of the fourth semiconductor structure along the fourth direction, and less than the length of the sixth semiconductor structure along the fourth direction, and the fourth direction is perpendicular to the third direction.

[0038] Optionally, the fourth semiconductor structure has a seventh boundary extending along the fourth direction, and the third shielding structure has a third target boundary extending along the fourth direction, the third target boundary being the boundary of the third shielding structure away from the fifth shielding structure; in the third direction, the seventh boundary is closer to the sixth semiconductor structure than the third target boundary;

[0039] The sixth semiconductor structure has an eighth boundary extending along the fourth direction, and the fifth shielding structure has a fourth target boundary extending along the fourth direction, the fourth target boundary being the boundary of the fifth shielding structure away from the third shielding structure; in the third direction, the eighth boundary is closer to the fourth semiconductor structure than the fourth target boundary.

[0040] On the other hand, a method for fabricating a thin-film transistor is provided, the method comprising:

[0041] A shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer are sequentially formed on one side of a substrate.

[0042] The electrode layer includes a first electrode pattern, a second electrode pattern, and a third electrode pattern. The third electrode pattern is located between the first electrode pattern and the second electrode pattern, and is spaced from both the first electrode pattern and the second electrode pattern.

[0043] The orthographic projection of the first electrode pattern on the substrate overlaps at least partially with the orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the target portion of the shielding layer on the substrate. The first electrode pattern and the semiconductor layer are electrically connected through a first via in the second insulating layer. The potential of the signal transmitted by the first electrode pattern is different from the potential of the signal transmitted by the target portion.

[0044] The orthographic projection of the second electrode pattern on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate, and the second electrode pattern and the semiconductor layer are electrically connected through a second via in the second insulating layer.

[0045] In another aspect, a display panel is provided, the display panel comprising: a substrate and a plurality of thin-film transistors as described above located on one side of the substrate.

[0046] In another aspect, a display device is provided, the display device comprising: a power supply component and a display panel as described above;

[0047] The power supply component is used to supply power to the display panel.

[0048] The beneficial effects of the technical solution provided in this application include at least the following:

[0049] This application provides a thin-film transistor (TFT), its fabrication method, a display panel, and a display device. The TFT includes a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer. The potential of the signal transmitted by the first electrode pattern in the electrode layer differs from the potential of the signal transmitted by the target portion of the shielding layer. Therefore, under the influence of the electric field generated by the first electrode pattern and the target portion, a carrier channel is generated on the surface of the semiconductor layer, reducing the impedance of the semiconductor layer and increasing the on-state current of the TFT. Furthermore, the increased on-state current of the TFT can improve the refresh rate of the display device, ensuring the display quality and smoothness, resulting in a better display effect. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the structure of a thin-film transistor provided in an embodiment of this application;

[0052] Figure 2 yes Figure 1 A top view of the thin-film transistor shown;

[0053] Figure 3 This is a top view of a shielding layer in a thin-film transistor provided in an embodiment of this application;

[0054] Figure 4This is a top view of a semiconductor layer in a thin-film transistor provided in an embodiment of this application;

[0055] Figure 5 This is a top view of a semiconductor layer and third electrode pattern in a thin-film transistor provided in an embodiment of this application;

[0056] Figure 6 This is a top view of a shielding layer and a semiconductor layer in a thin-film transistor provided in an embodiment of this application;

[0057] Figure 7 This is a schematic diagram of the structure of a shielding layer, a first insulating layer, a semiconductor layer, and a second insulating layer in a thin-film transistor according to an embodiment of this application;

[0058] Figure 8 This is a schematic diagram of another thin-film transistor structure provided in an embodiment of this application;

[0059] Figure 9 yes Figure 8 A top view of the thin-film transistor shown;

[0060] Figure 10 This is a schematic diagram of the structure of a shielding layer, a first insulating layer, a semiconductor layer, and a second insulating layer in a thin-film transistor provided in another embodiment of this application;

[0061] Figure 11 This is a top view of a shielding layer in another thin-film transistor provided in an embodiment of this application;

[0062] Figure 12 This is a top view of a semiconductor layer in another thin-film transistor provided in this application embodiment;

[0063] Figure 13 This is a top view of another semiconductor layer and third electrode pattern in a thin-film transistor provided in this application embodiment;

[0064] Figure 14 This is a top view of the shielding layer and semiconductor layer in another thin-film transistor provided in this application embodiment;

[0065] Figure 15 This is a graph showing the relationship between the input voltage and output current of a thin-film transistor according to an embodiment of this application.

[0066] Figure 16 It is a graph showing the relationship between the input voltage and output current of a thin-film transistor in related technologies;

[0067] Figure 17 This is another graph showing the relationship between the input voltage and output current of a thin-film transistor provided in this application embodiment;

[0068] Figure 18 This is a graph showing the relationship between the input voltage and output current of another thin-film transistor in related technologies;

[0069] Figure 19 This is a flowchart of a method for fabricating a thin-film transistor according to an embodiment of this application;

[0070] Figure 20 This is a schematic diagram of forming a semiconductor layer according to an embodiment of this application;

[0071] Figure 21 This is a schematic diagram of forming a first insulating layer according to an embodiment of this application;

[0072] Figure 22 This is a schematic diagram of forming a semiconductor layer according to an embodiment of this application;

[0073] Figure 23 This is a schematic diagram of forming a second insulating film provided in an embodiment of this application;

[0074] Figure 24 This is a top view of a second insulating film provided in an embodiment of this application;

[0075] Figure 25 This is a schematic diagram of an electrode layer formation provided in an embodiment of this application;

[0076] Figure 26 This is a schematic diagram of a semiconductor layer being conductive, provided in an embodiment of this application.

[0077] Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0078] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0079] TFTs, as integrated elements for switching control or peripheral driving circuits, are core components in display devices. Currently, the most widely used TFTs are amorphous silicon (a-Si) thin-film transistors and polycrystalline silicon thin-film transistors. Amorphous silicon thin-film transistors are widely used in driving circuits or as switching control devices in display devices; however, amorphous silicon has low mobility, typically below 1 cm² / (V·s). 2Polycrystalline silicon suffers from poor uniformity, complex manufacturing processes, high costs, and sensitivity to visible light, making it unsuitable for large-size and high-resolution display devices. Therefore, oxide semiconductor thin-film transistors (TFTs) have attracted significant attention, especially indium gallium zinc oxide (IGZO) TFTs (where the semiconductor layer 103 is made of IGZO, which exhibits high mobility, good uniformity, low processing temperature, high transmittance in the visible light region, and suitability for flexible displays). Consequently, with increasing demands for high mobility, indium gallium zinc tin oxide (IGZTO) materials are also gradually being applied to display devices, achieving mobility up to 20 cm⁻¹. 2 / V·S and above.

[0080] Currently, amorphous oxide semiconductors (AOS) have received widespread attention and research, such as indium tin oxide (ITO), aluminum zinc oxide (AZO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). Among them, indium gallium zinc oxide (IGZO) has been the most extensively studied and shows the most potential. Compared to bottom-gate thin-film transistors (TFTs), top-gate TFTs have a relatively simpler fabrication process and can more precisely control the dimensions of the channel region, thus making top-gate TFTs more widely used.

[0081] However, in the top-gate TFT, the third electrode pattern 1053 layer located on the side of the semiconductor layer 103 away from the substrate 2 will affect the conductor treatment of the semiconductor layer 103, which will lead to a larger impedance of the semiconductor layer 103, a smaller on-state current of the TFT, and a poorer display effect of the display device.

[0082] Figure 1 This is a schematic diagram of the structure of a thin-film transistor provided in an embodiment of this application. Figure 2 yes Figure 1 A top view of the thin-film transistor shown. (Reference) Figure 1 and Figure 2 The thin-film transistor 1 may include: a shielding layer 101, a first insulating layer 102, a semiconductor layer 103, a second insulating layer 104, and an electrode layer 105, which are stacked sequentially on the substrate 2 and along the side away from the substrate 2.

[0083] The electrode layer 105 includes a first electrode pattern 1051, a second electrode pattern 1052 and a third electrode pattern 1053. The third electrode pattern 1053 is located between the first electrode pattern 1051 and the second electrode pattern 1052, and is spaced from both the first electrode pattern 1051 and the second electrode pattern 1052.

[0084] The orthographic projection of the first electrode pattern 1051 on the substrate 2 at least partially overlaps with the orthographic projection of the semiconductor layer 103 on the substrate 2, and the first electrode pattern 1051 and the semiconductor layer 103 are electrically connected through a first via 104a in the second insulating layer 104. Furthermore, the orthographic projection of the first electrode pattern 1051 on the substrate 2 at least partially overlaps with the orthographic projection of the target portion of the shielding layer 101 on the substrate 2, and the potential of the signal transmitted by the first electrode pattern 1051 is different from the potential of the signal transmitted by the target portion. The orthographic projection of the second electrode pattern 1052 on the substrate 2 at least partially overlaps with the orthographic projection of the semiconductor layer 103 on the substrate 2, and the second electrode pattern 1052 and the semiconductor layer 103 are electrically connected through a second via 104b in the second insulating layer 104.

[0085] In this embodiment, since the potential of the signal transmitted by the target portion of the shielding layer 101 is different from the potential of the signal transmitted by the first electrode pattern 1051, an electric field can be generated between the target portion of the shielding layer 101 and the first electrode pattern 1051 in a direction perpendicular to the substrate 2 due to the difference in their potentials. Consequently, under the influence of this electric field, a carrier channel can be formed on the surface of the semiconductor layer 103 located between the target portion of the shielding layer 101 and the first electrode pattern 1051, thereby reducing the impedance of the semiconductor layer 103 and increasing the on-state current of the thin-film transistor 1. Furthermore, the increase in the on-state current of the thin-film transistor 1 can improve the charging efficiency of the thin-film transistor 1, thereby improving the refresh rate of the display device, ensuring the display quality and smoothness of the display device, and resulting in a better display effect.

[0086] In summary, this application provides a thin-film transistor (TFT) comprising a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer. The potential of the signal transmitted by the first electrode pattern in the electrode layer differs from the potential of the signal transmitted by the target portion of the shielding layer. Therefore, under the influence of the electric field generated by the first electrode pattern and the target portion, a carrier channel is generated on the surface of the semiconductor layer, thereby reducing the impedance of the semiconductor layer and increasing the on-state current of the TFT. Furthermore, the increased on-state current of the TFT can improve the refresh rate of the display device, ensuring the display quality and smoothness, resulting in a better display effect.

[0087] In addition, when the on-state current of the thin-film transistor 1 is high, the charging efficiency is high, which makes it easier to increase the pixel density (pixels per inch, PPI) of the display device, thereby making it easier to achieve the narrow bezel effect of the display device.

[0088] Optionally, the material of the shielding layer 101 can be one or more of titanium (Ti), copper (Cu), molybdenum-niobium (MoNb), and nickel-molybdenum titanium (MTD). The material of the first insulating layer 102 can be one or more of silicon oxide (SiO) and silicon nitride (SiN). The material of the semiconductor layer 103 can be amorphous indium gallium zinc oxide (a-IGZO) or indium gallium zinc tin oxide (IGZTO). The material of the second insulating layer 104 can be one or more of SiO and SiN. The material of the electrode layer 105 can be one or more of Ti, Cu, MoNb, and MTD.

[0089] As the first optional implementation method, refer to Figure 3 The shielding layer 101 has a first shielding structure 1011a and a second shielding structure 1012a, which are intersecting and are an integral structure.

[0090] The first shielding structure 1011a, when projected onto the substrate 2, covers the channel region of the thin-film transistor 1 to protect the channel region of the thin-film transistor 1. The channel region is the overlapping area of ​​the projected projection of the third electrode pattern 1053 onto the substrate 2 and the projected projection of the semiconductor layer 103 onto the substrate 2.

[0091] The orthographic projection of the first shielding structure 1011a on the substrate 2 covers the orthographic projection of the first via 104a on the substrate 2. That is, the connection between the first electrode pattern 1051 and the semiconductor layer 103 is located within the orthographic projection of the first shielding structure 1011a on the substrate 2. In this case, the first shielding structure 1011a can be the target portion of the shielding layer 101. Furthermore, the orthographic projection of the first shielding structure 1011a on the substrate 2 also covers the orthographic projection of the second via 104b on the substrate 2. That is, the connection between the second electrode pattern 1052 and the semiconductor layer 103 is located within the orthographic projection of the first shielding structure 1011a on the substrate 2.

[0092] The orthographic projection of the second shielding structure 1012a on the substrate 2 and the orthographic projection of the third electrode pattern 1053 on the substrate 2 at least partially overlap. Furthermore, the orthographic projection of the second shielding structure 1012a on the substrate 2 does not overlap with the orthographic projection of the semiconductor layer 103 on the substrate 2.

[0093] Therefore, the second shielding structure 1012a and the third electrode pattern 1053 can be electrically connected through the third via 102a in the first insulating layer 102 and the fourth via 104c in the second insulating layer 104. Furthermore, the signal transmitted by the second shielding structure 1012a and the signal transmitted by the third electrode pattern 1053 can be the same. In this case, the thin-film transistor 1 can be a dual-gate thin-film transistor. The second shielding structure 1012a can serve as the bottom gate pattern of the thin-film transistor 1 located on the side of the semiconductor layer 103 closer to the substrate 2, and the third electrode pattern 1053 can serve as the top gate pattern of the thin-film transistor 1 located on the side of the semiconductor layer 103 away from the substrate 2.

[0094] Furthermore, since the first shielding structure 1011a and the second shielding structure 1012a are an integral structure, the signal transmitted by the first shielding structure 1011a can also be the signal transmitted by the third electrode pattern 1053. This makes the potential of the signal transmitted by the first electrode pattern 1051 different from the potential of the signal transmitted by the first shielding structure 1011a (target portion), which at least partially overlaps with the first electrode pattern 1051. Consequently, an electric field can be generated between the first electrode pattern 1051 and the first shielding structure 1011a. Under the influence of this electric field, carrier channels are generated on the surface of the semiconductor layer 103, reducing the impedance of the semiconductor layer 103 and increasing the on-state current of the thin-film transistor 1.

[0095] refer to Figure 4 The semiconductor layer 103 may include a first semiconductor structure 1031a, a second semiconductor structure 1032a and a third semiconductor structure 1033a arranged along the first direction A and forming an integral structure.

[0096] The orthographic projection of the first semiconductor structure 1031a on the substrate 2 covers the orthographic projection of the first via 104a on the substrate 2, so as to ensure that the first electrode pattern 1051 and the first semiconductor structure 1031a are electrically connected through the first via 104a.

[0097] Combination Figures 3 to 6 The second semiconductor structure 1032a can serve as the semiconductor structure for forming the channel region. To ensure that the orthographic projection of the channel region on the substrate 2 is covered by the first shielding structure 1011a of the shielding layer 101, the orthographic projection of the second semiconductor structure 1032a on the substrate 2 can be positioned within the orthographic projection of the first shielding structure 1011a on the substrate 2. Therefore, even if the orthographic projection of the third electrode pattern 1053 on the substrate 2 includes portions not covered by the first shielding structure 1011a, it will not affect the channel region.

[0098] The orthogonal projection of the third semiconductor structure 1033a on the substrate 2 covers the orthogonal projection of the second via 104b on the substrate 2, so as to ensure that the second electrode pattern 1052 and the second semiconductor structure 1032a are electrically connected through the second via 104b.

[0099] In this embodiment, the orthographic projection of the second electrode pattern 1052 on the substrate 2 at least partially overlaps with the orthographic projection of the first shielding structure 1011a of the shielding layer 101 on the substrate 2. This allows the signal transmitted in the first electrode pattern 1051 to be transmitted to the second electrode pattern 1052 when the thin-film transistor 1 is in the on state. Consequently, the potential of the signal transmitted by the second electrode pattern 1052 differs from the potential of the signal transmitted by the first shielding structure 1011a, and an electric field can be formed between the second electrode pattern 1052 and the first shielding structure 1011a. Furthermore, under the influence of this electric field, the semiconductor layer 103 can ensure the stability of the carrier channels formed on its surface, resulting in lower impedance of the semiconductor layer 103 and further increasing the on-state current of the thin-film transistor 1.

[0100] refer to Figure 3 As can be seen, the first shielding structure 1011a is a strip-shaped structure extending along the first direction A, and the second shielding structure 1012a is a strip-shaped structure extending along the second direction B. The first direction A and the second direction B are perpendicular. That is, the shape of the orthographic projection of the shielding layer 101 onto the substrate 2 can be T-shaped.

[0101] refer to Figure 6 The first shielding structure 1011a has a first target boundary 1011a1 and a second target boundary 1011a2 that extend along the second direction B and are disposed opposite to each other. The first target boundary 1011a1 is closer to the first semiconductor structure 1031a relative to the second target boundary 1011a2, and the second target boundary 1011a2 is closer to the third semiconductor structure 1033a relative to the first target boundary 1011a1.

[0102] The first semiconductor structure 1031a has a first boundary 1031a1 and a second boundary 1031a2 extending along a first direction A, and a third boundary 1031a3 extending along a second direction B. The distance between the first boundary 1031a1 and the second boundary 1031a2 is greater than the length of the first shielding structure 1011a along the second direction B. In the first direction A, the third boundary 1031a3 is further away from the third semiconductor structure 1033a relative to the first target boundary 1011a1. That is, the overlapping portion of the first shielding structure 1011a and the first semiconductor structure 1031a can be located within the orthographic projection of the first semiconductor structure 1031a onto the substrate 2. This facilitates the design of the first via 104a in the second insulating layer 104 (avoiding excessively small dimensions of the first via 104a leading to greater fabrication difficulties) and ensures a reliable connection between the first electrode pattern 1051 and the first semiconductor structure 1031a.

[0103] Correspondingly, the third semiconductor structure 1033a has a fourth boundary 1033a1 and a fifth boundary 1033a2 extending along the first direction A, and a sixth boundary 1033a3 extending along the second direction B. The distance between the fourth boundary 1033a1 and the fifth boundary 1033a2 is greater than the length of the first shielding structure 1011a along the second direction B. In the first direction A, the sixth boundary 1033a3 is farther from the first semiconductor structure 1031a relative to the second target boundary 1011a2. That is, the overlapping portion of the first shielding structure 1011a and the third semiconductor structure 1033a can be located within the orthographic projection of the first semiconductor structure 1031a onto the substrate 2. This facilitates the design of the second via 104b in the second insulating layer 104 (avoiding the difficulty of fabrication due to the small size of the first via 104a), ensuring a reliable connection between the second electrode pattern 1052 and the second semiconductor structure 1032a.

[0104] The length of the second semiconductor structure 1032a along the second direction B is less than the length of the first shielding structure 1011a along the second direction B. This ensures that the orthogonal projection of the second semiconductor structure 1032a on the substrate 2 is within the orthogonal projection of the first shielding structure 1011a on the substrate 2.

[0105] Optionally, the shape of the first via 104a and the shape of the second via 104b can be rectangular, circular, or other shapes; this embodiment does not limit this. Furthermore, the dimensions of the first via 104a and the second via 104b can be the same or different; this embodiment does not limit this. For example, both the first via 104a and the second via 104b can be rectangular, and both have dimensions of 4μm (micrometers) × 6μm.

[0106] In the embodiments of this application, reference is made to Figure 5 The third electrode pattern 1053 is a strip-shaped structure extending along the second direction B. The portion of the third electrode pattern 1053 located in the channel region has a length along the first direction A that is less than or equal to the length of the second semiconductor structure 1032a along the first direction A. This design ensures that the first shielding structure 1011a covers the channel region, thus protecting the channel region.

[0107] refer to Figure 7 It can be seen that the orthogonal projection of the first via 104a on the substrate 2 includes a first via region 104a1 that overlaps with the orthogonal projection of the first electrode pattern 1051 on the substrate 2, and a second via region 104a2 that does not overlap with the orthogonal projection of the first electrode pattern 1051 on the substrate 2. The second via region 104a2 is used to expose at least a portion of the first semiconductor structure 1031a. Correspondingly, the orthogonal projection of the second via 104b on the substrate 2 includes a third via region 104b1 that overlaps with the orthogonal projection of the second electrode pattern 1052 on the substrate 2, and a fourth via region 104b2 that does not overlap with the orthogonal projection of the second electrode pattern 1052 on the substrate 2. The fourth via region 104b2 is used to expose at least a portion of the third semiconductor structure 1033a. For ease of illustration of the various via regions, Figure 7 The various patterns of the electrode layer are shown using dashed lines.

[0108] Typically, during the fabrication of the thin-film transistor 1, after forming the electrode layer 105, ions need to be doped into the semiconductor layer 103 to perform a conductor-enhancing treatment on the semiconductor layer 103. Therefore, by exposing at least a portion of the first semiconductor structure 1031a in the second aperture region 104a2 and at least a portion of the third semiconductor structure 1033a in the fourth aperture region 104b2, the area of ​​the semiconductor layer 103 covered by the electrode layer 105 can be reduced, ensuring effective ion doping during the conductor-enhancing treatment and guaranteeing the conductor-enhancing effect on the semiconductor layer 103.

[0109] In this embodiment, to reduce the number of masks required during fabrication, the second insulating layer 104 can be fabricated using the electrode layer 105 as a mask. That is, the fabricated second insulating layer 104 is only located below the first electrode pattern 1051, the third electrode pattern 1053, and the second electrode pattern 1052, and other areas do not require the design of this second insulating layer 104.

[0110] In the first optional implementation described above, the first electrode pattern 1051 can serve as the source of the thin-film transistor 1, the second electrode pattern 1052 can serve as the drain of the thin-film transistor 1, and the third electrode pattern 1053 can serve as the gate of the thin-film transistor 1.

[0111] As a second optional implementation method, combined with Figures 8 to 10 The first insulating layer 102 also has a fifth via 102b. The orthographic projection of the fifth via 102b on the substrate 2 at least partially overlaps with the orthographic projection of the first via 104a on the substrate 2. The first electrode pattern 1051 and the target portion are electrically connected through the first via 104a and the fifth via 102b.

[0112] In this embodiment, since the first electrode pattern 1051 and the target portion of the shielding layer 101 are electrically connected, theoretically, the potential of the signal transmitted by the first electrode pattern 1051 is the same as the potential of the signal transmitted by the target portion. However, under normal circumstances, due to the voltage drop of the film layer, the potential of the signal received by the first electrode pattern 1051 is different from the potential of the signal received by the target portion. Based on this, an electric field can be generated between the first electrode pattern 1051 and the target portion in the direction perpendicular to the substrate 2 due to the difference in their potentials. This allows the semiconductor layer 103 located between the target portion and the first electrode pattern 1051 to form carrier channels on its surface under the action of this electric field. As a result, the impedance of the semiconductor layer 103 can be reduced, and the on-state current of the thin-film transistor 1 can be increased.

[0113] refer to Figure 11 The shielding layer 101 has a third shielding structure 1011b, a fourth shielding structure 1012b and a fifth shielding structure 1013b arranged in pairs at intervals.

[0114] The orthographic projection of the third shielding structure 1011b on the substrate 2 covers the orthographic projection of the first via 104a on the substrate 2. That is, the connection between the first electrode pattern 1051 and the semiconductor layer 103 is located within the orthographic projection of the third shielding structure 1011b on the substrate 2. In this case, the third shielding structure 1011b can be the target portion of the shielding layer 101.

[0115] Combination Figure 9 ,as well as Figures 11 to 13 The orthographic projection of the fourth shielding structure 1012b on the substrate 2 covers the channel region of the thin-film transistor 1 to protect the channel region of the thin-film transistor 1. The channel region is the overlapping area of ​​the orthographic projection of the third electrode pattern 1053 on the substrate 2 and the orthographic projection of the semiconductor layer 103 on the substrate 2.

[0116] The orthographic projection of the fourth shielding structure 1012b onto the substrate 2 and the orthographic projection of the third electrode pattern 1053 onto the substrate 2 at least partially overlap, and the fourth shielding structure 1012b and the third electrode pattern 1053 are electrically connected through a third via 102a in the first insulating layer 102 and a fourth via 104c in the second insulating layer 104. This allows the signal transmitted by the fourth shielding structure 1012b to be the same as the signal transmitted by the third electrode pattern 1053. In this case, the thin-film transistor 1 can be a dual-gate thin-film transistor. The fourth shielding structure 1012b can serve as the bottom gate pattern of the thin-film transistor 1 located on the side of the semiconductor layer 103 closest to the substrate 2, and the third electrode pattern 1053 can serve as the top gate pattern of the thin-film transistor 1 located on the side of the semiconductor layer 103 furthest from the substrate 2.

[0117] The orthographic projection of the fifth shielding structure 1013b on the substrate 2 covers the orthographic projection of the second via 104b on the substrate 2. That is, the connection between the second electrode pattern 1052 and the semiconductor layer 103 is located within the orthographic projection of the fifth shielding structure 1013b on the substrate 2.

[0118] In this embodiment, since the first electrode pattern 1051 and the third shielding structure 1011b are electrically connected, and the third electrode pattern 1053 and the fourth shielding structure 1012b are electrically connected, the third shielding structure 1011b and the fourth shielding structure 1012b are spaced apart to avoid mutual interference between the signals transmitted by the two structures, thus ensuring the performance of the thin film transistor 1.

[0119] refer to Figure 10 The first insulating layer 102 also has a sixth via 102c. The orthographic projection of the sixth via 102c on the substrate 2 and the orthographic projection of the second via 104b on the substrate 2 at least partially overlap. The second electrode pattern 1052 and the fifth shielding structure 1013b are electrically connected through the second via 104b and the sixth via 102c.

[0120] In this embodiment, the orthographic projection of the second electrode pattern 1052 on the substrate 2 at least partially overlaps with the orthographic projection of the fifth shielding structure 1013b on the substrate 2, and they are electrically connected. This allows the signal transmitted in the first electrode pattern 1051 to be transmitted to the fifth shielding structure 1013b through the second electrode pattern 1052 when the thin-film transistor 1 is in the on state. Due to the voltage difference between the film layers, the potential of the signal transmitted by the second electrode pattern 1052 is different from the potential of the signal transmitted by the fifth shielding structure 1013b, thus an electric field can be formed between the second electrode pattern 1052 and the fifth shielding structure 1013b. Furthermore, under the influence of this electric field, the semiconductor layer 103 can ensure the stability of the carrier channels formed on its surface, resulting in a lower impedance of the semiconductor layer 103 and further increasing the on-state current of the thin-film transistor 1.

[0121] refer to Figure 11 The third shading structure 1011b, the fourth shading structure 1012b, and the fifth shading structure 1013b are arranged along the third direction C. (Reference) Figure 12 The semiconductor layer 103 includes a fourth semiconductor structure 1031b, a fifth semiconductor structure 1032b, and a sixth semiconductor structure 1033b arranged in a third direction C and forming an integral structure.

[0122] The orthographic projection of the fourth semiconductor structure 1031b on the substrate 2 partially overlaps with the orthographic projection of the third shielding structure 1011b on the substrate 2. The orthographic projection of the fifth semiconductor structure 1032b on the substrate 2 partially overlaps with the orthographic projection of the fourth shielding structure 1012b on the substrate 2. The orthographic projection of the sixth semiconductor structure 1033b on the substrate 2 partially overlaps with the orthographic projection of the fifth shielding structure 1013b on the substrate 2.

[0123] Since the third shielding structure 1011b, the fourth shielding structure 1012b and the fifth shielding structure 1013b are spaced apart from each other, and the fourth semiconductor structure 1031b, the fifth semiconductor structure 1032b and the sixth semiconductor structure 1033b are an integral structure, the semiconductor layer 103 includes not only the portion that overlaps with the shielding layer 101, but also the portion that does not overlap with the shielding layer 101.

[0124] Since the overlapping area of ​​the orthographic projection of the fifth semiconductor structure 1032b in semiconductor layer 103 onto the substrate 2 and the orthographic projection of the third electrode pattern 1053 onto the substrate 2 forms the channel region of the thin-film transistor 1, in order to design the aspect ratio of the channel region, it is necessary to design the length of the fifth semiconductor structure 1032b along the fourth direction D and the length of the third electrode pattern 1053 along the third direction C. The fourth direction D and the third direction C are perpendicular.

[0125] For ease of design, the length of the fifth semiconductor structure 1032b along the fourth direction D can be different from the length of the fourth semiconductor structure 1031b along the fourth direction D and the length of the sixth semiconductor structure 1033b along the fourth direction D. Optionally, refer to... Figure 12 The length of the fifth semiconductor structure 1032b along the fourth direction D is less than the length of the fourth semiconductor structure 1031b along the fourth direction D, and less than the length of the sixth semiconductor structure 1033b along the fourth direction D.

[0126] In the embodiments of this application, reference is made to Figure 14 The fourth semiconductor structure 1031b has a seventh boundary 1031b1 extending along the fourth direction D, and the third shielding structure 1011b has a third target boundary 1011b1 extending along the fourth direction D. This third target boundary 1011b1 is the boundary of the third shielding structure 1011b away from the fifth shielding structure 1013b. In the third direction C, the seventh boundary 1031b1 is closer to the sixth semiconductor structure 1033b than the third target boundary 1011b1.

[0127] The sixth semiconductor structure 1033b has an eighth boundary 1033b1 extending along the fourth direction D, and the fifth shielding structure 1013b has a fourth target boundary 1013b1 extending along the fourth direction D. This fourth target boundary 1013b1 is the boundary of the fifth shielding structure 1013b away from the third shielding structure 1011b. In the third direction C, the eighth boundary 1033b1 is closer to the fourth semiconductor structure 1031b than the fourth target boundary 1013b1.

[0128] Based on the above design, and referring to Figure 10 The orthogonal projection of the first via 104a on the substrate 2 can include a fifth via region 104a3 that overlaps with the orthogonal projection of the third shielding structure 1011b on the substrate 2, and a sixth via region 104a4 that overlaps with the orthogonal projection of the fourth semiconductor structure 1031b on the substrate 2. Furthermore, the orthogonal projection of the first electrode pattern 1051 on the substrate 2 can cover the orthogonal projection of the first via 104a on the substrate 2, thereby enabling the first electrode pattern 1051 to be electrically connected to the third shielding structure 1011b through the fifth via region 104a3, and to be electrically connected to the fourth semiconductor structure 1031b through the sixth via region 104a4.

[0129] Correspondingly, the orthogonal projection of the second via 104b on the substrate 2 includes a seventh via region 104b3 that overlaps with the orthogonal projection of the fifth shielding structure 1013b on the substrate 2, and an eighth via region 104b4 that overlaps with the orthogonal projection of the sixth semiconductor structure 1033b on the substrate 2. Furthermore, the orthogonal projection of the second electrode pattern 1052 on the substrate 2 covers the orthogonal projection of the second via 104b on the substrate 2, thereby enabling the second electrode pattern 1052 to be electrically connected to the fifth shielding structure 1013b through the seventh via region 104b3, and to be electrically connected to the sixth semiconductor structure 1033b through the eighth via region 104b4.

[0130] In the second implementation described above, the third shielding structure 1011b can serve as the source of the thin-film transistor 1, the fifth shielding structure 1013b can serve as the drain of the thin-film transistor 1, and the third electrode pattern 1053 can serve as the gate of the thin-film transistor 1. The first electrode pattern 1051 is used to connect the third shielding structure 1011b (source) and the semiconductor layer 103, and the second electrode pattern 1052 is used to connect the fifth shielding structure 1013b (drain) and the semiconductor layer 103.

[0131] In this embodiment, the material of the semiconductor layer 103 may have a certain impact on the on-state current of the thin film transistor 1. Therefore, in order to demonstrate that the on-state current of the thin film transistor 1 provided in this embodiment is indeed increased compared to the on-state current of the thin film transistor 1 in the display technology, this embodiment uses the following two schemes as examples for simple illustration.

[0132] Option 1: The semiconductor layer 103 is made of a-IGZO. Figure 15 This is a graph showing the relationship between the input voltage and output current of a thin-film transistor provided in an embodiment of this application. Figure 16 This is a graph showing the relationship between the input voltage and output current of a thin-film transistor in related technologies.

[0133] The on-state current Ion of thin-film transistor 1 can be calculated using the following formula (1):

[0134]

[0135] In the above formula (1), A can be an output current derived from the relationship curve between input voltage and output current. For example, A can be the output current when the input voltage is 15V. L can be the length of the channel region of the thin-film transistor, and W can be the width of the channel region of the thin-film transistor.

[0136] Optionally, taking a thin-film transistor channel region with a length of 6 μm and a width of 3 μm as an example. Based on the above... Figure 15 , Figure 16According to formula (1), the on-state current Ion of the thin-film transistor 1 provided in this application embodiment can be 14.3, while the on-state current Ion of the thin-film transistor 1 in the related technology is 7.18. That is, the on-state current of the thin-film transistor 1 provided in this application embodiment is approximately twice that of the on-state current of the thin-film transistor 1 in the prior art. This can improve the charging speed of the thin-film transistor 1, which is conducive to improving the refresh rate of the display device, thereby ensuring the display quality and smoothness of the display device and improving the display effect of the display device.

[0137] Option 2: The semiconductor layer 103 is made of IGZTO. Figure 17 This is a graph showing the relationship between the input voltage and output current of another thin-film transistor provided in this application embodiment. Figure 18 This is a graph showing the relationship between the input voltage and output current of another thin-film transistor in related technologies.

[0138] Optionally, taking a thin-film transistor channel region with a length of 6 μm and a width of 3 μm as an example. Based on the above... Figure 17 , Figure 18 As can be calculated using formula (1), the on-state current Ion of the thin-film transistor 1 provided in this embodiment is 32.4 W / m², while the on-state current Ion of the thin-film transistor 1 in the related art is 19.65 W / m². That is, the on-state current of the thin-film transistor 1 provided in this embodiment is larger than that of the thin-film transistor 1 in the prior art. This can improve the charging speed of the thin-film transistor 1, facilitate improving the refresh rate of the display device, thereby ensuring the display quality and smoothness of the display device and improving the display effect.

[0139] in, Figures 15 to 18 Both 1.0E-13 and 1.00E-13 can be used to represent 1 multiplied by 10 to the power of -13. 1.00E-00 can be used to represent 1 multiplied by 10 to the power of 0. And so on, which will not be repeated in the embodiments of this application.

[0140] In summary, this application provides a thin-film transistor (TFT) comprising a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer. The potential of the signal transmitted by the first electrode pattern in the electrode layer differs from the potential of the signal transmitted by the target portion of the shielding layer. Therefore, under the influence of the electric field generated by the first electrode pattern and the target portion, a carrier channel is generated on the surface of the semiconductor layer, reducing the impedance of the semiconductor layer and increasing the on-state current of the TFT. Furthermore, the increased on-state current of the TFT can improve the refresh rate of the display device, ensuring the display quality and smoothness, resulting in a better display effect.

[0141] This application embodiment also provides a method for fabricating a thin-film transistor 1, which may include: sequentially forming a shielding layer 101, a first insulating layer 102, a semiconductor layer 103, a second insulating layer 104, and an electrode layer 105 on one side of a substrate 2.

[0142] Among them, reference Figure 1 and Figure 2 The electrode layer 105 includes a first electrode pattern 1051, a second electrode pattern 1052 and a third electrode pattern 1053. The third electrode pattern 1053 is located between the first electrode pattern 1051 and the second electrode pattern 1052, and is spaced from both the first electrode pattern 1051 and the second electrode pattern 1052.

[0143] The orthographic projection of the first electrode pattern 1051 on the substrate 2 at least partially overlaps with the orthographic projection of the semiconductor layer 103 on the substrate 2, and the first electrode pattern 1051 and the semiconductor layer 103 are electrically connected through a first via 104a in the second insulating layer 104. Furthermore, the orthographic projection of the first electrode pattern 1051 on the substrate 2 at least partially overlaps with the orthographic projection of the target portion of the shielding layer 101 on the substrate 2, and the potential of the signal transmitted by the first electrode pattern 1051 is different from the potential of the signal transmitted by the target portion. The orthographic projection of the second electrode pattern 1052 on the substrate 2 at least partially overlaps with the orthographic projection of the semiconductor layer 103 on the substrate 2, and the second electrode pattern 1052 and the semiconductor layer 103 are electrically connected through a second via 104b in the second insulating layer 104.

[0144] In this embodiment, since the potential of the signal transmitted by the target portion of the shielding layer 101 is different from the potential of the signal transmitted by the first electrode pattern 1051, an electric field can be generated between the target portion of the shielding layer 101 and the first electrode pattern 1051 in a direction perpendicular to the substrate 2 due to the difference in their potentials. Consequently, under the influence of this electric field, a carrier channel can be formed on the surface of the semiconductor layer 103 located between the target portion of the shielding layer 101 and the first electrode pattern 1051, thereby reducing the impedance of the semiconductor layer 103 and increasing the on-state current of the thin-film transistor 1. Furthermore, the increase in the on-state current of the thin-film transistor 1 can improve the charging efficiency of the thin-film transistor 1, thereby improving the refresh rate of the display device, ensuring the display quality and smoothness of the display device, and resulting in a better display effect.

[0145] In summary, this application provides a method for fabricating a thin-film transistor (TFT). The TFT fabricated by this method includes a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer. The potential of the signal transmitted by the first electrode pattern in the electrode layer differs from the potential of the signal transmitted by the target portion of the shielding layer. Therefore, under the influence of the electric field generated by the first electrode pattern and the target portion, a carrier channel is generated on the surface of the semiconductor layer, thereby reducing the impedance of the semiconductor layer and increasing the on-state current of the TFT. Furthermore, the increased on-state current of the TFT can improve the refresh rate of the display device, ensuring the display quality and smoothness of the display device, resulting in a better display effect.

[0146] Figure 19 This is a flowchart illustrating a method for fabricating a thin-film transistor according to an embodiment of this application. The method involves fabricating... Figure 1 The thin-film transistor shown is an example. (Reference) Figure 19 The method may include:

[0147] Step S101: Form a shielding layer on one side of the substrate.

[0148] In the embodiments of this application, reference is made to Figure 3 and Figure 20 The masking layer 101 can be located on one side of the substrate 2. The material of the masking layer 101 can be one or more of Ti, Cu, MoNb, and MTD. The process of forming the masking layer 101 includes: forming a masking film on one side of the substrate 2; and patterning the masking film using a first photomask to obtain the masking layer 101. The patterning process includes: photoresist coating, exposure, development, etching, and photoresist removal.

[0149] Step S102: A first insulating layer is formed on the side of the shielding layer away from the substrate.

[0150] In the embodiments of this application, reference is made to Figure 21 The first insulating layer 102 is located on the side of the shielding layer 101 away from the substrate 2.

[0151] The material of the first insulating layer 102 can be one or more of SiO and SiN. Furthermore, the first insulating layer 102 can cover the entire shielding layer 101 to insulate the shielding layer 101 from the subsequently formed semiconductor layer 103.

[0152] Optionally, the first insulating layer 102 may have a third via 102a, which can also be obtained through patterning. The third via 102a is used to electrically connect the third electrode pattern 1053 in the subsequently formed electrode layer 105 and the shielding layer 101.

[0153] Step S103: A semiconductor layer is formed on the side of the first insulating layer away from the substrate.

[0154] In the embodiments of this application, reference is made to Figure 6 and Figure 22 The semiconductor layer 103 is located on the side of the first insulating layer 102 away from the substrate 2. The material of the semiconductor layer 103 can be a-IGZO or IGZTO. The process of forming the semiconductor layer 103 includes: forming a semiconductor thin film on one side of the substrate 2; and patterning the semiconductor thin film using a second mask to obtain the semiconductor layer 103.

[0155] Step S104: Form a second insulating film on the side of the semiconductor layer away from the substrate.

[0156] In the embodiments of this application, reference is made to Figure 23 and Figure 24 The second insulating film M is located on the side of the semiconductor layer 103 away from the substrate 2. The material of the second insulating film M can be one or more of SiO and SiN. Furthermore, the material of the second insulating film M can be the same as or different from the material of the first insulating layer 102, and this embodiment does not limit this.

[0157] The second insulating film M may include a first via 104a, a second via 104b, and a fourth via 104c. The first via 104a is used to electrically connect the first electrode pattern 1051 in the subsequently formed electrode layer 105 to the semiconductor layer 103. The second via 104b is used to electrically connect the second electrode pattern 1052 in the subsequently formed electrode layer 105 to the semiconductor layer 103. The fourth via 104c is used to electrically connect the third electrode pattern 1053 in the subsequently formed electrode layer 105 to the shielding layer 101.

[0158] Furthermore, the first via 104a, the second via 104b, and the fourth via 104c can also be obtained through patterning. Moreover, to ensure the reliability of the electrical connection between the subsequently formed first electrode pattern 1051 and the semiconductor layer 103, the orthographic projection of the first via 104a on the substrate 2 must be located within the orthographic projection of the semiconductor layer 103 on the substrate 2. Similarly, to ensure the reliability of the electrical connection between the subsequently formed second electrode pattern 1052 and the semiconductor layer 103, the orthographic projection of the second via 104b on the substrate 2 must be located within the orthographic projection of the semiconductor layer 103 on the substrate 2.

[0159] Step S105: An electrode layer is formed on the side of the second insulating film away from the substrate.

[0160] In the embodiments of this application, reference is made to Figure 25The electrode layer 105 is located on the side of the second insulating film M away from the substrate 2. The material of the electrode layer 105 can be one or more of Ti, Cu, MoNb, and MTD. The process of forming the electrode layer 105 includes: forming an electrode film on one side of the substrate 2; and patterning the electrode film using a third mask to obtain the electrode layer 105.

[0161] The electrode layer 105 includes a first electrode pattern 1051, a second electrode pattern 1052, and a third electrode pattern 1053. The third electrode pattern 1053 is located between the first electrode pattern 1051 and the second electrode pattern 1052, and is spaced apart from both the first electrode pattern 1051 and the second electrode pattern 1052. The first electrode pattern 1051 and the semiconductor layer 103 are electrically connected through a first via 104a in the second insulating film, and the second electrode pattern 1052 and the semiconductor layer 103 are electrically connected through a second via 104b in the second insulating film. The third electrode pattern 1053 and the second shielding structure 1012a in the shielding layer 101 are electrically connected through a third via 102a in the first insulating layer 102 and a fourth via 104c in the second insulating film 105.

[0162] Step S106: Etch the second insulating film to obtain the second insulating layer.

[0163] In this embodiment of the application, in order to facilitate the conductor-forming process of the semiconductor layer 103, the second insulating film can be etched so that the formed second insulating layer 104 can expose a large portion of the semiconductor layer 103, thereby ensuring effective ion doping during the conductor-forming process and ensuring the conductor-forming effect of the semiconductor layer 103.

[0164] Step S107: Conduct the semiconductor layer into a conductor.

[0165] In the embodiments of this application, reference is made to Figure 26 The semiconductor layer 103 can be processed using plasma. For example, plasma processing can be performed using helium (He) and argon (Ar), or using hydrogen (H2).

[0166] In summary, this application provides a method for fabricating a thin-film transistor (TFT). The TFT fabricated by this method includes a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer. The potential of the signal transmitted by the first electrode pattern in the electrode layer differs from the potential of the signal transmitted by the target portion of the shielding layer. Therefore, under the influence of the electric field generated by the first electrode pattern and the target portion, a carrier channel is generated on the surface of the semiconductor layer, reducing the impedance of the semiconductor layer and increasing the on-state current of the TFT. Furthermore, the increased on-state current of the TFT can improve the refresh rate of the display device, ensuring the display quality and smoothness of the display device, resulting in a better display effect.

[0167] This application also provides a display panel, which may include: a substrate 2 and a plurality of thin-film transistors 1 as provided in the above embodiments located on one side of the substrate 2. The thin-film transistors 1 may be transistors in the gate-driven on-array (GOA) circuit of the display panel. Alternatively, the thin-film transistors 1 may be transistors in the pixel circuit of a sub-pixel in the display panel.

[0168] Figure 27 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. (Reference) Figure 27 The display device may include a power supply component 02 and a display panel 01 as provided in the above embodiments. The power supply component 02 can be used to supply power to the display panel 01.

[0169] Optionally, the display device can be: a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, electronic paper, a low-temperature poly-silicon (LTPS) display device, a low-temperature poly-silicon oxide (LTPO) display device, an oxide display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0170] Since the display device can have essentially the same technical effects as the thin-film transistor 1 described in the previous embodiments, the technical effects of the thin-film transistor 1 will not be repeated here for the sake of brevity.

[0171] The terminology used in the embodiments section of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," "third," and similar terms used in the patent application specification and claims of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including," and similar terms mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms "connected," "linked," and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up," "down," "left," "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. As used herein, “about,” “approximately,” “roughly,” or “substantially the same” includes the stated value and means within an acceptable range of deviation from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0172] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to indicate precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0173] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A thin film transistor, characterized by comprising: The thin-film transistor includes: A shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer are sequentially stacked on a substrate and along the side away from the substrate. The shielding layer has a first shielding structure and a second shielding structure that are intersecting and integrally formed; The electrode layer includes a first electrode pattern, a second electrode pattern, and a third electrode pattern. The third electrode pattern is located between the first electrode pattern and the second electrode pattern and is spaced apart from both the first electrode pattern and the second electrode pattern. The orthographic projection of the first shielding structure on the substrate covers the overlapping area of ​​the orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the semiconductor layer on the substrate. The first shielding structure is the target portion. The orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the third electrode pattern on the substrate. The second shielding structure and the third electrode pattern are electrically connected through a third via in the first insulating layer and a fourth via in the second insulating layer. The orthographic projection of the first electrode pattern on the substrate overlaps at least partially with the orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the target portion on the substrate. The first electrode pattern and the semiconductor layer are electrically connected through a first via in the second insulating layer. The potential of the signal transmitted by the first electrode pattern is different from the potential of the signal transmitted by the target portion. The orthographic projection of the second electrode pattern on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate, and the second electrode pattern and the semiconductor layer are electrically connected through a second via in the second insulating layer.

2. The thin-film transistor according to claim 1, characterized in that, The semiconductor layer includes a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure arranged along a first direction and forming an integral structure. The orthogonal projection of the first semiconductor structure on the substrate covers the orthogonal projection of the first via on the substrate. The orthographic projection of the second semiconductor structure on the substrate is located within the orthographic projection of the first shielding structure on the substrate; The orthogonal projection of the third semiconductor structure onto the substrate covers the orthogonal projection of the second via onto the substrate.

3. The thin-film transistor according to claim 2, characterized in that, The first shielding structure is a strip-shaped structure extending along the first direction, and the second shielding structure is a strip-shaped structure extending along the second direction, wherein the first direction and the second direction are perpendicular. The first shielding structure has a first target boundary and a second target boundary that extend along a second direction and are disposed opposite to each other. The first target boundary is closer to the first semiconductor structure relative to the second target boundary, and the second target boundary is closer to the third semiconductor structure relative to the first target boundary. The first semiconductor structure has a first boundary and a second boundary extending along a first direction, and a third boundary extending along a second direction; the distance between the first boundary and the second boundary is greater than the length of the first shielding structure along the second direction; In the first direction, the third boundary is further away from the third semiconductor structure relative to the first target boundary; The third semiconductor structure has a fourth boundary and a fifth boundary extending along the first direction, and a sixth boundary extending along the second direction; the distance between the fourth boundary and the fifth boundary is greater than the length of the first shielding structure along the second direction; in the first direction, the sixth boundary is further away from the first semiconductor structure relative to the second target boundary; The length of the second semiconductor structure along the second direction is less than the length of the first shielding structure along the second direction.

4. The thin-film transistor according to claim 2, characterized in that, The third electrode pattern is a strip-shaped structure extending along the second direction, and the first direction and the second direction are perpendicular. The overlapping area of ​​the orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the semiconductor layer on the substrate is the channel region of the thin-film transistor. The portion of the third electrode pattern located in the channel region has a length along the first direction that is less than or equal to the length of the second semiconductor structure along the first direction.

5. The thin-film transistor according to claim 1, characterized in that, The orthographic projection of the second shielding structure on the substrate does not overlap with the orthographic projection of the semiconductor layer on the substrate.

6. The thin-film transistor according to any one of claims 2 to 4, characterized in that, The orthographic projection of the first via on the substrate includes: a first hole region that overlaps with the orthographic projection of the first electrode pattern on the substrate, and a second hole region that does not overlap with the orthographic projection of the first electrode pattern on the substrate, the second hole region being used to expose at least a portion of the first semiconductor structure; The orthographic projection of the second via on the substrate includes: a third via region that overlaps with the orthographic projection of the second electrode pattern on the substrate, and a fourth via region that does not overlap with the orthographic projection of the second electrode pattern on the substrate, the fourth via region being used to expose at least a portion of the third semiconductor structure.

7. A thin-film transistor, characterized in that, The thin-film transistor includes: A shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer are sequentially stacked on a substrate and along the side away from the substrate. The shielding layer has a third shielding structure, a fourth shielding structure and a fifth shielding structure arranged in pairs at intervals; The electrode layer includes a first electrode pattern, a second electrode pattern, and a third electrode pattern. The third electrode pattern is located between the first electrode pattern and the second electrode pattern, and is spaced from both the first electrode pattern and the second electrode pattern. The orthographic projection of the first electrode pattern on the substrate overlaps at least partially with the orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the target portion of the shielding layer on the substrate, and the first electrode pattern and the semiconductor layer are electrically connected through a first via in the second insulating layer. The orthographic projection of the second electrode pattern on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate, and the second electrode pattern and the semiconductor layer are electrically connected through a second via in the second insulating layer; The first insulating layer also has a fifth via; the orthographic projection of the fifth via on the substrate and the orthographic projection of the first via on the substrate at least partially overlap, and the first electrode pattern and the target portion are electrically connected through the first via and the fifth via; The orthogonal projection of the third shielding structure on the substrate covers the orthogonal projection of the first via on the substrate, and the third shielding structure is the target portion; The orthographic projection of the fourth shielding structure on the substrate covers the overlapping area of ​​the orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the semiconductor layer on the substrate; the orthographic projection of the fourth shielding structure on the substrate and the orthographic projection of the third electrode pattern on the substrate at least partially overlap, and the fourth shielding structure and the third electrode pattern are electrically connected through the third via in the first insulating layer and the fourth via in the second insulating layer. The orthogonal projection of the fifth shielding structure on the substrate covers the orthogonal projection of the second via on the substrate.

8. The thin-film transistor according to claim 7, characterized in that, The first insulating layer also has a sixth through-hole; The orthographic projection of the sixth via on the substrate and the orthographic projection of the second via on the substrate at least partially overlap, and the second electrode pattern and the fifth shielding structure are electrically connected through the second via and the sixth via.

9. The thin-film transistor according to claim 7, characterized in that, The third shielding structure, the fourth shielding structure, and the fifth shielding structure are arranged along a third direction; the semiconductor layer includes a fourth semiconductor structure, a fifth semiconductor structure, and a sixth semiconductor structure that are arranged along the third direction and are integral structures. The orthographic projection of the fourth semiconductor structure on the substrate and the orthographic projection of the third shielding structure on the substrate partially overlap; the orthographic projection of the fifth semiconductor structure on the substrate and the orthographic projection of the fourth shielding structure on the substrate partially overlap; the orthographic projection of the sixth semiconductor structure on the substrate and the orthographic projection of the fifth shielding structure on the substrate partially overlap. Wherein, the length of the fifth semiconductor structure along the fourth direction is less than the length of the fourth semiconductor structure along the fourth direction, and less than the length of the sixth semiconductor structure along the fourth direction, and the fourth direction is perpendicular to the third direction.

10. The thin-film transistor according to claim 9, characterized in that, The fourth semiconductor structure has a seventh boundary extending along the fourth direction, and the third shielding structure has a third target boundary extending along the fourth direction, the third target boundary being the boundary of the third shielding structure away from the fifth shielding structure. In the third direction, the seventh boundary is closer to the sixth semiconductor structure relative to the third target boundary; The sixth semiconductor structure has an eighth boundary extending along the fourth direction, and the fifth shielding structure has a fourth target boundary extending along the fourth direction, the fourth target boundary being the boundary of the fifth shielding structure away from the third shielding structure. In the third direction, the eighth boundary is closer to the fourth semiconductor structure relative to the fourth target boundary.

11. A method for fabricating a thin-film transistor, characterized in that, The method includes: A shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, and an electrode layer are sequentially formed on one side of a substrate. The shielding layer has a first shielding structure and a second shielding structure that are intersecting and integrally formed; The electrode layer includes a first electrode pattern, a second electrode pattern, and a third electrode pattern. The third electrode pattern is located between the first electrode pattern and the second electrode pattern and is spaced apart from both the first electrode pattern and the second electrode pattern. The orthographic projection of the first shielding structure on the substrate covers the overlapping area of ​​the orthographic projection of the third electrode pattern on the substrate and the orthographic projection of the semiconductor layer on the substrate. The first shielding structure is the target portion. The orthographic projection of the second shielding structure on the substrate at least partially overlaps with the orthographic projection of the third electrode pattern on the substrate. The second shielding structure and the third electrode pattern are electrically connected through a third via in the first insulating layer and a fourth via in the second insulating layer. The orthographic projection of the first electrode pattern on the substrate overlaps at least partially with the orthographic projection of the semiconductor layer on the substrate and the orthographic projection of the target portion of the shielding layer on the substrate. The first electrode pattern and the semiconductor layer are electrically connected through a first via in the second insulating layer. The potential of the signal transmitted by the first electrode pattern is different from the potential of the signal transmitted by the target portion. The orthographic projection of the second electrode pattern on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate, and the second electrode pattern and the semiconductor layer are electrically connected through a second via in the second insulating layer.

12. A display panel, characterized in that, The display panel includes: a substrate and a plurality of thin-film transistors as described in any one of claims 1 to 10 located on one side of the substrate.

13. A display device, characterized in that, The display device includes: a power supply component and a display panel as described in claim 12; The power supply component is used to supply power to the display panel.

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