Data synchronization method, system, device and storage medium in baseband

Abstract

This invention provides a method, system, device, and storage medium for in-baseband data synchronization. One method is applied to a master device, which is a baseband unit or its corresponding acceleration subsystem. The baseband unit and the acceleration subsystem form a master-slave relationship. The method includes: sending a 1pps+tod clock synchronization signal to the slave device via a reserved pin in a PCIe slot; acquiring clock time information from the master device based on the 1pps signal, and generating a first data synchronization pointer for the data to be transmitted based on the clock time information; and sending the data to be transmitted carrying the first data synchronization pointer to the slave device. This invention enables the transmission of clock synchronization signals between the master and slave devices using reserved pins in a PCIe slot. The slave device performs local clock synchronization based on the received synchronization signal and extracts data based on the synchronization pointer. This improves the synchronization accuracy of data processing and reduces the capacity of the processor chip.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically, to a method, system, device, and storage medium for data synchronization within baseband. Background Technology

[0002] Due to the limitations of 5G high-frequency bands, in areas where sites are available, the only way to improve user experience is through the deployment of encrypted macro base stations. However, when site acquisition is difficult and macro base stations cannot be expanded, small base stations must be used to increase network capacity. Therefore, to meet future capacity growth demands, changing the network structure and building a multi-band, multi-standard, and multi-form indoor and outdoor layered three-dimensional network is the goal of network development, and small base stations are a necessary means to improve deep coverage and capacity.

[0003] The 5G extended active indoor distributed base station consists of three parts: a baseband unit (BBU), an extension unit (HUB), and a remote radio unit (RRU). Based on the x86 platform, this indoor distributed base station complies with OTII server technical specifications and is more suitable for wireless access rooms and edge rooms with poor conditions. It is of great significance for promoting the actual deployment of future virtualized 5G base station BBU products, exploring further edge computing services, and reducing access room renovation costs.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To address the problems in existing technologies, the present invention aims to provide a baseband data synchronization method, system, device, and storage medium that overcomes the difficulties of existing technologies. It enables the transmission of clock synchronization signals between the master and slave devices using reserved pins in a PCIe slot. The slave device performs local clock synchronization based on the received synchronization signal and extracts data based on the synchronization pointer. This improves the synchronization accuracy of data processing while reducing the data processing latency of the slave device and reducing the capacity of the processor chip.

[0006] An embodiment of the present invention provides a baseband data synchronization method, characterized in that it is applied to a master device, wherein the master device is a baseband unit or an acceleration subsystem corresponding to the baseband unit, and the baseband unit and the acceleration subsystem constitute a master-slave device relationship. The baseband data synchronization method includes the following steps:

[0007] Send a 1pps+tod clock synchronization signal to the slave device via a reserved pin in the PCIe slot;

[0008] The master device acquires clock time information based on the 1pps signal, and generates the first data synchronization pointer for the data to be sent based on the clock time information.

[0009] Send the data to be sent, carrying the first data synchronization pointer, to the slave device.

[0010] Send the data to be sent, carrying the first data synchronization pointer, to the slave device, including:

[0011] The data to be sent, carrying the first data synchronization pointer, is then sent down and filled into the buffer provided by the device hardware interface.

[0012] Optionally, before sending a 1pps+tod clock synchronization signal to the slave device via the reserved pin of the PCIe slot, the data synchronization method further includes:

[0013] Synchronize to the backhaul network via SyncE+1588, and restore the 1pps+tod clock synchronization signal via the SOC network port.

[0014] Optionally, in the 1pps+tod clock synchronization signal, the time information is encapsulated into the tod signal based on whole seconds.

[0015] Embodiments of the present invention also provide a baseband data synchronization method, which is applied to a slave device, wherein the slave device is a baseband unit or an acceleration subsystem corresponding to the baseband unit, and the baseband unit and the acceleration subsystem constitute a master-slave device relationship. The baseband data synchronization method includes:

[0016] Receive 1pps+tod clock synchronization signal from the master device, obtain the time interval based on the 1pps signal, and generate multiple second data synchronization pointers in sequence according to the time interval based on the tod information;

[0017] A 1pps signal is input to the slave device clock, sampled under the slave device clock, and when the second data synchronization pointer is sampled, the data to be sent by the master device carrying the first data synchronization pointer is obtained based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer mark the synchronization time information.

[0018] Optionally, obtaining the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer includes:

[0019] Based on the second data synchronization pointer, retrieve the data to be sent from the buffer provided by the slave device hardware interface, carrying the first data synchronization pointer.

[0020] Optionally, multiple second data synchronization pointers are generated sequentially according to time intervals based on the tod information, including:

[0021] Parse the whole second time from the tod information, and generate multiple second data synchronization pointers in sequence according to the time interval based on the whole second time.

[0022] Embodiments of the present invention also provide an intra-baseband data synchronization system, which includes a baseband unit and an acceleration subsystem constituting a master-slave device relationship;

[0023] The master device is used to send a 1pps+tod clock synchronization signal to the slave device through the reserved pin of the PCIe slot, collect clock time information from the master device based on the 1pps signal, generate a first data packet synchronization pointer for the data to be sent based on the clock time information, and send the data to be sent carrying the first data synchronization pointer to the slave device.

[0024] The slave device is used to receive a 1pps+tod clock synchronization signal from the master device, obtain the time interval based on the 1pps signal, and generate multiple second data synchronization pointers in sequence according to the time interval based on the tod information. The 1pps signal is used as the input source of the slave device clock, and sampling is performed under the slave device clock. When the second data synchronization pointer is sampled, the data to be sent by the master device carrying the first data synchronization pointer is obtained based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer point to the synchronization time information.

[0025] Embodiments of the present invention also provide an intra-baseband data synchronization system applied to a master device, wherein the master device is a baseband unit or an acceleration subsystem corresponding to the baseband unit, and the baseband unit and the acceleration subsystem constitute a master-slave device relationship. This intra-baseband data synchronization system is used to implement the aforementioned intra-baseband data synchronization method. The intra-baseband data synchronization system includes:

[0026] The clock synchronization signal transmission module sends a 1pps+tod clock synchronization signal to the slave device through the reserved pin of the PCIe slot.

[0027] The synchronization pointer generation module collects clock time information from the master device based on the 1pps signal, and generates the first data synchronization pointer for the data to be sent based on the clock time information.

[0028] The data sending module sends the data to be sent, carrying the first data synchronization pointer, to the slave device.

[0029] Embodiments of the present invention also provide an intra-baseband data synchronization system applied to a slave device, wherein the slave device is a baseband unit or an acceleration subsystem corresponding to the baseband unit, and the baseband unit and the acceleration subsystem constitute a master-slave device relationship. This intra-baseband data synchronization system is used to implement the aforementioned intra-baseband data synchronization method. The intra-baseband data synchronization system is as follows:

[0030] The clock synchronization signal receiving module receives a 1pps+tod clock synchronization signal from the master device, obtains the time interval based on the 1pps signal, and generates multiple second data synchronization pointers in sequence according to the time interval based on the tod information.

[0031] The data synchronization acquisition module inputs a 1pps signal to the slave device clock, samples it under the slave device clock, and, when the second data synchronization pointer is acquired, acquires the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer mark the synchronization time information.

[0032] Embodiments of the present invention also provide an in-baseband data synchronization device, comprising:

[0033] processor;

[0034] Memory, which stores the processor's executable instructions;

[0035] The processor is configured to execute the steps of the above-described baseband data synchronization method by executing executable instructions.

[0036] Embodiments of the present invention also provide a computer-readable storage medium for storing a program that, when executed, implements the steps of the above-described baseband data synchronization method.

[0037] The purpose of this invention is to provide a baseband data synchronization method, system, device, and storage medium that can utilize reserved pins in a PCIe slot to transmit clock synchronization signals between a master device and a slave device. The slave device performs local clock synchronization based on the received synchronization signal and extracts data based on the synchronization pointer. This improves the synchronization accuracy of data processing while reducing the data processing latency of the slave device and reducing the capacity of the processor chip. Attached Figure Description

[0038] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0039] Figure 1 This is a diagram of the architecture of an existing baseband data synchronization system;

[0040] Figure 2 This is a flowchart of an existing baseband data synchronization method;

[0041] Figure 3 This is a flowchart of one embodiment of the baseband data synchronization method of the present invention;

[0042] Figure 4 This is a flowchart of a second embodiment of the baseband data synchronization method of the present invention;

[0043] Figure 5 This is a structural diagram of the baseband data synchronization system provided by the present invention;

[0044] Figure 6 This is an architecture diagram of an in-baseband data synchronization system according to an embodiment of the present invention;

[0045] Figure 7 This is a flowchart of an application scenario of the baseband data synchronization method of the present invention;

[0046] Figure 8 This is a schematic diagram of a module in one embodiment of the baseband data synchronization of the present invention;

[0047] Figure 9 This is a schematic diagram of a module in a second embodiment of the baseband data synchronization of the present invention;

[0048] Figure 10 This is a schematic diagram of the operation of the baseband data synchronization system of the present invention. Detailed Implementation

[0049] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to fully and completely convey the concept of the exemplary embodiments to those skilled in the art.

[0050] The accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware forwarding modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0051] Furthermore, the processes shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps can be broken down, some steps can be combined or partially combined, and the actual execution order may change depending on the actual situation. The terms "first," "second," and similar terms used in the specific description do not indicate any order, quantity, or importance, but are only used to distinguish different components. It should be noted that, unless otherwise specified, embodiments of the present invention and features in different embodiments can be combined with each other.

[0052] In practice, the inventors of this case discovered that, based on the ORAN LLS interface definition, using Option 8 to split the BBU(DU) and HUB can effectively reduce the cost of pRRU.

[0053] Specifically, the baseband unit, as the main unit, offloads the channel encoding / decoding and fronthaul interface functions, which have high real-time requirements at the protocol stack physical layer, to the hardware acceleration subsystem to improve processing performance and reduce processor load. Taking the downlink direction as an example, baseband data is forwarded to the acceleration subsystem through the hardware PCIe interface between the two, and then synchronized by the acceleration subsystem before being transmitted to the extension unit via the fronthaul interface.

[0054] The current system architecture uses a passive synchronization mode, refer to Figure 1 The baseband data transmission system architecture based on passive synchronization mode is as follows:

[0055] The acceleration subsystem needs to obtain a GPS synchronization source for time synchronization through the SMA (SubMiniature version A) interface on the panel;

[0056] The main unit polls the in-band synchronization flag signal provided by the acceleration subsystem to trigger baseband data DMA (Direct Memory Access) data channel transmission;

[0057] The acceleration subsystem extracts baseband data based on the local data synchronization pointer to achieve baseband data synchronization.

[0058] refer to Figure 2 , Figure 2 For based on Figure 1 The baseband data synchronization process for the architecture shown is as follows:

[0059] Protocol stack startup;

[0060] The baseband data blocks are counted, and the two initial data blocks are placed into two separate buffers.

[0061] A polling mechanism is used to determine the flag bit for data transmission.

[0062] When the flag is detected, the data is forwarded to the buffer of the acceleration subsystem;

[0063] Ping-pong operation is used for filling, with even-numbered bits placed in the low buffer and odd-numbered bits placed in the high buffer. The logic processing unit also uses ping-pong operation to extract data from the buffer.

[0064] The acceleration subsystem generates a local pointer signal using clock timing information to extract data from the buffer and complete the baseband data synchronization between the main and auxiliary units.

[0065] It can be noted that there is no strict clock synchronization process between the baseband unit and the acceleration subsystem. Instead, data synchronization is achieved by polling the synchronization signal provided by the acceleration subsystem. This can easily introduce deviations in the time of post-data transmission processing, requiring data calibration through the front-end interface. This increases the processing complexity of the acceleration subsystem, as well as the hardware cost and the capacity of the processing chip.

[0066] Therefore, given the large data synchronization delay and low accuracy of the baseband unit and acceleration subsystem, it is necessary to improve the existing synchronization scheme to improve data synchronization accuracy and reduce the data processing delay of the acceleration subsystem.

[0067] The inventive concept of this invention is to utilize the reserved pins of the PCIe slot defined by PCISIG to transmit clock synchronization signals between the master and slave devices. The slave device performs local clock synchronization based on the received synchronization signals and extracts data based on the synchronization pointer. This improves the synchronization accuracy of data processing, while reducing the data processing latency of the acceleration subsystem and reducing the capacity of the processor chip.

[0068] The master and slave devices are defined by the data flow direction. Specifically, the baseband unit and the acceleration subsystem constitute the master-slave relationship. That is, when the master device is the baseband unit, the slave device refers to the acceleration subsystem, and when the master device is the acceleration subsystem, the slave device is the baseband unit.

[0069] Figure 3 This is a flowchart illustrating an embodiment of the baseband data synchronization method provided by the present invention. The main device executing this method is a baseband unit or the acceleration subsystem corresponding to the baseband unit. The baseband data synchronization method may include:

[0070] Step 310: Send a 1pps+tod clock synchronization signal to the slave device via the reserved pin of the PCIe slot;

[0071] Step 320: Collect clock time information from the master device based on the 1pps signal, and generate a first data synchronization pointer for the data to be sent based on the clock time information;

[0072] Step 330: Send the data to be sent, carrying the first data synchronization pointer, to the slave device.

[0073] In the 1pps+tod clock synchronization signal, the 1pps signal provides a precise clock synchronization signal, using the rising edge as the accurate time point, and the tod (time of today) information contains the time information corresponding to the rising edge of the current 1pps signal.

[0074] In this case, upon receiving the 1pps+tod clock synchronization signal from the device, the local clock can be synchronized locally based on the 1pps+tod clock synchronization signal.

[0075] The pulse width of a 1pps signal represents the frequency and can be set as needed.

[0076] Therefore, embodiments of the present invention can utilize reserved pins in the PCIe slot to transmit clock synchronization signals between the master and slave devices. The slave device performs local clock synchronization based on the received synchronization signal and extracts data based on the synchronization pointer. This improves the synchronization accuracy of data processing while reducing the data processing latency of the slave device and reducing the capacity of the processor chip.

[0077] In an optional embodiment, the data synchronization method further includes: prior to sending a 1pps+tod clock synchronization signal to the slave device via the PCIe slot reserved pin.

[0078] Synchronize to the backhaul network via SyncE+1588, and restore the 1pps+tod clock synchronization signal via the SOC network port.

[0079] Synchronous Ethernet (SyncE) is an ITU-T standard for computer networks that defines how clock signals are transmitted in the Ethernet physical layer. The purpose of Synchronous Ethernet is to provide synchronization signals for various resources within the network. Synchronous Ethernet signals are transmitted in the Ethernet physical layer and should be traceable to an external clock.

[0080] 1588 time synchronization is a high-precision time synchronization protocol. Its implementation process involves transmitting 1pps (second pulse) and tod (day time) of the clock source provided by the source node to each slave node in the form of message exchange, thereby achieving time synchronization between the slave nodes and the source node.

[0081] This embodiment uses a hybrid clock source of SyncE+1588 to synchronize external data to the master device.

[0082] In this embodiment of the invention, the master device marks the time information of the data to be sent by adding a first data synchronization pointer, so that the slave device can identify and extract the data synchronously.

[0083] In an optional embodiment, sending the data to be sent, carrying the first data synchronization pointer, to the slave device specifically includes the following steps:

[0084] The data to be sent, carrying the first data synchronization pointer, is then sent down and filled into the buffer provided by the device hardware interface.

[0085] In this embodiment, the master device sends the data to be sent to the buffer provided by the slave device for the slave device to retrieve.

[0086] In an optional embodiment, in the 1pps+tod clock synchronization signal, time information is encapsulated into the tod signal based on whole seconds.

[0087] Figure 4 This invention provides another embodiment of an intra-baseband data synchronization method, in which the slave device is the execution subject of this method. For example... Figure 4 As shown, the baseband data synchronization method includes the following steps:

[0088] Step 410: Receive 1pps+tod clock synchronization signal from the master device, obtain the time interval based on the 1pps signal, and generate multiple second data synchronization pointers in sequence according to the time interval based on the tod information;

[0089] Step 420: Input the 1pps signal into the slave device clock, sample it under the slave device clock, and when the second data synchronization pointer is sampled, obtain the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer mark the synchronization time information.

[0090] Combination Figure 3 It can be seen that the slave device obtains a 1pps+tod clock synchronization signal from the master device and synchronizes its timing locally according to this clock synchronization signal, thereby maintaining time synchronization between the slave device and the master device. In this case, each time the second data synchronization pointer is sampled, it triggers the acquisition of data to be sent.

[0091] When acquiring data to be sent, the data pointing to the synchronization time information can be accurately obtained based on the local second data synchronization pointer. This data to be sent carries the first data synchronization pointer. The first and second data synchronization information can point to the same time information.

[0092] In an optional embodiment, obtaining the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer includes:

[0093] Based on the second data synchronization pointer, retrieve the data to be sent from the buffer provided by the slave device hardware interface, carrying the first data synchronization pointer.

[0094] In an optional embodiment, multiple second data synchronization pointers are generated sequentially according to time intervals based on the tod information, including:

[0095] Parse the whole second time from the tod information, and generate multiple second data synchronization pointers in sequence according to the time interval based on the whole second time.

[0096] Figure 5This is a structural diagram of the baseband data synchronization system provided by the present invention. The system includes:

[0097] The baseband unit and acceleration subsystem that constitute the master-slave device relationship;

[0098] The master device 510 is used to send a 1pps+tod clock synchronization signal to the slave device 520 through the reserved pin of the PCIe slot, collect clock time information from the master device 510 based on the 1pps signal, generate a first data packet synchronization pointer for the data to be sent based on the clock time information, and send the data to be sent carrying the first data synchronization pointer to the slave device 520.

[0099] The slave device 520 is used to receive a 1pps+tod clock synchronization signal from the master device 510, obtain the time interval based on the 1pps signal, and generate multiple second data synchronization pointers in sequence according to the time interval based on the tod information. The 1pps signal is used as the input source of the slave device clock, and sampling is performed under the slave device clock. When the second data synchronization pointer is sampled, the slave device obtains the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer point to the synchronization time information.

[0100] Figure 6 This is an architecture diagram of the baseband data synchronization system of the present invention, in which a clock synchronization channel is added between the baseband unit and the acceleration subsystem.

[0101] The baseband unit synchronizes to the backhaul network via SyncE+1588 through the server remote management controller (BMC).

[0102] The BMC transmits the 1pps+tod clock synchronization signal to the CLK in the acceleration subsystem via the PCIe slot reserved pin PCIe CLK.

[0103] In this scenario, the baseband unit and the acceleration subsystem each maintain time synchronization locally.

[0104] In this scenario, the baseband unit can retrieve the backhaul data synchronized with the backhaul network from its local buffer, insert a first data synchronization pointer, and then send it to the buffer provided by the acceleration subsystem hardware interface. The acceleration subsystem retrieves the data according to the indication of the second data synchronization pointer and transmits it to the RRU / HUB.

[0105] Figure 7 This is a flowchart of a baseband data synchronization method for one application scenario of the present invention. The method specifically includes the following steps.

[0106] Step 710: System initialization configuration and startup, which includes the startup of the main unit protocol stack and the distribution of basic configurations, as well as the configuration of hardware interfaces of the acceleration subsystem.

[0107] Step 720: The baseband unit synchronizes to the backhaul network via SyncE+1588 and recovers the 1pps+tod signal from the SOC network port. This signal is transmitted in-band to the acceleration subsystem in the form of a PCIe x16 reserved pin.

[0108] The time information can be encapsulated into the tod signal based on whole seconds.

[0109] Step 730: The baseband unit generates a first data synchronization pointer signal based on the clock time information, sends down the baseband data, fills it into the buffer area provided by the acceleration subsystem hardware interface, and waits for the acceleration subsystem to retrieve it.

[0110] For example, pointers for each data block are generated by clock counting.

[0111] Step 740: The acceleration subsystem obtains 1pps information through the reserved pin of the PCIe slot, and at the same time, the PLL of the acceleration subsystem is locked on the 1pps clock and the PLL outputs the system clock.

[0112] Step 750: The acceleration subsystem obtains the TOD information through the reserved pins of the PCIe slot, parses out the whole second time, and generates a second data synchronization pointer with equal intervals based on the time information, which is used to read the baseband data in the buffer area.

[0113] Step 760: The acceleration subsystem samples under the local system clock. When the second data synchronization pointer is sampled, the buffer data is extracted and split into data of corresponding bit width according to different requirements to realize data synchronization between the baseband unit and the acceleration subsystem.

[0114] Figure 8 This is a schematic diagram of a module of an embodiment of the baseband data synchronization system of the present invention. The baseband data synchronization system of the present invention is applied to a master device, which is a baseband unit or an acceleration subsystem corresponding to the baseband unit. The baseband unit and the acceleration subsystem constitute a master-slave relationship, such as... Figure 8 As shown, the baseband data synchronization system includes, but is not limited to:

[0115] The clock synchronization signal transmission module 810 sends a 1pps+tod clock synchronization signal to the slave device through the reserved pin of the PCIe slot.

[0116] The synchronization pointer generation module 820 collects clock time information from the master device based on the 1pps signal, and generates the first data synchronization pointer for the data to be sent based on the clock time information.

[0117] The data transmission module 830 sends the data to be transmitted, carrying the first data synchronization pointer, to the slave device.

[0118] The implementation principle of the above modules can be found in the relevant introduction in the baseband data synchronization method, and will not be repeated here.

[0119] The baseband data synchronization system of this invention can utilize reserved pins in the PCIe slot to transmit clock synchronization signals between the master and slave devices. The slave device performs local clock synchronization based on the received synchronization signal and retrieves data based on the synchronization pointer. This improves the synchronization accuracy of data processing while reducing the data processing latency of the slave device and reducing the capacity of the processor chip.

[0120] Optionally, the data transmission module 830 is specifically used for:

[0121] The data to be sent, carrying the first data synchronization pointer, is then sent down and filled into the buffer provided by the device hardware interface.

[0122] Optionally, the data synchronization system also includes:

[0123] Before sending a 1pps+tod clock synchronization signal to the slave device through the reserved pin of the PCIe slot, the backhaul network synchronization module synchronizes to the backhaul network via SyncE+1588 and restores the 1pps+tod clock synchronization signal through the SOC network port.

[0124] Figure 9 This is a schematic diagram of another embodiment of the baseband data synchronization system of the present invention. Figure 9 As shown, the baseband data synchronization system is applied to slave devices, which are baseband units or the corresponding acceleration subsystems. The baseband units and acceleration subsystems form a master-slave relationship. The baseband data synchronization system includes:

[0125] The clock synchronization signal receiving module 910 receives a 1pps+tod clock synchronization signal from the master device, obtains the time interval based on the 1pps signal, and generates multiple second data synchronization pointers in sequence according to the time interval based on the tod information.

[0126] The data synchronization acquisition module 920 inputs a 1pps signal to the slave device clock, samples it under the slave device clock, and, when the second data synchronization pointer is acquired, acquires the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer mark the synchronization time information.

[0127] The implementation principle of the above-mentioned module can be found in the relevant introduction in the baseband data synchronization method, and will not be repeated here.

[0128] The baseband data synchronization system of this invention can utilize reserved pins in the PCIe slot to transmit clock synchronization signals between the master and slave devices. The slave device performs local clock synchronization based on the received synchronization signal and retrieves data based on the synchronization pointer. This improves the synchronization accuracy of data processing while reducing the data processing latency of the slave device and reducing the capacity of the processor chip.

[0129] This invention also provides an in-baseband data synchronization device, including a processor and a memory storing executable instructions for the processor. The processor is configured to execute steps of an in-baseband data synchronization method by executing the executable instructions.

[0130] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "platform."

[0131] Figure 10 This is a schematic diagram of the baseband data synchronization device of the present invention. Refer to the following... Figure 10 To describe an electronic device 1000 according to this embodiment of the present invention. Figure 10 The electronic device 1000 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0132] like Figure 10 As shown, the electronic device 1000 is presented in the form of a general-purpose computing device. The components of the electronic device 1000 may include, but are not limited to: at least one processing unit 1010, at least one storage unit 1020, a bus 1030 connecting different platform components (including storage unit 1020 and processing unit 1010), a display unit 1040, etc.

[0133] The storage unit stores program code, which can be executed by the processing unit 1010 to perform the steps described in the baseband data synchronization method section of this specification, according to various exemplary embodiments of the present invention. For example, the processing unit 1010 can perform, as follows: Figures 3-4 The steps are shown in the figure.

[0134] Storage unit 1020 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 1021 and / or a cache memory unit 1022, and may further include a read-only memory unit (ROM) 1023.

[0135] Storage unit 1020 may also include a program / utility 1024 having a set (at least one) program module 1025, such program module 1025 including but not limited to: processing system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0136] Bus 1030 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the multiple bus structures.

[0137] The electronic device 1000 can also communicate with one or more external devices 1070 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with the electronic device 1000, and / or with any device that enables the electronic device 1000 to communicate with one or more other computing devices (e.g., router, modem, etc.). Such communication can be performed through the input / output (I / O) interface 1050.

[0138] Furthermore, the electronic device 1000 can also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via the network adapter 1060. The network adapter 1060 can communicate with other modules of the electronic device 1000 via the bus 1030. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with the electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms.

[0139] This invention also provides a computer-readable storage medium for storing a program, which, when executed, implements the steps of an intra-baseband data synchronization method. In some possible implementations, various aspects of this invention can also be implemented as a program product comprising program code that, when run on a terminal device, causes the terminal device to perform the steps described in the above-described intra-baseband data synchronization method section of this specification according to various exemplary embodiments of the invention.

[0140] According to embodiments of the present invention, a program product for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0141] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0142] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0143] Program code for performing the processing of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0144] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for data synchronization in a baseband, the method comprising: Applied to a master device, wherein the master device is a baseband unit or an acceleration subsystem corresponding to the baseband unit, and the baseband unit and the acceleration subsystem constitute a master-slave device relationship, the data synchronization method within the baseband includes: Send a 1pps+tod clock synchronization signal to the slave device via a reserved pin in the PCIe slot; The master device acquires clock time information based on the 1pps signal, and generates a first data synchronization pointer for the data to be sent based on the clock time information. The data to be sent, carrying the first data synchronization pointer, is sent to the slave device.

2. The method for in-band data synchronization as claimed in claim 1, wherein, Sending the data to be sent, carrying the first data synchronization pointer, to the slave device includes: The data to be sent, carrying the first data synchronization pointer, is sent down and filled into the buffer area provided by the slave device hardware interface.

3. The baseband data synchronization method according to claim 1, characterized in that, Before sending a 1pps+tod clock synchronization signal to the slave device via the reserved pin in the PCIe slot, the data synchronization method further includes: The clock is synchronized to the backhaul network via SyncE+1588, and the 1pps+tod clock synchronization signal is restored by the SOC network port.

4. The baseband data synchronization method according to claim 3, characterized in that, In the 1pps+tod clock synchronization signal, time information is encapsulated into the tod signal based on whole seconds.

5. A method for data synchronization within baseband, characterized in that, Applied to slave devices, where the slave device is a baseband unit or an acceleration subsystem corresponding to the baseband unit, and the baseband unit and the acceleration subsystem constitute a master-slave device relationship, the baseband data synchronization method includes: Receive a 1pps+tod clock synchronization signal from the master device, obtain the time interval based on the 1pps signal, and generate multiple second data synchronization pointers sequentially according to the time interval based on the tod information; The 1pps signal is input to the slave device clock, sampled under the slave device clock, and when the second data synchronization pointer is sampled, the data to be sent by the master device carrying the first data synchronization pointer is obtained based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer mark the synchronization time information.

6. The baseband data synchronization method according to claim 5, characterized in that, The step of obtaining the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer includes: Based on the second data synchronization pointer, the data to be sent, carrying the first data synchronization pointer, is extracted from the buffer provided by the slave device hardware interface.

7. The baseband data synchronization method according to claim 5, characterized in that, The step of generating multiple second data synchronization pointers sequentially according to the time interval based on the tod information includes: The whole second time is parsed from the TOD information, and multiple second data synchronization pointers are generated sequentially according to the time interval based on the whole second time.

8. A baseband data synchronization system, characterized in that, This includes the baseband unit and acceleration subsystem that constitute the master-slave device relationship; The master device is used to send a 1pps+tod clock synchronization signal to the slave device through the reserved pin of the PCIe slot, collect clock time information of the master device according to the 1pps signal, generate a first data synchronization pointer for the data to be sent according to the clock time information, and send the data to be sent carrying the first data synchronization pointer to the slave device. The slave device is configured to receive a 1pps+tod clock synchronization signal from the master device, obtain a time interval based on the 1pps signal, and generate multiple second data synchronization pointers sequentially according to the time interval based on the tod information. The 1pps signal is used as the input source of the slave device clock, and sampling is performed under the slave device clock. When the second data synchronization pointer is sampled, the slave device obtains the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer point to synchronization time information.

9. A baseband data synchronization system, characterized in that, Applied to a master device, wherein the master device is a baseband unit or the acceleration subsystem corresponding to the baseband unit, the baseband unit and the acceleration subsystem constitute a master-slave device relationship, and the baseband data synchronization system includes: The clock synchronization signal transmission module sends a 1pps+tod clock synchronization signal to the slave device through the reserved pin of the PCIe slot. The synchronization pointer generation module collects clock time information from the master device based on the 1pps signal, and generates a first data synchronization pointer for the data to be sent based on the clock time information. The data sending module sends the data to be sent, carrying the first data synchronization pointer, to the slave device.

10. A baseband data synchronization system, characterized in that, Applied to slave devices, where the slave device is a baseband unit or an acceleration subsystem corresponding to the baseband unit, the baseband unit and the acceleration subsystem constitute a master-slave relationship, and the baseband data synchronization system includes: The clock synchronization signal receiving module receives a 1pps+tod clock synchronization signal from the master device, obtains the time interval based on the 1pps signal, and generates multiple second data synchronization pointers sequentially according to the time interval based on the tod information. The data synchronization acquisition module inputs the 1pps signal into the slave device clock, samples it under the slave device clock, and, when the second data synchronization pointer is acquired, acquires the data to be sent by the master device carrying the first data synchronization pointer based on the second data synchronization pointer. The first data synchronization pointer and the second data synchronization pointer mark the synchronization time information.

11. A baseband data synchronization device, characterized in that, include: processor; A memory in which executable instructions of the processor are stored; The processor is configured to perform the steps of the baseband data synchronization method according to any one of claims 1 to 7 by executing the executable instructions.

12. A computer-readable storage medium for storing a program, characterized in that, When the program is executed by the processor, it implements the steps of the baseband data synchronization method according to any one of claims 1 to 7.

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