Liquid crystal panel

Abstract

Problem: Inhibition of display failure. Solution: A liquid crystal panel (11) includes: an array substrate (21); a counter substrate (20) disposed opposite the array substrate (21); and a liquid crystal layer (22) interposed between the array substrate (21) and the counter substrate (20), the array substrate (21) is provided with: a plurality of pixel electrodes (24) arranged at a gap apart in the plane of the array substrate (21); a common electrode (25) disposed overlapping the plurality of pixel electrodes (24); an insulating film (37) disposed on the upper layer side of the common electrode (25); and an alignment film (33) disposed on the upper layer side of the insulating film (37), the counter substrate (20) is provided with: a light shielding portion (29) that separates between the plurality of pixel electrodes (24); and a spacer (30) disposed overlapping the light shielding portion (29) and protruding from the counter substrate (20) toward the liquid crystal layer (22) side, the alignment film (33) is connected to the common electrode (25) directly or via other components through an opening (37A) provided in the insulating film (37), the opening (37) is disposed on the insulating film (37) at a position that does not overlap the spacer (30) and overlaps the light shielding portion (29).

Description

Technical Field

[0001] The technology disclosed in this specification relates to liquid crystal panels. Background Technology

[0002] As an example of a conventional liquid crystal display device, the liquid crystal display device described in Patent Document 1 is known. The liquid crystal display device described in Patent Document 1 has a common wiring, a gate wiring, a source wiring, and an alignment film in the outer peripheral region of the liquid crystal cell. The alignment film is insulated from the gate wiring and the source wiring via an insulating film. The common wiring has a common potential exposed through an opening formed in the insulating film and is electrically connected to the alignment film. Because a common potential close to the average potential of the cell is supplied to the alignment film, it is possible to prevent poor or degraded image display caused by impurity ions remaining on or inside the alignment film.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2001-330841 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] In the liquid crystal display device described in Patent Document 1, an opening is formed in the insulating film to electrically connect the common potential exposure portion of the common wiring to the alignment film. The alignment film has a first portion that contacts the common potential exposure portion and a second portion stacked on the insulating film, with a step formed between the first portion and the second portion. When such a step is formed in the alignment film, the liquid crystal molecules may become misaligned, potentially leading to display defects caused by misalignment.

[0008] The technology described in this specification is based on the above-mentioned situation and is intended to suppress display defects.

[0009] Solution for solving the problem

[0010] (1) The liquid crystal panel of this embodiment includes an array substrate; a counter substrate disposed opposite to the array substrate; a liquid crystal layer sandwiched between the array substrate and the counter substrate; the array substrate is provided with: a plurality of pixel electrodes arranged at intervals in the plane of the array substrate; a common electrode disposed overlapping the plurality of pixel electrodes; an insulating film disposed on the upper side of the common electrode; and an alignment film disposed on the upper side of the insulating film; at least one of the array substrate and the counter substrate is provided with: a light-shielding portion separating the plurality of pixel electrodes; and a spacer disposed overlapping the light-shielding portion and protruding from at least one of the array substrate and the counter substrate toward the liquid crystal layer; the alignment film is connected to the common electrode directly or via other components through an opening provided in the insulating film; in the insulating film, the opening is disposed at a position that does not overlap with the spacer but overlaps with the light-shielding portion.

[0011] (2) In addition, in the above-mentioned liquid crystal panel, based on (1) above, the array substrate is provided with: a plurality of thin film transistors, which are arranged at intervals in a first direction and a second direction intersecting the first direction; a plurality of first wirings, which extend along the first direction and are arranged at intervals in the second direction; and a plurality of second wirings, which extend along the second direction and intersect the first wirings, and are arranged at intervals in the first direction; a plurality of pixel electrodes are arranged at intervals in the first direction and the second direction, and are connected to a plurality of thin film transistors; the first wirings are connected to a plurality of thin film transistors arranged along the first direction; the second wirings are connected to a plurality of thin film transistors arranged along the second direction; the spacers are arranged overlapping the intersections of the first wirings and the second wirings, and the number of spacers is less than the number of intersections; the openings overlap at least one of the first wirings and the second wirings, and are arranged side by side with the spacers along at least one of the first direction and the second direction, and the number of openings is less than the number of intersections minus the number of spacers.

[0012] (3) In addition, based on (2) above, the number of openings in the above liquid crystal panel is the number of openings minus the number of spacers.

[0013] (4) In addition, based on (2) or (3) above, the liquid crystal panel has one of the multiple spacers arranged along the first direction at each of the multiple intersections, and one of the multiple intersections arranged along the second direction at each of the multiple intersections.

[0014] (5) In addition, based on any one of (2) to (4) above, the light-shielding portion of the above liquid crystal panel has: a first light-shielding portion that extends along the first direction and overlaps with the thin film transistor, the first wiring, the spacer and the opening; and a second light-shielding portion that extends along the second direction, overlaps with the second wiring, and has a width narrower than the first light-shielding portion.

[0015] (6) In addition, based on any one of (1) to (5) above, the pixel electrode of the liquid crystal panel is disposed on the upper side of the insulating film and the lower side of the alignment film.

[0016] (7) In addition, based on (6) above, the pixel electrode of the above liquid crystal panel is composed of a part of the transparent electrode film. In the array substrate, a connection electrode is provided as the other component. The connection electrode is composed of a part of the transparent electrode film that is different from the pixel electrode. It is in contact with the alignment film and connected to the common electrode through the opening.

[0017] (8) In addition, based on (7) above, the above liquid crystal panel has a plurality of pixel electrodes arranged at intervals in a second direction that intersects the first direction and the first direction, and the connecting electrode is located between two pixel electrodes adjacent to one of the first direction and the second direction, and is not arranged between two pixel electrodes adjacent to the other of the first direction and the second direction.

[0018] (9) In addition, based on (7) above, the above-mentioned liquid crystal panel has a plurality of pixel electrodes arranged at intervals in a second direction that intersects the first direction and the first direction, and the connecting electrode has: an electrode body located between two adjacent pixel electrodes in one of the first direction and the second direction, and connected to the common electrode through the opening; and an extension located between two adjacent pixel electrodes in the other of the first direction and the second direction, extending out from the electrode body.

[0019] (10) In addition, based on (9) above, the above-mentioned liquid crystal panel, as the opening, the insulating film includes: a first opening located between two adjacent pixel electrodes in one of the first direction and the second direction; and a second opening located between two adjacent pixel electrodes in one of the first direction and the second direction, disposed at a position that is spaced apart from the first opening in one of the first direction and the second direction. As the electrode body, the connecting electrode includes: a first electrode body that overlaps with the first opening and is connected to the common electrode through the first opening; and a second electrode body that overlaps with the second electrode body and is connected to the common electrode through the second opening. The extension is connected to the first electrode body and the second electrode body.

[0020] (11) In addition, based on (9) or (10) above, the liquid crystal panel is provided with the spacer protruding from the opposing substrate toward the liquid crystal layer side, and the array substrate is provided with: a first planarization film disposed on the lower layer side of the common electrode; and a second planarization film disposed on the lower layer side of the alignment film at the upper layer side of the pixel electrode and the connecting electrode, the first planarization film having a thickness greater than the insulating film and overlapping with the spacer, the common electrode and the pixel electrode, and the second planarization film having a thickness greater than the insulating film and overlapping with the spacer and the extension.

[0021] (12) In addition, based on (9) or (10) above, the common electrode of the above liquid crystal panel includes a plurality of position detection electrodes arranged at intervals in the first direction and the second direction, and a first wiring is provided on the array substrate between two adjacent pixel electrodes in the second direction and extending along the first direction. The first wiring is disposed on a lower layer side than the common electrode and between two adjacent position detection electrodes in the second direction. The extension is located between two adjacent position detection electrodes in the second direction and overlaps with the first wiring.

[0022] (13) In addition, based on (12) above, the above liquid crystal panel has an electrode body that does not overlap with one of the two position detection electrodes adjacent in the second direction, is configured to overlap with the other position detection electrode, and is connected to the other position detection electrode.

[0023] (14) In addition, based on (12) or (13) above, the liquid crystal panel is provided with the spacer protruding from the opposing substrate toward the liquid crystal layer side, and the array substrate is provided with: a first planarization film disposed on the lower layer side of the common electrode; and a second planarization film disposed on the lower layer side of the alignment film at the upper layer side of the pixel electrode and the connecting electrode, the first planarization film having a thickness greater than the insulating film and overlapping with the spacer, the common electrode and the pixel electrode, the second planarization film having a thickness greater than the insulating film and overlapping with the spacer and the extension, and the first wiring being disposed on the lower layer side than the first planarization film.

[0024] (15) In addition, based on any one of (6), (7), (8), (9), (10), (12), and (13) above, the liquid crystal panel has the spacer protruding from the opposing substrate toward the liquid crystal layer side, and a planarization film disposed on the lower layer side of the common electrode is provided on the array substrate. The planarization film has: a first film thickness portion, the film thickness of which is greater than the film thickness of the insulating film, which does not overlap with the spacer, and is disposed overlapping with the common electrode and the pixel electrode; and a second film thickness portion, the film thickness of which is greater than the first film thickness portion, and is disposed overlapping with the spacer.

[0025] (15) In addition, the liquid crystal panel is provided with any one of the spacers in (6) to (10) protruding from the opposing substrate toward the liquid crystal layer side. The array substrate is provided with: a first planarization film disposed on the lower layer side of the common electrode; and a second planarization film disposed on the lower layer side of the alignment film at the upper layer side of the pixel electrode. The thickness of the first planarization film is greater than the thickness of the insulating film, and it overlaps with the spacer, the common electrode and the pixel electrode. The thickness of the second planarization film is greater than the thickness of the insulating film, and it overlaps with the spacer and the extension.

[0026] Invention Effects

[0027] The techniques described in this specification can suppress display defects. Attached Figure Description

[0028] Figure 1 This is a schematic top view of the connection structure of the liquid crystal panel, flexible substrate, and control circuit board constituting the liquid crystal display device according to the first embodiment.

[0029] Figure 2 It is a top view of the pixel arrangement in the display area of ​​the array substrate that makes up the liquid crystal panel.

[0030] Figure 3It's enlarged. Figure 2 A top view of a portion (near the TFT).

[0031] Figure 4 It is a top view of the pixel arrangement in the display area of ​​the opposing substrate that constitutes the liquid crystal panel.

[0032] Figure 5 It's enlarged. Figure 4 A top view of a portion (near the spacer).

[0033] Figure 6 It is in the LCD panel Figure 2 A cross-sectional view of the vi-vi line.

[0034] Figure 7 It is in the LCD panel Figure 3 A cross-sectional view of line vii-vii.

[0035] Figure 8 Is with Figure 2 The top view of the same area is a top view that uses different shading to represent the first and second metal films.

[0036] Figure 9 Is with Figure 3 The top view of the same area is a top view that uses different shading to represent the first and second metal films.

[0037] Figure 10 Is with Figure 2 The top view of the same area is a top view with the second transparent electrode film shown in shade.

[0038] Figure 11 Is with Figure 3 The top view of the same area is a top view of the first transparent electrode film and the second transparent electrode film represented by different shading.

[0039] Figure 12 Is with Figure 2 The top view of the same area is a top view with the first transparent electrode film shown in shade.

[0040] Figure 13 It is in the LCD panel Figure 2 A cross-sectional view of line xiii-xiii.

[0041] Figure 14 This is the sixth step in the method of manufacturing an array substrate, which involves exposing the planarization film to the desired state. Figure 7 Cross-sectional view at the same cutting location.

[0042] Figure 15 This is the sixth step in the method for manufacturing an array substrate, which involves comparing the state of the exposed planarization film after development with... Figure 7 Cross-sectional view at the same cutting location.

[0043] Figure 16 It is near the TFT and the second spacer in the liquid crystal panel according to the second embodiment (with) Figure 7 Cross-sectional view (at the same location).

[0044] Figure 17 This is a top view of the pixel arrangement in the display area of ​​the array substrate according to the third embodiment, and a top view in which the second transparent electrode film is shown in shadow.

[0045] Figure 18 It is near the TFT of the amplification array substrate (and) Figure 11 The top view (within the same range) shows the first transparent electrode film and the second transparent electrode film in different shades.

[0046] Figure 19 It is on the LCD panel Figure 18 Cross-sectional view of the xix-xix line.

[0047] Figure 20 The fourth embodiment relates to the array substrate near the TFT (and) Figure 11 The magnified top view (within the same range) shows the first and second transparent electrode films with different shading.

[0048] Figure 21 It is in the LCD panel Figure 20 A cross-sectional view of the xxi-xxi line.

[0049] Figure 22 It is in the LCD panel Figure 20 Cross-sectional view of line xxii-xxii.

[0050] Figure 23 It is in the LCD panel Figure 20 A cross-sectional view of the xxiii-xxiii line.

[0051] Figure 24 The fifth embodiment relates to the array substrate near the TFT (and) Figure 11 The magnified top view (within the same range) shows the first and second transparent electrode films with different shading.

[0052] Figure 25 This is a top view of the touch electrodes and touch wiring of the liquid crystal panel according to the sixth embodiment.

[0053] Figure 26It is a magnified top view of the area near the boundary of two adjacent touch electrodes in the Y-axis direction on the array substrate, and a top view showing the first transparent electrode film and the second transparent electrode film with different shades.

[0054] Figure 27 It is in the LCD panel Figure 26 A cross-sectional view of the xxvii-xxvii line.

[0055] Figure 28 It is in the LCD panel Figure 26 Cross-sectional view of the xxviii-xxviii line.

[0056] Figure 29 It is near the TFT and the second spacer in the liquid crystal panel according to the seventh embodiment (with) Figure 7 Cross-sectional view (at the same location).

[0057] Figure 30 It is near the pixel electrode and extension in the LCD panel (and) Figure 23 Cross-sectional view (at the same location). Detailed Implementation

[0058] <First Embodiment> According to Figures 1 to 15 The first embodiment will be described. In this embodiment, a liquid crystal display device 10 is exemplified. Furthermore, the X-axis, Y-axis, and Z-axis are shown in a portion of each figure, and the directions of each axis are depicted as shown in the figures.

[0059] Figure 1 This is a schematic top view of the connection structure of the liquid crystal panel 11, flexible substrate 13, and control circuit substrate 14 constituting the liquid crystal display device 10. Figure 1 As shown, the liquid crystal display device 10 includes at least a liquid crystal panel 11 and a backlight device (illumination device) for illuminating the liquid crystal panel 11. In the liquid crystal panel 11, a driver 12 for display driving and a flexible substrate 13 are mounted via an ACF (Anisotropic Conductive Film). The flexible substrate 13 is connected to a control circuit board (signal supply source) 14 that supplies various input signals to the driver 12 from the outside. The backlight device has a known structure, for example, including optical components that convert light from a light source such as an LED into planar light by imparting optical effects upon the light from the light source.

[0060] like Figure 1 As shown, the central portion of the liquid crystal panel 11 is the display area (active area) AA, which can display images. The outer peripheral portion of the liquid crystal panel 11 surrounding the display area AA becomes the non-display area (non-active area) NAA, which appears as a frame (border) when viewed from above. Furthermore, in Figure 1In the diagram, the dashed line represents the outline of the display area AA, and the area outside the dashed line is called the non-display area NAA. The liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. The surface-side (front-side) substrate of the pair of substrates 20 and 21 serves as the opposing substrate (CF substrate) 20. The inner-side (back-side) substrate of the pair of substrates 20 and 21 serves as the array substrate (active matrix substrate) 21. The opposing substrate 20 and the array substrate 21 each have substantially transparent glass substrates 20GS and 21GS, respectively, and various films are laminated on the inner surface of each glass substrate 20GS and 21GS. Additionally, polarizing plates are attached to the outer surface of the two substrates 20 and 21. Furthermore, in the non-display area NAA of the array substrate 21, a pair of gate circuit sections are provided, sandwiching the display area A from both sides in the X-axis direction, but these are not shown in the diagram here. The gate circuit sections are used to supply scan signals to the gate wiring 26 described later, and are monolithically disposed on the array substrate 21.

[0061] Figure 2 This is a top view of the pixel arrangement in the display area AA of the array substrate 21 that constitutes the liquid crystal panel 11. Figure 3 It's enlarged. Figure 2 A top view of a portion (near TFT23). For example... Figure 2 As shown, on the inner surface of the display area AA of the array substrate 21, a plurality of TFTs (thin-film transistors, switching elements) 23 and pixel electrodes 24 are arranged at intervals within the surface of the array substrate 21. The plurality of TFTs 23 and pixel electrodes 24 are arranged in a matrix (row-column) configuration at intervals along the X-axis (first direction) and the Y-axis (second direction) intersecting the X-axis. Around the TFTs 23 and pixel electrodes 24, gate wiring (first wiring, scan wiring) 26 and source wiring (second wiring, signal wiring) 27 are arranged in a surrounding grid pattern. The gate wiring 26 extends in a generally straight line along the X-axis and is arranged at intervals along the Y-axis, sandwiching the pixel electrodes 24. The linewidth of the gate wiring 26 varies depending on its position along the X-axis. The source wiring 27 is repeatedly bent into a sawtooth shape and extends generally along the Y-axis. Multiple source wiring 27 are arranged at intervals along the X-axis, sandwiching the pixel electrodes 24. Gate wiring 26 and source wiring 27 intersect each other, and the number of these intersection portions 21X is the value obtained by multiplying the number of gate wirings 26 by the number of source wirings 27. For example... Figure 3As shown, gate wiring 26 is connected to each gate electrode 23A of a plurality of TFTs 23 arranged along the X-axis direction. Source wiring 27 is connected to each source electrode 23B of a plurality of TFTs 23 arranged along the Y-axis direction. TFTs 23 are driven based on various signals supplied to the gate wiring 26 and source wiring 27 respectively, and with this driving, the supply of potential to the pixel electrode 24 connected to the drain electrode 23C of the TFT 23 is controlled. Each TFT 23 is sandwiched between its own pixel electrode 24 and gate wiring 26 along the Y-axis direction. Furthermore, relative to the source wiring 27 to which it is connected, the plurality of TFTs 23 include a portion located at... Figure 2 and Figure 3 TFT 23 on the right and TFT 23 on the left of the figure. Relative to the source wiring 27, which is the object of connection, located... Figure 2 and Figure 3 Two TFTs 23 on the right and two TFs 23 on the left are arranged along the Y-axis. Furthermore, all TFTs 23 are positioned relative to the pixel electrode 24, which is the object to be connected. Figure 2 and Figure 3 The lower side.

[0062] Figure 4 This is a top view of the pixel arrangement in the display area AA of the array substrate 20 that constitutes the liquid crystal panel 11. Figure 5 It is Figure 4 A magnified top view of a portion (near spacer 30). For example... Figure 4 As shown, a light-shielding portion (inter-pixel light-shielding portion, black matrix) 29 and spacers 30 are provided on the inner surface side of the display area AA of the target substrate 20. The light-shielding portion 29 is made of a light-shielding material (e.g., a material containing pigments such as carbon black in a photosensitive resin material such as acrylic or polyimide) having excellent light-shielding properties, such as an OD (Optical Density) value of 3 or more, preferably 4 or more. The light-shielding portion 29 can block light irradiated from a backlight device, etc. In the display area AA, the planar shape of the light-shielding portion 29 is approximately lattice-shaped, separating adjacent pixel electrodes 24. The light-shielding portion 29 is configured to overlap with at least the gate wiring 26 and the source wiring 27 on the array substrate 21 side when viewed from above. The light-shielding portion 29 has a first light-shielding portion 29A extending along the X-axis direction and a second light-shielding portion 29B extending along the Y-axis direction and intersecting with the first light-shielding portion 29A. The intersection of the first light-shielding portion 29A and the second light-shielding portion 29B is connected to each other. The first light-shielding portion 29A is wider than the second light-shielding portion 29B. The first light-shielding portion 29A is configured to overlap at least with the TFT 23, the gate wiring 26, and the spacer 30 (see reference). Figure 2The second light-shielding portion 29B is narrower than the first light-shielding portion 29A. The second light-shielding portion 29B is configured to overlap with at least the source wiring 27. In the plane of the opposing substrate 20, the area surrounded by the first light-shielding portion 29A and the second light-shielding portion 29B overlaps with most of the pixel electrode 24 and most of the color filter 28, respectively. The above-mentioned area allows the transmitted light from the pixel electrode 24 and the color filter 28 to pass through and exit to the outside of the liquid crystal panel 11. In addition, the light-shielding portion 29 is also provided in the non-display area NAA of the opposing substrate 20, and is configured as a single sheet covering almost the entire area of ​​the non-display area NAA.

[0063] Spacer 30 is used to maintain the spacing between a pair of substrates 20, 21. Figure 4 and Figure 5 As shown, the spacer 30 has a generally circular planar shape. The spacer 30 is arranged overlapping the intersection 21X of the gate wiring 26 and source wiring 27 on the array substrate 21 (see reference). Figure 2The spacers 30 are arranged overlapping the intersections of the first light-shielding portion 29A and the second light-shielding portion 29B constituting the light-shielding portion 29. Therefore, light leakage that may occur near the spacers 30 due to the intersections of the first light-shielding portion 29A and the second light-shielding portion 29B can be appropriately prevented. The number of spacers 30 is less than the number of intersections 21X (intersections of the first light-shielding portion 29A and the second light-shielding portion 29B) between the gate wiring 26 and the source wiring 27. Specifically, one spacer 30 is arranged at each of the plurality of intersections 21X arranged along the X-axis direction. One spacer 30 is also arranged at each of the plurality of intersections 21X arranged along the Y-axis direction. Thus, the plurality of spacers 30 are arranged in a staggered (houndstooth) planar configuration within the surface of the opposing substrate 20. Therefore, the number of spacers 30 is approximately half the total number of intersections 21X of the gate wiring 26 and the source wiring 27. This avoids uneven distribution of multiple spacers 30 within the surfaces of the array substrate 21 and the opposing substrate 20, thus maintaining a more stable spacing between the array substrate 21 and the opposing substrate 20. The spacers 30 include two types: a first spacer (main spacer) 30a and a second spacer (sub-spacer) 30β. Hereinafter, when distinguishing spacers 30, the first spacer will be labeled "α" and the second spacer will be labeled "β"; otherwise, no label will be used. The diameter of the first spacer 30a is smaller than that of the second spacer 303. The number of first spacers 30a is less than the number of second spacers 303. These differences between the first spacers 30a and the second spacers 303 will be explained later. Furthermore, the light-shielding portion 29 has a third light-shielding portion 29C connected to the intersection of the first light-shielding portion 29A and the second light-shielding portion 29B. The third light-shielding portion 29C is generally fan-shaped and concentric with the spacer 30. Four third light-shielding portions 29C are connected at the intersection of the first light-shielding portion 29A and the second light-shielding portion 29B. These four third light-shielding portions 29C are generally circular, mimicking the planar shape of the spacer 30, and their diameter is larger than that of the spacer 30. Most of the third light-shielding portions 29C do not overlap with the spacer 30, but a portion does. Light leakage near the spacer 30 caused by these third light-shielding portions 29C can be more effectively prevented. The third light-shielding portion 29C includes one third light-shielding portion 29Cα that overlaps with the first spacer 30α and another third light-shielding portion 29Cβ that overlaps with the second spacer 30β. The diameter of one third light-shielding portion 29Cα is larger than that of the other third light-shielding portion 29Cβ. Furthermore, in Figure 2 and Figure 3 In the middle, the light-shielding part 29 and the isolation element 30 are illustrated by thick double-dotted lines.

[0064] Figure 6This is a cross-sectional view near the center of the pixel electrode 24 (pixel PX) in the liquid crystal panel 11. Figure 2 (The cross-sectional diagram of the vi-vi line). For example... Figure 6 As shown, the liquid crystal panel 11 has a liquid crystal layer (dielectric layer) 22 disposed between a pair of substrates 20 and 21 and containing liquid crystal molecules, which are substances whose optical properties change with the application of an electric field. In the display area AA on the inner surface side of the opposing substrate 20 constituting the liquid crystal panel 11, a three-color filter 28 displaying blue (B), green (G), and red (R) is provided. A plurality of filters 28 displaying different colors are arranged adjacent to each other in the extending direction (X-axis direction) of the gate wiring 26. The plurality of filters 28 displaying different colors extend along the extending direction (approximately Y-axis direction) of the source wiring 27. Thus, the plurality of filters 28 displaying different colors are arranged in a stripe pattern as a whole. These filters 28 are configured to overlap with the pixel electrodes 24 on the array substrate 21 side when viewed from above. The boundaries (color boundaries) of the plurality of filters 28 displaying different colors overlap with the source wiring 27. In this liquid crystal panel 11, R, G, and B color filters 28 arranged along the X-axis and three pixel electrodes 24 opposite each color filter 28 constitute three-color pixels PX. Furthermore, in this liquid crystal panel 11, the R, G, and B three-color pixels PX adjacent along the X-axis constitute a display pixel capable of displaying a specified grayscale. The Y-axis spacing of the pixels PX is approximately three times the X-axis spacing. Light-shielding portions 29 are arranged to separate adjacent color filters 28. Specifically, a first light-shielding portion 29A separates two adjacent color filters 28 in the Y-axis direction. A second light-shielding portion 29B separates two adjacent color filters 28 in the X-axis direction. On the upper layer side of the color filters 28 (liquid crystal layer 22 side), an outer coating film 31 is provided, which is arranged in a flat surface covering approximately the entire area of ​​the opposing substrate 20, for planarization purposes.

[0065] Next, refer to Figure 6 The pixel electrode 24 and common electrode 25 provided on the array substrate 21 will be described. For example... Figure 6 As shown, on the inner surface side of the display area AA of the array substrate 21, a common electrode 25 is formed on a layer lower than the pixel electrodes 24, overlapping all the pixel electrodes 24. The common electrode 25 extends over approximately the entire area of ​​the display area AA. The common electrode 25 is connected to a common wiring, through which a common potential signal (reference potential signal) is supplied. A flexible substrate 13 is connected to the common wiring, and a common potential signal (reference potential signal) is supplied from the control circuit substrate 14. Figure 1When the pixel electrode 24 is charged as driven by the TFT 23, a potential difference is generated between the overlapping pixel electrode 24 and the common electrode 25. Therefore, an edge electric field (tilted electric field) is generated between the pixel electrode 24 and the common electrode 25, in addition to the component along the surface of the array substrate 21, which includes a component relative to the normal direction of the surface of the array substrate 21. By utilizing this edge electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled. That is, the operating mode of the liquid crystal panel 11 according to this embodiment is set to FFS (Fringe Field Switching) mode.

[0066] like Figure 6 As shown, alignment films 32 and 33 for aligning the liquid crystal molecules contained in the liquid crystal layer 22 are respectively provided on the innermost surfaces of the opposing substrate 20 and the array substrate 21. Specifically, on the opposing substrate 20, an alignment film 32 is provided on the upper side (liquid crystal layer 22 side) of the outer coating film 31. The alignment film 32 is formed as a single surface on the innermost surface of the opposing substrate 20. An alignment film 33 is provided on the upper side of the pixel electrode 24 in the array substrate 21. The alignment film 33 is formed as a single surface on the innermost layer of the array substrate 21. The alignment films 32 and 33 are configured as photoalignment films capable of imparting alignment constraint forces to the liquid crystal molecules through photoalignment treatment on their surfaces.

[0067] Here, refer to Figure 6 and Figure 7 Various films that have been stacked on the inner surface of the array substrate 21 will be described. Figure 7 This is a cross-sectional view of TFT 23 and the vicinity of the second separator 30β in the liquid crystal panel 11. Figure 3 (Cross-section view of line vii-vii). For example... Figure 7As shown, on the array substrate 21, starting from the lower layer side (glass substrate 21GS side), a first metal film, a gate insulating film 34, a semiconductor film, a second metal film, a first interlayer insulating film 35, a planarization film 36, a first transparent electrode film, a second interlayer insulating film (insulating film) 37, a second transparent electrode film, and an alignment film 33 are sequentially stacked. The first metal film and the second metal film are either single-layer films made of a metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or multilayer films or alloys made of different types of metal materials, and have conductivity and light-shielding properties. The first metal film constitutes the gate wiring 26, the gate 23A of the TFT 23, etc. The second metal film constitutes the source wiring 27, the source 23B and drain 23C of the TFT 23, etc. The semiconductor film is made of a thin film using materials such as oxide semiconductors and amorphous silicon, and constitutes the channel portion 23D of the TFT 23, etc. The first and second transparent electrode films are made of transparent electrode materials (e.g., ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), etc.). The thickness of the first and second transparent electrode films is, for example, set to approximately 0.05 μm to 0.1 μm. The first transparent electrode film constitutes the common electrode 25, etc. The second transparent electrode film constitutes the pixel electrode 24, etc. The alignment film 33 is as described above.

[0068] The gate insulating film 34, the first interlayer insulating film 35, and the second interlayer insulating film 37 are respectively composed of inorganic materials such as silicon nitride (SiNx) and silicon oxide (SiO2). The thickness of the gate insulating film 34, the first interlayer insulating film 35, and the second interlayer insulating film 37 is, for example, about 0.2 μm to 0.7 μm, which is slightly larger than the thickness of the first transparent electrode film and the second transparent electrode film. The planarization film 36 is, for example, composed of organic materials such as PMMA (acrylic resin) and has photosensitivity. The thickness of the planarization film 36 is, for example, about 1 μm to 3 μm, which is much larger than the thickness of the gate insulating film 34, the first interlayer insulating film 35, and the second interlayer insulating film 37. The planarization film 36 is used to planarize the inner surface (the surface on the side of the liquid crystal layer 22) of the array substrate 21. The gate insulating film 34 keeps the lower-side first metal film, the upper-side semiconductor film, and the second metal film in an insulating state. For example, the intersection 21X of the gate wiring 26 formed by the first metal film and the source wiring 27 formed by the second metal film is kept insulated by the gate insulating film 34. Additionally, the overlapping portion of the gate 23A formed by the first metal film and the channel portion 23D formed by the semiconductor film is kept insulated by the gate insulating film 34. The first interlayer insulating film 35 and the planarization film 36 keep the lower-side semiconductor film and the second metal film, as well as the upper-side first transparent electrode film, insulated. For example, the overlapping portion of the source wiring 27 formed by the second metal film and the common electrode 25 formed by the first transparent electrode film is kept insulated by the first interlayer insulating film 35 and the planarization film 36. The second interlayer insulating film 37 keeps the lower-side first transparent electrode film and the upper-side second transparent electrode film insulated. For example, the overlapping portion of the common electrode 25 formed by the first transparent electrode film and the pixel electrode 24 formed by the second transparent electrode film is kept insulated by the second interlayer insulating film 37. A first contact hole 21CH1 is formed together in the first interlayer insulating film 35, the planarization film 36, and the second interlayer insulating film 37. The first contact hole 21CH1 is disposed at a position overlapping with a portion (contact portion 24B) of the drain electrode 23C made of the second metal film and the pixel electrode 24 made of the second transparent electrode film in the first interlayer insulating film 35, the planarization film 36, and the second interlayer insulating film 37. The drain electrode 23C and the pixel electrode 24 are connected through the first contact hole 21CH1.

[0069] Next, refer to Figures 7 to 9 The TFT23 will be explained. Figure 8 Is with Figure 2 The top view of the same area is a top view that uses different shading to represent the first metal film (gate 23A, etc.) and the second metal film (source 23B and drain 23C, etc.). Figure 9 Is with Figure 3Top views of the same area are top views that use different shading to represent the first metal film (gate 23A, etc.) and the second metal film (source 23B and drain 23C, etc.). For example... Figures 7 to 9 As shown, TFT 23 has a gate 23A. Gate 23A is formed by a portion of gate wiring 26 (near the intersection 21X with source wiring 27). Gate 23A is formed by locally widening gate wiring 26. Gate 23A drives TFT 23 based on a scan signal supplied to gate wiring 26. TFT 23 is positioned relative to the source wiring 27 to which it is connected. Figure 8 and Figure 9 As shown on the right side. TFT 23 has a source electrode 23B. The source electrode 23B is formed by a portion of the source wiring 27 (the intersection 21X with the gate wiring 26) that is connected to the source wiring. The source electrode 23B is formed by locally widening the source wiring 27. The source electrode 23B is disposed at one end of TFT 23 in the X-axis direction. Figure 8 and Figure 9 (Shown at the left end). The entire area of ​​the source 23B overlaps with a portion of the gate 23A and is connected to the channel portion 23D. TFT 23 has a drain 23C. The drain 23C is disposed at a position spaced apart from the source 23B, i.e., at the other end of the TFT 23 in the X-axis direction (…). Figure 8 and Figure 9 (As shown on the right). The drain 23C is configured to partially overlap with the gate 23A, and the overlapping portion with the gate 23A is connected to the channel portion 23D. The center portion of the drain 23C is connected to the pixel electrode 24. Furthermore, the end of the drain 23C opposite to the connection portion with the channel portion 23D overlaps with the widened portion 26A of the gate wiring 26. The widened portion 26A has a width equal to or less than that of the gate 23A. This widened portion 26A is provided so that even if the drain 23C is misaligned relative to the gate wiring 26 in the X-axis direction during the fabrication of the array substrate 21, the capacitance between the gate wiring 26 and the drain 23C (i.e., the pixel electrode 24) will not change.

[0070] like Figures 7 to 9 As shown, TFT 23 has a channel portion 23D. The channel portion 23D overlaps with the gate 23A across the gate insulating film 34. The channel portion 23D overlaps with a portion of the gate 23A and extends along the X-axis direction. One end of the channel portion 23D is connected to the source 23B. The other end of the channel portion 23D is connected to the drain 23C. Then, when TFT 23 becomes on based on the scan signal supplied to the gate 23A, the image signal (data signal) supplied to the source wiring 27 is supplied from the source 23B to the drain 23C via the channel portion 23D. As a result, the pixel electrode 24 is charged to a potential based on the image signal.

[0071] Reference Figure 7 , Figure 10 as well as Figure 11 The pixel electrode 24 will be described. Figure 12 Is with Figure 2 The top view of the same area is a top view in which the second transparent electrode film (pixel electrode 24, etc.) is shown in shade. Figure 11 Is with Figure 3 The top views of the same area are top views showing the first transparent electrode film (common electrode 25, etc.) and the second transparent electrode film with different shading. For example... Figure 10 as well as Figure 11 As shown, the pixel electrode 24 has a generally square pixel electrode body 24A with a longitudinally elongated planar shape. The long side of the pixel electrode body 24A extends along the source wiring 27. Specifically, the two side edges of the long side of the pixel electrode body 24A are slightly inclined relative to the Y-axis direction. Multiple (in) Figure 10 as well as Figure 11 There are two slits 24A1. Furthermore, the specific number, shape, and formation range of the slits 24A1 can be appropriately changed beyond what is shown in the illustration. Additionally, the pixel electrode 24 has a contact portion 24B that protrudes to one side from the pixel electrode body 24A along the Y-axis direction. The contact portion 24B protrudes from the pixel electrode body 24A towards... Figure 10 and Figure 11 The lower part protrudes and is configured to overlap with a portion of the drain 23C. For example... Figure 7 As shown, the contact portion 24B is connected to the drain electrode 23C through the first contact hole 21CH1.

[0072] Reference Figure 7 , Figure 11 as well as Figure 12 The common electrode 25 will be described. Figure 12 Is with Figure 2 The top view of the same area is a top view in which the first transparent electrode film (common electrode 25, etc.) is shaded. For example... Figure 11 and Figure 12 As shown, the common electrode 25 is arranged as a single sheet covering almost the entire display area AA. Openings 25A are partially formed in the common electrode 25. Multiple openings 25A are formed at locations overlapping with the multiple TFTs 23 (particularly the drain 23C and the first contact hole 21CH1) in the common electrode 25. The multiple openings 25A are arranged in a matrix in the common electrode 25, spaced apart in the X-axis and Y-axis directions. Figure 7 As shown, the common electrode 25 avoids short-circuiting with the pixel electrode 24 through the opening 25A.

[0073] Reference Figure 7 and Figure 13Explain the spacer 30 of the opposing substrate 20. Figure 13 This is a cross-sectional view of TFT 23 and the vicinity of the first spacer 30a in the liquid crystal panel 11. Figure 2 (Cross-sectional view of line xiii-xiii). For example... Figure 7 and Figure 13 As shown, the spacer 30 protrudes from the opposing substrate 20 toward the array substrate 21 (the liquid crystal layer 22 side described later) along the Z-axis direction (the normal direction of the surface of the opposing substrate 20). Specifically, the spacer 30 is made of resin material and protrudes from the surface of the outer coating film 31 toward the liquid crystal layer 22 side along the Z-axis in the display area AA of the opposing substrate 20, with its protruding front surface facing the array substrate 21. The spacer 30 is generally a slightly tapered cylinder (see reference). Figure 2 as well as Figure 3 ).like Figure 13 As shown, the protrusion dimension of the first spacer 30a from the opposing substrate 20 is larger than that of the second spacer 30β. The protruding front end surface of the first spacer 30a contacts the alignment film 33 on the array substrate 21 side. Thus, the pair of substrates 20, 21 maintain a spacing (cell gap) equal to the thickness of the liquid crystal layer 22. In contrast, as... Figure 7 As shown, the protrusion dimension of the second spacer 30β from the opposing substrate 20 is smaller than that of the first spacer 30a. A gap exists between the protruding tip surface of the second spacer 30β and the alignment film 33 on the array substrate 21 side. When an external force, such as pressing inward, is applied to either of the pair of substrates 20 and 21, the amount of deflection (deformation) of either substrate 20 or 21 is allowed to correspond to the gap between the second spacer 30β disposed on the opposing substrate 20 and the alignment film 33 on the array substrate 21 side. However, when either of the pair of substrates 20 or 21 slightly deflects, the protruding tip surface of the second spacer 30β contacts the alignment film 33 on the array substrate 21 side. Therefore, either of the pair of substrates 20 or 21 is further restricted from deflection. In this way, the thickness of the liquid crystal layer 22 can be maintained using the first spacer 30a and the second spacer 30β.

[0074] Near the spacer 30 with the structure described above, there is a concern that the liquid crystal molecules contained in the liquid crystal layer 22 may become misaligned, resulting in display defects caused by misalignment. In this regard, the spacer 30 is configured to overlap with the light-shielding portion 29. Specifically, the intersection of the first light-shielding portion 29A and the second light-shielding portion 29B of the light-shielding portion 29 overlaps with the spacer 30. Furthermore, the third light-shielding portion 29C of the light-shielding portion 29 is configured to surround the spacer 30. By blocking light near the spacer 30 with such light-shielding portions 29, it is difficult to observe display defects caused by the spacer 30.

[0075] Reference Figure 7 and Figure 13This describes the planarization film 36 on the array substrate 21. For example... Figure 7 and Figure 13 As shown, the planarization film 36 has a first thickness portion 36A and a second thickness portion 36B, which is thicker than the first thickness portion 36A. The thickness of the first thickness portion 36A is greater than the thickness of the second interlayer insulating film 37, but less than the thickness of the second thickness portion 36B. The first thickness portion 36A occupies most of the planarization film 36, except for the portions that overlap with the plurality of spacers 30. The first thickness portion 36A does not overlap with the spacers 30, but is disposed overlapping with the common electrode 25 and the pixel electrode 24. The thickness of the second thickness portion 36B is greater than that of the first thickness portion 36A. Therefore, the portion of the alignment film 33 that overlaps with the second thickness portion 36B is configured to protrude toward the liquid crystal layer 22 in the Z-axis direction compared to the portion that overlaps with the first thickness portion 36A. A plurality of second thickness portions 36B are arranged at intervals in the X-axis and Y-axis directions. The plurality of second thickness portions 36B are disposed overlapping with the plurality of spacers 30. Thus, the second film thickness portions 36B are arranged in an interlaced planar configuration within the surface of the array substrate 21, suitable for the planar configuration of the spacers 30. Therefore, the number of second film thickness portions 36B is the same as the number of spacers 30. The second film thickness portions 36B are formed by the portion of the planarization film 36 that overlaps with the spacers 30, and therefore, their planar shape is approximately circular. The protruding base end portion (the portion with the largest diameter) of the spacer 30 in the second film thickness portion 36B is equal to its size (diameter) when viewed in planar view. Therefore, the second film thickness portions 36B can receive the protruding front end surface of the spacers 30 across almost the entire area via the alignment film 33. This can limit the deflection of the array substrate 21 or the opposing substrate 20. In addition, the second film thickness portions 36B are arranged overlapping with the intersection 21X of the gate wiring 26 and the source wiring 27.

[0076] like Figure 7 As shown, in the array substrate 21 of this embodiment, an opening 37A is provided on the second interlayer insulating film 37 located on the lower layer side of the alignment film 33 on the upper layer side of the common electrode 25. The alignment film 33 is connected to the common electrode 25 on the lower layer side through the opening 37A of the second interlayer insulating film 37. As a result, impurity ions, i.e., charges, are difficult to remain on the surface or inside the alignment film 33, thus making it difficult to produce display defects such as afterimages, burn-in, and flicker caused by residual charges in the alignment film 33. Furthermore, "the alignment film 33 is connected to the common electrode 25 on the lower layer side through the opening 37A of the second interlayer insulating film 37" means that, viewed from the Z-axis direction, charge movement can occur between the alignment film 33 and the common electrode 25 in the area overlapping with the opening 37A of the second interlayer insulating film 37. Therefore, "the alignment film 33 is connected to the common electrode 25 on the lower layer side through the opening 37A of the second interlayer insulating film 37" includes not only... Figure 7The structure shown includes a direct contact between the alignment film 33 and the common electrode 25 through the opening 37A of the second interlayer insulating film 37. It also includes a structure, as detailed in the third embodiment below, where the alignment film 33 is indirectly connected to the common electrode 25 through the opening 37A of the second interlayer insulating film 37 and via other components (connecting electrode 40). Furthermore, the "other components" referred to here are conductive components. However, the second interlayer insulating film 37 in this embodiment is disposed between the pixel electrode 24 on the upper side and the common electrode 25 on the lower side in the Z-axis direction. Therefore, the thickness of the second interlayer insulating film 37 is much smaller than that of a typical planarization film, which is suitable for maintaining a sufficiently high intensity of the electric field generated between the pixel electrode 24 and the common electrode 25. On the other hand, the thickness of the second interlayer insulating film 37 is generally larger than the thickness of the pixel electrode 24 and the common electrode 25. Here, a step is formed in the alignment film 33 between the portion that contacts the common electrode 25 through the opening 37A of the second interlayer insulating film 37 and the portion disposed on the upper side of the second interlayer insulating film 37. The size of this step depends on the film thickness of the second interlayer insulating film 37. Since the film thickness of the second interlayer insulating film 37 is set as described above, alignment defects in the liquid crystal molecules contained in the liquid crystal layer 22 caused by the aforementioned step near the opening 37A are unavoidable to some extent. That is, there is concern about display defects caused by alignment defects of liquid crystal molecules occurring near the opening 37A of the second interlayer insulating film 37.

[0077] Therefore, as Figure 5 , Figure 7 and Figure 13As shown, in the second interlayer insulating film 37 according to this embodiment, the opening 37A is disposed at a position that does not overlap with the spacer 30 but overlaps with the light-shielding portion 29 of the opposing substrate 20. Therefore, even if misalignment of liquid crystal molecules occurs near the opening 37A of the second interlayer insulating film 37 due to the steps of the alignment film 33, the light-shielding portion 29 can block light transmitted near the opening 37A. This makes display defects such as bright spots (light leakage) caused by misalignment of liquid crystal molecules near the opening 37A less visually noticeable. Furthermore, since the opening 37A of the second interlayer insulating film 37 is disposed at a position that does not overlap with the spacer 30, the flatness of the surface of the array substrate 21 opposite to the spacer 30 is ensured. This sufficiently ensures the contact area between the array substrate 21 and the alignment film 33 with the spacer 30, thus fully utilizing the function of the spacer 30 (cell thickness retention function). Moreover, the load from the spacer 30 is less likely to act on the portion of the alignment film 33 located near the opening 37A of the second interlayer insulating film 37. Therefore, it is difficult to cause cutting on the alignment film 33 caused by interference from the spacer 30. As a result, the alignment film 33 can be prevented from being cut away near the opening 37A of the second interlayer insulating film 37, and thus, the electrical connection between the alignment film 33 and the common electrode 25 can be easily maintained through the opening 37A of the second interlayer insulating film 37. As a result, it is less likely for charge to remain on the alignment film 33.

[0078] Figure 11 and Figure 12 In the diagram, the opening 37A of the second interlayer insulating film 37 is illustrated by a double-dotted line. (See diagram below.) Figure 11 and Figure 12 As shown, in the second interlayer insulating film 37, the opening 37A is located between two adjacent pixel electrodes 24 in the X-axis direction, but not between two adjacent pixel electrodes 24 in the Y-axis direction. The opening 37A of the second interlayer insulating film 37 overlaps with the source wiring 27. Specifically, the second interlayer insulating film 37 is configured such that the opening 37A overlaps with the portion of the source wiring 27 widened by the source electrode 23B, and is adjacent to the source electrode 23B in the X-axis direction. The second interlayer insulating film 37 is formed such that the opening 37A is located relative to the intersection 21X of the gate wiring 26 and the source wiring 27. Figure 11 and Figure 12On the upper side, i.e., in the Y-axis direction, the TFT 23 side, which is the connection object of the gate wiring 26 and source wiring 27 forming the intersection 21X, is arranged adjacent to each other. In the second interlayer insulating film 37, the opening 37A is arranged side by side with the spacer 30 along the X-axis direction. Specifically, the second interlayer insulating film 37 is arranged such that the straight line connecting the center of the opening 37A in top view and the center of the spacer 30 in top view is approximately parallel to the X-axis direction. The number of openings 37A in the second interlayer insulating film 37 is the number obtained by subtracting the number of spacers 30 from the number of intersections 21X of the gate wiring 26 and source wiring 27 (approximately half of the total number of intersections 21X of the gate wiring 26 and source wiring 27). That is, the spacer 30 and the opening 37A of the second interlayer insulating film 37 are arranged without omission near the intersection 21X of the gate wiring 26 and source wiring 27, and there are no intersections 21X without spacers 30 or openings 37A. Thus, it can be said that the spacer 30 and the openings 37A of the second interlayer insulating film 37 are complementaryly arranged within the surface of the array substrate 21. This ensures that the number of spacers 30 and openings 37A in the second interlayer insulating film 37 are adequately provided. More specifically, in the second interlayer insulating film 37, one opening 37A is provided at each of the plurality of intersections 21X arranged along the X-axis direction. Similarly, one opening 37A is provided at each of the plurality of intersections 21X arranged along the Y-axis direction. Thus, the plurality of openings 37A in the second interlayer insulating film 37 are arranged in an alternating planar configuration within the surface of the array substrate 21. This avoids uneven distribution of the plurality of openings 37A within the surface of the array substrate 21, thereby completely removing the charge accumulated in the alignment film 33.

[0079] In addition, such as Figure 5 , Figure 11 and Figure 12As shown, the first light-shielding portion 29A of the light-shielding portion 29, in addition to the TFT 23, gate wiring 26, and spacer 30, is also disposed overlapping with the opening 37A of the second interlayer insulating film 37. Specifically, the first light-shielding portion 29A extending along the X-axis direction is disposed overlapping with a plurality of spacers 30 and openings 37A arranged alternately along the X-axis direction. The first light-shielding portion 29A overlapping with the plurality of openings 37A is wider than the second light-shielding portion 29B. Therefore, even if the openings 37A are provided on the second interlayer insulating film 37 and the openings 37A experience a positional shift in the Y-axis direction, the reliability of maintaining the overlapping relationship between the openings 37A and the first light-shielding portion 29A is increased. In this embodiment, the opening 37A of the second interlayer insulating film 37 is disposed overlapping with the intersection of the first light-shielding portion 29A and the second light-shielding portion 29B. Therefore, it can be said that the opening 37A of the second interlayer insulating film 37 is disposed overlapping with the second light-shielding portion 29B in addition to the first light-shielding portion 29A.

[0080] This embodiment describes the structure described above. Next, a method for manufacturing the array substrate 21 constituting the liquid crystal panel 11 will be described. The method for manufacturing the array substrate 21 in this embodiment includes at least the following steps: a first step of forming a first metal film and patterning it; a second step of forming a gate insulating film 34; a third step of forming a semiconductor film and patterning it; a fourth step of forming a second metal film and patterning it; a fifth step of forming a first interlayer insulating film 35; a sixth step of forming a planarization film 36 and patterning it; a seventh step of forming a first transparent electrode film and patterning it; an eighth step of forming a second interlayer insulating film 37 and patterning it; a ninth step of forming a second transparent electrode film and patterning it; and a tenth step of forming an alignment film 33 and performing light alignment processing. Hereinafter, using… Figure 14 and Figure 15 The sixth process will be explained.

[0081] Figure 14 This is the sixth step in the manufacturing method of the array substrate 21, which involves exposing the planarization film 36 to the state of the film. Figure 7 Cross-sectional view at the same cutting location. Figure 15 This is the sixth step in the manufacturing method of the array substrate 21, which involves comparing the state of the exposed planarization film 36 after development with... Figure 7 Cross-sectional view at the same cutting position. In the sixth process, as... Figure 14 As shown, a planarization film 36 is formed on the upper side of the first interlayer insulating film 35. The planarization film 36 is made of a positive photosensitive material. Therefore, the planarization film 36 is not laminated on the upper side to form a resist film, but is exposed using an exposure apparatus and a photomask 10P.

[0082] Here, the photomask 10P will be described. The photomask 10P used here is a so-called halftone mask. The photomask 10P includes: a transparent substrate 10P1 with sufficiently high light transmittance; a light-shielding film 10P2 formed on the surface of the substrate 10P1; and a semi-transparent film 10P3 formed on the surface of the substrate 10P1 and partially laminated on the light-shielding film 10P2. The light-shielding film 10P2 blocks exposure light from the light source of the exposure apparatus, and the transmittance of the exposure light is almost 0%. The semi-transparent film 10P3 allows the exposure light from the light source of the exposure apparatus to pass through at a specified transmittance. The transmittance of the exposure light of the semi-transparent film 10P3 is higher than that of the light-shielding film 10P2, for example, about 10% to 70%. The light-shielding film 10P2 and the semi-transparent film 10P3 are patterned in the surface of the substrate 10P1 in a specified distribution pattern. The light-shielding film 10P2 is selectively disposed at a position overlapping with a predetermined portion of the second film thickness 36B in the planarization film 36. The semi-permeable film 10P3 is selectively disposed at least at a position in the planarization film 36 overlapping with a predetermined portion of the first film thickness 36A. In this embodiment, the semi-permeable film 10P3 is also disposed at a position overlapping with the light-shielding film 10P2. That is, the semi-permeable film 10P3 is disposed at a position overlapping with a portion other than the predetermined portion of the first contact hole 21CH1 in the planarization film 36. The photomask 10P has: a light-shielding region 10LSA, which blocks exposure light based on the pattern of the light-shielding film 10P2 and the semi-permeable film 10P3; a transmittance region 10TA, which allows exposure light to pass through; and a semi-permeable region 10HTA, which allows exposure light to pass through partially. The light-shielding region 10LSA is formed within the same area as the light-shielding film 10P2. The non-forming range of the transmissive region 10TA and the non-forming range of the light-shielding film 10P2 coincide with the non-forming range of the semi-permeable film 10P3. The transmissive region 10TA is configured to overlap with the predetermined portion of the formation of the first contact hole 21CH1 in the planarization film 36. The non-forming range of the semi-permeable region 10HTA and the forming range of the light-shielding film 10P2 coincide with the forming range of the semi-permeable film 10P3. Furthermore, in Figure 14 In the image, the exposure light that illuminates the planarization film 36 is indicated by a downward arrow.

[0083] In the sixth step, if the exposure light emitted from the light source of the exposure apparatus irradiates the planarization film 36 through the photomask 10P configured as described above, selective exposure of the planarization film 36 is performed. Specifically, the portion of the planarization film 36 overlapping with the transmittance region 10TA of the photomask 10P is exposed throughout its entire depth. In the portion of the planarization film 36 overlapping with the semi-transparent region 10HTA of the photomask 10P, the upper surface side portion (upper layer side portion) is selectively exposed, while the bottom surface side portion (lower layer side portion) is selectively not exposed. The portion of the planarization film 36 overlapping with the light-shielding region 10LSA of the photomask 10P is not exposed. If the planarization film 36, which has been selectively exposed in this way, is developed, then... Figure 15 As shown, the exposed portions of the planarization film 36 are selectively removed based on the exposure amount. Specifically, the portion of the planarization film 36 overlapping with the transmittance region 10TA of the photomask 10P is removed throughout its depth, becoming the first contact hole 21CH1. In the portion of the planarization film 36 overlapping with the semi-transparent region 10HTA of the photomask 10P, the upper side portion is selectively removed, while the lower side portion is selectively retained, becoming the first film thickness portion 36A. The portion of the planarization film 36 overlapping with the light-shielding region 10LSA of the photomask 10P remains throughout its depth, becoming the second film thickness portion 36B, which has a greater thickness than the first film thickness portion 36A. The planarization film 36 is patterned using the photomask 10P.

[0084] Furthermore, in order to form the first contact hole 21CH1 in the first interlayer insulating film 35, the patterned planarization film 36 described above can be used as a mask to etch the first interlayer insulating film 35. Alternatively, in the eighth step, while etching the second interlayer insulating film 37 to form the opening 37A and the first contact hole 21CH1, the first interlayer insulating film 35 can be etched to form the first contact hole 21CH1 of the first interlayer insulating film 35. Using the latter method, in addition to requiring fewer etching passes, the drain electrode 23C can be protected by the first interlayer insulating film 35 at least during the seventh step.

[0085] As described above, the liquid crystal panel 11 of this embodiment includes an array substrate 21, a counter substrate 20 disposed opposite to the array substrate 21, and a liquid crystal layer 22 sandwiched between the array substrate 21 and the counter substrate 20. The array substrate 21 is provided with a plurality of pixel electrodes 24 spaced apart in-plane, a common electrode 25 overlapping the plurality of pixel electrodes 24, a second interlayer insulating film (insulating film) 37 disposed on the upper side of the common electrode 25, and a second interlayer insulating film 37 disposed on the upper side of the second interlayer insulating film 37. The alignment film 33 has a light-shielding portion 29 separating multiple pixel electrodes 24 on at least one of the array substrate 21 and the opposing substrate 20, and an isolator 30 that overlaps with the light-shielding portion 29 and protrudes from the liquid crystal layer 22 side in at least one direction of the array substrate 21 and the opposing substrate 20. The alignment film 33 is directly connected to the common electrode 25 through an opening 37A provided in the second interlayer insulating film 37 or other components. In the second interlayer insulating film 37, the opening 37 is disposed at a position that does not overlap with the isolator 30 but overlaps with the light-shielding portion 29.

[0086] According to this structure, the alignment state of the liquid crystal layer 22 is controlled by the electric field generated between the multiple overlapping pixel electrodes 24 and the common electrode 25. This allows for image display. Furthermore, when an external force is applied to the array substrate 21 or the opposing substrate 20, the deflection of the array substrate 21 or the opposing substrate 20 can be limited by the spacer 30. This maintains the spacing between the array substrate 21 and the opposing substrate 20, i.e., the thickness of the liquid crystal layer 22. The alignment film 33 is connected to the common electrode 25 directly or via other components through the opening 37A of the second interlayer insulating film 37, making it difficult for residual charge to remain in the alignment film 33. This reduces the likelihood of display defects caused by residual charge in the alignment film 33.

[0087] Here, a step is created between the portion of the alignment film 33 that is directly or via other components connected to the common electrode 25 through the opening 37A of the second interlayer insulating film 37 and the portion disposed on the upper side of the second interlayer insulating film 37. Therefore, there is a concern that near the opening 37A of the second interlayer insulating film 37, the liquid crystal molecules contained in the liquid crystal layer 22 may experience misalignment, resulting in display defects caused by misalignment.

[0088] Regarding this, since the second interlayer insulating film 37 is disposed at the position where the opening 37A overlaps with the light-shielding portion 29, even if misalignment occurs in the liquid crystal molecules near the opening 37A, it is difficult to visually identify display defects caused by misalignment. Furthermore, since the opening 37A of the second interlayer insulating film 37 is positioned where it does not overlap with the spacer 30, the flatness of the opposing surfaces of the array substrate 21 and the opposing substrate 20 opposite to the spacer 30 is ensured. This sufficiently ensures the contact area of ​​either the array substrate 21 or the opposing substrate 20 with respect to the spacer 30, thus fully utilizing the function of the spacer 30. Moreover, since the load from the spacer 30 is less likely to act on the portion of the alignment film 33 located near the opening 37A of the second interlayer insulating film 37, cutting caused by the spacer 30 is less likely to occur. Therefore, it is easier to maintain the electrical connection between the alignment film 33 and the common electrode 25 through the opening 37A of the second interlayer insulating film 37, and it is less likely for residual charge to remain on the alignment film 33. Furthermore, there is a concern that the liquid crystal molecules contained in the liquid crystal layer 22 may become misaligned near the spacer 30, resulting in display defects caused by misalignment. In this regard, the spacer 30 is arranged overlapping with the light-shielding portion 29, making it difficult to visually identify display defects caused by the spacer 30.

[0089] Additionally, the array substrate 21 includes: a plurality of TFTs (thin-film transistors) 23 arranged with gaps in a first direction and a second direction intersecting the first direction; a plurality of gate wirings (first wirings) 26 extending along the first direction and arranged with gaps in the second direction; and a plurality of source wirings (second wirings) 27 extending along the second direction, intersecting the gate wirings 26, and arranged with gaps in the first direction; a plurality of pixel electrodes 24 arranged with gaps in the first and second directions and connected to the plurality of TFTs 23; the gate wirings 26 connected to the plurality of TFTs 23 arranged along the first direction; the source wirings 27 connected to the plurality of TFTs 23 arranged along the second direction; spacers 30 are disposed overlapping the intersection 21X of the gate wirings 26 and the source wirings 27, and the number of spacers 30 is less than the number of intersection 21X; openings 37A overlap with at least one of the gate wirings 26 and the source wirings 27, and are disposed side by side with the spacers 30 along at least one of the first and second directions, and the number of openings 37A is less than or equal to the number of intersection 21X minus the number of spacers 30. In this way, in the second interlayer insulating film 37, the opening 37A overlaps with at least one of the gate wiring 26 and the source wiring 27, and is arranged side by side along at least one of the isolation elements 30 configured to overlap with the intersection 21X of the gate wiring 26 and the source wiring 27 in the first and second directions. The number of such openings 37A is less than or equal to the number of intersections 21X of the gate wiring 26 and the source wiring 27 minus the number of isolation elements 30. Thus, the number of isolation elements 30 and the number of openings 37A in the second interlayer insulating film 37 can be sufficiently ensured respectively.

[0090] Furthermore, the number of openings 37A is the number minus the number of spacers 30 from the number of intersections 21X. Thus, the spacers 30 and the openings 37A of the second interlayer insulating film 37 are complementaryly arranged within the surface of the array substrate 21. This ensures that the number of openings 37A in both the spacers 30 and the second interlayer insulating film 37 is adequately guaranteed.

[0091] Furthermore, one spacer 30 is disposed at each of the multiple intersections 21X arranged along the first direction, and one spacer 30 is disposed at each of the multiple intersections 21X arranged along the second direction. In this way, the multiple spacers 30 and the openings 37A of the second interlayer insulating film 37 are respectively arranged in a staggered planar configuration. Since uneven distribution of the multiple spacers 30 within the surfaces of the array substrate 21 and the opposing substrate 20 is avoided, the spacing between the array substrate 21 and the opposing substrate 20 can be maintained more stably. Since uneven distribution of the multiple openings 37A within the surface of the second interlayer insulating film 37 within the surface of the array substrate 21 is avoided, the charge accumulated in the alignment film 33 can be completely removed.

[0092] Furthermore, the light-shielding portion 29 has a first light-shielding portion 29A extending along a first direction and overlapping with the TFT 23, gate wiring 26, spacer 30, and opening 37A, and a second light-shielding portion 29B extending along a second direction and overlapping with source wiring 27, and having a width narrower than the first light-shielding portion 29A. Thus, the first light-shielding portion 29A, which overlaps with the opening 37A of the second interlayer insulating film 37, is wider than the second light-shielding portion 29B. Therefore, even if the opening 37A is offset when it is provided on the second interlayer insulating film 37, the reliability of maintaining the overlap relationship between the opening 37A and the first light-shielding portion 29A is increased.

[0093] Furthermore, the pixel electrode 24 is disposed on the upper side of the second interlayer insulating film 37 and on the lower side of the alignment film 33. Thus, the second interlayer insulating film 37 is positioned between the upper pixel electrode 24 and the lower common electrode 25. Therefore, the thickness of the second interlayer insulating film 37 is much smaller than that of a typical planarization film, which is suitable for maintaining a sufficiently high intensity of the electric field generated between the pixel electrode 24 and the common electrode 25. On the other hand, the thickness of the second interlayer insulating film 37 is generally larger than the thickness of the pixel electrode 24 and the common electrode 25. Here, the step formed between the portion of the alignment film 33 that is directly or via other components connected to the common electrode 25 through the opening 37A of the second interlayer insulating film 37 and the portion disposed on the upper side of the second interlayer insulating film 37 depends on the thickness of the second interlayer insulating film 37. Since the thickness of the second interlayer insulating film 37 is set as described above, misalignment of liquid crystal molecules near the opening 37A is unavoidable to some extent. In this regard, since the second interlayer insulating film 37 is disposed at the position where the opening 37A overlaps with the light-shielding portion 29, even if the liquid crystal molecules near the opening 37A have misalignment, it is difficult to visually identify the display defects caused by misalignment.

[0094] Furthermore, the spacer 30 protrudes from the opposing substrate 20 toward the liquid crystal layer 22. A planarization film 36 is disposed on the array substrate 21 on the lower side of the common electrode 25. The planarization film 36 has a first thickness portion 36A, which is thicker than the second interlayer insulating film 37, and does not overlap with the spacer 30, but overlaps with the common electrode 25 and the pixel electrode 24; and a second thickness portion 36B, which is thicker than the first thickness portion 36A, and overlaps with the spacer 30. Thus, the portion of the alignment film 33 that overlaps with the second thickness portion 36B of the planarization film 36 is configured to protrude further toward the liquid crystal layer 22 than the portion that overlaps with the first thickness portion 36A. When an external force is applied to the array substrate 21 or the opposing substrate 20, the spacer 30 protruding from the opposing substrate 20 toward the liquid crystal layer 22 is supported by the portion of the alignment film 33 on the array substrate 21 that overlaps with the second thickness portion 36B. This limits the deflection of the array substrate 21 or the opposing substrate 20. Furthermore, since the portion of a planarization film 36 that overlaps with the spacer 30 is selectively designated as the second film thickness portion 36B, it is not necessary to provide two planarization films.

[0095] <Second Embodiment> According to Figure 16 The second embodiment will be described. In this second embodiment, a structure is shown in which the film laminated and formed on the inner surface side of the array substrate 121 is modified. Furthermore, repeated descriptions of the same structure, function, and effects as in the first embodiment described above are omitted.

[0096] Figure 16 It is near TFT 123 and spacer 130 of LCD panel 111 (and) Figure 7 A cross-sectional view (at the same location). For example... Figure 16 As shown, in the array substrate 121 of this embodiment, a first planarization film 38 is disposed on the upper side of the first interlayer insulating film 135 on the lower side of the common electrode 125 formed by the first transparent electrode film, and a second planarization film 39 is disposed on the lower side of the alignment film 133 on the upper side of the pixel electrode 124 formed by the second transparent electrode film. Furthermore, in this embodiment, with the provision of the first planarization film 38 and the second planarization film 39, the planarization film 36 described in the first embodiment (see reference...) Figure 7 ) was removed.

[0097] Both the first planarization film 38 and the second planarization film 39 are made of organic materials such as PMMA (acrylic resin) and are photosensitive. The formation range of the first planarization film 38 within the surface of the array substrate 121 is the same as the formation range of the planarization film 36 described in the first embodiment. Therefore, the first planarization film 38 is disposed overlapping with the spacer 130, the common electrode 125, and the pixel electrode 124. In addition, a first contact hole 21CH1 is provided on the first planarization film 38 in a manner that communicates with the first interlayer insulating film 135 and the second interlayer insulating film 137. The film thickness of the first planarization film 38 is greater than that of the second interlayer insulating film 137, which is the same as the first film thickness portion 36A described in the first embodiment (see reference). Figure 7 The thickness of the first planarization film 38 is the same as that of the spacer 130. Regardless of its positional relationship with the spacer 130, the thickness of the first planarization film 38 is approximately uniform over the entire area within the surface of the array substrate 121.

[0098] The second planarization film 39 is disposed overlapping the spacers 130. Specifically, the second planarization film 39 is distributed at multiple positions spaced apart in the X-axis and Y-axis directions, overlapping with the spacers 130 respectively. Thus, the second planarization film 39 is arranged in an interlaced pattern within the surface of the array substrate 121, suitable for the planar arrangement of the spacers 130. That is, the formation range of the second planarization film 39 within the surface of the array substrate 121 is the same as the second film thickness 36B described in the first embodiment (see reference). Figure 7The formation range of the second planarization film 39 is the same as that of the spacer 130 when viewed from above. The formation range of the second planarization film 39 when viewed from above is approximately circular, just like that of the spacer 130. The thickness of the second planarization film 39 is greater than that of the second interlayer insulating film 137, and is the same as the thickness of the second thickness portion 36B minus the thickness of the first thickness portion 36A as described in the first embodiment above. The second planarization film 39 is arranged to overlap with the first planarization film 38. Therefore, the portion of the alignment film 133 that overlaps with the second planarization film 39 is arranged to protrude toward the liquid crystal layer 122 in the Z-axis direction in proportion to the portion that overlaps with the first planarization film 38 but does not overlap with the second planarization film 39. With this configuration, the second planarization film 39 can receive the protruding front end surface of the spacer 130 across almost the entire area of ​​the alignment film 133. As a result, the deflection of the array substrate 121 or the opposing substrate 120 can be limited. Furthermore, since the second planarization film 39 is disposed on the upper side of the pixel electrode 124 and the lower side of the alignment film 133, the spacer 130 can protect the pixel electrode 124 and the common electrode 125 from the forces acting on them when they come into contact with the portion of the alignment film 133 that overlaps with the second planarization film 39. Therefore, the pixel electrode 124 and the common electrode 125 are less susceptible to damage. In addition, compared to the case where the thickness of a planarization film 36 is locally different as in the first embodiment, the second planarization film 39, which overlaps with the spacer 130, has high flatness. Therefore, the spacer 130 can be stably supported by the second planarization film 39.

[0099] As explained above, according to this embodiment, the spacer 130 protrudes from the opposing substrate 120 toward the liquid crystal layer 122. A first planarization film 38 is disposed on the lower layer side of the common electrode 125, and a second planarization film 39 is disposed on the upper layer side of the pixel electrode 124 and the lower layer side of the alignment film 133. The thickness of the first planarization film 38 is greater than the thickness of the second interlayer insulating film 137, and it overlaps with the spacer 130, the common electrode 125, and the pixel electrode 124. The thickness of the second planarization film 39 is greater than the thickness of the second interlayer insulating film 137, and it overlaps with the spacer 130. Thus, the second planarization film 39 overlaps with both the spacer 130 and the first planarization film 38. Therefore, the portion of the alignment film 133 that overlaps with the second planarization film 39 protrudes toward the liquid crystal layer 122 compared to the portion that does not overlap with the second planarization film 39 but overlaps with the first planarization film 38. The spacer 130, protruding from the opposing substrate 120 toward the liquid crystal layer 122, is supported by the portion of the alignment film 133 on the array substrate 121 that overlaps with the second planarization film 39 when an external force is applied to the array substrate 121 or the opposing substrate 120. This limits the deflection of the array substrate 121 or the opposing substrate 120. Furthermore, since the second planarization film 39 is disposed on the upper side of the pixel electrode 124, the spacer 130 protects the pixel electrode 124 and the common electrode 125 from forces acting when they come into contact with the portion of the alignment film 133 that overlaps with the second planarization film 39. This reduces the risk of damage to the pixel electrode 124 and the common electrode 125. Additionally, compared to the case where the thickness of a single planarization film is locally uneven, the second planarization film 39 overlapping with the spacer 130 has high flatness. Therefore, the spacer 130 can be stably supported by the second planarization film 39.

[0100] <Third Embodiment> According to Figures 17 to 19 The third embodiment will be described. In this third embodiment, an embodiment in which a connecting electrode 40 is added to the configuration described in the second embodiment above is shown. Furthermore, repeated descriptions of the same structure, function, and effects as in the second embodiment above are omitted.

[0101] Figure 17 It is a top view showing the pixel arrangement of the display area AA of the array substrate 221, and a top view showing the second transparent electrode film (pixel electrode 224, etc.) in shaded form. Figure 18 It is near TFT 223 on the amplification array substrate 221 (and) Figure 11 The top view (within the same range) shows the first transparent electrode film (common electrode 225, etc.) and the second transparent electrode film with different shading. Figure 19 This is a cross-sectional view of TFT 223 and the vicinity of spacer 230 in LCD panel 211. Figure 18(Cross-section of the xix-xix line).

[0102] like Figures 17 to 19 As shown, a connection electrode (other component) 40 connected to a common electrode 225 is provided on the array substrate 221 according to this embodiment. The connection electrode 40 is composed of a portion of the second transparent electrode film that is different from the pixel electrode 224. That is, the connection electrode 40 is located on the upper side of the second interlayer insulating film 237 and on the lower side of the second planarization film 239. The connection electrode 40 does not overlap with the second planarization film 239, but overlaps with the opening 237A of the second interlayer insulating film 237. The entire area of ​​the connection electrode 40 that does not overlap with the second planarization film 239 is in contact with the alignment film 233. Moreover, the connection electrode 40 that overlaps with the opening 237A of the second interlayer insulating film 237 is connected to the common electrode 225 on the lower side through the opening 237A. In other words, the alignment film 233 is indirectly connected to the common electrode 225 via the connection electrode 40, which is an other component. As a result, the charge present on the surface or inside the alignment film 233 can flow into the common electrode 225 via the connection electrode 40. Regardless of the extent of the opening 237A in the second interlayer insulating film 237, the contact area between the connecting electrode 40 and the alignment film 233 can be expanded according to the formation range of the connecting electrode 40, thus making it less likely for residual charge to be generated in the alignment film 233. In particular, this is preferred when there are many spacers 230 and few openings 237A.

[0103] like Figure 17 As shown, multiple connecting electrodes 40 are provided in a manner that individually overlaps with all the openings 237A provided on the second interlayer insulating film 237. The number of connecting electrodes 40 is equal to the number of openings 237A provided on the second interlayer insulating film 237. The planar arrangement of the multiple connecting electrodes 40 in the plane of the array substrate 221 is the same as the planar arrangement of the multiple openings 237A in the second interlayer insulating film 237. The connecting electrodes 40 are located between two adjacent pixel electrodes 224 in the X-axis direction, but not between two adjacent pixel electrodes 224 in the Y-axis direction. Figure 18 and Figure 19 As shown, the connecting electrode 40 does not overlap with the second planarization film 239 and the separator 230, but overlaps with the source wiring 227 and the source electrode 223B. Figure 18As shown, the connecting electrode 40 is square in top view, and its dimensions in the X and Y axes (the formed area in top view) are larger than the dimensions in the X and Y axes of the opening 237A of the second interlayer insulating film 237. The connecting electrode 40 overlaps with the entire area of ​​the opening 237A of the second interlayer insulating film 237, and also overlaps with the periphery of the opening 237A. The connecting electrode 40 is arranged side by side with the spacer 230 along the X-axis. The connecting electrode 40 is configured such that the straight line connecting the top view center of the connecting electrode 40 and the top view center of the spacer 230 is approximately parallel to the X-axis. Thus, the configuration of the connecting electrode 40 is limited to a configuration sandwiched between two adjacent pixel electrodes 224 in the X-axis direction. Therefore, it is difficult for the connecting electrode 40, which is composed of a portion different from the pixel electrode 224 in the second transparent electrode film, to short-circuit with the pixel electrode 224.

[0104] As explained above, according to this embodiment, the pixel electrode 224 is composed of a portion of the second transparent electrode film (transparent electrode film). A connection electrode 40, which is composed of a portion of the second transparent electrode film different from the pixel electrode 224, is provided as another component on the array substrate 221. This connection electrode 40 contacts the alignment film 233 and is connected to the common electrode 225 through an opening 237A. Thus, the connection electrode 40, which contacts the alignment film 233, is connected to the common electrode 225 through the opening 237A. Therefore, the charge on the alignment film 233 can flow into the common electrode 225 via the connection electrode 40. Regardless of the extent of the opening 237A in the second interlayer insulating film 237, the contact area between the connection electrode 40 and the alignment film 233 can be expanded according to the formation extent of the connection electrode 40, thus reducing the likelihood of charge residue on the alignment film 233. In particular, it is preferable when the number of spacers 230 is large and the number of openings 237A is small.

[0105] Furthermore, multiple pixel electrodes 224 are arranged with spacing between them in both the first direction and the second direction intersecting the first direction. The connecting electrode 40 is located between two adjacent pixel electrodes 224 in one of the first and second directions, and is not positioned between two adjacent pixel electrodes 224 in the other direction. In this way, the arrangement of the connecting electrode 40 is limited to being sandwiched between two adjacent pixel electrodes 224 in one of the first and second directions. Therefore, the connecting electrode 40, which is formed by a portion of the second transparent electrode film that differs from the pixel electrode 224, is less likely to short-circuit with the pixel electrode 224.

[0106] <Fourth Implementation Method> According to Figures 20 to 23The fourth embodiment will be described. In this fourth embodiment, an embodiment in which the configuration of the connecting electrode 340 is changed from the third embodiment described above is shown. Furthermore, repeated descriptions of the same structures, functions, and effects as in the second and third embodiments described above are omitted.

[0107] Figure 20 It is near TFT223 on the amplification array substrate 321 (and) Figure 11 The top view (within the same range) shows the first transparent electrode film (common electrode 325, etc.) and the second transparent electrode film (pixel electrode 324, etc.) with different shading. Figure 21 It is in LCD panel 211 Figure 20 A cross-sectional view of the xxi-xxi line. Figure 22 It is in LCD panel 211 Figure 20 Cross-sectional view of line xxii-xxii. Figure 23 It is in LCD panel 211 Figure 20 A cross-sectional view of the xxiii-xxiii line.

[0108] like Figure 20 As shown, the connection electrode 340 according to this embodiment has an electrode body 41 connected to a common electrode 325 through an opening 337A, and an extension portion 42 extending from the electrode body 41. The electrode body 41 is located between two adjacent pixel electrodes 324 in the X-axis direction and is arranged overlapping the opening 337A of the second interlayer insulating film 337. Figure 20 and Figure 21 As shown, the electrode body 41 does not overlap with the second planarization film 239 and the separator 230, but overlaps with the source wiring 327 and the source electrode 323B. That is, the electrode body 41 overlaps with the connection electrode 40 described in the third embodiment (see above). Figure 18 The electrode body 41 is roughly the same in configuration. When viewed from above, it is square, and its dimensions in the X-axis and Y-axis directions (the forming range when viewed from above) are larger than those in the X-axis and Y-axis directions of the connecting electrode 40 described in the third embodiment above.

[0109] like Figure 20 As shown, the extension 42 is disposed between two adjacent pixel electrodes 324 in the Y-axis direction, and is in the form of a strip extending along the X-axis direction. The extension 42 has a length that intersects with a plurality of source wirings 327. That is, the extension 42 is configured to intersect with both the source wirings 327 overlapping the electrode body 41 (opening 337A) and the source wirings 327 overlapping the separator 330. Figure 20 as well as Figure 21 As shown, the portion of the extension 42 that intersects with the source wiring 327 overlapping the electrode body 41 is connected to the electrode body 41. Thus, as... Figure 21and Figure 22 As shown, the connecting electrode 340 has an extension 42 extending from the electrode body 41 that is connected to the common electrode 325 through the opening 337A, and therefore, it is similar to the connecting electrode 40 described in the third embodiment above (see reference). Figure 18 Compared to the configuration without the extension 42, the contact area with the alignment film 333 is expanded. Therefore, compared to the third embodiment, it is less likely for charge residue to accumulate on the alignment film 333. In particular, the third embodiment is preferable when the number of spacers 330 is large and the number of openings 337A is small. Furthermore, since the electrode body 41 is located between two adjacent pixel electrodes 324 in the X-axis direction, and the extension 42 is located between two adjacent pixel electrodes 324 in the Y-axis direction, short circuits between the connecting electrode 340 and the pixel electrode 324, which are made of the same second transparent electrode film, can be avoided.

[0110] like Figure 20 and Figure 23 As shown, a portion of the extension 42 is disposed overlapping the spacer 330 and the second planarization film 339. The second planarization film 339 is located on the upper side of the pixel electrode 324 and the extension 42, which are composed of the second transparent electrode film, and on the lower side of the alignment film 333. With this configuration, when the spacer 330 comes into contact with the portion of the alignment film 333 that overlaps with the second planarization film 339, the second planarization film 339, located on the upper side of the pixel electrode 324 and the extension 42, can withstand the force exerted by the spacer 330. As a result, since the pixel electrode 324, the common electrode 325, and the extension 42 can be protected, the pixel electrode 324, the common electrode 325, and the extension 42 are less likely to be damaged. In particular, since the extension 42 is less likely to be damaged, it is less likely to break in the extension 42, and therefore it is less likely to cause a short circuit between two adjacent pixel electrodes 324 in the Y-axis direction due to a break in the extension 42. Furthermore, the second interlayer insulating film 337 located on the lower side of the extension 42 is planarized along the entire length of the extension 42 by a first planarization film 338 serving as its base. Therefore, portions in the extension 42 that do not overlap with the second planarization film 339 but overlap with the first planarization film 338 (see reference) are avoided. Figure 22 ) and the portion overlapping with both the first planarization film 338 and the second planarization film 339 (see reference) Figure 23 Steps are created between the extensions. As a result, the extension 42 has good coverage.

[0111] As explained above, according to this embodiment, multiple pixel electrodes 324 are arranged at intervals in both the first direction and the second direction intersecting the first direction. The connecting electrode 340 has: an electrode body 41 located between two adjacent pixel electrodes 324 in one of the first and second directions, connected to a common electrode 325 through an opening 337A; and an extension 42 located between two adjacent pixel electrodes 324 in the other of the first and second directions, extending from the electrode body 41. Thus, the connecting electrode 340 has an extension 42 extending from the electrode body 41 connected to the common electrode 325 through the opening 337A, thereby expanding the contact area with the alignment film 333 compared to the case where the connecting electrode is only composed of the electrode body 41. This makes it more difficult for charge residue to accumulate on the alignment film 333. Furthermore, while the electrode body 41 is located between two adjacent pixel electrodes 324 in one of the first and second directions, the extension 42 is located between two adjacent pixel electrodes 324 in the other of the first and second directions. By configuring the connecting electrode 340 in the second transparent electrode film as described above, which is composed of a portion different from the pixel electrode 324, short circuits with the pixel electrode 324 can be avoided.

[0112] Furthermore, the spacer 330 protrudes from the opposing substrate 320 toward the liquid crystal layer 322. A first planarization film 338 is disposed on the lower layer side of the common electrode 325, and a second planarization film 339 is disposed on the lower layer side of the alignment film 333 on the upper layer side of the pixel electrode 324 and the connecting electrode 340. The first planarization film 338 is thicker than the second interlayer insulating film 337 and overlaps with the spacer 330, the common electrode 325, and the pixel electrode 324. The second planarization film 339 is thicker than the second interlayer insulating film 337 and overlaps with the spacer 330 and the extension 42. Thus, the second planarization film 339 overlaps with the spacer 330, the extension 42, and the first planarization film 338. Therefore, the portion of the alignment film 333 that overlaps with the second planarization film 339 is configured to protrude towards the liquid crystal layer 322 side compared to the portion that does not overlap with the second planarization film 339 but overlaps with the first planarization film 338. The spacer 330, protruding from the opposing substrate 320 towards the liquid crystal layer 322 side, is supported by the portion of the alignment film 333 on the array substrate 321 that overlaps with the second planarization film 339 when an external force is applied to the array substrate 321 or the opposing substrate 320. This limits the deflection of the array substrate 321 or the opposing substrate 320. Furthermore, since the second planarization film 339 is disposed on the upper side of the pixel electrode 324, the spacer 330 protects the pixel electrode 324, the common electrode 325, and the extension 42 from the force acting when they come into contact with the portion of the alignment film 333 that overlaps with the second planarization film 339. Therefore, the pixel electrode 324, the common electrode 325, and the extension 42 are less susceptible to damage. In particular, since the extension 42 is less susceptible to damage, it is difficult for a short circuit to occur between two pixel electrodes 324 adjacent to each other in the first and second directions via the extension 42. Furthermore, compared to the case where the thickness of a planarization film is locally uneven, the second planarization film 339, which overlaps with the separator 330, has high flatness. Therefore, the separator 330 can be stably supported by the second planarization film 339.

[0113] <Fifth Implementation Method> According to Figure 24 The fifth embodiment will be described. In this fifth embodiment, an embodiment is shown in which the arrangement of the spacer 43, etc., and the configuration of the connecting electrode 440 are changed from the fourth embodiment described above. Furthermore, repeated descriptions of the same structure, function, and effects as those in the second to fourth embodiments described above are omitted.

[0114] Figure 24 It is near TFT223 on the amplification array substrate 421 (and) Figure 11The top view (within the same area) shows the first transparent electrode film (common electrode 425, etc.) and the second transparent electrode film (pixel electrode 424, etc.) with different shading. Additionally, Figure 24 In the diagram, the light-shielding portion 429 and the separator 430 are illustrated with thick double-dotted lines, and the formation range of the second planarization film 439 is illustrated with thin double-dotted lines.

[0115] like Figure 24 As shown, among the plurality of spacers 430 involved in this embodiment, two spacers 430 are included that overlap with two intersections 421X that sandwich pixel electrodes 424 in the X-axis direction among a plurality of intersections 421X arranged side by side along the X-axis direction. Each of these two spacers 430 includes a first spacer 430α and a second spacer 430β. In the second interlayer insulating film, two openings 437A are provided that overlap with the two intersections 421X that overlap with the two spacers 430 among the plurality of intersections 421X arranged along the X-axis direction. The two openings 437A include: a first opening 437Aα, located between two adjacent pixel electrodes 424 in the X-axis direction; and a second opening 437Aβ, located between two adjacent pixel electrodes 424 in the X-axis direction, and disposed at a position that is spaced apart from the first opening 437Aα in the X-axis direction. In addition, when distinguishing between the two openings 437A, the first opening will be labeled "α" and the second opening will be labeled "β". When not distinguishing between them and referring to them collectively, no label will be used.

[0116] The connecting electrode 440 has two electrode bodies 441 that overlap with the two openings 437A described above. These two electrode bodies 441 include a first electrode body 441α that overlaps with the first opening 437Aα and a second electrode body 441β that overlaps with the second opening 437Aβ. Furthermore, hereinafter, when distinguishing the electrode bodies 441, the symbol for the first electrode body will be marked with the suffix "α", and the symbol for the second electrode body will be marked with the suffix "β". Without distinction, the reference numerals will not be used in the accompanying drawings. The first electrode body 441α is connected to the common electrode 425 through the overlapping first opening 437Aα. The second electrode body 441β is connected to the common electrode 425 through the overlapping second opening 437Aβ. Moreover, these first electrode bodies 441α and second electrode bodies 441β are connected to a common extension 442. In this way, even if a poor connection occurs between either the first electrode body 441α or the second electrode body 441β and the common electrode 425, the connecting electrode 440 and the common electrode 425 can still be maintained in a connected state. That is, the redundancy of the connecting electrode 440 is ensured. As a result, the reliability of the connecting electrode 440 in performing its function is improved.

[0117] As described above, according to this embodiment, the second interlayer insulating film as an opening 437A includes: a first opening 437Aα, located between two adjacent pixel electrodes 424 in one of the first and second directions; and a second opening 437Aβ, located between two adjacent pixel electrodes 424 in one of the first and second directions, and disposed at a position spaced apart from the first opening 437Aα in one of the first and second directions. The connecting electrode 440 as an electrode body 441 has: a first electrode body 441α, which overlaps with the first opening 437Aα and is connected to the common electrode 425 through the first opening 437Aα; a second electrode body 441β, which overlaps with the second opening 437Aβ and is connected to the common electrode 425 through the second opening 437Aβ; and an extension 441α, which is connected to the first electrode body 441a and the second electrode body 441β. In this way, the connecting electrode 440 has a first electrode body 441α and a second electrode body 441β connected to the extension 442. Therefore, even if a poor connection occurs between either the first electrode body 441α or the second electrode body 441β and the common electrode 425, the connection between the connecting electrode 440 and the common electrode 425 can be maintained. As a result, the reliability of the connecting electrode 440 in performing its function is improved.

[0118] <Sixth Implementation Method> According to Figures 25 to 28 The sixth embodiment will be described. In this sixth embodiment, an embodiment in which the configuration of the common electrode 525 is changed from the fourth embodiment described above is shown. Furthermore, repeated descriptions of the same structure, function, and effects as those in the second to fourth embodiments are omitted.

[0119] Figure 25 This is a top view showing the touch electrodes 43 and touch wiring 44 of the LCD panel 511. Figure 25As shown, the liquid crystal panel 511 of this embodiment has a generally rectangular planar shape with an elongated shape. In addition to displaying images, it also has a touch panel function (position detection function) that detects the user's input position (input position) based on the displayed image. The touch panel pattern for performing the touch panel function is integrated (embedded) on the liquid crystal panel 511. The touch panel pattern uses a projection-type electrostatic capacitance method, and its detection method is self-capacitance. The touch panel pattern is composed of a plurality of touch electrodes (position detection electrodes) 43 arranged in a matrix within the surface of the liquid crystal panel 511. The touch electrodes 43 are disposed in the display area AA of the liquid crystal panel 511. Therefore, the display area AA of the liquid crystal panel 511 is approximately the same as the touch area (position input area) where the input position can be detected. Furthermore, the non-display area NAA is approximately the same as the non-touch area (non-position input area) where the input position cannot be detected. Based on the image displayed in display area AA of the liquid crystal panel 511, when a user brings a position input object, such as a user's finger or a stylus operated by the user, close to the surface (display surface) of the liquid crystal panel 511, an electrostatic capacitance is formed between the position input object and the touch electrode 43. Therefore, the electrostatic capacitance detected by the touch electrode 43 located near the position input object changes as the position input object approaches, and differs from the electrostatic capacitance of the touch electrode 43 located further away from the position input object. Based on this difference in electrostatic capacitance, the detection circuit described later can detect the input position.

[0120] like Figure 25 As shown, in the display area AA, multiple touch electrodes 43 are arranged at intervals along the X-axis and Y-axis directions. The touch electrodes 43 are roughly square when viewed from above, with one side measuring approximately several millimeters. The size of the touch electrodes 43 when viewed from above is much larger than the pixels PX described later, and they are arranged across a range spanning multiple (tens to hundreds) pixels PX in the X-axis and Y-axis directions. Furthermore, specific values ​​such as the size of one side of the touch electrodes 43 and the number of electrodes in the touch area can be appropriately changed. Additionally, in the non-display area NAA of the array substrate 521, a pair of gate circuit sections 45 are provided, flanking the display area A from both sides in the X-axis direction. The gate circuit sections 45 supply scan signals to the gate wiring 526 and are monolithically disposed on the array substrate 521.

[0121] like Figure 25As shown, a plurality of touch wirings (position detection wirings) 44 disposed on the liquid crystal panel 511 are selectively connected to a plurality of touch electrodes 43. The touch wirings 44 extend generally along the Y-axis direction. One end portion of the touch wirings 44 in the Y-axis direction is connected to a driver 512 in the non-display area NAA. The other end portion of the touch wirings 44 in the Y-axis direction is connected to a specific touch electrode 43 among the plurality of touch electrodes 43 arranged along the Y-axis direction in the display area AA. The Y-axis direction of the touch wirings 44 is limited to the range from the driver 512 to the connected touch electrode 43, and is not disposed further from the driver 512 than the connected touch electrode 43. Figure 1 The opposite side of the lower side ( Figure 1 (The upper side). Furthermore, depending on the number of touch wires 44, only one touch wire 44 may be connected to one touch electrode 43, but multiple touch wires 44 may also be connected to one touch electrode 43. Additionally, the number of touch wires 44 connected to one touch electrode 43 may vary depending on the position of the touch electrode 43. In this case, for example, it is preferable to have more touch wires 44 connected to touch electrodes 43 farther from the driver 512 than to have more touch wires 44 connected to touch electrodes 43 closer to the driver 512, but this is not a limitation. Furthermore, in Figure 25 In the diagram, a black circle indicates the connection point of the touch wiring 44 to the touch electrode 43. Furthermore, the touch wiring 44 is connected to the detection circuit. The detection circuit can be housed within the driver 512, or it can be mounted externally to the liquid crystal panel 511 via the flexible substrate 513.

[0122] like Figure 25As shown, the touch electrode 43 is composed of a common electrode 525. A slit 525B is formed on the common electrode 525, which is configured to separate adjacent touch electrodes 43. The slit 525B generally appears as a grid when viewed from above. The slit 525B includes a first slit 525B1 that spans approximately the entire length of the common electrode 525 along the X-axis direction, and a second slit 525B2 that spans approximately the entire length of the common electrode 525 along the Y-axis direction. The common electrode 525 is composed of a plurality of touch electrodes 43, which are divided into a generally checkerboard pattern by the slits 525B when viewed from above, and are electrically independent of each other. The touch electrodes 43 arranged along the Y-axis direction are separated by the first slit 525B1. The touch electrodes 43 arranged along the X-axis direction are separated by the second slit 525B2. Furthermore, the first slit 525B1 is configured to overlap with the gate wiring 526 described later. Furthermore, the second slit 525B2 is configured to overlap with the source wiring 527. The driver 512 supplies the touch wiring 44, connected to such touch electrodes 43, with a common potential signal for image display functions and touch signals (position detection signals) for touch panel functions in a time-divided manner. The timing of supplying the common potential signal from the driver 512 to the touch wiring 44 is the display period. The timing of supplying the touch signal from the driver 512 to the touch wiring 44 is the sensing period (position detection period). This common potential signal is transmitted to all touch wiring 44 at the same timing (display period), so that all touch electrodes 43 function as a common electrode 525 based on a reference potential of the common potential signal.

[0123] Figure 26 It is a magnified top view of the area near the boundary of two adjacent touch electrodes 43 in the Y-axis direction in the array substrate 521, and a top view showing the first transparent electrode film (common electrode 525, etc.) and the second transparent electrode film (pixel electrode 524, etc.) with different shades.

[0124] Figure 27 It is in the LCD panel 511 Figure 26 A cross-sectional view of the xxvii-xxvii line. Figure 28 It is in the LCD panel 511 Figure 26 A cross-sectional view of the xxviii-xxviii line. (See diagram below.) Figure 26 and Figure 27As shown, among the multiple gate wirings 526 involved in this embodiment, there is a gate wiring 526 that overlaps with a first slit 525B1, which separates two adjacent touch electrodes 43 in the Y-axis direction. The minimum linewidth of the gate wiring 526 overlapping with the first slit 525B1 is larger than the width of the first slit 525B1. Multiple connection electrodes 540 disposed in the plane of the array substrate 521 include connection electrodes 540 having an extension 542 located between two adjacent touch electrodes 43 in the Y-axis direction. The extension 542 located between two adjacent touch electrodes 43 in the Y-axis direction is disposed overlapping with both the first slit 525B1 and the gate wiring 526. The width of the extension 542 is smaller than the width of the first slit 525B1. The entire area of ​​the extension 542 overlaps with the first slit 525B1. The spacing between one of the side edges of the extension 542 and the edge of one of the two adjacent touch electrodes 43 facing the first slit 525B1 in the Y-axis direction is approximately equal to the spacing between the other side edge and the edge of the other touch electrode 43 facing the first slit 525B1.

[0125] However, as Figure 27As shown, the gate wiring 526 is made of a first metal film, and therefore is disposed on the lower layer side compared to the common electrode 525, which is made of a first transparent electrode film. In this embodiment, a first slit 525B1 is formed on the common electrode 525, which is positioned between the gate wiring 526 and the pixel electrode 524 in the Z-axis direction, and is arranged overlapping with the gate wiring 526. Therefore, an electric field (parasitic capacitance) may be generated between the gate wiring 526 located between two adjacent touch electrodes 43 in the Y-axis direction and between two adjacent pixel electrodes 524 in the Y-axis direction through the first slit 525B1 of the common electrode 525. In this regard, the extension 542 of the connection electrode 540 in the second transparent electrode film, which is composed of a portion different from the pixel electrode 524, is located between two adjacent touch electrodes 43 in the Y-axis direction (first slit 525B1) and is arranged overlapping with the gate wiring 526, and therefore can shield the electric field generated between the gate wiring 526 and the two adjacent pixel electrodes 524 in the Y-axis direction. Therefore, the orientation of the liquid crystal molecules contained in the liquid crystal layer 522, which is caused by the aforementioned electric field, is less likely to become disordered. In particular, in this embodiment, the second planarization film 539 disposed at the position overlapping with the separator 530 is positioned between the second transparent electrode film and the alignment film 533. Thus, the second planarization film 539 is not positioned between the gate wiring 526 formed by the first metal film and the extension 542 of the connection electrode 540 formed by the second transparent electrode film. Based on this positional relationship, the structure of the second film thickness 36B, which does not have the second planarization film 539 as in the first embodiment but has the planarization film 36 disposed at the position overlapping with the separator 530 (see...) Figure 7 In contrast, the extension 542 and the gate wiring 526 are positioned close to the second planarization film 539 by an amount of film thickness. As a result, the extension 542 can effectively shield the electric field that may be generated between the gate wiring 526 and the two pixel electrodes 524 adjacent in the Y-axis direction.

[0126] Next, refer to Figure 27 as well as Figure 28 Various films that have been laminated on the inner surface of the array substrate 521 according to this embodiment will be described. Figure 27 and Figure 28As shown, on the array substrate 521, in addition to a third metal film disposed on the upper side of the first planarization film 538, a third interlayer insulating film 46 is also disposed on the upper side of the third metal film and the lower side of the first transparent electrode film. Similar to the first and second metal films, the third metal film is a single-layer film made of a metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials. The third metal film constitutes the aforementioned touch wiring 44, etc. The touch wiring 44 is overlapped with the source wiring 527. This suppresses the decrease in the aperture ratio of the pixel PX associated with the placement of the touch wiring 44.

[0127] like Figure 27 and Figure 28 As shown, the third interlayer insulating film 46, like the gate insulating film 534, the first interlayer insulating film 535, and the second interlayer insulating film 537, is made of inorganic materials such as silicon nitride (SiNx) and silicon oxide (SiO2). The third interlayer insulating film 46 is situated between the common electrode 525, which is formed by the first transparent electrode film on the upper side, and the touch wiring 44, which is formed by the third metal film on the lower side, preventing accidental short circuits. Furthermore, a partial opening is provided in the third interlayer insulating film 46 in the area overlapping with both the touch wiring 44 and the touch electrode 43, which is the object to which the touch wiring 44 is connected. The touch wiring 44 is connected to the touch electrode 43 through this opening in the third interlayer insulating film 46.

[0128] like Figure 26 and Figure 27 As shown, the extension 542 constituting the connection electrode 540 according to this embodiment does not overlap with any of the touch electrodes 43. In contrast, the electrode body 541 and the extension 542 connected to it are... Figure 26 The upper adjacent touch electrode 43 overlaps, but with the extension 542 at... Figure 26 The lower adjacent touch electrodes 43 do not overlap. In the second interlayer insulating film 537, an opening 537A is provided at the position where it overlaps with both the electrode body 541 and the touch electrode 43 that overlaps with the electrode body 541. Thus, the electrode body 541 overlaps with the touch electrode 43 that is the connection target of the connecting electrode 540, but does not overlap with the touch electrode 43 that is not the connection target of the connecting electrode 540. Therefore, the parasitic capacitance that may be generated between the connecting electrode 540 and the touch electrode 43 that is not the connection target is reduced, thereby improving the position detection sensitivity.

[0129] As explained above, according to this embodiment, the common electrode 525 includes a plurality of touch electrodes (position detection electrodes) 43 arranged at intervals in both the first and second directions. A gate wiring 526, located between two adjacent pixel electrodes 524 in the second direction and extending along the first direction, is disposed on the array substrate 521. The gate wiring 526 is positioned below the common electrode 525, between two adjacent touch electrodes 43 in the second direction. An extension 542 is located between two adjacent touch electrodes 43 in the second direction and overlaps with the gate wiring 526. Because the gate wiring 526, positioned below the common electrode 525, is located between two adjacent touch electrodes 43 in the second direction, an electric field may be generated between the gate wiring 526 and the two adjacent pixel electrodes 524 in the second direction. In this regard, the extension 542 of the connection electrode 540 in the second transparent electrode film, which is composed of a portion different from that of the pixel electrode 524, is located between two adjacent touch electrodes 43 in the second direction and overlaps with the gate wiring 526. Therefore, it can shield the electric field that may be generated between the gate wiring 526 and the two adjacent pixel electrodes 524 in the second direction. As a result, the orientation of the liquid crystal molecules contained in the liquid crystal layer 522, which is caused by the aforementioned electric field, is less likely to be disordered.

[0130] Furthermore, the electrode body 541 does not overlap with one of the two adjacent touch electrodes 43 in the second direction, but overlaps with the other touch electrode 43 and is connected to the other touch electrode 43. In this way, the electrode body 541 constituting the connecting electrode 540 is configured such that it overlaps with one of the two adjacent touch electrodes 43 in the second direction, but does not overlap with the other touch electrode 43 that is not a connection target. This reduces parasitic capacitance between the connecting electrode 540 and the other touch electrode 43, thus improving position detection sensitivity.

[0131] Furthermore, the spacer 530 protrudes from the opposing substrate 520 toward the liquid crystal layer 522. A first planarization film 538 is disposed on the lower side of the common electrode 525, and a second planarization film 539 is disposed on the lower side of the alignment film 533 on the upper side of the pixel electrode 524 and the connecting electrode 540. The first planarization film 538 is thicker than the second interlayer insulating film 537 and overlaps with the spacer 530, the common electrode 525, and the pixel electrode 524. The second planarization film 539 is thicker than the second interlayer insulating film 537 and overlaps with the spacer 530 and the extension 542. The gate wiring 526 is disposed on the lower side of the first planarization film 538. Thus, the second planarization film 539 overlaps with the spacer 530, the extension 542, and the first planarization film 538. Therefore, the portion of the alignment film 533 that overlaps with the second planarization film 539 is configured to protrude towards the liquid crystal layer 522 side compared to the portion that does not overlap with the second planarization film 539 but overlaps with the first planarization film 538. The spacer 530, protruding from the opposing substrate 520 towards the liquid crystal layer 522 side, is supported by the portion of the alignment film 533 on the array substrate 521 that overlaps with the second planarization film 539 when an external force is applied to the array substrate 521 or the opposing substrate 520. This limits the deflection of the array substrate 521 or the opposing substrate 520. Furthermore, since the second planarization film 539 is disposed on the upper side of the pixel electrode 524, the spacer 530 protects the pixel electrode 524, the common electrode 525, and the extension 542 from the force acting when they come into contact with the portion of the alignment film 533 that overlaps with the second planarization film 539. Therefore, the pixel electrode 524, the common electrode 525, and the extension 542 are less susceptible to damage. In particular, since the extension 542 is less susceptible to damage, it is difficult for a short circuit to occur between two pixel electrodes 524 adjacent to each other in the first and second directions via the extension 542. Furthermore, compared to the case where the thickness of a planarization film is locally different, the second planarization film 539 overlapping the separator 530 has high flatness. Therefore, the separator 530 can be stably supported by the second planarization film 539. Specifically, since the second planarization film 539 is not positioned between the gate wiring 526 disposed on a layer lower than the first planarization film 538 and the extension 542 connecting the electrode 540, the electric field generated between the gate wiring 526 and the two pixel electrodes 524 adjacent in the second direction can be effectively shielded by the extension 542.

[0132] <Seventh Implementation Method> According to Figure 29 or Figure 30The seventh embodiment will be described. In this seventh embodiment, an embodiment is shown in which the connection electrode 640 described in the fourth embodiment is added to the configuration described in the first embodiment. Furthermore, repeated descriptions of the same structures, functions, and effects as in the first and fourth embodiments are omitted.

[0133] Figure 29 It is near TFT 623 and the second spacer 630β of the LCD panel 611 (with) Figure 7 Cross-sectional view (at the same location). Figure 30 It is near the pixel electrode 624 and extension 642 of the liquid crystal panel 611 (and) Figure 23 A cross-sectional view (at the same location). For example... Figure 29 As shown, a connection electrode 640 composed of a second transparent electrode film is provided on the array substrate 621 according to this embodiment. The connection electrode 640 is in contact with the alignment film 633 on the upper side. The electrode body 641 constituting the connection electrode 640 is connected to the common electrode 625 through an opening 637A of the second interlayer insulating film 637 on the lower side. As a result, the charge present on the surface or inside the alignment film 633 can flow into the common electrode 625 through the connection electrode 640. The electrode body 641 does not overlap with the separator 630, but is arranged to overlap with the first film thickness portion 636A in the planarization film 636.

[0134] In this embodiment, as in the second to sixth embodiments described above, there is no second planarization film 39 between the alignment film 633 and the second transparent electrode film (see reference). Figure 16 Therefore, as Figure 30 As shown, the extension 642 constituting the connection electrode 640 in this embodiment also contacts the alignment film 633 at the position where it overlaps with the spacer 630. The extension 642 contacts the alignment film 633 along its entire length, maximizing the contact area with the alignment film 633. As a result, it is more difficult for residual charge to be generated on the alignment film 633.

[0135] <Other Embodiments> The technology disclosed in this specification is not limited to the embodiments described above and the accompanying drawings. For example, the following embodiments are also included in the scope of the technology.

[0136] (1) The specific planar configuration (arrangement pattern) and quantity of the openings 37A, 237A, 337A, 437A, 537A, 637A of the second interlayer insulating films 37, 137, 237, 337, 537, 637 and the separators 30, 130, 230, 330, 430, 530, 630 can be appropriately changed beyond the illustration. For example, the intersections 21X and 421X of the gate wirings 26 and 526 and the source wirings 27, 227, 327 and 527 may also include intersections 21X and 421X of the openings 37A, 237A, 337A, 437A, 530 and 630 that do not overlap with the separators 30, 130, 230, 330, 430, 530 and 630 and are not near the second interlayer insulating films 37, 137, 237, 337, 537 and 637.

[0137] (2) The openings 37A, 237A, 337A, 437A, 537A, and 637A of the second interlayer insulating films 37, 137, 237, 337, 537, and 637A can be configured at positions that overlap with the intersections 21X and 421X of the gate wirings 26 and 526 and the source wirings 27, 227, 327, and 527 (the intersections of the first light-shielding portion 29A and the second light-shielding portion 29B).

[0138] (3) The openings 37A, 237A, 337A, 437A, 537A, and 637A of the second interlayer insulating films 37, 137, 237, 337, 537, and 637 can be positioned at a location that does not overlap with the second light-shielding portion 29B but overlaps with the first light-shielding portion 29A. Furthermore, the openings 37A, 237A, 337A, 437A, 537A, and 637A of the second interlayer insulating films 37, 137, 237, 337, 537, and 637A can be positioned at a location that does not overlap with the first light-shielding portion 29A but overlaps with the second light-shielding portion 29B. In addition, the openings 37A, 237A, 337A, 437A, 537A, and 637A of the second interlayer insulating films 37, 137, 237, 337, 537, and 637A can be positioned at a position that does not overlap with the first light-shielding portion 29A and the second light-shielding portion 29B but overlaps with the third light-shielding portion 29C.

[0139] (4) The light-shielding parts 29 and 429 can also be configured such that the entire area of ​​the third light-shielding part 29C does not overlap with the separators 30, 130, 230, 330, 430, 530, and 630.

[0140] (5) The light-shielding parts 29 and 429 may also be provided on the array substrates 21, 121, 221, 321, 421, 521, and 621. Alternatively, the light-shielding parts 29 and 429 may also be provided on both the opposing substrates 20, 120, 320, and 520 and the array substrates 21, 121, 221, 321, 521, and 621.

[0141] (6) As in (5) above, when at least a portion of the light-shielding portions 29 and 429 are provided on the array substrates 21, 121, 221, 321, 421, 521, and 621, the filter 8 may also be provided on the array substrates 21, 121, 221, 321, 421, 521, and 621.

[0142] (7) The light-shielding parts 29 and 429 may also not include the third light-shielding part 29C. In addition, the light-shielding parts 29 and 429 may also not include the second light-shielding part 29B.

[0143] (8) The ratio of the number of first separator 30α and second separator 30β, 130β and 230β contained in separators 30, 130, 230, 330, 430, 530 and 630 can be appropriately changed in addition to the figures shown.

[0144] (9) Isolators 30, 130, 230, 330, 430, 530, and 630 may also exclude the second isolator 30β, 130β, and 230β, and only include the first isolator 30α. Conversely, isolators 30, 130, 230, 330, 430, 530, and 630 may also exclude the first isolator 30α, and only include the second isolators 30β, 130β, and 230β.

[0145] (10) Isolators 30, 130, 230, 330, 430, 530, and 630 can also be disposed on array substrates 21, 121, 221, 421, 521, and 621.

[0146] (11) The photomask 10P used when exposing the planarization film 36, and the semi-transparent film 10P3, may not be formed within the area overlapping with the light-shielding film 10P2.

[0147] (12) The photomask 10P used when exposing the planarization film 36 can be a so-called grayscale mask. The grayscale mask has a semi-transparent region 10HTA by forming a slit below the resolution of the exposure device on a portion of the light-shielding film formed on the surface of the transparent substrate.

[0148] (13) Negative photosensitive materials can also be used as materials for planarization films 36 and 636. Similarly, negative photosensitive materials can also be used as materials for the first planarization films 38, 338, 538 and the second planarization films 39, 239, 339, 439, 539.

[0149] (14) The connecting electrodes 40, 440, and 540 described in the third, fifth, and sixth embodiments may also be added to the structure described in the first embodiment. In particular, if the connecting electrodes 440 and 540 described in the fifth and sixth embodiments are added to the structure described in the first embodiment, the contact area between the connecting electrodes 440 and 540 and the alignment film 533 can be increased.

[0150] (15) The specific planar configuration (arrangement pattern), number, etc. of the connecting electrodes 40, 340, 440, 540, 640 described in the third to seventh embodiments can be appropriately changed beyond those shown in the figures. In short, the planar configuration, number, etc. of the connecting electrodes 40, 340, 440, 540, 640 can be changed according to the planar configuration, number, etc. of the openings 237A, 337A, 437A, 537A, 637 of the second interlayer insulating film 237, 337, 537, 637.

[0151] (16) In the structures described in the third to seventh embodiments, the second interlayer insulating film 237, 337, 537, 637 may include openings 237A, 337A, 437A, 537A, 637A that are configured to connect electrodes 40, 340, 440, 540, 640 without overlapping.

[0152] (17) As a variation of the fourth and fifth embodiments, the extensions 42 and 442 of the connecting electrodes 340 and 440 may also be arranged to overlap with the source wiring 327. Alternatively, the connecting electrodes 340 and 440 may also have a first extension overlapping with the gate wiring 526 and a second extension overlapping with the source wiring 327 as extensions 42 and 442.

[0153] (18) As a variation of the fifth embodiment, the connecting electrode 440 may also have three or more electrode bodies 41, 441, 541, and 641. In this case, the three or more electrode bodies 41, 441, 541, and 641 may also be connected to a common extension 442.

[0154] (19) The configuration of the spacer 430 described in the fifth embodiment can also be applied to the structures described in the first, second, third, fourth, sixth, and seventh embodiments. Conversely, the configurations of the spacers 30, 130, 230, 330, 530, and 630 described in the first, second, third, fourth, sixth, and seventh embodiments can also be applied to the structures described in the fifth embodiment.

[0155] (20) The touch electrode 43 and touch wiring 44 described in the sixth embodiment can also be added to the structure described in the first and seventh embodiments.

[0156] (21) As a variation of the sixth embodiment, all touch wiring 44 may extend along the Y-axis to the touch electrode 43 furthest from the driver 512. In this case, all touch wiring 44 may be of equal length.

[0157] (22) As a variation of the sixth embodiment, an opening may be provided on the touch electrode 43 at a position overlapping with the touch wiring 44. This can reduce the parasitic capacitance generated between the touch electrode 43 and the touch wiring 44 which is not connected to the touch electrode 43.

[0158] (23) The second planarization films 239, 339, 439, and 539 described in the second to sixth embodiments may also be located on the lower side of the first transparent electrode film on the upper side of the first planarization films 338 and 538.

[0159] (24) Apart from the illustration, the positional relationship of TFTs 23, 123, 223, 323, 423, 623, pixel electrodes 24, 124, 224, 524, 524, 624, and gate wirings 26, 526 in the Y-axis direction can be appropriately changed. For example, the positional relationship of TFTs 23, 123, 223, 323, 423, 623, and gate wirings 26, 526 in the Y-axis direction can also be overlapping.

[0160] (25) The orientation films 33, 133, 233, 333, 533, and 633 are not limited to the type that undergoes photo-orientation treatment, but can also be the type that undergoes rubbing treatment.

[0161] (26) The specific planar shapes of pixel electrodes 24, 124, 224, 324, 424, 524, and 624 can be appropriately changed in addition to those shown in the figure. The planar shape of the pixel electrode body 24A of pixel electrodes 24, 124, 224, 324, 424, 524, and 624 can also be, for example, a square, a parallelogram, etc.

[0162] (27) The top view patterns of gate wirings 26, 526 and source wirings 27, 227, 327, 527 can be appropriately modified. For example, gate wirings 26, 526 may not extend in a straight line, but rather extend at an angle and bend repeatedly along the way. Additionally, source wirings 27, 227, 327, 527 may extend in a straight line along the Y-axis direction. Alternatively, gate wirings 26, 526 and source wirings 27, 227, 327, 527 may all extend in a straight line, but rather extend at an angle and bend repeatedly along the way. Alternatively, gate wirings 26, 526 and source wirings 27, 227, 327, 527 may all extend in a straight line, but rather extend at an angle and bend repeatedly along the way.

[0163] (28) Alternatively, the common electrodes 25, 125, 225, 325, 525, and 625 may be located on the upper side of the second interlayer insulating films 37, 137, 237, 337, 537, and 637, and the pixel electrodes 24, 124, 224, 424, 524, and 624 may be located on the lower side of the second interlayer insulating films 37, 137, 237, 337, 537, and 637. That is, the first transparent electrode film constitutes the pixel electrodes 24, 124, 224, 324, 424, 524, and 624, and the second transparent electrode film constitutes the common electrodes 25, 125, 225, 325, 425, 525, and 625. In this case, on the array substrates 21, 121, 221, 321, 521, 521, 621, an insulating film is provided on the lower side of the alignment films 33, 133, 233, 533, 633, located on the upper side of the common electrodes 25, 125, 225, 325, 525, 525, 625. The insulating film has openings for connecting the common electrodes 25, 125, 225, 325, 525, 625 directly or via other components to the alignment films 33, 133, 233, 533, 633.

[0164] (30) TFT23, 123, 223, 323, 423, and 623 can be bottom gate type in addition to top gate type.

[0165] (31) Semiconductor films can also be amorphous silicon films, oxide semiconductor films, etc.

[0166] (32) The surface of the LCD panels 11, 111, 211, 511, and 611 can be bent.

[0167] (33) The display modes of LCD panels 11, 111, 211, 511, and 611 can also be IPS mode, etc.

[0168] (34) The planar shape of the LCD panels 11, 111, 211, 511, and 611 can also be square, circular, semi-circular, oblong, elliptical, trapezoidal, etc.

[0169] (35) In addition to transmissive type, LCD panels 11, 111, 211, 511 and 611 can also be reflective or semi-transmissive.

[0170] (36) Alternatively, a conductive film may be provided between the common electrodes 25, 125, 225, 325, 425, 525, 625 (first transparent electrode film) and the second interlayer insulating films 37, 137, 237, 337, 537, 637. This conductive film may be used to construct other components that overlap with the openings 37A, 237A, 337A, 437A, 537A, 637A of the second interlayer insulating films 37, 137, 237, 337, 537, 637. The entire area of ​​these other components is in contact with the common electrodes 25, 125, 225, 325, 425, 525, 625. On other components, the upper-side alignment films 33, 133, 233, 337, 537, and 637 are connected via openings 37A, 237A, 337A, 437A, 537A, and 637A in the second interlayer insulating films 37, 137, 237, 337, 537, and 633. The alignment films 33, 133, 233, 333, 533, and 633 are indirectly connected to the common electrodes 25, 125, 225, 325, 525, and 625 via other components. (Explanation of reference numerals in the drawings.)

[0171] 1. 111, 211, 511, 611… LCD panel (display panel); 20, 120, 320, 520… Opposing substrate; 21, 121, 221, 321, 421, 521, 621… Array substrate; 21X, 421X… Cross section; 22, 122, 322, 522… Liquid crystal layer; 23, 123, 223, 323, 423, 623… TFT (Thin Film Transistor); 24, 124… Pixel electrodes: 224, 324, 424, 524, 624…; Common electrode: 25, 125, 225, 325, 425, 525, 625…; Gate wiring (first wiring): 26, 526…; Source wiring (second wiring): 27, 227, 327, 527…; Light-shielding portion: 29, 429…; Light-shielding portion: 29A…; Second light-shielding portion: 29B…; Pixel electrodes: 20, 130, 230, 330, 430, 530… 630… spacer, 33, 133, 233, 333, 533, 633… alignment film, 36, 636… planarization film, 36A, 636A… first film thickness, 36B… second film thickness, 37, 137, 237, 337, 537, 637… second interlayer insulating film (insulating film), 37A, 237A, 337A, 437A, 537A, 637A… opening, 38, 338, 538… first Planarization film, 39, 239, 339, 439, 539… second planarization film, 40, 440, 540, 640… connecting electrode (other components), 41, 441, 541, 641… electrode body, 42, 442, 542, 642… extension, 43… touch electrode (position detection electrode), 437Aα… first opening, 437Aβ… second opening, 441α… first electrode body, 441β… second electrode body

Claims

1. A liquid crystal panel, characterized in that, include: Array substrate; An opposing substrate, which is configured opposite to the array substrate; A liquid crystal layer is sandwiched between the array substrate and the opposing substrate. The array substrate includes: a plurality of pixel electrodes arranged at intervals in-plane of the array substrate; a common electrode overlapping the plurality of pixel electrodes; an insulating film disposed on the upper side of the common electrode; and an alignment film disposed on the upper side of the insulating film. The array substrate and the opposing substrate are provided with: a light-shielding portion separating the plurality of pixel electrodes; and a spacer disposed overlapping with the light-shielding portion and protruding from at least one of the array substrate and the opposing substrate toward the liquid crystal layer side. The alignment film is connected to the common electrode directly or via other components through an opening in the insulating film. In the insulating film, the opening is positioned where it does not overlap with the spacer but overlaps with the light-shielding portion. The pixel electrode is disposed on the upper side of the insulating film and on the lower side of the alignment film. The pixel electrode is composed of a portion of a transparent electrode film. In the array substrate, a connection electrode is provided as one of the other components. The connection electrode is formed by a portion of the transparent electrode film that differs from the pixel electrode, contacts the alignment film, and is connected to the common electrode through the opening. The array substrate is provided with: Multiple thin-film transistors; as well as Multiple first wirings extend along a first direction, and the first wirings are connected to the gate electrodes of the multiple thin-film transistors. The pixel electrodes are arranged in multiple, spaced apart, in the first direction and in the second direction intersecting the first direction. The connecting electrode is located between two adjacent pixel electrodes in the second direction and is connected to the common electrode through the opening. The connecting electrode has: An electrode body is located between two adjacent pixel electrodes in one of the first and second directions, and is connected to the common electrode through the opening; An extension, located between two pixel electrodes adjacent to the other of the first and second directions, extends from the electrode body.

2. The liquid crystal panel as described in claim 1, characterized in that, The array substrate is provided with: The plurality of thin-film transistors are arranged at open intervals in the first direction and the second direction, respectively; Multiple first wirings are arranged at open intervals in the second direction; as well as Multiple second wirings extend along the second direction and intersect with the first wiring, arranged with gaps in the first direction. The plurality of pixel electrodes are connected to the plurality of thin-film transistors. The first wiring is connected to a plurality of thin-film transistors arranged along the first direction. The second wiring is connected to a plurality of thin-film transistors arranged along the second direction. The spacers are configured to overlap with the intersections of the first and second wirings, and their number is less than the number of intersections. The opening overlaps with at least one of the first wiring and the second wiring, and is arranged side by side with the spacer along at least one of the first direction and the second direction, and the number of openings is less than or equal to the number of the number of the intersections minus the number of the spacers.

3. The liquid crystal panel as described in claim 2, characterized in that, The number of openings is the number obtained by subtracting the number of spacers from the number of intersections.

4. The liquid crystal panel as described in claim 2 or 3, characterized in that, One of the plurality of spacers is disposed at each of the plurality of intersections arranged along the first direction, and one of the plurality of intersections is disposed at each of the plurality of intersections arranged along the second direction.

5. The liquid crystal panel as described in claim 2 or 3, characterized in that, The light-shielding part has: A first light-shielding portion extends along the first direction and overlaps with the thin-film transistor, the first wiring, the spacer, and the opening; The second light-shielding portion extends along the second direction, overlaps with the second wiring, and is narrower than the first light-shielding portion.

6. The liquid crystal panel as described in claim 1, characterized in that, As the opening, the insulating film comprises: A first opening is located between two adjacent pixel electrodes in one of the first and second directions; as well as The second opening is located between two adjacent pixel electrodes in one of the first and second directions, and is configured at a position spaced apart from the first opening in the one of the first and second directions. As the electrode body, the connecting electrode includes: A first electrode body, which overlaps with the first opening, is connected to the common electrode through the first opening; and The second electrode body, which overlaps with the second electrode body, is connected to the common electrode through the second opening. The extension is connected to the first electrode body and the second electrode body.

7. The liquid crystal panel as described in claim 1 or 6, characterized in that, The spacer protrudes from the opposing substrate toward the liquid crystal layer side. The array substrate is provided with: A first planarization film is disposed on the lower side of the common electrode; as well as A second planarization film is disposed on the upper side of the pixel electrode and the connecting electrode, on the lower side of the alignment film. The thickness of the first planarization film is greater than that of the insulating film, and it is arranged to overlap with the spacer, the common electrode, and the pixel electrode. The second planarization film has a greater thickness than the insulating film and is configured to overlap with the spacer and the extension.

8. The liquid crystal panel as described in claim 1 or 6, characterized in that, The common electrode includes a plurality of position detection electrodes arranged at intervals in the first direction and the second direction, respectively. A first wiring is disposed on the array substrate between two adjacent pixel electrodes in the second direction and extending along the first direction. The first wiring is positioned on a lower layer side than the common electrode and is located between two adjacent position detection electrodes in the second direction. The extension is located between two adjacent position detection electrodes in the second direction and is configured to overlap with the first wiring.

9. The liquid crystal panel as described in claim 8, characterized in that, The electrode body does not overlap with one of the two adjacent position detection electrodes in the second direction, but is configured to overlap with the other position detection electrode and is connected to the other position detection electrode.

10. The liquid crystal panel as described in claim 8, characterized in that, The spacer protrudes from the opposing substrate toward the liquid crystal layer side. The array substrate is provided with: A first planarization film is disposed on the lower side of the common electrode; as well as A second planarization film is disposed on the upper side of the pixel electrode and the connecting electrode, on the lower side of the alignment film. The thickness of the first planarization film is greater than that of the insulating film, and it is arranged to overlap with the spacer, the common electrode, and the pixel electrode. The second planarization film has a greater thickness than the insulating film and is disposed overlapping the spacer and the extension. The first wiring is configured on a lower layer side than the first planarization film.

11. The liquid crystal panel as described in any one of claims 1, 6, and 9, characterized in that, The spacer protrudes from the opposing substrate toward the liquid crystal layer side. The array substrate is provided with: A first planarization film is disposed on the lower side of the common electrode; as well as A second planarization film is disposed on the upper side of the pixel electrode, on the lower side of the alignment film. The thickness of the first planarization film is greater than that of the insulating film, and it is arranged to overlap with the spacer, the common electrode, and the pixel electrode. The second planarization film has a greater thickness than the insulating film and is configured to overlap with the spacer and the extension.

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