Processing method and device of network on chip and network on chip
By optimizing bit width and virtual channel allocation in the on-chip network, the problems of high latency and low throughput caused by load imbalance are solved, achieving more efficient data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF SCI & TECH OF CHINA
- Filing Date
- 2023-03-31
- Publication Date
- 2026-06-16
AI Technical Summary
Existing on-chip networks suffer from load imbalance, resulting in high latency and low network throughput.
By determining multiple configuration schemes based on the bit width and virtual channel information of each link in the on-chip network, and then selecting a sampling configuration scheme from the multiple configuration schemes based on the target optimization index, bit width allocation information, and virtual channel allocation information, the bit width and virtual channel allocation of the on-chip network are optimized, thereby improving the resource utilization of frequently used links.
By optimizing the bit width and virtual channel allocation of the on-chip network, latency was reduced and network throughput was increased, thereby improving the overall performance of the on-chip network.
Smart Images

Figure CN116360998B_ABST