Sub-pixel circuit, display panel and display device

Abstract

Sub-pixel circuits, display panels, and display devices are disclosed. A sub-pixel circuit for operating a sub-pixel of a display panel can include a light emitting circuit including a light emitting element that receives a high potential voltage, the light emitting circuit configured to control the light emitting element according to a driving voltage and output a control voltage; a reference circuit configured to receive the control voltage and a low potential voltage, and control a driving current flowing through the light emitting element; an amplification circuit configured to compare the control voltage with a data voltage to generate the driving voltage for controlling the light emitting circuit; and an input circuit configured to receive the data voltage and a first scan signal, and control a timing of applying the data voltage to the amplification circuit based on the first scan signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0182401, filed on December 20, 2021, which is incorporated herein by reference for all purposes as fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to subpixel circuits, display panels, and display devices. Background Technology

[0004] Representative display devices that display images based on digital data include liquid crystal displays (LCDs) that use liquid crystals and organic light-emitting diodes (OLEDs) that use organic light-emitting diodes (OLEDs).

[0005] In these display devices, organic light-emitting diode (OLED) displays utilize organic light-emitting diodes (OLEDs), thus offering fast response times and various advantages in contrast, luminous efficiency, brightness, and viewing angle. In this case, the OLEDs can be implemented using either inorganic or organic materials.

[0006] Organic light-emitting diode (OLED) displays include light-emitting diodes arranged in sub-pixels on a display panel, and the brightness represented by each sub-pixel is controlled by controlling the current flowing to the light-emitting diodes to make them emit light.

[0007] Such a display device may have a sub-pixel circuit disposed on the display panel to drive a light-emitting element. For example, the sub-pixel circuit includes a drive transistor for controlling the drive current flowing through the light-emitting element, and at least one scan transistor for controlling the gate-source voltage of the drive transistor according to a scan signal. The scan transistor of the sub-pixel circuit may be controlled by a scan signal output from a gate drive circuit disposed on the substrate of the display panel.

[0008] In this situation, characteristic values ​​such as the threshold voltage or mobility of the driving transistors that make up each sub-pixel may vary depending on the driving time, or the characteristic values ​​of each transistor may deviate due to differences in the driving time of each sub-pixel. This can cause brightness deviations between sub-pixels (brightness non-uniformity), thereby degrading image quality.

[0009] To address the brightness discrepancy between subpixels, display devices have employed techniques for sensing the characteristic values ​​of subpixels (e.g., the threshold voltage or mobility of the driving transistor) and compensating for these characteristic values.

[0010] However, since the light emitting element constituting the sub-pixel can also be deteriorated depending on the use time of the display device, it is difficult to compensate for the deterioration of the light emitting element and the characteristic value of the driving transistor at the same time. SUMMARY

[0011] The inventors of the present disclosure invented a sub-pixel circuit, a display panel, and a display device capable of compensating for the deterioration of the driving transistor and the deterioration of the light emitting element at the same time. Accordingly, embodiments of the present disclosure relate to a sub-pixel circuit, a display panel, and a display device substantially eliminating one or more problems resulting from limitations and disadvantages of the related art.

[0012] Embodiments of the present disclosure can provide a sub-pixel circuit, a display panel, and a display device capable of compensating for the deterioration of the driving transistor and the deterioration of the light emitting element at the same time.

[0013] Embodiments of the present disclosure can provide a sub-pixel circuit, a display panel, and a display device capable of compensating for the deterioration of the driving transistor and the deterioration of the light emitting element at the same time by controlling a driving current flowing through the light emitting element to be proportional to a data voltage.

[0014] Embodiments of the present disclosure can provide a sub-pixel circuit, a display panel, and a display device in which the driving current flowing through the light emitting element is controlled to be proportional to the data voltage regardless of a change in the characteristic value of the driving transistor.

[0015] Additional features and aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings or can be learned by practice of the invention as provided herein. The other features and aspects of the present inventive concept will become apparent from a review of the ensuing description and the claims that follow.

[0016] To achieve these and other aspects of the present inventive concept, as embodied and broadly described herein, a sub-pixel circuit for operating at least one sub-pixel of a plurality of sub-pixels disposed on a display panel can include a light emitting circuit including a light emitting element receiving a high potential voltage, the light emitting circuit configured to control the light emitting element according to a driving voltage and output a control voltage; a reference circuit configured to receive the control voltage and a low potential voltage, and control a driving current flowing through the light emitting element; an amplification circuit configured to compare the control voltage with a data voltage to generate the driving voltage for controlling the light emitting circuit; and an input circuit configured to receive the data voltage and a first scan signal, and control a timing of applying the data voltage to the amplification circuit based on the first scan signal.

[0017] In another aspect, a display panel can include a plurality of sub-pixels and the sub-pixel circuit detailed above.

[0018] In yet another aspect, a display device can include a display panel including a plurality of subpixels and a subpixel circuit for operating at least one of the plurality of subpixels, a gate driving circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, respectively, a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines, respectively, and a timing controller configured to drive the gate driving circuit and the data driving circuit. The subpixel circuit can include a light emitting circuit including a light emitting element receiving a high potential voltage, the light emitting circuit configured to control the light emitting element according to a driving voltage and output a control voltage, a reference circuit configured to receive the control voltage and a low potential voltage and control a driving current flowing through the light emitting element, an amplification circuit configured to compare the control voltage with a data voltage to generate the driving voltage for controlling the light emitting circuit, and an input circuit configured to receive the data voltage and a first scan signal and control a timing of applying the data voltage to the amplification circuit based on the first scan signal.

[0019] According to embodiments of the present disclosure, it is possible to provide a subpixel circuit, a display panel, and a display device capable of simultaneously compensating for deterioration of a driving transistor and deterioration of a light emitting element.

[0020] According to embodiments of the present disclosure, it is possible to provide a subpixel circuit, a display panel, and a display device capable of simultaneously compensating for deterioration of a driving transistor and deterioration of a light emitting element by controlling a driving current flowing through the light emitting element to be proportional to a data voltage.

[0021] According to embodiments of the present disclosure, it is possible to provide a subpixel circuit, a display panel, and a display device in which a driving current flowing through a light emitting element is controlled to be proportional to a data voltage regardless of a change in a characteristic value of a driving transistor.

[0022] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the subject application as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. In the drawings:

[0024] Figure 1 is a diagram schematically illustrating a configuration of a display device according to various example embodiments of the present disclosure;

[0025] Figure 2 is a diagram illustrating an example of a system of a display device according to example embodiments of the present disclosure;

[0026] Figure 3 FIG. 1 is a diagram showing an example of a sub-pixel circuit of a display device.

[0027] Figure 4 FIG. 2 is a signal timing diagram showing an example of externally compensating for threshold voltage of a driving transistor in a display device;

[0028] Figure 5 FIG. 3 is a signal timing diagram showing an example of externally compensating for mobility of a driving transistor in a display device;

[0029] Figure 6 FIG. 4 is a signal timing diagram showing an example of internally compensating for threshold voltage and mobility of a driving transistor in a display device;

[0030] Figure 7 FIG. 5 is a block diagram showing a sub-pixel circuit according to an example embodiment of the present disclosure;

[0031] Figure 8 FIG. 6 is a diagram showing a detailed configuration of a sub-pixel circuit according to an example embodiment of the present disclosure;

[0032] Figure 9 FIG. 7 is an example signal waveform diagram showing an operation of a sub-pixel circuit according to an example embodiment of the present disclosure;

[0033] Figure 10 FIG. 8 is a signal waveform diagram showing that a current flowing through a reference circuit varies depending on a data voltage in a sub-pixel circuit according to an example embodiment of the present disclosure;

[0034] Figure 11A Figure 11B Figure 11C FIG. 9 is a signal waveform diagram showing a current and voltage variation of a sub-pixel circuit when a driving transistor has different threshold voltages in the sub-pixel circuit according to an example embodiment of the present disclosure;

[0035] Figure 12 FIG. 10 is a diagram showing a detailed configuration of another sub-pixel circuit according to an example embodiment of the present disclosure; and

[0036] Figure 13 FIG. 11 is an example signal waveform diagram showing an operation of another sub-pixel circuit according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] ​​The advantages and features of the present disclosure and a method of achieving the same will be clarified by the following example embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, the example embodiments are provided so that the present disclosure can be sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. Also, the scope of protection of the present disclosure is defined by the claims and their equivalents.

[0038] Unless otherwise specified, the same reference numerals will always denote the same elements throughout the following description. The names of the individual elements used in the following description are selected only for the convenience of writing the specification and thus can be different from the names used in the actual product.

[0039] In the following description, detailed descriptions of known functions or configurations related to one aspect of the example embodiments of the present disclosure can be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0040] In the case where the terms "comprise", "have", "include", "contain", "consist of", "consist", "formed of", and the like are used, one or more other elements can be added unless a more restrictive term is used, for example, "only". An element described in the singular is intended to include the plural unless the context clearly indicates otherwise.

[0041] Although the terms "first", "second", A, B, (a), (b), etc. can be used in this document to describe various elements, these elements should not be construed as being limited by these terms, as these terms are not used to define a particular order or priority. These terms are only used to distinguish one element from another element. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element without departing from the scope of the present disclosure.

[0042] In the case where the expression "connected to", "coupled to", "adhered to" another element or layer, or "in contact with", "overlapping" another element or layer is used for an element or layer, unless otherwise specified, the element or layer can not only be directly connected, coupled or adhered to another element or layer, or directly "in contact with", "overlapping" another element or layer, but also indirectly connected, coupled or adhered to another element or layer, or indirectly "in contact with", "overlapping" another element or layer through one or more intermediate elements or layers "disposed" or "inserted" between the elements or layers.

[0043] When the temporal relationship between processes, operations, procedures, steps, events, etc., is described as such as "after", "following", "next", or "before", the relationship covers not only continuous or sequential order but also non-continuous or non-sequential relationships, unless more restrictive terms such as "exactly", "closely", or "directly" are used.

[0044] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to illustrate various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the descriptions in the accompanying drawings.

[0045] When interpreting components, even without an explicit description of such error or tolerance range, the component (including its dimensions and relative dimensions) will be interpreted as including a normal error or tolerance range. Tolerances or error ranges can be caused by various factors, such as process factors, internal or external influences, noise, etc. Furthermore, the term "may" fully encompasses all the meanings of the term "able to".

[0046] Implementations of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings.

[0047] Figure 1 This is a diagram schematically illustrating the configuration of a display device according to various exemplary embodiments of the present disclosure.

[0048] like Figure 1 As shown, a display device 100 according to an example embodiment of the present disclosure may include a display panel 110, in which a plurality of gate lines GL and data lines DL are connected, and a plurality of sub-pixels SP are arranged in a matrix. The display device 100 may further include a gate driving circuit 120 for driving the plurality of gate lines GL, a data driving circuit 130 for supplying data voltage through the plurality of data lines DL, a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130, and a power management circuit 150.

[0049] The display panel 110 displays images based on scan signals transmitted from the gate drive circuit 120 via multiple gate lines GL and data voltages transmitted from the data drive circuit 130 via multiple data lines DL.

[0050] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates and may operate in any known mode, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or rim field switching (FFS) mode. In the case of an organic light-emitting display, the display panel 110 may be implemented as a top-emitting scheme, a bottom-emitting scheme, or a dual-emitting scheme.

[0051] In the display panel 110, a plurality of pixels can be arranged in a matrix form. Each pixel can include sub-pixels SP having different colors, for example, a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The sub-pixels SP can be defined by a plurality of data lines DL and a plurality of gate lines GL, respectively.

[0052] One sub-pixel SP can include, for example, a thin film transistor (TFT) formed at an intersection between one data line DL and one gate line GL, a light emitting element such as an organic light emitting diode charged with a data voltage, and a storage capacitor electrically connected to the light emitting element to maintain a voltage.

[0053] For example, if the display device 100 having a resolution of 2160×3840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 3840 data lines DL can be connected to 2160 gate lines GL and the four sub-pixels WRGB, respectively. Accordingly, 3840×4 = 15360 data lines DL can be provided in the display device 100. Each sub-pixel SP can be provided at an intersection between a corresponding gate line GL and a corresponding data line DL.

[0054] The gate driving circuit 120 can be controlled by the timing controller 140 to sequentially output a scan signal to a plurality of gate lines GL provided in the display panel 110, thereby controlling a driving timing of a plurality of sub-pixels SP.

[0055] In the display device 100 having a resolution of, for example, 2160×3840, sequentially outputting a scan signal to 2160 gate lines GL from a first gate line to a 2160th gate line can be referred to as 2160-phase driving. Sequentially outputting a scan signal to each unit of four gate lines GL, for example, sequentially outputting a scan signal to a fifth gate line to an eighth gate line after sequentially outputting a scan signal to a first gate line to a fourth gate line, is referred to as a 4-phase driving method. In other words, sequentially outputting a scan signal to every N gate lines GL can be referred to as N-phase driving.

[0056] The gate driving circuit 120 can include one or more gate driving integrated circuits (GDICs). Depending on the driving scheme to be implemented, the gate driving circuit 120 can be located on only one side or each of two opposite sides of the display panel 110. The gate driving circuit 120 can be implemented in a gate-in-panel (GIP) form in which it is embedded in a bezel area of the display panel 110.

[0057] The data driving circuit 130 can receive image data DATA from the timing controller 140 and convert the received image data DATA into an analog data voltage. Then, as the data voltage can be output to each data line DL according to the timing of a scan signal applied to a corresponding gate line GL, each sub-pixel SP connected to the data line DL can display a light emission signal having a luminance corresponding to the data voltage.

[0058] Likewise, the data driving circuit 130 can include one or more source driving integrated circuits SDIC. The source driving integrated circuits SDIC can be connected to bonding pads of the display panel 110 in a tape automated bonding (TAB) type or a chip on glass (COG) type, or directly disposed on the display panel 110.

[0059] In some cases, each source driving integrated circuit SDIC can be integrated and disposed on the display panel 110. Also, each source driving integrated circuit SDIC can be implemented in a chip on film (COF) type. In this case, each source driving integrated circuit SDIC can be mounted on a circuit film, and can be electrically connected to a corresponding data line DL of the display panel 110 through the circuit film.

[0060] The timing controller 140 can provide various control signals to the gate driving circuit 120 and the data driving circuit 130, and can control the operations of the gate driving circuit 120 and the data driving circuit 130. In other words, the timing controller 140 can control the gate driving circuit 120 to output a scan signal according to a timing implemented in each frame, while on the other hand, can transfer image data DATA received from an external device (for example, via a host system 200) to the data driving circuit 130.

[0061] In this case, the timing controller 140 receives several timing signals along with the image data DATA from the external host system 200, the timing signals including, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a master clock MCLK.

[0062] The host system 200 can be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device, but the present application is not limited thereto.

[0063] Accordingly, the timing controller 140 can generate control signals according to various timing signals received from the host system 200, and can transfer the control signals to the gate driving circuit 120 and the data driving circuit 130.

[0064] For example, the timing controller 140 can output several gate control signals including, for example, a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE to control the gate driving circuit 120. The gate start pulse GSP can control the timing at which one or more gate driver integrated circuits GDIC constituting the gate driving circuit 120 start operation. The gate clock GCLK is a clock signal commonly input to the one or more gate driver integrated circuits GDIC and can control the shift timing of the scan signal. The gate output enable signal GOE can specify timing information regarding the one or more gate driver integrated circuits GDIC.

[0065] The timing controller 140 can output various data control signals including, for example, a source start pulse SSP, a source sampling clock SCLK, and a source output enable signal SOE to control the data driving circuit 130. The source start pulse SSP can control the timing at which one or more source driver integrated circuits SDIC constituting the data driving circuit 130 start data sampling. The source sampling clock SCLK is a clock signal that can control the timing at which data is sampled in the source driver integrated circuits SDIC. The source output enable signal SOE can control the output timing of the data driving circuit 130.

[0066] The display device 100 can further include a power management circuit 150 that supplies various voltages or currents to, for example, the display panel 110, the gate driving circuit 120, and the data driving circuit 130 or controls various voltages or currents to be supplied.

[0067] The power management circuit 150 can adjust a direct current (DC) input voltage Vin provided from the host system 200 to generate power required to drive the display panel 100, the gate driving circuit 120, and the data driving circuit 130.

[0068] The sub-pixels SP can be positioned at intersections between corresponding gate lines GL and corresponding data lines DL, and a light emitting element can be disposed in each sub-pixel SP. For example, an organic light emitting diode display can include a light emitting element such as an organic light emitting diode in each sub-pixel SP and can display an image by controlling a current flowing to the light emitting element according to a data voltage.

[0069] The display device 100 can be one of various types of devices such as a liquid crystal display, an organic light emitting diode display, or a plasma display panel.

[0070] Figure 2 FIG. 1 is a diagram illustrating an example of a system of a display device according to an example embodiment of the present disclosure.

[0071] As Figure 2As illustrated, in the display device 100 according to the example embodiment of the disclosure, the source driving integrated circuits SDIC included in the data driving circuit 130 can be implemented in a chip on film (COF) type among various types (e.g., TAB, COG, or COF), and the gate driving circuit 120 can be implemented in a gate in panel (GIP) type among various types (e.g., TAB, COG, COF, or GIP).

[0072] When the gate driving circuit 120 is implemented in the GIP type, the plurality of gate driving integrated circuits GDIC included in the gate driving circuit 120 can be directly formed in the bezel area of the display panel 110. In this case, the gate driving integrated circuits GDIC can receive various signals (e.g., a clock signal, a gate high signal, a gate low signal, etc.) for generating a scan signal through the gate driving related signal lines provided in the bezel area.

[0073] Similarly, one or more source driving integrated circuits SDIC included in the data driving circuit 130 can each be mounted on the source film SF, and one side of the source film SF can be electrically connected with the display panel 110. Lines for electrically connecting the source driver integrated circuits SDIC and the display panel 110 can be provided on the source film SF.

[0074] The display device 100 can include at least one source printed circuit board SPCB for circuit connection between the plurality of source driving integrated circuits SDIC and other devices, and can include a control printed circuit board CPCB for mounting control components and various electronic devices.

[0075] The other side of the source film SF on which the source driving integrated circuits SDIC are mounted can be connected to the at least one source printed circuit board SPCB. In other words, one side of the source film SF on which the source driving integrated circuits SDIC are mounted can be electrically connected with the display panel 110, and the other side thereof can be electrically connected with the source printed circuit board SPCB.

[0076] The timing controller 140 and the power management circuit (power management IC) 150 can be mounted on the control printed circuit board CPCB. The timing controller 140 can control operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 can supply a power voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120 and can control the supplied voltage or current.

[0077] The at least one source printed circuit board SP CB and the control printed circuit board CPCB can be electrically connected by at least one connection member. The connection member can include, for example, a flexible printed circuit FPC or a flexible flat cable FFC. The at least one source printed circuit board SP CB and the control printed circuit board CPCB can be integrated into a single printed circuit board.

[0078] The display device 100 can further include a setting plate 170 electrically connected to the control printed circuit board CPCB. In this case, the setting plate 170 can also be referred to as a power plate. A main power management circuit 160 for managing overall power of the display device 100 can be provided on the setting plate 170. The main power management circuit 160 can interact with the power management circuit 150.

[0079] In the example display device 100 thus configured, a power voltage can be generated in the setting plate 170 and delivered to the power management circuit 150 in the control printed circuit board CPCB. The power management circuit 150 can deliver the power voltage for display driving or characteristic value sensing to the source printed circuit board SP CB through the flexible printed circuit FPC or the flexible flat cable FFC. The power voltage delivered to the source printed circuit board SP CB can be supplied through the source driving integrated circuit SDIC to emit light or sense a specific sub-pixel SP in the display panel 110.

[0080] Each sub-pixel SP disposed in the display panel 110 in the display device 100 can include a light emitting element and a circuit element for driving the light emitting element, for example, an organic light emitting diode, for example, a driving transistor.

[0081] The type and number of the circuit elements constituting each sub-pixel SP can vary depending on the function to be provided and the design scheme.

[0082] Figure 3 FIG. 1 is a diagram illustrating an example of a sub-pixel circuit of a display device.

[0083] As shown in FIG. 1, an example sub-pixel circuit can include one or more transistors and a capacitor and can have a light emitting element disposed therein. Figure 3

[0084] For example, the sub-pixel circuit can include a driving transistor DRT, a scan transistor SCT, a sensing transistor SENT, a storage capacitor Cst, and a light emitting element ED.

[0085] The driving transistor DRT can include a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT can be a gate node to which a data voltage Vdata is applied from the data driving circuit 130 through a corresponding data line DL when the scan transistor SCT is turned on.​

[0086] The second node N2 of the drive transistor DRT can be electrically connected with the anode electrode of the light emitting diode ED and can be one of a source node or a drain node.

[0087] The third node N3 of the drive transistor DRT can be electrically connected with the drive voltage line DVL to which a high potential voltage EVDD is applied and can be the other of a drain node and a source node.

[0088] In this case, during a display driving period, a high potential voltage EVDD required for displaying an image can be supplied to the drive voltage line DVL. For example, the high potential voltage EVDD for displaying an image can be 27 V.

[0089] The scan transistor SCT can be electrically connected between the first node N1 of the drive transistor DRT and the data line DL, and a corresponding gate line GL can be connected to the gate node of the scan transistor SCT. Accordingly, the scan transistor SCT can operate according to a first scan signal SCAN1 supplied through the gate line GL. When turned on, the scan transistor SCT can transfer a data voltage Vdata supplied through the data line DL to the gate node (i.e., the first node N1) of the drive transistor DRT, thereby controlling the operation of the drive transistor DRT.

[0090] The sensing transistor SENT can be electrically connected between the second node N2 of the drive transistor DRT and the reference voltage line RVL, and a corresponding gate line GL can be connected to the gate node of the sensing transistor SENT. The sensing transistor SENT can operate according to a second scan signal SCAN2 supplied through the gate line GL. When the sensing transistor SENT is turned on, a reference voltage Vref supplied through the reference voltage line RVL can be transmitted to the second node N2 of the drive transistor DRT.

[0091] In other words, when the scan transistor SCT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the voltage of the second node N2 of the drive transistor DRT can be controlled so that a current for driving the light emitting diode ED can be supplied.

[0092] The gate nodes of the scan transistor SCT and the sensing transistor SENT can be commonly connected to one gate line GL, or can be connected to different gate lines GL. An example in which the scan transistor SCT and the sensing transistor SENT are connected to different gate lines GL is illustrated. In this example case, the scan transistor SCT and the sensing transistor SENT can be independently controlled by the first scan signal SCAN1 and the second scan signal SCAN2, respectively, which are transferred through different gate lines GL.

[0093] On the other hand, if the scan transistor SCT and the sense transistor SENT are commonly connected to one gate line GL, the scan transistor SCT and the sense transistor SENT can be simultaneously controlled by the first scan signal SCAN1 or the second scan signal SCAN2 transmitted through the one gate line GL, and the aperture ratio of the sub-pixel SP can increase.

[0094] Each transistor provided in the sub-pixel circuit can be an N-type transistor or a P-type transistor. Figure 3 In the illustrated example, the transistors are N-type transistors.

[0095] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the drive transistor DRT and can hold the data voltage Vdata during one frame.

[0096] The storage capacitor Cst can also be connected between the first node N1 and the third node N3 of the drive transistor DRT, according to the type of the drive transistor DRT. The anode electrode of the light emitting diode ED can be electrically connected with the second node N2 of the drive transistor DRT, and the low potential voltage EVSS can be applied to the cathode electrode of the light emitting diode ED.

[0097] The low potential voltage EVSS can be a ground voltage or a voltage higher or lower than the ground voltage. The low potential voltage EVSS can vary according to the driving state. For example, the low potential voltage EVSS at the time of display driving and the low potential voltage EVSS at the time of sensing driving can be set to be different from each other.

[0098] The scan transistor SCT and the sense transistor SENT can be referred to as switching transistors controlled by the scan signals SCAN1 and SCAN2, respectively.

[0099] The structure of the sub-pixel SP can further include one or more additional transistors, or in some cases, one or more additional capacitors.

[0100] In this case, in order to effectively sense the characteristic value (e.g., threshold voltage or mobility) of the drive transistor DRT, the display device 100 can use a method for measuring the current flow caused by the voltage charged to the storage capacitor Cst during the characteristic value sensing period of the drive transistor DRT. This is referred to as current sensing.

[0101] In other words, the characteristic value or the change in the characteristic value of the drive transistor DRT in the sub-pixel SP can be derived by measuring the current flow caused by the voltage charged to the storage capacitor Cst during the characteristic value sensing period of the drive transistor DRT.

[0102] In this case, the reference voltage line RVL can be used not only to deliver the reference voltage Vref but also to serve as a sensing line for sensing a characteristic value of the driving transistor DRT in the sub-pixel. Accordingly, the reference voltage line RVL can also be referred to as a sensing line or a sensing channel.

[0103] More specifically, the characteristic value of the driving transistor DRT or the change in the characteristic value can correspond to a difference between the gate node voltage and the source node voltage of the driving transistor DRT.

[0104] The compensation for the characteristic value of the driving transistor DRT can be performed through external compensation that senses and compensates for the characteristic value of the driving transistor DRT using an external compensation circuit. Alternatively, the compensation can be performed through internal compensation that senses and compensates for the characteristic value of the driving transistor DRT inside the sub-pixel SP, instead of performing the compensation using an additional external configuration.

[0105] In this case, the external compensation can be performed before the display device 100 is shipped, and the internal compensation can be performed after the display device 100 is shipped. However, even after the display device 100 is shipped, the internal compensation and the external compensation can be performed together.

[0106] Figure 4 is a signal timing diagram illustrating an example of performing external compensation for a threshold voltage of a driving transistor in a display device.

[0107] As Figure 4 indicated, the sensing of the threshold voltage Vth of the driving transistor DRT in the example display device 100 can be performed in an initialization phase INITIAL, a tracking phase TRACKING, and a sampling phase SAMPLING.

[0108] In this case, since the scan transistor SCT and the sensing transistor SENT are simultaneously turned on and turned off for sensing the threshold voltage Vth of the driving transistor DRT, the first scan signal SCAN1 and the second scan signal SCAN2 can be applied together through one gate line GL, or the first scan signal SCAN1 and the second scan signal SCAN2 can be simultaneously applied through different gate lines GL, respectively.

[0109] The initialization phase INITIAL is a period in which the second node N2 of the driving transistor DRT can be charged with the reference voltage Vref to sense the threshold voltage Vth of the driving transistor DRT, and the first scan signal SCAN1 and the second scan signal SCAN2 having a high level can be applied through the gate line GL.

[0110] The tracking phase TRACKING is a period in which the charge can be stored in the storage capacitor Cst after the charging of the second node N2 of the driving transistor DRT is completed.

[0111] The sampling phase SAMPLING is a period in which the current flow from the charge stored in the storage capacitor Cst is detected after the storage capacitor Cst of the driving transistor DRT is charged.

[0112] If the first scan signal SCAN1 and the second scan signal SCAN2 at the on level are applied at the same time in the initialization phase INITIAL, the scan transistor SCT can be turned on. Accordingly, the first node N1 of the driving transistor DRT can be initialized to the sensing data voltage Vdata_sen for sensing the threshold voltage Vth.

[0113] The sensing transistor SENT can also be turned on by the first scan signal SCAN1 and the second scan signal SCAN2 at the on level, and the reference voltage Vref can be applied through the reference voltage line RVL. Accordingly, the second node N2 of the driving transistor DRT can be initialized to the reference voltage Vref.

[0114] In the tracking phase TRACKING, the voltage of the second node N2 of the driving transistor DRT reflecting the threshold voltage Vth of the driving transistor DRT can be tracked. To this end, in the tracking phase TRACKING, the scan transistor SCT and the sensing transistor SENT can be maintained in the on state, and the reference voltage Vref applied through the reference voltage line RVL can be cut off.

[0115] Accordingly, the second node N2 of the driving transistor DRT can be floated, and the voltage at the second node N2 of the driving transistor DRT can start to rise from the reference voltage Vref. In this case, since the sensing transistor SENT is turned on, the increase in the voltage at the second node N2 of the driving transistor DRT can cause the voltage on the reference voltage line RVL to increase.

[0116] In this process, the voltage at the second node N2 of the driving transistor DRT can increase and then saturate. The saturation voltage at which the second node N2 of the driving transistor DRT reaches the saturation state can correspond to the difference (Vdata_sen-Vth) between the sensing data voltage Vdata_sen for sensing the threshold voltage Vth and the threshold voltage Vth of the driving transistor DRT.

[0117] In the sampling phase SAMPLING, the first scan signal SCAN1 and the second scan signal SCAN2 to the gate line GL can be maintained at a high level, and the charge stored in the storage capacitor Cst of the driving transistor DRT can be detected by a characteristic value detection circuit included in the data driving circuit 130.

[0118] Figure 5 is a signal timing chart illustrating an example of externally compensating for mobility of a driving transistor in a display device.

[0119] As illustrated in Figure 5 , sensing of the mobility of the driving transistor DRT in the example display device 100 can be performed in the initialization phase INITIAL, the tracking phase TRACKING, and the sampling phase SAMPLING, as with sensing of the threshold voltage Vth.

[0120] In the initialization phase INITIAL, the scan transistor SCT can be turned on by the first scan signal SCAN1 at an on level, so that the first node N1 of the driving transistor DRT can be initialized to a data voltage Vdata_sen for mobility sensing. Further, the sensing transistor SENT can be turned on by the second scan signal SCAN2 at an on level, and in this state, the second node N2 of the driving transistor DRT can be initialized to a reference voltage Vref.

[0121] The tracking phase TRACKING is a phase for tracking the mobility of the driving transistor DRT. The mobility of the driving transistor DRT can indicate a current driving capability of the driving transistor DRT, and can be calculated by tracking the voltage of the second node N2 of the driving transistor DRT throughout the tracking phase TRACKING.

[0122] In the tracking phase TRACKING, the scan transistor SCT can be turned off by the first scan signal SCAN1 at an off level, and a switch through which the reference voltage Vref is applied to the reference voltage line RVL can be turned off. Accordingly, both the first node N1 and the second node N2 of the driving transistor DRT can be floated, and the voltage of both the first node N1 and the second node N2 of the driving transistor DRT can increase.

[0123] In particular, since the voltage at the second node N2 of the driving transistor DRT can be initialized to the reference voltage Vref, it can increase from the reference voltage Vref. In this case, since the sensing transistor SENT is on, the increase in the voltage at the second node N2 of the driving transistor DRT can cause the voltage on the reference voltage line RVL to increase.

[0124] In the sampling phase SAMPLING, the characteristic value sensing circuit can detect the voltage of the second node N2 of the drive transistor DRT at a predetermined amount of time Δt after the voltage at the second node N2 starts to increase.

[0125] In this case, the sensing voltage detected by the characteristic value sensing circuit can indicate the voltage Vref+ΔV, i.e., the reference voltage Vref plus the predetermined voltage ΔV. The mobility of the drive transistor DRT can be calculated based on the thus-detected sensing voltage Vref+ΔV, the known reference voltage Vref, and the amount of time Δt of the voltage increase ΔV of the second node N2.

[0126] In other words, the mobility of the drive transistor DRT is proportional to the voltage change ΔV / Δt per unit time on the reference voltage line RVL throughout the tracking phase TRACKING and the sampling phase SAMPLING. Thus, the mobility of the drive transistor DRT can be proportional to the slope of the voltage waveform on the reference voltage line RVL.

[0127] Figure 6 is a signal timing diagram illustrating an example of internal compensation of a threshold voltage and a mobility of a drive transistor in a display device.

[0128] As Figure 6 indicated, the internal compensation of the characteristic values of the drive transistor DRT in the display device 100 can be performed in the initialization phase INITIAL, the threshold voltage sensing phase Vth SENSING, the mobility compensation phase μCOMPENSATION, and the emission phase EMISSION.

[0129] In the initialization phase INITIAL, a second scan signal SCAN2 of a high level can be input to turn on the sensing transistor SENT, thereby initializing the voltage of the second node N2 (i.e., the source node voltage of the drive transistor DRT) to the reference voltage Vref.

[0130] Thereafter, a first scan signal SCAN1 of a high level can be provided to turn on the scan transistor SCT, and a data voltage Vdata can be provided to the first node N1 (i.e., the gate node of the drive transistor DRT) to turn on the drive transistor DRT. Subsequently, if the data voltage Vdata decreases to the level of the bias voltage Vos, the voltage of the first node N1 can become the level of the bias voltage Vos.

[0131] If a low level of the second scan signal SCAN2 is applied to turn off the sensing transistor SENT in the threshold voltage sensing phase Vth SENSING, the voltage of the second node N2 can rise to a voltage that is the difference between the bias voltage Vos of the driving transistor DRT and the threshold voltage Vth, such that the storage capacitor Cst is charged with a voltage of the threshold voltage Vth level.

[0132] In the mobility compensation phase μCOMPENSATION, the voltage of the first node N1 can be increased to the level of the data voltage Vdata by applying the gray scale to be displayed through the display panel 110, i.e., the corresponding data voltage Vdata. Accordingly, the second node N2 can be gradually charged according to the mobility (μ) characteristics of the driving transistor DRT. Accordingly, the storage capacitor Cst can store the difference voltage, i.e., the sum of the data voltage Vdata and the threshold voltage Vth minus the voltage variation ΔV according to the bias voltage Vos and the mobility μ.

[0133] In the emission phase EMISSION, a low level of the first scan signal SCAN1 can be applied to turn off the scan transistor SCT, such that the driving transistor DRT applies a current whose threshold voltage Vth and mobility μ have been corrected through the voltage level stored in the storage capacitor Cst to the light emitting diode EL.

[0134] Such internal compensation or external compensation can be performed after a power-on signal is generated in the display device 100 and before display driving starts. For example, if the power-on signal is applied to the display device 100, the timing controller 140 can load various parameters for driving the display panel 110, and then can drive the display.

[0135] In this case, the parameters for driving the display panel 110 can include information about sensing and compensation of the characteristic values previously performed on the display panel 110. In the parameter loading process, sensing and compensation of the characteristic values (threshold voltage and mobility) of the driving transistor DRT can be performed. As described above, the process of sensing the characteristic values in the parameter loading process after the power-on signal is generated can be referred to as a power-on sensing process.

[0136] Alternatively, a period in which the characteristic values of the driving transistor DRT are sensed and compensated can be made after a power-off signal of the display device 100 is generated. For example, when the power-off signal is generated in the display device 100, the timing controller 140 can cut off the data voltage supplied to the display panel 110, and can sense the characteristic values of the driving transistor DRT for a predetermined time. As such, the sensing process for sensing the characteristic values in a state in which the data voltage is cut off when the power-off signal is generated can be referred to as a power-off sensing process.

[0137] Further, the sensing and compensation of the characteristic value of the driving transistor DRT can be performed in real time while driving the display. This sensing process is referred to as a real-time (RT) sensing process. In the real-time sensing process, the sensing process can be performed on one or more subpixels SP in one or more subpixel SP rows during each blank period during a display driving period.

[0138] In other words, during a display driving period in which an image is displayed on the display panel 110, a blank period in which no data voltage is supplied to the subpixels SP can exist within a frame or between a frame and a next frame. In the blank period, the characteristic value sensing and compensation of one or more subpixels SP can be performed.

[0139] As such, when the sensing process is performed in the blank period, the row of the subpixels SP on which the sensing process is performed can be randomly selected. Thus, after the sensing process is performed in the blank period, the abnormality that can occur in the display driving period can be mitigated. During the display driving period after the sensing process is performed during the blank period, the recovery data voltage can be supplied to the subpixels SP on which the sensing process has been performed. Thus, in the display driving period after the sensing process in the blank period, the abnormality in the row of the subpixels SP on which the sensing process has been completed can be further mitigated.

[0140] In this case, because saturation of the voltage at the second node N2 of the driving transistor DRT can take a relatively long time, the threshold voltage sensing of the driving transistor DRT can take a long time, and thus the sensing and compensation of the driving transistor DRT can be mainly performed as the power-off sensing process. In contrast, because the mobility sensing of the driving transistor DRT can take a relatively short time compared to the threshold voltage sensing process, the mobility sensing and compensation can be performed as the real-time sensing process.

[0141] However, in the display device 100, the light emitting element ED constituting the subpixel can also be degraded depending on the driving time. The above-described internal compensation and external compensation can not be able to compensate for the degradation of the light emitting element ED and the characteristic value of the driving transistor DRT at the same time.

[0142] Therefore, embodiments of the disclosure provide a subpixel circuit, a display panel, and a display device capable of compensating for the degradation of the light emitting element ED and the degradation of the driving transistor DRT at the same time by presenting a new subpixel circuit controlled such that a driving current flowing through the light emitting element ED can be proportional to a data voltage Vdata.

[0143] Therefore, a subpixel circuit, a display panel, and a display device in which a driving current flowing through a light emitting element ED can be maintained constant despite a change in a characteristic value of a driving transistor DRT can be provided.

[0144] Figure 7 is a block diagram illustrating a sub-pixel circuit according to an example embodiment of the present disclosure.

[0145] As Figure 7 indicated, the sub-pixel circuit 300 according to an example embodiment of the present disclosure can include a light emitting circuit 310, a reference circuit 320, an amplification circuit 330, and an input circuit 340.

[0146] The light emitting circuit 310 can receive a high potential voltage EVDD to display an image, and can control the operation of the light emitting element ED according to a driving voltage Vd at an output node of the amplification circuit 330. When the light emitting element ED is turned on, a driving current Id will flow through the light emitting circuit 310.

[0147] During a display driving period, the high potential voltage EVDD can have a level required to display an image. For example, the high potential voltage EVDD to display an image can be 27 V, but the present disclosure is not limited thereto.

[0148] The reference circuit 320 can be positioned between a control voltage Vc, which is an output voltage of the light emitting circuit 310, and a low potential voltage EVSS, and can control a change in the driving current Id. For example, when the control voltage Vc corresponding to the output node of the light emitting circuit 310 has the same potential as the data voltage Vdata, the current I3 applied to the amplification circuit 330 can become 0, so that the driving current Id has the same value as a reference current Iref flowing through the reference circuit 320.

[0149] The low potential voltage EVSS can be a ground voltage or a voltage higher or lower than the ground voltage. The low potential voltage EVSS can vary according to a driving state. For example, the low potential voltage EVSS at the time of display driving and the low potential voltage EVSS at the time of sensing driving can be set to be different from each other.

[0150] The amplification circuit 330 can compare the control voltage Vc with the data voltage Vdata to generate a driving voltage Vd for controlling the operation of the light emitting circuit 310. For example, the amplification circuit 330 can be formed of an operational amplifier having an inverting input terminal (-) to which the control voltage Vc of the output node of the light emitting circuit 310 is applied and a non-inverting input terminal (+) to which the data voltage from the input circuit 340 is applied.

[0151] The resistance value of the reference circuit 320 can decrease in inverse proportion to the driving voltage Vd of the amplification circuit 330. When the control voltage Vc is greater than the data voltage Vdata, the driving voltage Vd corresponding to the output node of the amplification circuit 330 can decrease.

[0152] Accordingly, when the control voltage Vc and the data voltage Vdata have the same level, the operation of the amplification circuit 330 can stop, and the control voltage Vc can be maintained at the same level as the data voltage Vdata.

[0153] The input circuit 340 can determine the time at which the data voltage Vdata is applied to the non-inverting input terminal (+) of the amplification circuit 330 through the scan signal SCAN.

[0154] In other words, the example sub-pixel circuit 300 of the present disclosure can be controlled to allow the control voltage Vc to be maintained at a level proportional to the data voltage Vdata, so that the drive current Id flowing through the light emitting element ED is proportional to the level of the data voltage Vdata. Accordingly, regardless of the deterioration of the light emitting element ED or the characteristic value of the drive transistor, a current proportional to the data voltage Vdata can flow through the light emitting element ED, thereby maintaining the brightness of the display device 100 continuously.

[0155] Figure 8 is a diagram illustrating a detailed configuration of a sub-pixel circuit according to an example embodiment of the present disclosure.

[0156] As Figure 8 indicated, the sub-pixel circuit 300 according to an example embodiment of the present disclosure can include a light emitting circuit 310, a reference circuit 320, an amplification circuit 330, and an input circuit 340. Described below is an example sub-pixel circuit 300, for example, among a plurality of sub-pixels constituting the display panel 110, to which the nth scan signal SCAN(n) is applied.

[0157] The light emitting circuit 310 can include a light emitting element ED having an anode electrode to which a high potential voltage EVDD can be applied, and a drive transistor Td having a drain node connected to a cathode electrode of the light emitting element, and a gate node to which a drive voltage Vd of the amplification circuit 330 can be applied.

[0158] When the light emitting element ED is turned on by the high potential voltage EVDD and the drive transistor Td is turned on by the drive voltage Vd of the amplification circuit 330, a drive current Id can flow through the light emitting circuit 310.

[0159] The reference circuit 320 can include a reference transistor Tref having a drain node and a gate node to which a control voltage Vc can be applied, and a source node to which a low potential voltage EVSS can be applied.

[0160] In this case, when the control voltage Vc and the data voltage Vdata have the same level of potential, the entire driving current Id flowing through the light emitting circuit 310 can flow through the reference circuit 320, and the driving current Id can have the same value as the reference current Iref.

[0161] The amplification circuit 330 can include a control transistor Tc, a reset transistor Trst, and a first capacitor Cl. The control transistor Tc can have a gate node to which the control voltage Vc can be applied and a source node connected to a gate node of the driving transistor Td. The reset transistor Trst can have a drain node to receive the reset voltage Vrst, a gate node to which the (n-1)th scan signal SCAN(n-1) can be applied, and a source node common with the control transistor Tc. The first capacitor Cl can be connected to the source node of the control transistor Tc to transfer the power voltage Vp for driving the driving transistor Td.

[0162] The reset voltage Vrst can be applied at a voltage level configured to turn off the driving transistor Td.

[0163] The power voltage Vp can be applied at a level capable of driving the driving transistor Td at a certain point of time, and the level can be changed by the charge stored in the first capacitor Cl. In other words, the power voltage Vp can not continuously maintain a constant voltage level.

[0164] The input circuit 340 can include a switching transistor Tsw and a second capacitor C2. The switching transistor Tsw can have a gate node to which the nth scan signal SCAN(n) can be applied, a drain node to which the data voltage Vdata can be applied, and a source node connected to a drain node of the control transistor Tc. The second capacitor C2 can be connected between the source node of the switching transistor Tsw and a low potential voltage EVSS.

[0165] Accordingly, the input circuit 340 can supply the data voltage Vdata to the amplification circuit 330 through the nth scan signal SCAN(n). The second capacitor C2 can be used to stably transfer the data voltage Vdata.

[0166] The transistors Td, Tref, Tc, Trst, and Tsw constituting the example pixel circuit 300 can be P-type transistors or N-type transistors.

[0167] P-type transistors are relatively more reliable than N-type transistors. In the case of P-type transistors, since the driving transistor Td can be fixed to the high potential voltage EVDD during a period in which the light emitting element ED emits light, a current flowing through the light emitting element ED can be stably supplied without significant fluctuation.

[0168] When operating in the saturation region, the P-type transistor can flow a constant current regardless of the change in threshold voltage, thereby providing relatively high reliability.

[0169] On the other hand, since the N-type transistor uses electrons rather than holes as carriers, the N-type transistor has a higher mobility than the P-type transistor, thereby enabling an increase in switching speed.

[0170] The N-type transistor can be an oxide transistor formed of an oxide semiconductor (e.g., a transistor having a channel formed of an oxide semiconductor such as indium, gallium, zinc oxide, or IGZO). The P-type transistor can be a silicon transistor formed of a semiconductor such as silicon (e.g., a transistor having a polysilicon channel formed by a low-temperature process called LTPS or low-temperature polysilicon).

[0171] Described here is an example in which the transistors Td, Tref, Tc, Trst, and Tsw constituting the sub-pixel circuit 300 are N-type transistors.

[0172] The terms "source node" and "drain node" of a transistor can be used interchangeably depending on the input voltage.

[0173] Figure 9 is an example signal waveform diagram illustrating the operation of the sub-pixel circuit according to an example embodiment of the present disclosure.

[0174] Referring to Figure 9 , the operation of the sub-pixel circuit 300 driven by the nth scan signal SCAN(n) in the display device 100 according to an example embodiment of the present disclosure is described below.

[0175] If the reset transistor Trst is turned on by the (n-1)th scan signal SCAN(n-1), the reset voltage Vrst can be applied to the gate node of the driving transistor Td to turn off the driving transistor Td. The power voltage Vp can decrease to the level of the reset voltage Vrst.

[0176] Thereafter, if the nth scan signal SCAN(n) is applied to turn on the switching transistor Tsw, the data voltage Vdata can be applied to the second capacitor C2. In this case, the power voltage Vp can increase at a constant slope. If the power voltage Vp reaches the threshold voltage level of the driving transistor Td, the driving transistor Td can be turned on, and the driving current Id flowing through the light emitting element ED can be transferred to the reference circuit 320 through the driving transistor Td.

[0177] The control voltage Vc corresponding to the output voltage of the light emitting circuit 310 can increase through the driving current Id flowing from the light emitting circuit 310 to the reference circuit 320.

[0178] If the control voltage Vc increases and reaches the sum Vdata+Vth(Tc) of the data voltage Vdata and the threshold voltage Vth(Tc) of the control transistor Tc, the control transistor Tc can be turned on. If the control transistor Tc is turned on, the charge stored in the first capacitor C1 can move to the second capacitor C2, so that the drive current Id flowing through the drive transistor Td can decrease. Accordingly, the control voltage Vc can decrease, and the control transistor Tc can be turned off.

[0179] As the control transistor Tc is repeatedly turned on and off for a short period, the control voltage Vc can maintain the level of the sum Vdata+Vth(Tc) of the data voltage Vdata and the threshold voltage Vth(Tc) of the control transistor Tc.

[0180] In this state, the reference current Iref flowing through the reference transistor Tref in the saturation region can be expressed as follows:

[0181] Iref = K * [(Vc - Vth(Tref)] 2 = K * [(Vdata + Vth(Tc) - Vth(Tref)] 2

[0182] Here, K = Cox * (W / L) * μ, W and L respectively denote the channel width and length of the reference transistor Tref, Cox denotes the capacitance of the gate insulating film, and μ denotes the mobility of the reference transistor Tref.

[0183] In this case, if the deposition conditions of the control transistor Tc and the reference transistor Tref positioned adjacent to each other are maintained to be the same, the threshold voltage Vth(Tc) of the control transistor Tc and the threshold voltage Vth(Tref) of the reference transistor Tref can have the same value. In other words, the control transistor Tc and the reference transistor Tref can be formed to have the same threshold voltage Vth by maintaining the thickness and composition ratio of the gate node, the source node, the drain node, and the insulating film located therebetween under the same conditions in the process of depositing the control transistor Tc and the reference transistor Tref.

[0184] If the threshold voltage Vth(Tc) of the control transistor Tc and the threshold voltage Vth(Tref) of the reference transistor Tref have the same value, the reference current Iref flowing through the reference transistor Tref can be expressed as:

[0185] Iref = K * Vdata 2

[0186] In other words, since both the drive current Id flowing through the light emitting element ED and the reference current Iref flowing through the reference transistor Tref are proportional to the data voltage Vdata, the drive current Id for driving the light emitting element ED can be adjusted by the data voltage Vdata regardless of the characteristic value of the light emitting element ED or the characteristic value of the drive transistor Td.

[0187] On the other hand, if the drive transistor Td is an oxide transistor, the threshold voltage Vth can be shifted due to positive bias temperature stress (PBTS). However, in this case, the shift of the threshold voltage Vth can be minimized by increasing the amplitude of the high potential voltage EVDD to increase the drive current Id flowing through the light emitting element ED and reduce the gate-source node voltage of the drive transistor Td.

[0188] For example, the high potential voltage EVDD can be set to 28 V or more to reduce the shift of the threshold voltage Vth of the drive transistor Td due to positive bias temperature stress (PBTS).

[0189] Therefore, the example pixel circuit 300 of the present disclosure can control by allowing the control voltage Vc corresponding to the output voltage of the light emitting circuit 310 to maintain a level corresponding to the sum Vdata+Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata to allow the drive current Id flowing through the light emitting element ED to be proportional to the level of the data voltage Vdata. Therefore, in the example pixel circuit 300 of the present disclosure, a current proportional to the data voltage Vdata can flow through the light emitting element ED regardless of the deterioration of the light emitting element ED or the characteristic value of the drive transistor Td. Therefore, it is possible to provide a display panel 110 and a display device 100 having uniform brightness.

[0190] Figure 10 is a signal waveform diagram showing that the current flowing through the reference circuit according to the example embodiment of the present disclosure varies depending on the data voltage in the sub-pixel circuit.

[0191] As Figure 10 shown, the sub-pixel circuit 300 according to the example embodiment of the present disclosure can be controlled to allow the drive current Id flowing through the light emitting circuit 310 and the reference current Iref flowing through the reference circuit 320 to be proportional to the level of the data voltage Vdata by allowing the control voltage Vc corresponding to the output node of the light emitting circuit 310 to maintain a level corresponding to the sum Vdata+Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata.

[0192] For example, when the control voltage Vc is maintained at a level corresponding to the sum Vdata+Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata, the drive current Id flowing through the light emitting circuit 310 and the reference current Iref flowing through the reference circuit 320 can maintain the same value. In this case, it can be identified that, when the data voltage Vdata is sequentially changed to the levels of 3 V, 2 V, 1 V, 0 V, -1 V, and -2 V, the drive current Id flowing through the light emitting circuit 310 and the reference current flowing through the reference circuit 320 each have a value substantially proportional to the data voltage Vdata.

[0193] Figure 11A 、 Figure 11B and Figure 11C are signal waveform diagrams illustrating changes in current and voltage of a sub-pixel circuit when a drive transistor has different threshold voltages in the sub-pixel circuit according to an example embodiment of the present disclosure.

[0194] As shown in Figure 11A 、 Figure 11B and Figure 11C , in the sub-pixel circuit 300 according to an example embodiment of the present disclosure, a characteristic value such as a threshold voltage of the drive transistor Td can change as a drive time increases.

[0195] In consideration of this, in a case where the threshold voltage of the drive transistor Td has a reference voltage and increases by 1 V from the reference voltage, changes in the drive voltage Vd corresponding to the output voltage of the amplification circuit 330, the drive current Id flowing through the light emitting circuit 310, and the control voltage Vc corresponding to the output voltage of the light emitting circuit 310 are measured.

[0196] It can be determined that, when the threshold voltage of the drive transistor Td increases, the level of the drive voltage Vd corresponding to the output voltage of the amplification circuit 330 changes Figure 11A .

[0197] However, although the threshold voltage of the drive transistor Td increases, the control voltage Vc corresponding to the output voltage of the light emitting circuit 310 always maintains a level corresponding to the sum Vdata+Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata Figure 11B .

[0198] Therefore, although the threshold voltage of the drive transistor Td changes, the drive current Id flowing through the light emitting circuit 310 and the reference current Iref flowing through the reference circuit 320 can maintain constant values Figure 11C .

[0199] Thus, since the drive current Id flowing through the light emitting element ED has a value proportional to the data voltage Vdata regardless of the deterioration of the light emitting element ED or the characteristic value of the drive transistor Td in the example sub-pixel circuit 300 of the present disclosure, the display device 100 can maintain uniform luminance despite an increase in the drive time.

[0200] In the example sub-pixel circuit 300 of the present disclosure, the amplification circuit 330 can alternatively reset the drive transistor Td by controlling the power voltage Vp instead of implementing the reset transistor Trst.

[0201] Figure 12 is a view showing a detailed configuration of another sub-pixel circuit according to an example embodiment of the present disclosure.

[0202] As Figure 12 indicated, the sub-pixel circuit 300 according to an example embodiment of the present disclosure can include a light emitting circuit 310, a reference circuit 320, an amplification circuit 330, and an input circuit 340. Described below is an example in which an nth scan signal SCAN(n) is applied between a plurality of sub-pixels constituting the display panel 110.

[0203] The light emitting circuit 310 can include a light emitting element ED and a drive transistor Td. The light emitting element ED can have an anode electrode to which a high potential voltage EVDD can be applied. The drive transistor Td can have a drain node connected to a cathode electrode of the light emitting element ED and a gate node to which a drive voltage Vd of the amplification circuit 330 can be applied.

[0204] When the light emitting element ED is turned on by the high potential voltage EVDD and the drive transistor Td is turned on by the drive voltage Vd of the amplification circuit 330, a drive current Id can flow through the light emitting circuit 310.

[0205] The reference circuit 320 can include a reference transistor Tref having a drain node and a gate node to which a control voltage Vc corresponding to an output voltage of the light emitting circuit 310 can be applied and a source node to which a low potential voltage EVSS can be applied.

[0206] In this case, when the control voltage Vc and the data voltage Vdata have the same level of potential, the entire drive current Id flowing through the light emitting circuit 310 can flow through the reference circuit 320, and the drive current Id can have the same value as the reference current Iref.

[0207] The amplification circuit 330 can include a control transistor Tc and a first capacitor C1. The control transistor Tc can have a gate node to which a control voltage Vc can be applied and a source node connected to a gate node of the drive transistor Td. The first capacitor C1 can be connected to the source node of the control transistor Tc to pass a power voltage Vp. The power voltage Vp can have a level capable of driving the drive transistor Td.

[0208] The input circuit 340 can include a switching transistor Tsw and a second capacitor C2. The switching transistor Tsw can have a gate node to which an nth scan signal SCAN(n) can be applied, a drain node to which a data voltage Vdata can be applied, and a source node connected to a drain node of the control transistor Tc. The second capacitor C2 can be connected between the source node of the switching transistor Tsw and a low potential voltage EVSS.

[0209] Accordingly, the input circuit 340 can supply the data voltage Vdata to the amplification circuit 330 through the nth scan signal SCAN(n). The second capacitor C2 can be used to stably pass the data voltage Vdata.

[0210] The transistors Td, Tref, Tc, and Tsw constituting the example sub-pixel circuit 300 can be P-type transistors or N-type transistors.

[0211] P-type transistors are relatively more reliable than N-type transistors. In the case of P-type transistors, since the drive transistor Td can be fixed to a high potential voltage EVDD during a period in which the light emitting element ED emits light, a current flowing through the light emitting element ED can be stably supplied without significant fluctuation.

[0212] When operated in a saturation region, P-type transistors can flow a constant current regardless of a change in threshold voltage, thereby providing relatively high reliability.

[0213] On the other hand, since N-type transistors use electrons rather than holes as carriers, N-type transistors have a higher mobility than P-type transistors, thereby enabling an increase in switching speed.

[0214] N-type transistors can be oxide transistors (e.g., transistors having a channel formed of an oxide semiconductor such as indium, gallium, zinc oxide, or IGZO) formed of an oxide semiconductor. P-type transistors can be silicon transistors (e.g., transistors having a polysilicon channel formed by a low-temperature process called LTPS or low-temperature polysilicon) formed of a semiconductor such as silicon.

[0215] Described herein is an example in which the transistors Td, Tref, Tc, and Tsw constituting the sub-pixel circuit 300 are N-type transistors.

[0216] The terms "source node" and "drain node" of the transistor can be used interchangeably according to the input voltage.

[0217] Figure 13 is an example signal waveform diagram illustrating an operation of another sub-pixel circuit according to an example embodiment of the present disclosure.

[0218] Referring to FIGS. 1 and 2, Figure 13 The operation of the sub-pixel circuit 300 according to an example embodiment of the present disclosure is described below.

[0219] The power voltage Vp can be applied in the form of a pulse from the power management circuit 150 according to one or more timing signals.

[0220] If the power voltage Vp is applied at a low level before the nth scan signal SCAN(n) is applied, the driving transistor Td can be turned off by the power voltage Vp.

[0221] Thereafter, if the nth scan signal SCAN(n) is applied to turn on the switching transistor Tsw, the data voltage Vdata can be applied to the second capacitor C2. After the nth scan signal SCAN(n) is applied, the power voltage Vp can be switched to a high level. If the power voltage Vp reaches a threshold voltage level of the driving transistor Td, the driving transistor Td can be turned on, and the driving current Id flowing through the light emitting element ED can be transferred to the reference circuit 320 through the driving transistor Td.

[0222] The control voltage Vc corresponding to the output voltage of the light emitting circuit 310 can be increased by the driving current Id flowing from the light emitting circuit 310 to the reference circuit 320.

[0223] If the control voltage Vc reaches a level of a sum Vdata+Vth(Tc) of the data voltage Vdata and the threshold voltage Vth(Tc) of the control transistor Tc, the control transistor Tc can be turned on. If the control transistor Tc is turned on, the charge stored in the first capacitor C1 can move to the second capacitor C2, so that the driving current Id flowing through the driving transistor Td can decrease. Accordingly, the control voltage Vc can decrease, and the control transistor Tc can be turned off.

[0224] As the control transistor Tc repeatedly turns on and off for a short period, the control voltage Vc can maintain a level of the sum Vdata+Vth(Tc) of the data voltage Vdata and the threshold voltage Vth(Tc) of the control transistor Tc.

[0225] In this case, if the deposition conditions of the control transistor Tc and the reference transistor Tref positioned adjacent to each other are the same, the threshold voltage Vth(Tc) of the control transistor Tc and the threshold voltage Vth(Tref) of the reference transistor Tref can have the same value. In other words, the control transistor Tc and the reference transistor Tref can be formed to have the same threshold voltage Vth by maintaining the thickness and the composition ratio of the gate node, the source node, the drain node, and the insulating film positioned therebetween under the same conditions in a process of depositing the control transistor Tc and the reference transistor Tref.

[0226] If the threshold voltage Vth(Tc) of the control transistor Tc and the threshold voltage Vth(Tref) of the reference transistor Tref have the same value, the reference current Iref flowing through the reference transistor Tref can be expressed as:

[0227] Iref = K * Vdata 2

[0228] In other words, since the driving current Id flowing through the light emitting element ED and the reference current Iref flowing through the reference transistor Tref are both proportional to the data voltage Vdata, the driving current Id for driving the light emitting element ED can be adjusted by the data voltage Vdata regardless of the characteristic value of the light emitting element ED or the driving transistor Td.

[0229] Therefore, the example pixel circuit 300 of the present disclosure can control by allowing the control voltage Vc corresponding to the output voltage of the light emitting circuit 310 to be maintained at a level corresponding to the sum Vdata + Vth(Tc) of the threshold voltage Vth(Tc) of the control transistor Tc and the data voltage Vdata, to allow the driving current Id flowing through the light emitting element ED to be proportional to the level of the data voltage Vdata.

[0230] Therefore, in the example pixel circuit 300 of the present disclosure, regardless of the degradation of the light emitting element ED or the characteristic value of the driving transistor Td, a current proportional to the data voltage Vdata can flow through the light emitting element ED. Therefore, it is possible to provide a display panel 110 and a display device 100 having uniform brightness.

[0231] The foregoing example embodiments are briefly described below.

[0232] A sub-pixel circuit for operating at least one sub-pixel of a plurality of sub-pixels disposed on a display panel can include a light emitting circuit including a light emitting element receiving a high potential voltage, the light emitting circuit configured to control the light emitting element according to a driving voltage and output a control voltage, a reference circuit configured to receive the control voltage and a low potential voltage and control a driving current flowing through the light emitting element, an amplification circuit configured to compare the control voltage with a data voltage to generate the driving voltage for controlling the light emitting circuit, and an input circuit configured to receive the data voltage and a first scan signal and control a timing of applying the data voltage to the amplification circuit based on the first scan signal.

[0233] In some embodiments, the reference circuit can include a light emitting element having an anode electrode receiving the high potential voltage, and a driving transistor having a drain node connected to a cathode electrode of the light emitting element and a gate node receiving the driving voltage.

[0234] In some embodiments, the light emitting circuit can include a reference transistor having a drain node and a gate node receiving the control voltage and a source node receiving the low potential voltage.

[0235] In some embodiments, the amplification circuit can include an operational amplifier having an inverting input terminal receiving the control voltage, a non-inverting input terminal receiving the data voltage of the input circuit, and an output terminal configured to output the driving voltage.

[0236] In some embodiments, the amplification circuit can include a control transistor having a gate node receiving the control voltage and a source node supplying the driving voltage to the light emitting circuit, and a first capacitor connected to the source node of the control transistor to transfer the input power voltage.

[0237] In some embodiments, the reference circuit can include a reference transistor having a drain node and a gate node each configured to receive the control voltage and a source node configured to receive the low potential voltage, and the control transistor and the reference transistor can have the same threshold voltage.

[0238] In some embodiments, the control transistor and the reference transistor can have at least one of the following: the same thickness, the same composition ratio, and the same structure of the gate node, the source node, the drain node, and an insulating film located between the gate node and the source node and the drain node, respectively.

[0239] In some embodiments, the amplification circuit can further include a reset transistor having a drain node receiving a reset voltage, a gate node receiving a second scan signal before the input circuit receives a first scan signal, and a source node common with the control transistor.

[0240] In some embodiments, the driving transistor can be configured to be reset by the second scan signal and turned on by the first scan signal.

[0241] In some embodiments, a driving current flowing through the light emitting circuit has a same value as a reference current flowing through the reference circuit at a control voltage corresponding to a level of a sum of the data voltage and a threshold voltage of the control transistor.

[0242] In some embodiments, the input circuit can include a switch transistor having a gate node receiving the first scan signal, a drain node receiving the data voltage, and a source node connected to the amplification circuit, and a second capacitor connected between the source node of the switch transistor and a low potential voltage.

[0243] In some embodiments, the light emitting circuit can include a driving transistor having a drain node connected to a cathode electrode of the light emitting element and a gate node receiving a driving voltage, and the driving transistor can be configured to be reset by the input power voltage and turned on by the first scan signal before the input circuit receives the first scan signal.

[0244] In some embodiments, the light emitting circuit, the reference circuit, the amplification circuit, and the input circuit can include N-type transistors.

[0245] In some embodiments, the driving current can be proportional to the data voltage.

[0246] In some embodiments, the display panel can include a plurality of sub-pixels and the sub-pixel circuit of any of the above-described embodiments.

[0247] The display device can include a display panel including a plurality of sub-pixels and a sub-pixel circuit for operating at least one of the plurality of sub-pixels, a gate driving circuit configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, respectively, a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines, respectively, and a timing controller configured to drive the gate driving circuit and the data driving circuit. Here, the sub-pixel circuit can include an emission circuit including an emission element receiving a high potential voltage, the emission circuit being configured to control the emission element according to a driving voltage and output a control voltage, a reference circuit configured to receive the control voltage and a low potential voltage and control a driving current flowing through the emission element, an amplification circuit configured to compare the control voltage with a data voltage to generate the driving voltage for controlling the emission circuit, and an input circuit configured to receive the data voltage and a first scan signal and control a timing of applying the data voltage to the amplification circuit based on the first scan signal.

[0248] In some embodiments, the amplification circuit can include a control transistor having a gate node receiving the control voltage and a source node supplying the driving voltage to the emission circuit, and a first capacitor connected to the source node of the control transistor to transfer the input power voltage.

[0249] In some embodiments, the reference circuit can include a reference transistor having a drain node and a gate node each configured to receive the control voltage and a source node configured to receive the low potential voltage, and the control transistor and the reference transistor have the same threshold voltage.

[0250] In some embodiments, the amplification circuit can further include a reset transistor having a drain node receiving a reset voltage, a gate node receiving a second scan signal before the input circuit receives the first scan signal, and a source node shared with the control transistor, and the driving transistor can be configured to be reset by the second scan signal and turned on by the first scan signal.

[0251] In some embodiments, the driving current can be proportional to the data voltage.

[0252] The above description has been presented to enable any person skilled in the art to make and use the various possible embodiments of the disclosure. Although embodiments of the disclosure have been described in detail with reference to the accompanying drawings, the disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the disclosure. Therefore, the example embodiments disclosed in the disclosure are provided only for illustrative purposes and are not intended to limit the technical concept of the disclosure. Thus, it should be understood that the above-described example embodiments are illustrative in all aspects and do not limit the disclosure.

[0253] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

1. A subpixel circuit for operating at least one subpixel among a plurality of subpixels disposed on a display panel, the subpixel circuit comprising: A light-emitting circuit includes a light-emitting element that receives a high-potential voltage, the light-emitting circuit being configured to control the light-emitting element according to a driving voltage and to output a control voltage; A reference circuit is configured to receive the control voltage and the low potential voltage, and to control the drive current flowing through the light-emitting element; An amplifier circuit is configured to compare the control voltage with a data voltage to generate a drive voltage for controlling the light-emitting circuit; as well as An input circuit is configured to receive the data voltage and a first scan signal, and to control the timing of applying the data voltage to the amplifier circuit based on the first scan signal; The amplifier circuit includes: A control transistor having a gate node for receiving the control voltage, a source node for supplying the driving voltage to the light-emitting circuit, and a drain node connected to the input circuit; and A first capacitor is connected to the source node of the control transistor to deliver the input electrical voltage.

2. The sub-pixel circuit according to claim 1, wherein, The light-emitting circuit includes: The light-emitting element has an anode electrode that receives the high potential voltage; and A driving transistor having a drain node connected to the cathode electrode of the light-emitting element and a gate node receiving the driving voltage.

3. The sub-pixel circuit according to claim 1, wherein, The reference circuit includes a reference transistor having a drain node and a gate node for receiving the control voltage and a source node for receiving the low potential voltage.

4. The sub-pixel circuit according to claim 1, wherein, The amplifier circuit includes an operational amplifier having an inverting input terminal for receiving the control voltage, a non-inverting input terminal for receiving the data voltage from the input circuit, and an output terminal configured to output the drive voltage.

5. The sub-pixel circuit according to claim 1, wherein: The reference circuit includes a reference transistor having a drain node and a gate node each configured to receive the control voltage, and a source node configured to receive the low potential voltage. and The control transistor and the reference transistor have the same threshold voltage.

6. The sub-pixel circuit according to claim 5, wherein, The control transistor and the reference transistor have at least one of the following: the gate node, the source node, the drain node, and the insulating film located between the gate node and the source node and the drain node each have the same thickness, the same composition ratio, and the same structure.

7. The sub-pixel circuit according to claim 1, wherein, The amplifier circuit further includes a reset transistor having a drain node for receiving a reset voltage, a gate node for receiving a second scan signal before the input circuit receives the first scan signal, and a source node shared with the control transistor.

8. The sub-pixel circuit according to claim 7, wherein, The driving transistor is configured to be reset by the second scan signal and turned on by the first scan signal.

9. The sub-pixel circuit according to claim 1, wherein, Under a control voltage corresponding to the sum of the data voltage and the threshold voltage of the control transistor, the driving current flowing through the light-emitting circuit has the same value as the reference current flowing through the reference circuit.

10. The sub-pixel circuit according to claim 1, wherein, The input circuit includes: A switching transistor having a gate node for receiving the first scan signal, a drain node for receiving the data voltage, and a source node connected to the amplifier circuit; and A second capacitor is connected between the source node of the switching transistor and the low potential voltage.

11. The sub-pixel circuit according to claim 10, wherein: The light-emitting circuit includes a driving transistor having a drain node connected to the cathode electrode of the light-emitting element and a gate node receiving the driving voltage. The driving transistor is configured to be reset by the input power voltage and turned on by the first scan signal before the input circuit receives the first scan signal.

12. The sub-pixel circuit according to claim 1, wherein, The light-emitting circuit, the reference circuit, the amplification circuit, and the input circuit all include N-type transistors.

13. The sub-pixel circuit according to claim 1, wherein, The drive current is proportional to the data voltage.

14. A display panel, comprising: Multiple sub-pixels; as well as The subpixel circuit according to any one of claims 1 to 13 is used to operate at least one of the plurality of subpixels.

15. A display device, comprising: The display panel includes a plurality of sub-pixels and sub-pixel circuitry for operating at least one of the plurality of sub-pixels; A gate driving circuit is configured to supply multiple scan signals to the display panel through multiple gate lines; A data driving circuit is configured to supply multiple data voltages to the display panel via multiple data lines; as well as A timing controller is configured to drive the gate drive circuit and the data drive circuit. The sub-pixel circuit includes: A light-emitting circuit includes a light-emitting element that receives a high-potential voltage, the light-emitting circuit being configured to control the light-emitting element according to a driving voltage and to output a control voltage; A reference circuit is configured to receive the control voltage and the low potential voltage, and to control the drive current flowing through the light-emitting element; An amplifier circuit configured to compare the control voltage with a data voltage to generate a drive voltage for controlling the light-emitting circuit; and An input circuit is configured to receive the data voltage and a first scan signal, and to control the timing of applying the data voltage to the amplifier circuit based on the first scan signal; The amplifier circuit includes: A control transistor having a gate node for receiving the control voltage, a source node for supplying the driving voltage to the light-emitting circuit, and a drain node connected to the input circuit; and A first capacitor is connected to the source node of the control transistor to deliver the input electrical voltage.

16. The display device according to claim 15, wherein: The reference circuit includes a reference transistor having a drain node and a gate node each configured to receive the control voltage, and a source node configured to receive the low potential voltage. and The control transistor and the reference transistor have the same threshold voltage.

17. The display device according to claim 15, wherein: The amplifier circuit further includes a reset transistor having a drain node for receiving a reset voltage, a gate node for receiving a second scan signal before the input circuit receives the first scan signal, and a source node shared with the control transistor. and The driving transistor is configured to be reset by the second scan signal and turned on by the first scan signal.

18. The display device according to claim 15, wherein, The drive current is proportional to the data voltage.

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