Semiconductor structure and method of forming the same

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having gate structures formed thereon, source / drain doped layers formed in the substrate on both sides of the gate structures, source / drain interconnect lines formed between adjacent gate structures, the source / drain interconnect lines covering the top of the source / drain doped layers and electrically connected to the source / drain doped layers, and an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer covering the gate structures and the source / drain interconnect lines; forming a first interconnect plug through the interlayer dielectric layer, the first interconnect plug being on top of a gate structure and electrically connected to the gate structure, or the first interconnect plug being on top of a source / drain interconnect line and electrically connected to the source / drain interconnect line; forming a growth inhibition layer on top of the first interconnect plug; forming a first opening through the interlayer dielectric layer; and forming a second interconnect plug in the first opening, the second interconnect plug being electrically connected to a structure to be interconnected. The probability of the first interconnect plug contacting an adjacent second interconnect plug is reduced, thereby affecting the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the requirements of interconnects after the critical size reduction, the conduction between different metal layers or between a metal layer and a substrate is currently achieved through interconnect structures. As technology nodes advance, the size of interconnect structures is becoming smaller and smaller; correspondingly, the process of forming interconnect structures is becoming more and more difficult. The formation quality of interconnect structures has a significant impact on the back end of line (BEOL) electrical performance and device reliability, and in severe cases, it can affect the normal operation of semiconductor devices. Summary of the Invention

[0004] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure located on the substrate; sidewalls located on the sidewalls of the gate structure; source / drain doped layers located within the substrate on both sides of the gate structure; source / drain interconnects located on top of the source / drain doped layers and electrically connected to the source / drain doped layers; an interlayer dielectric layer located on the exposed substrate of the gate structure, and covering the gate structure and the source / drain interconnects; a first interconnect plug located in and penetrating the interlayer dielectric layer, the first interconnect plug being located on top of the gate structure and electrically connected to the gate structure, or the first interconnect plug being located on top of the source / drain interconnects and electrically connected to the source / drain interconnects, wherein the portion of the gate structure and the source / drain interconnects not connected to the first interconnect plug is used as the interconnected structure; a second interconnect plug located in and penetrating the interlayer dielectric layer on top of the interconnected structure, the second interconnect plug being electrically connected to the interconnected structure; and a growth suppression layer located on top of the first interconnect plug, with the growth suppression layer exposing the second interconnect plug.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, and source and drain interconnects are formed between adjacent gate structures, covering the top of the source and drain doped layers and electrically connected to the source and drain doped layers; an interlayer dielectric layer is formed on the substrate, covering the gate structure and the source and drain interconnects; forming a first interconnect plug penetrating the interlayer dielectric layer in the interlayer dielectric layer, wherein the first interconnect plug is located on top of the gate structure and electrically connected to the gate structure, or the first interconnect plug is located on top of the source and drain interconnects and electrically connected to the source and drain interconnects; wherein the gate structure and the source and drain interconnects not connected to the first interconnect plug are used as interconnected structures; forming a growth suppression layer on top of the first interconnect plug; forming a first opening penetrating the interlayer dielectric layer after forming the growth suppression layer, wherein the bottom of the first opening exposes the top of the interconnected structure; and forming a second interconnect plug in the first opening, wherein the second interconnect plug is electrically connected to the interconnected structure.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a method for forming a semiconductor structure. A first interconnect plug is formed in an interlayer dielectric layer, penetrating the interlayer dielectric layer. The first interconnect plug is located on top of a gate structure and electrically connected to the gate structure, or it is located on top of a source-drain interconnect and electrically connected to the source-drain interconnect. In the gate structure and the source-drain interconnect, the portion not connected to the first interconnect plug serves as the interconnect structure to be interconnected. A growth suppression layer is formed on top of the first interconnect plug. The growth suppression layer suppresses the growth rate of metal material on its surface. During the formation of a second interconnect plug, it can suppress the growth rate of the material forming the second interconnect plug on top of the first interconnect plug, making it less likely for the first interconnect plug to grow into the formation region of the second interconnect plug. Consequently, it reduces the probability of the first interconnect plug contacting an adjacent second interconnect plug, reducing the probability of voids appearing in the second interconnect plug, thereby affecting the performance of the semiconductor structure. Attached Figure Description

[0009] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0010] Figure 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0011] Figure 7 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0012] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one semiconductor structure formation method as an example.

[0014] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 A substrate is provided, the substrate including a substrate 10 and fins 12 protruding from the substrate 10, a gate structure 18 is formed on the substrate, source and drain doped layers 20 are formed in the substrate on both sides of the gate structure 18, a gate capping layer 15 is formed on the top of the gate structure 18, a source and drain interconnect 19 is formed between adjacent gate structures 18, covering the top of the source and drain doped layers 20 and electrically connecting the source and drain doped layers 20, a source and drain capping layer 17 is formed on the top of the source and drain interconnect 19, and an interlayer dielectric layer 13 is formed on the substrate covering the gate structure 18 and the source and drain interconnect 19.

[0016] refer to Figure 2 A gate opening 11 is formed on the top of the gate structure 18, penetrating the interlayer dielectric layer 13 and the gate cap layer 15.

[0017] refer to Figure 3 A gate plug 21 is formed in the gate opening 11.

[0018] refer to Figure 4 A source / drain opening 23 is formed at the top of the source / drain interconnect 19, penetrating the interlayer dielectric layer 13 and the source / drain cap layer 17.

[0019] refer to Figure 5 A source drain plug 26 is formed in the source drain opening 23.

[0020] Research has revealed that during the formation of the source / drain plug 26 in the source / drain opening 23, a portion of the material forming the source / drain plug 26 is deposited on the top surface of the gate plug 21. As the distance between the source / drain plug 26 and the gate plug 21 becomes smaller, the gate plug 21 is more likely to grow into the formation region of the source / drain plug 26. Consequently, this increases the probability of the gate plug 21 contacting the adjacent source / drain plug 26, increasing the probability of voids appearing in the source / drain plug 26, thereby affecting the performance of the semiconductor structure.

[0021] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, on which a gate structure is formed, source / drain doped layers are formed in the substrate on both sides of the gate structure, and source / drain interconnects are formed between adjacent gate structures, covering the top of the source / drain doped layers and electrically connected to the source / drain doped layers; an interlayer dielectric layer is formed on the substrate, covering the gate structure and the source / drain interconnects; forming a first interconnect plug penetrating the interlayer dielectric layer in the interlayer dielectric layer, the first interconnect plug being located on top of the gate structure and electrically connected to the gate structure, or the first interconnect plug being located on top of the source / drain interconnects and electrically connected to the source / drain interconnects; in the gate structure and the source / drain interconnects, the portion not connected to the first interconnect plug is used as a structure to be interconnected; forming a growth suppression layer on top of the first interconnect plug; after forming the growth suppression layer, forming a first opening penetrating the interlayer dielectric layer, the bottom of the first opening exposing the top of the structure to be interconnected; forming a second interconnect plug in the first opening, the second interconnect plug being electrically connected to the structure to be interconnected.

[0022] In this embodiment of the invention, a first interconnect plug is formed penetrating the interlayer dielectric layer. The first interconnect plug is located on top of the gate structure and electrically connected to it, or it is located on top of the source / drain interconnect and electrically connected to it. In the gate structure and source / drain interconnect, the portion not connected to the first interconnect plug serves as the interconnect structure to be interconnected. A growth suppression layer is formed on top of the first interconnect plug. The growth suppression layer suppresses the growth rate of the metal material on its surface. During the formation of the second interconnect plug, it can suppress the growth rate of the material forming the second interconnect plug on top of the first interconnect plug, making it less likely for the first interconnect plug to grow into the formation region of the second interconnect plug. Consequently, it reduces the probability of the first interconnect plug contacting an adjacent second interconnect plug, reducing the probability of voids appearing in the second interconnect plug, thereby improving the performance of the semiconductor structure.

[0023] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Figure 6 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0025] The semiconductor structure includes: a substrate; a gate structure 208 located on the substrate; sidewalls 206 located on the sidewalls of the gate structure 208; source / drain doped layers 220 located within the substrate on both sides of the gate structure 208; source / drain interconnects 209 located on top of the source / drain doped layers 220 and electrically connected to them; an interlayer dielectric layer 203 located on the exposed substrate of the gate structure 208, and covering the gate structure 208 and the source / drain interconnects 209; and a first interconnect plug 211 located in and penetrating the interlayer dielectric layer 203, the first interconnect plug 211 being located on top of the gate structure 208 and connected to it. The gate structure 208 is electrically connected, or the first interconnect plug 211 is located on top of the source-drain interconnect 209 and electrically connected to the source-drain interconnect 209. In the gate structure 208 and the source-drain interconnect 209, the one not connected to the first interconnect plug 211 is used as the structure to be interconnected; the second interconnect plug 215 is located in the interlayer dielectric layer 203 on top of the structure to be interconnected and penetrates the interlayer dielectric layer 203. The second interconnect plug 215 is electrically connected to the structure to be interconnected; the growth inhibition layer 212 is located on top of the first interconnect plug 211, and the growth inhibition layer 212 exposes the second interconnect plug 215.

[0026] In this embodiment, a growth inhibition layer 212 is provided on the top of the first interconnect plug 211. The growth inhibition layer 212 has the function of inhibiting the growth rate of metal material on its surface. In the formation process of the second interconnect plug 215, the growth rate of the material forming the second interconnect plug 215 on the top of the first interconnect plug 211 can be inhibited, making it difficult for the first interconnect plug 211 to grow into the formation area of ​​the second interconnect plug 215. Correspondingly, the probability of the first interconnect plug 211 contacting the adjacent second interconnect plug 215 is reduced, and the probability of voids appearing in the second interconnect plug 215 is reduced, thereby improving the performance of the semiconductor structure.

[0027] It should be noted that, in this embodiment, the first interconnect plug 211 is located at the top of the gate structure 208 as an example, and correspondingly, the second interconnect plug 215 is located at the top of the source-drain interconnect 209.

[0028] In other embodiments, when the first interconnect plug is located on top of the source-drain interconnect, the second interconnect plug is correspondingly located on top of the gate structure.

[0029] The substrate is used to provide a process platform for subsequent process manufacturing.

[0030] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 200 and fins 202 protruding from the substrate 200. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0031] In this embodiment, the material of the fin 202 is the same as that of the substrate 200, which is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0032] In this embodiment, the semiconductor structure further includes an isolation layer 201 located on the substrate 200 exposed by the fin 202 and covering part of the sidewall of the fin 202.

[0033] The isolation layer 201 is used to isolate adjacent devices. The material of the isolation layer 201 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 201 is silicon oxide.

[0034] When the device is in operation, the gate structure 208 is used to control the opening or closing of the conductive channel.

[0035] In this embodiment, the gate structure 208 is located on the substrate 200, and the gate structure 208 spans the fin 202 and covers part of the top and part of the sidewall of the fin 202.

[0036] In this embodiment, the gate structure 208 includes a metal gate structure. The gate structure 208 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer. Specifically, the top surface of the gate structure 208 exposes the gate electrode layer.

[0037] The gate electrode layer in the metal gate structure is made of metal. In the formation process of the first interconnect plug 211, the selected deposition process is used to form the first interconnect plug 211 on the top of the gate structure 208.

[0038] The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0039] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0040] As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also consist only of a work function layer.

[0041] The source and drain doped layers 220 are used as the source and drain regions of the transistor.

[0042] When the semiconductor structure is an NMOS transistor, the source / drain doped layer 220 includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When the semiconductor structure is a PMOS transistor, the source / drain doped layer 220 includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.

[0043] The source-drain interconnect 209 is used to realize the electrical connection between the source-drain doped layer 220 and external circuits or other interconnect structures.

[0044] In this embodiment, the source-drain interconnect 209 is made of cobalt. Cobalt has low resistivity, which helps to improve the signal delay of the subsequent RC circuit, increase the processing speed of the chip, and also helps to reduce the resistance of the source-drain interconnect 209, thereby reducing power consumption. In other embodiments, the source-drain interconnect can also be made of conductive materials such as tungsten or ruthenium.

[0045] The sidewall 206 is used to protect the sidewalls of the gate structure 208. The sidewall 206 can be a single-layer structure or a multilayer structure, and the material of the sidewall 206 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 206 is a single-layer structure, and the material of the sidewall 206 is silicon oxide.

[0046] In this embodiment, the semiconductor structure further includes a gate cap layer 205, located on top of the gate structure 208.

[0047] The gate cap layer 205 is used to protect the top of the gate structure 208 and reduce the probability of damage to the gate structure 208 and short circuit between the second interconnect plug 215 and the gate structure 208 during the formation process of the second interconnect plug 215.

[0048] The gate cap layer 205 is made of a material that has etching selectivity with the sidewall 206 and the interlayer dielectric layer 203, which helps to ensure that the gate cap layer 205 can protect the top of the gate structure 208.

[0049] The gate cap layer 205 is made of one or more of SiC, SiCO, SiN, and SiCN. In this embodiment, the gate cap layer 205 is made of SiN.

[0050] In this embodiment, the semiconductor structure further includes a source / drain capping layer 207, located on top of the source / drain interconnect 209.

[0051] On the one hand, the source / drain cap layer 207 is used to protect the top of the source / drain interconnect 209, and in the process of forming the first interconnect plug 211, it reduces the probability of damage to the source / drain interconnect 209 and short circuit between the first interconnect plug 211 and the source / drain interconnect 209.

[0052] On the other hand, in the formation process of the first interconnect plug 211, the sidewall of the source / drain cap layer 207 acts as an etching stop, realizing the self-alignment of the first interconnect plug 211 and the gate structure 208.

[0053] The source / drain capping layer 207 is made of a material that has etching selectivity with the gate capping layer 205 and the interlayer dielectric layer 203, which helps to ensure that the source / drain capping layer 207 can protect the top of the source / drain interconnect 209.

[0054] By using the source / drain capping layer 207 and the gate capping layer 205, the overlay alignment accuracy can be better defined, improving the alignment accuracy between the first interconnect plug 211 and the corresponding gate structure 208, as well as the alignment accuracy between the second interconnect plug 215 and the corresponding source / drain interconnect 209, thereby improving the performance of the semiconductor structure.

[0055] In this embodiment, the source / drain capping layer 207 is made of one or more of SiC, SiCO, SiN, and SiCN. In this embodiment, the source / drain capping layer 207 is made of SiCN.

[0056] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 203, located on the substrate, and covering the top of the gate structure 208 and the source-drain interconnect 209.

[0057] The interlayer dielectric layer 203 serves to isolate adjacent devices and also provides space for the first interconnect plug 211 and the second interconnect plug 215.

[0058] The interlayer dielectric layer 203 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the interlayer dielectric layer 203 is made of silicon oxide.

[0059] In this embodiment, among the first interconnect plug 211 and the second interconnect plug 215, the one connected to the gate structure 208 serves as the gate plug, and the gate plug also penetrates the gate cap layer 205.

[0060] The first interconnect plug 211 is used to realize the electrical connection between the gate structure 208 and external circuits or other interconnect structures.

[0061] In this embodiment, the first interconnect plug 211 is made of tungsten. On one hand, tungsten has low resistivity, which helps improve the signal delay of the subsequent RC circuit and increases the chip's processing speed. It also helps reduce the resistance of the first interconnect plug 211, thus reducing power consumption. On the other hand, tungsten is less likely to react with the solution used in the polishing process, reducing the probability of damage to the first interconnect plug 211 and thus minimizing its impact on electrical performance. In other embodiments, the first interconnect plug can also be made of conductive materials such as cobalt, molybdenum, or ruthenium.

[0062] In this embodiment, the gate plug is located between adjacent source / drain cap layers 207.

[0063] Specifically, in the formation process of the first interconnect plug 211, the sidewall of the source / drain cap layer 207 is used as the lateral etching stop position, and a gate opening (not shown) is formed between adjacent source / drain cap layers 207, penetrating the interlayer dielectric layer 203 and exposing the top of the gate structure 208.

[0064] Therefore, in the process of forming the gate opening, the source / drain capping layer 207 can achieve a self-alignment effect, reducing the probability that the etching process forming the gate opening will damage the top of the source / drain interconnect 209, thereby improving the performance of the semiconductor structure.

[0065] The gate plug penetrates the gate cap layer 205, enabling the first interconnect plug 111 to be electrically connected to the gate structure 208.

[0066] The growth inhibition layer 212 has the function of inhibiting the growth rate of metal material on its surface. In the formation process of the second interconnect plug 215, it can inhibit the growth rate of the material forming the second interconnect plug 215 on the top of the first interconnect plug 211.

[0067] It should be noted that the thickness of the growth inhibition layer 212 should not be too large or too small. Although the growth inhibition layer 212 can suppress the growth rate of the material forming the second interconnect plug on top of the first interconnect plug 211, the conductive material forming the second interconnect plug will still deposit a portion of the conductive material on the surface of the growth inhibition layer 212. If the thickness of the growth inhibition layer 212 is too large, the space occupied by the growth inhibition layer 212 and the portion of the conductive material deposited on its surface will be too large, increasing the probability that the portion of the conductive material deposited on the surface of the growth inhibition layer 212 will come into contact with the second interconnect plug 215, causing the first interconnect plug 211 and the second interconnect plug 215 to short-circuit with each other, thereby affecting the performance of the semiconductor structure. If the thickness of the growth inhibition layer 212 is too small, the effect of the growth inhibition layer 212 in inhibiting the growth of metal material on its surface will be insignificant, increasing the probability that the first interconnect plug 211 will come into contact with the adjacent second interconnect plug 215, increasing the probability of voids appearing in the second interconnect plug 215, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the growth inhibition layer 212 is 5 angstroms to 200 angstroms.

[0068] In this embodiment, the material of the growth inhibition layer 212 includes one or both of titanium nitride and fluorine-free tungsten.

[0069] Specifically, both titanium nitride and fluorine-free tungsten are metal mixtures. In the formation process of the second interconnect plug 215, the deposition rate of the material forming the second interconnect plug on the metal mixture is slower than that on the pure metal material, thereby enabling the growth inhibition layer 212 to inhibit the growth rate of the metal material on its surface.

[0070] It should be noted that the fluorine-free tungsten is doped tungsten. Compared with pure metallic tungsten, in the process of forming the second interconnect plug 215, the deposition rate of the material forming the second interconnect plug on the fluorine-free tungsten is slower than that on the pure metallic tungsten.

[0071] In this embodiment, among the first interconnect plug 211 and the second interconnect plug 215, the one connected to the source-drain interconnect line 209 serves as the source-drain plug. Therefore, the second interconnect plug 215 serves as the source-drain plug.

[0072] The second interconnect plug 215 is electrically connected to the source / drain interconnect 209, thereby enabling the source / drain doped layer 220 to be electrically connected to other interconnect structures or external circuits.

[0073] In this embodiment, the material of the second interconnect plug 215 is cobalt. Cobalt has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. At the same time, it also helps to reduce the resistance of the second interconnect plug 215, thereby reducing power consumption.

[0074] It should be noted that cobalt readily reacts with the solution used in the polishing process. Therefore, in this embodiment, by forming the first interconnect plug 211 first and then the second interconnect plug 215, the material forming the second interconnect plug 215 only needs to undergo one polishing process, reducing the probability of damage to the second interconnect plug 215 and thus improving the performance of the semiconductor structure. In other embodiments, the material of the second interconnect plug can also be conductive materials such as tungsten, molybdenum, and ruthenium.

[0075] Figure 7 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention.

[0076] In this embodiment, the top of the first interconnect plug 311 is lower than the top of the interlayer dielectric layer 303, and the growth inhibition layer 312 fills the space enclosed by the top of the first interconnect plug 311 and the interlayer dielectric layer 303.

[0077] Specifically, since the growth inhibition layer 312 is made of a metal mixture, it has a conductive function, enabling the interconnect structure formed in subsequent processes to be electrically connected to the first interconnect plug through the growth inhibition layer.

[0078] It should be noted that the top of the growth inhibition layer 312 is flush with the top of the interlayer dielectric layer 303, which makes the top surface of the growth inhibition layer 312 and the interlayer dielectric layer 303 have a high degree of flatness, providing a better process foundation for subsequent process manufacturing.

[0079] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0080] refer to Figure 8 A substrate is provided, on which a gate structure 108 is formed. Source and drain doped layers 120 are formed in the substrate on both sides of the gate structure 108. Source and drain interconnects 109 are formed between adjacent gate structures 108, covering the top of the source and drain doped layers 120 and electrically connecting the source and drain doped layers 120. An interlayer dielectric layer 103 is formed on the substrate, covering the gate structure 108 and the source and drain interconnects 109.

[0081] The substrate is used to provide a process platform for subsequent process manufacturing.

[0082] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 102 protruding from the substrate 100. In other embodiments, when the substrate is used to form a planar field-effect transistor, the substrate is correspondingly a planar substrate.

[0083] In this embodiment, the material of the fin 102 is the same as that of the substrate 100, which is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0084] In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 102, forming an isolation layer 101 on the substrate 100 exposed by the fin 102, the isolation layer 101 covering part of the sidewall of the fin 102.

[0085] The isolation layer 101 is used to isolate adjacent devices. The material of the isolation layer 101 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 101 is silicon oxide.

[0086] When the device is in operation, the gate structure 108 is used to control the opening or closing of the conductive channel.

[0087] In this embodiment, the gate structure 108 is located on the substrate 100, and the gate structure 108 spans the fin 102 and covers part of the top and part of the sidewall of the fin 102.

[0088] In this embodiment, the gate structure 108 includes a metal gate structure.

[0089] The middle gate electrode layer of the metal gate structure is made of metal, which facilitates the formation of the first interconnect plug on top of the gate structure 108 by the subsequent deposition process.

[0090] In this embodiment, the gate structure 108 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0091] The gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0092] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0093] As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also consist only of a work function layer.

[0094] The source and drain doped layers 120 are used as the source and drain regions of the transistor.

[0095] When forming an NMOS transistor, the source / drain doped layer 120 includes a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, thereby improving the carrier mobility of the NMOS transistor. The N-type ions are P-ions, As-ions, or Sb-ions. When forming a PMOS transistor, the source / drain doped layer 120 includes a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor. The P-type ions are B-ions, Ga-ions, or In-ions.

[0096] The source-drain interconnect 109 is used to realize the electrical connection between the source-drain doped layer 120 and external circuits or other interconnect structures.

[0097] In this embodiment, the source-drain interconnect 109 is made of cobalt. Cobalt has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the source-drain interconnect 109, thereby reducing power consumption. In other embodiments, the source-drain interconnect can also be made of conductive materials such as tungsten or ruthenium.

[0098] In this embodiment, the method for forming the semiconductor structure further includes: sidewalls 106 are formed on the sidewalls of the gate structure 108.

[0099] The sidewall 106 is used to protect the sidewalls of the gate structure 108. The sidewall 106 can be a single-layer structure or a multilayer structure, and the material of the sidewall 106 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 106 is a single-layer structure, and the material of the sidewall 106 is silicon oxide.

[0100] In this embodiment, a gate cap layer 105 is formed on the top of the gate structure 108.

[0101] The gate cap layer 105 is used to protect the top of the gate structure 108, thereby reducing the probability of damage to the gate structure 108 and short circuit between the second interconnect plug and the gate structure 108 during the subsequent formation of the second interconnect plug.

[0102] The gate cap layer 105 is made of a material that has etching selectivity with the sidewall 106 and the interlayer dielectric layer 103, which helps to ensure that the gate cap layer 105 can protect the top of the gate structure 108.

[0103] The gate cap layer 105 is made of one or more of SiC, SiCO, SiN, and SiCN. In this embodiment, the gate cap layer 105 is made of SiN.

[0104] In this embodiment, an active drain capping layer 107 is formed on the top of the source-drain interconnect 109.

[0105] On the one hand, the source / drain cap layer 107 is used to protect the top of the source / drain interconnect 109, thereby reducing the probability of damage to the source / drain interconnect 109 and short circuit between the first interconnect plug and the source / drain interconnect 109 during the subsequent formation of the first interconnect plug.

[0106] On the other hand, during the subsequent formation of the gate opening, the sidewall of the source / drain cap layer 107 acts as an etching stop, enabling the subsequent formation of the first interconnect plug to self-align with the gate structure 108.

[0107] The source / drain capping layer 107 is made of a material that has etch selectivity with the gate capping layer 105 and the interlayer dielectric layer 103, which helps to ensure that the source / drain capping layer 107 can protect the top of the source / drain interconnect 109 and stop the etching during the formation of the gate opening.

[0108] The source / drain capping layer 107 is made of one or more of SiC, SiCO, SiN, and SiCN. In this embodiment, the source / drain capping layer 107 is made of SiCN.

[0109] The interlayer dielectric layer 103 serves to isolate adjacent devices and also occupies space for the subsequently formed first interconnect plug and second interconnect plug.

[0110] The interlayer dielectric layer 103 is made of an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. As an example, the interlayer dielectric layer 103 is made of silicon oxide.

[0111] refer to Figures 9 to 10A first interconnect plug 111 is formed in the interlayer dielectric layer 103, penetrating the interlayer dielectric layer 103. The first interconnect plug 111 is located on top of the gate structure 108 and is electrically connected to the gate structure 108. In the gate structure 108 and the source-drain interconnect line 109, the part not connected to the first interconnect plug 111 is used as the interconnect structure to be interconnected.

[0112] The first interconnect plug 111 is used to realize the electrical connection between the gate structure 108 and external circuits or other interconnect structures.

[0113] Reference Figures 9 to 10 The steps for forming the first interconnect plug 111 are described in detail.

[0114] refer to Figure 9 A second opening 110 is formed through the interlayer dielectric layer 103, and the bottom of the second opening 110 exposes the top of the gate structure 108.

[0115] In this embodiment, when the first interconnect plug 111 is located on top of the gate structure 108, the second opening 110 is a gate opening that exposes the top of the gate structure 108.

[0116] The second opening 110 provides a spatial location for forming the first interconnect plug 111.

[0117] In this embodiment, during the step of forming the gate opening, the sidewall of the source / drain capping layer 107 is used as the lateral etching stop position, and a gate opening is formed between adjacent source / drain capping layers 107, penetrating the interlayer dielectric layer 103 and exposing the top of the gate structure 108.

[0118] Specifically, during the formation of the gate opening, the source / drain capping layer 107 can achieve a self-alignment effect, reducing the probability that the etching process forming the gate opening will damage the top of the source / drain interconnect 109, thereby improving the performance of the semiconductor structure.

[0119] In this embodiment, during the step of forming the gate opening, the gate opening also penetrates the gate cap layer 105, so that the first interconnect plug 111 formed in the gate opening can be electrically connected to the gate structure 108.

[0120] In this embodiment, the process of forming the second opening 110 through the interlayer dielectric layer 103 includes a dry etching process.

[0121] refer to Figure 10 A first interconnect plug 111 is formed in the second opening 110.

[0122] In this embodiment, the first interconnect plug 111 is made of tungsten. On one hand, tungsten has low resistivity, which helps improve the signal delay in the subsequent RC circuit and increases the chip's processing speed. It also helps reduce the resistance of the first interconnect plug 111, thus reducing power consumption. On the other hand, tungsten is less likely to react with the solution used in subsequent polishing processes, reducing the probability of damage to the first interconnect plug 111 and thus minimizing its impact on electrical performance. In other embodiments, the first interconnect plug can also be made of conductive materials such as cobalt, molybdenum, and ruthenium.

[0123] In this embodiment, the step of forming the first interconnect plug 111 in the second opening 110 includes: forming a first conductive material layer (not shown) in the second opening 110 and on top of the interlayer dielectric layer 103; taking the top of the interlayer dielectric layer 103 as the stop position, performing planarization on the first conductive material layer above the top of the interlayer dielectric layer 103, and using the remaining first conductive material layer in the second opening 110 as the first interconnect plug 111.

[0124] In this embodiment, the process of forming the first interconnect plug 111 in the second opening 110 includes an area-selective-deposition (ASD) process.

[0125] Specifically, the surface of the interlayer dielectric layer 103 is passivated using a mixed plasma of H2 and Ar or H2 plasma. After passivation, a first interconnect plug 111 is selectively formed on the top of the gate structure 108 exposed by the second opening 110.

[0126] The selective deposition process features deposition flexibility, with different deposition rates on different materials to meet the required process requirements. During the selective deposition process for forming the first interconnect plug 111 on the top of the gate structure 108 exposed by the second opening 110, on one hand, the deposition rate of the first interconnect plug 111 on the top of the gate structure 108 exposed by the second opening 110 is much greater than the deposition rate on the surface of the interlayer dielectric layer 103, resulting in a small amount of the first interconnect plug 111 deposited on the surface of the interlayer dielectric layer 103. Simultaneously, in the subsequent cleaning process, the small amount of the first interconnect plug 111 formed on the surface of the interlayer dielectric layer 103 is completely removed. On the other hand, since the gate electrode layer in the gate structure 108 is made of a metallic material, the deposition rate of the first interconnect plug 111 on the metallic material surface is much greater than the deposition rate on the non-metallic material surface, resulting in only a small amount of the first interconnect plug 111 deposited on the surface of the interlayer dielectric layer 103.

[0127] In this embodiment, a chemical mechanical polishing process is used to planarize the first conductive material layer above the top of the interlayer dielectric layer 103, so that the top surface of the first interconnect plug 111 has a high degree of flatness, which provides a process basis for the subsequent formation of a growth inhibition layer on the top of the first interconnect plug 111.

[0128] refer to Figure 11 A growth inhibition layer 112 is formed on top of the first interconnect plug 111.

[0129] The growth inhibition layer 112 has the function of inhibiting the growth rate of metal material on its surface. In the subsequent formation of the second interconnect plug, it can inhibit the growth rate of the material forming the second interconnect plug on the top of the first interconnect plug 111, making it difficult for the first interconnect plug 111 to grow into the formation area of ​​the second interconnect plug. Correspondingly, it reduces the probability of the first interconnect plug 111 contacting the adjacent second interconnect plug, reduces the probability of voids appearing in the second interconnect plug, and thus improves the performance of the semiconductor structure.

[0130] In this embodiment, a selective deposition process is used to form a growth inhibition layer 112 on the top of the first interconnect plug 111.

[0131] Specifically, the surface of the interlayer dielectric layer 103 is passivated using a mixed plasma of H2 and Ar or H2 plasma. After passivation, a growth inhibition layer 112 is selectively formed on the top of the first interconnect plug 111.

[0132] The selective deposition process features deposition flexibility, with different deposition rates on different materials to meet the required process requirements. In the process of forming a growth inhibition layer 112 on top of the first interconnect plug 111 using selective deposition, on the one hand, the deposition rate of the growth inhibition layer 112 on top of the first interconnect plug 111 is much greater than the deposition rate on the surface of the interlayer dielectric layer 103, resulting in a small amount of the growth inhibition layer 112 being deposited on the surface of the interlayer dielectric layer 103. Simultaneously, in the subsequent cleaning process, the small amount of growth inhibition layer 112 formed on the surface of the interlayer dielectric layer 103 is completely removed. On the other hand, since the material of the first interconnect plug 111 is a metallic material, the deposition rate of the growth inhibition layer 112 on the metallic material surface is much greater than the deposition rate on the non-metallic material surface, resulting in only a small amount of the first interconnect plug 111 being deposited on the surface of the interlayer dielectric layer 103.

[0133] It should be noted that the thickness of the growth inhibition layer 112 should not be too large or too small. Although the growth inhibition layer 112 can suppress the growth rate of the material forming the second interconnect plug on top of the first interconnect plug 111, the conductive material forming the second interconnect plug will still deposit a portion of conductive material on the surface of the growth inhibition layer 112. If the thickness of the growth inhibition layer 112 is too large, the space occupied by the growth inhibition layer 112 and the portion of conductive material deposited on its surface will be too large, increasing the probability that the portion of conductive material deposited on the surface of the growth inhibition layer 112 will come into contact with the second interconnect plug, causing the first interconnect plug 111 and the second interconnect plug to short-circuit with each other, thereby affecting the performance of the semiconductor structure. If the thickness of the growth inhibition layer 112 is too small, the effect of the growth inhibition layer 112 in suppressing the growth of metal material on its surface will be insignificant, increasing the probability that the first interconnect plug 111 will come into contact with the adjacent second interconnect plug, increasing the probability of voids appearing in the second interconnect plug, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the growth inhibition layer 112 is 5 angstroms to 200 angstroms.

[0134] In this embodiment, the material of the growth inhibition layer 112 includes one or more of titanium nitride and fluorine-free tungsten.

[0135] Specifically, both titanium nitride and fluorine-free tungsten are metal mixtures. In the subsequent deposition process to form the second interconnect plug, the deposition rate of the material forming the second interconnect plug on the metal mixture is slower than that on the pure metal material, thereby enabling the growth inhibition layer 112 to inhibit the growth rate of the metal material on its surface.

[0136] refer to Figure 12 After the growth inhibition layer 112 is formed, a first opening 113 is formed that penetrates the interlayer dielectric layer 103, and the bottom of the first opening 113 exposes the top of the structure to be interconnected.

[0137] It should be noted that the first opening 113 provides space for the subsequent formation of the second interconnect plug.

[0138] It should also be noted that, since the gate structure 108 is electrically connected to the first interconnect plug 111, and the source-drain interconnect line 109 which is not electrically connected to the first interconnect plug 111 is used as the interconnect structure, in this embodiment, the first opening 113 is a source-drain opening that exposes the top of the source-drain interconnect line 109.

[0139] In this embodiment, during the step of forming the source drain opening, the source drain opening also penetrates the source drain cap layer 107.

[0140] Specifically, the source-drain opening penetrates the source-drain cap layer 107, and the source-drain opening exposes the top surface of the source-drain interconnect 109, so that the second interconnect plug subsequently formed in the source-drain opening can be electrically connected to the source-drain interconnect 109.

[0141] In this embodiment, the process of forming the first opening 113 through the interlayer dielectric layer 103 includes a dry etching process.

[0142] refer to Figures 13 to 14 A second interconnect plug 115 is formed in the first opening 113, and the second interconnect plug 115 is electrically connected to the structure to be interconnected.

[0143] The second interconnect plug 115 and the source-drain interconnect 109 form a source-drain plug, thereby realizing the electrical connection of the source-drain doped layer 120 with other interconnect structures or external circuits.

[0144] In this embodiment, the material of the second interconnect plug 115 is cobalt. On one hand, cobalt has low resistivity, which helps improve the signal delay of the subsequent RC circuit and increases the chip's processing speed. It also helps reduce the resistance of the second interconnect plug 115, thereby reducing power consumption. In other embodiments, the material of the second interconnect plug can also be conductive materials such as tungsten, molybdenum, and ruthenium. On the other hand, cobalt readily reacts with the solution used in the subsequent polishing process. Therefore, in this embodiment, by forming the first interconnect plug 111 first and then the second interconnect plug 115, the material forming the second interconnect plug 115 only needs to undergo one polishing process, reducing the probability of damage to the second interconnect plug 115 and thus improving the performance of the semiconductor structure.

[0145] In this embodiment, the process of forming the second interconnect plug 115 in the first opening 113 includes a selective deposition process.

[0146] Specifically, the surface of the interlayer dielectric layer 103 is passivated using a mixed plasma of H2 and Ar or H2 plasma. After passivation, a second interconnect plug 115 is selectively formed on top of the source-drain interconnect 109.

[0147] The selective deposition process features deposition flexibility, with different deposition rates on different materials to meet the required process requirements. During the formation of the second interconnect plug 115 on top of the source / drain interconnect 109 using selective deposition, on the one hand, the deposition rate of the material forming the second interconnect plug 115 on the growth inhibition layer 112 is much lower than the deposition rate on top of the source / drain interconnect 109. This makes it less likely for the first interconnect plug 111 to grow into the formation region of the second interconnect plug 115, thus reducing the probability of the first interconnect plug 111 contacting the adjacent second interconnect plug 115 and reducing the probability of voids appearing in the second interconnect plug 115, thereby improving the performance of the semiconductor structure. On the other hand, the deposition rate of the material forming the second interconnect plug 115 on top of the source / drain interconnect 109 is much higher than the deposition rate on the surface of the interlayer dielectric layer 103, resulting in a small amount of the second interconnect plug 115 being deposited on the surface of the interlayer dielectric layer 103. Simultaneously, in the subsequent cleaning process, the small amount of the second interconnect plug 115 formed on the surface of the interlayer dielectric layer 103 is completely removed.

[0148] Continue to refer to Figure 14 The method for forming the semiconductor structure further includes: planarizing the second interconnect plug 115 to remove the second interconnect plug material located on top of the interlayer dielectric layer 103, and removing the growth inhibition layer 112 during the planarization process.

[0149] Specifically, the second interconnect plug 115 is planarized, and the growth inhibition layer 112 is removed at the same time, so that the top surface of the interlayer dielectric layer 103, the first interconnect plug 111 and the second interconnect plug 115 has a high degree of flatness, which provides a process basis for the subsequent formation of interconnects on the top of the interlayer dielectric layer 103, the first interconnect plug 111 and the second interconnect plug 115.

[0150] In this embodiment, the planarization process for the second interconnect plug 115 includes a chemical mechanical polishing process.

[0151] It should be noted that in this embodiment, a first interconnect plug 111 electrically connected to the gate structure 108 is formed first, and a second interconnect plug 115 electrically connected to the source-drain interconnect line 109 is formed as a specific embodiment.

[0152] In other embodiments, a first interconnect plug electrically connected to the source-drain interconnect may be formed first, and then a second interconnect plug electrically connected to the gate structure may be formed.

[0153] Therefore, the step of forming a first interconnect plug electrically connected to the source-drain interconnect includes: forming a second opening through the interlayer dielectric layer, the bottom of the second opening exposing the top of the source-drain interconnect; and forming the first interconnect plug in the second opening.

[0154] The second opening provides space for forming the first interconnect plug.

[0155] The second opening is a source / drain opening that exposes the top of the source / drain interconnect.

[0156] The step of forming a second interconnect plug electrically connected to the gate structure includes: forming a first opening through the interlayer dielectric layer, the bottom of the first opening exposing the top of the gate structure; and forming a second interconnect plug in the first opening.

[0157] The first opening provides space for forming the second interconnect plug.

[0158] The first opening is a gate opening that exposes the top of the gate structure.

[0159] In other embodiments, after forming a first interconnect plug extending through the interlayer dielectric layer in the interlayer dielectric layer, and before forming a growth inhibition layer on top of the first interconnect plug, the forming method further includes: removing a portion of the height of the first interconnect plug to form a groove surrounded by the remaining first interconnect plug and the interlayer dielectric layer.

[0160] The groove provides space for the formation of the growth inhibition layer.

[0161] Specifically, since the growth inhibition layer is made of a metal mixture, it has electrical conductivity, enabling the interconnect structure formed in subsequent processes to be electrically connected to the first interconnect plug through the growth inhibition layer.

[0162] It should be noted that the growth inhibition layer located in the groove is flush with the top of the interlayer dielectric layer, which makes the top surface of the growth inhibition layer and the interlayer dielectric layer highly flat, providing a good process foundation for subsequent process manufacturing.

[0163] In the step of forming a growth inhibition layer on top of the first interconnect plug, the growth inhibition layer is formed in the groove.

[0164] The top of the growth inhibition layer is flush with the top of the interlayer dielectric layer. The growth inhibition layer has the function of inhibiting the growth rate of the metal material on its surface. During the formation of the second interconnect plug, it can inhibit the growth rate of the material forming the second interconnect plug on the top of the first interconnect plug.

[0165] It should be noted that, since the second interconnect plug is planarized after its formation, even if the top of the growth inhibition layer is higher than the top of the groove, the growth inhibition layer above the top of the interlayer dielectric layer can be removed during the planarization process.

[0166] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A gate structure is located on the substrate; Sidewall, located on the sidewall of the gate structure; Source and drain doped layers are located within the substrate on both sides of the gate structure; The source-drain interconnect is located on top of the source-drain doped layer and is electrically connected to the source-drain doped layer; An interlayer dielectric layer is located on the substrate exposed by the gate structure, and the interlayer dielectric layer covers the gate structure and the source-drain interconnects; A first interconnect plug is located in and penetrates the interlayer dielectric layer. The first interconnect plug is located on top of the gate structure and electrically connected to the gate structure. Alternatively, the first interconnect plug is located on top of the source-drain interconnect and electrically connected to the source-drain interconnect. In the gate structure and the source-drain interconnect, the part not connected to the first interconnect plug is used as the structure to be interconnected. The second interconnect plug is located in the interlayer dielectric layer at the top of the structure to be interconnected and penetrates the interlayer dielectric layer. The second interconnect plug is electrically connected to the structure to be interconnected. A growth inhibition layer is located on top of the first interconnect plug, and the growth inhibition layer exposes the second interconnect plug.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a gate cap layer located on top of the gate structure; In the first interconnect plug and the second interconnect plug, the one connected to the gate structure serves as the gate plug, and the gate plug also penetrates the gate cap layer.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a source / drain capping layer located on top of the source / drain interconnect; In the first interconnect plug and the second interconnect plug, the one connected to the source-drain interconnect line serves as the source-drain plug, and the one connected to the gate structure serves as the gate plug. The source-drain plug also penetrates the source-drain cap layer, and the gate plug is located between adjacent source-drain cap layers.

4. The semiconductor structure as described in claim 1, characterized in that, The top of the first interconnect plug is lower than the top of the interlayer dielectric layer; The growth inhibition layer fills the space enclosed by the top of the first interconnect plug and the interlayer dielectric layer.

5. The semiconductor structure as described in claim 1, characterized in that, The growth inhibition layer is made of one or both of titanium nitride and fluorine-free tungsten.

6. The semiconductor structure as described in claim 1, characterized in that, The thickness of the growth inhibition layer is from 5 angstroms to 200 angstroms.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the first interconnect plug includes one or more of tungsten, cobalt, molybdenum, and ruthenium; The material of the second interconnect plug includes one or more of cobalt, tungsten, molybdenum and ruthenium.

8. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a metal gate structure.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a gate structure is formed, and source / drain doped layers are formed in the substrate on both sides of the gate structure. A source / drain interconnect is formed between adjacent gate structures, covering the top of the source / drain doped layers and electrically connecting the source / drain doped layers. An interlayer dielectric layer is formed on the substrate, covering the gate structure and the source / drain interconnect. A first interconnect plug is formed in the interlayer dielectric layer, penetrating the interlayer dielectric layer. The first interconnect plug is located on top of the gate structure and electrically connected to the gate structure. Alternatively, the first interconnect plug is located on top of the source-drain interconnect and electrically connected to the source-drain interconnect. In the gate structure and the source-drain interconnect, the part not connected to the first interconnect plug is used as the structure to be interconnected. A growth inhibition layer is formed on top of the first interconnect plug; After the growth inhibition layer is formed, a first opening is formed that penetrates the interlayer dielectric layer, and the bottom of the first opening exposes the top of the structure to be interconnected. A second interconnect plug is formed in the first opening, and the second interconnect plug is electrically connected to the structure to be interconnected.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the first interconnect plug includes: forming a second opening through the interlayer dielectric layer, wherein the bottom of the second opening exposes the top of the gate structure or the top of the source-drain interconnect; A first interconnect plug is formed in the second opening.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing the substrate, an active drain capping layer is formed on top of the source-drain interconnect; When the first interconnect plug is located on top of the gate structure, the first opening is a source / drain opening that exposes the top of the source / drain interconnect, and the second opening is a gate opening that exposes the top of the gate structure. In the step of forming the gate opening, the sidewall of the source / drain capping layer is used as the lateral etching stop position, and a gate opening is formed between adjacent source / drain capping layers, penetrating the interlayer dielectric layer and exposing the top of the gate structure. In the step of forming the source-drain opening, the source-drain opening also penetrates the source-drain cap layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, a gate cap layer is formed on top of the gate structure; In the step of forming the gate opening, the gate opening also extends through the gate cap layer.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming a first interconnect plug penetrating the interlayer dielectric layer in the interlayer dielectric layer, and before forming a growth inhibition layer on top of the first interconnect plug, the forming method further includes: removing a portion of the height of the first interconnect plug to form a groove surrounded by the remaining first interconnect plug and the interlayer dielectric layer; In the step of forming a growth inhibition layer on top of the first interconnect plug, the growth inhibition layer is formed in the groove.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, A growth inhibition layer is formed on top of the first interconnect plug using a selective deposition process.

15. The method for forming a semiconductor structure as described in claim 9, characterized in that, The growth inhibition layer is made of one or both of titanium nitride and fluorine-free tungsten.

16. The method for forming a semiconductor structure as described in claim 9, characterized in that, The gate structure includes a metal gate structure.

17. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process of forming the second interconnect plug in the first opening includes a selective deposition process.

18. The method for forming a semiconductor structure as described in claim 9, characterized in that, The forming method further includes: planarizing the second interconnect plug to remove the second interconnect plug material layer located on top of the interlayer dielectric layer, and removing the growth inhibition layer during the planarization process.

19. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the first interconnect plug includes one or more of tungsten, cobalt, molybdenum, and ruthenium; The material of the second interconnect plug includes one or more of cobalt, tungsten, molybdenum and ruthenium.

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