Method, medium, and apparatus for computational optimization of low-precision machine learning operations

Abstract

The present application is entitled "Computational Optimization of Low Precision Machine Learning Operations". One embodiment provides a general purpose graphics processing unit including a dynamic precision floating point unit including a control unit having precision tracking hardware logic to track an available number of precision bits of computational data related to a target precision, wherein the dynamic precision floating point unit includes computational logic to output data at a plurality of precisions.

Description

Technical Field

[0001] The embodiments generally relate to data processing, and more specifically to data processing via a general-purpose graphics processing unit. Background Technology

[0002] Current parallel graphics data processing includes developing systems and methods to perform specific operations on graphics data, such as linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors (GPUs) use fixed-function computing units to process graphics data; however, recently, partial programmability of GPUs has been made, enabling such processors to support a wide variety of operations for processing vertex and fragment data.

[0003] To further enhance performance, graphics processing units (GPUs) typically implement processing techniques such as attempting to process as much graphics data as possible across different parts of the graphics pipeline in parallel. Parallel GPUs with a Single Instruction Multiple Thread (SIMT) architecture are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as often as possible to increase processing efficiency. A general overview of the software and hardware used in SIMT architectures can be found in Shane Cook's CUDA Programming, Chapter 3, pp. 37–51 (2013) and / or Nicholas Wilt's CUDA Handbook, A Comprehensive Guide to GPU Programming, Sections 2.6.2–3.1.2 (June 2013). Attached Figure Description

[0004] A more specific description of the invention can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments and are therefore not intended to limit the scope of all embodiments.

[0005] Figure 1 This is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein.

[0006] Figures 2A-2D A parallel processor component according to an embodiment is shown.

[0007] Figures 3A-3B This is a block diagram of a graphics multiprocessor according to an embodiment.

[0008] Figures 4A-4F An example architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors.

[0009] Figure 5 A graphics processing pipeline according to an embodiment is shown.

[0010] Figure 6 A machine learning software stack according to an embodiment is shown.

[0011] Figure 7 A highly parallel general-purpose graphics processing unit according to an embodiment is shown.

[0012] Figure 8 A multi-GPU computing system according to an embodiment is shown.

[0013] Figures 9A-9B The layers of a demonstration deep neural network are shown.

[0014] Figure 10 An example recurrent neural network is shown.

[0015] Figure 11 The training and deployment of a deep neural network are illustrated.

[0016] Figure 12 This is a block diagram illustrating distributed learning.

[0017] Figure 13 A sample reasoning on-chip system (SOC) suitable for performing reasoning using a trained model is shown.

[0018] Figure 14 The components of a dynamic precision floating-point unit according to an embodiment are shown.

[0019] Figure 15 Additional details regarding the dynamic precision floating-point unit are provided according to embodiments.

[0020] Figure 16 The thread assignment of a dynamic precision processing system according to an embodiment is shown.

[0021] Figure 17 The logic for performing numerical operations with less-than-required precision according to an embodiment is shown.

[0022] Figure 18 The cyclic vectorization of a SIMD cell according to an embodiment is illustrated.

[0023] Figure 19 A thread processing system according to an embodiment is shown.

[0024] Figure 20 The logic for assigning threads for computation according to an embodiment is shown.

[0025] Figure 21 A deep neural network 2100 is shown that can be processed using computational logic provided by the embodiments described herein.

[0026] Figure 22 This is a block diagram of logic 2200, according to an embodiment, for preventing errors or significant loss of precision when performing low-precision operations for machine learning.

[0027] Figure 23 This is a block diagram of a processing system according to an embodiment.

[0028] Figure 24 It is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0029] Figure 25 It is a block diagram of a graphics processor, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores.

[0030] Figure 26 This is a block diagram of a graphics processing engine for a graphics processor according to some embodiments.

[0031] Figure 27 This is a block diagram of a graphics processor provided by an additional embodiment.

[0032] Figure 28 The diagram illustrates thread execution logic including an array of processing elements employed in some embodiments.

[0033] Figure 29 This is a block diagram illustrating a graphics processor instruction format according to some embodiments.

[0034] Figure 30 This is a block diagram of a graphics processor according to another embodiment.

[0035] Figures 31A-31B The graphics processor command format and command sequence are illustrated according to some embodiments.

[0036] Figure 32 An exemplary graphical software architecture for a data processing system is shown according to some embodiments.

[0037] Figure 33 This is a block diagram illustrating an IP core development system according to an embodiment.

[0038] Figure 34 This is a block diagram illustrating an exemplary system-on-chip integrated circuit according to an embodiment.

[0039] Figure 35 This is a block diagram illustrating an additional graphics processor according to an embodiment.

[0040] Figure 36 This is a block diagram illustrating an additional exemplary graphics processor of a system-on-a-chip integrated circuit according to an embodiment. Detailed Implementation

[0041] In some embodiments, a graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0042] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of embodiments of the invention.

[0043] System Overview

[0044] Figure 1 This is a block diagram illustrating a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 communicating via interconnect paths and a system memory 104, the interconnect paths including a memory hub 105. The memory hub 105 may be a separate component within a chipset assembly or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that enables the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 enables a display controller to provide output to one or more display devices 110A, which may be included within the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0045] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112 coupled to a memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standards-based communication link technologies or protocols (such as, but not limited to, PCI Express), or it can be a vendor-specific communication interface or communication architecture. In one embodiment, the one or more parallel processors 112 form a compute-intensive parallel or vector processing system including a large number of processing cores and / or processing clusters, such as integrated many-core (MIC) processors. In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via an I / O hub 107. The one or more parallel processors 112 may also include a display controller and a display interface (not shown) to enable direct connections to one or more display devices 110B.

[0046] Within the I / O subsystem 111, system storage unit 114 can be connected to I / O hub 107 to provide storage for computing system 100. I / O switch 116 can be used to provide an interface mechanism to enable connectivity between I / O hub 107 and other components that can be integrated into the platform (such as network adapter 118 and / or wireless network adapter 119) and various other devices that can be added via one or more plug-in devices 120. Network adapter 118 can be an Ethernet adapter or another wired network adapter. Wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more radio devices.

[0047] The computing system 100 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., and may also be connected to the I / O hub 107. Any suitable protocol can be used, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interface and / or (multiple) protocols, such as NV-Link high-speed interconnects or interconnect protocols known in the art, to implement [the connection / connection]. Figure 1 The communication paths that connect the various components in the system.

[0048] In one embodiment, the one or more parallel processors 112 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processors 112, memory hub 105, processor(s)102, and I / O hub 107 may be integrated into a system-on-a-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may interconnect with other multi-chip modules to form a modular computing system.

[0049] It will be understood that the computing system 100 shown herein is illustrative and variations and modifications are possible. The connectivity topology can be modified as desired, including the number and arrangement of bridges, the number of processors(102), and the number of parallel processors(112). For example, in some embodiments, system memory 104 is connected directly to processors(102) rather than via bridges, while other devices communicate with system memory 104 via memory hub 105 and processors(102). In other alternative topologies, parallel processors(112) are connected to I / O hub 107 or directly to one of the processors(102), rather than to memory hub 105. In other embodiments, I / O hub 107 and memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors(102) attached via multiple sockets, which may be coupled to two or more instances of parallel processors(112).

[0050] Some of the specific components shown in this document are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may use different terminology with... Figure 1 The components shown are similar to those in the diagram. For example, in some architectures, the memory hub 105 may be referred to as the Northbridge, while the I / O hub 107 may be referred to as the Southbridge.

[0051] Figure 2AA parallel processor 200 according to an embodiment is illustrated. Various components of the parallel processor 200 can be implemented using one or more integrated circuit devices such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). According to an embodiment, the illustrated parallel processor 200 is... Figure 1 The variants of the one or more parallel processors 112 shown in the figure.

[0052] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. This parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface, such as a memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar switch 216, wherein the host interface 206 receives commands relating to performing processing operations, and the memory crossbar switch 216 receives commands relating to performing memory operations.

[0053] When host interface 206 receives a command buffer via I / O unit 204, host interface 206 can route work operations for executing those commands to front end 208. In one embodiment, front end 208 is coupled to scheduler 210, which is configured to distribute commands or other work items to processing cluster array 212. In one embodiment, scheduler 210 ensures that processing cluster array 212 is properly configured and in an active state before distributing tasks to the processing clusters of processing cluster array 212. In one embodiment, scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granular levels, enabling context switching and rapid preemption of threads that can execute on processing array 212. In one embodiment, host software can check for workloads available for scheduling on processing array 212 via one of a plurality of graphics processing doorbells. The workload can then be automatically distributed across processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0054] Processing cluster array 212 may include up to "N" processing clusters (e.g., clusters 214A, 214B to 214N). Each cluster 214A-214N of processing cluster array 212 can execute a large number of concurrent threads. Scheduler 210 may use various scheduling and / or work distribution algorithms to allocate work to clusters 214A-214N of processing cluster array 212, the algorithms of which may vary depending on the workload generated by each type of program or computation. Scheduling may be handled dynamically by scheduler 210 or may be partially assisted by compiler logic during the compilation of program logic configured for execution by processing cluster array 212. In one embodiment, different clusters 214A-214N of processing cluster array 212 may be assigned to process different types of programs or to perform different types of computations.

[0055] The processing cluster array 212 can be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations.

[0056] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic, tessellation logic, and other vertex processing logic for performing texture operations. Additionally, the processing cluster array 212 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 222) and then written back to system memory.

[0057] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations across multiple clusters 214A-214N of the processing cluster array 212. In some embodiments, portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. Intermediate data generated by one or more of the clusters 214A-214N may be stored in a buffer to allow intermediate data to be transferred between the clusters 214A-214N for further processing.

[0058] During operation, the processing cluster array 212 may receive processing tasks to be executed via scheduler 210, which receives commands defining the processing tasks from front-end 208. For graphics processing operations, a processing task may include data to be processed, as well as state parameters defining how the data should be processed (e.g., what program to execute) and an index of commands, such as surface (patch) data, primitive data, vertex data, and / or pixel data. Scheduler 210 may be configured to obtain an index corresponding to the task or may receive an index from front-end 208. Front-end 208 may be configured to ensure that the processing cluster array 212 is configured to be active before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0059] Each of one or more instances of parallel processing unit 202 may be coupled to parallel processor memory 222. Parallel processor memory 222 may be accessed via memory crossbar switch 216, which receives memory requests from processing cluster array 212 and I / O unit 204. Memory crossbar switch 216 may access parallel processor memory 222 via memory interface 218. Memory interface 218 may include multiple partition units (e.g., partition units 220A, 220B through 220N), each of which may be coupled to a portion (e.g., memory cell) of parallel processor memory 222. In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that a first partition unit 220A has a corresponding first memory cell 224A, a second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0060] In various embodiments, memory cells 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, memory cells 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will appreciate that the specific implementation of memory cells 224A-224N can vary and can be selected from a variety of conventional designs. Rendering targets such as frame buffers or texture maps can be stored across memory cells 224A-224N, allowing partitioning cells 220A-220N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of parallel processor memory 222. In some embodiments, local instances of parallel processor memory 222 may be excluded to support a unified memory design utilizing system memory along with local cache memory.

[0061] In one embodiment, any one of the clusters 214A-214N of the processing cluster array 212 can process any data to be written to memory cells 224A-224N within the parallel processor memory 222. The memory crossbar switch 216 can be configured to transfer the output of each cluster 214A-214N to any partition cell 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 via the memory crossbar switch 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar switch 216 has a connection to the memory interface 218 for communication with I / O unit 204, and a connection to a local instance of the parallel processor memory 222, thereby enabling processing units within different processing clusters 214A-214N to communicate with system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 can use virtual channels to separate traffic flows between clusters 214A-214N and partition units 220A-220N.

[0062] Although a single instance of the parallel processing unit 202 is shown within the parallel processor 200, any number of instances of the parallel processing unit 202 may be included. For example, multiple instances of the parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Even if different instances of the parallel processing unit 202 have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences, these different instances may be configured to interoperate. For example, and in one embodiment, some instances of the parallel processing unit 202 may include higher precision floating-point units relative to other instances. Systems combining one or more instances of the parallel processing unit 202 or the parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0063] Figure 2B This is a block diagram of partitioning unit 220 according to an embodiment. In one embodiment, partitioning unit 220 is... Figure 2AAn example of one of the partition units 220A-220N. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from memory crossbar switch 216 and ROP 226. The L2 cache 221 outputs read miss and urgent write-back requests to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory cells in the parallel processor memory, such as (e.g., within the parallel processor memory 222) memory cells 224A-224N of FIG2.

[0064] In graphics applications, ROP 226 is a processing unit that performs raster operations such as stencil printing, z-checking, and blending. ROP 226 then outputs the processed graphics data, which is stored in graphics memory. In some embodiments, ROP 226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. The compression logic can be lossless compression logic utilizing one or more of a variety of compression algorithms. The type of compression performed by ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, Δ color compression is performed on depth and color data on a per-tile basis.

[0065] In some embodiments, ROP 226 is included within each processing cluster (e.g., clusters 214A-214N of FIG. 2) rather than within partition unit 220. In such embodiments, read and write requests for pixel data are transmitted via memory crossbar switch 216, rather than pixel fragment data. The processed graphics data can be displayed on a display device (such as...) Figure 1 On one or more display devices 110, it is routed for further processing by processor(s) 102, or routed for use by... Figure 2A Further processing is performed within one of the processing entities of the parallel processor 200.

[0066] Figure 2CThis is a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of FIG. 2. The processing cluster 214 can be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a specific program executing on a specific set of input data. In some embodiments, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters. Unlike a SIMD execution regime in which all processing engines typically execute the same instructions, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that a SIMD processing regime represents a subset of the functionality of a SIMT processing regime.

[0067] The operation of processing cluster 214 can be controlled via pipeline manager 232, which distributes processing tasks to the SIMT parallel processors. Pipeline manager 232 receives instructions from scheduler 210 of Figure 2 and manages the execution of those instructions via graphics multiprocessor 234 and / or texture unit 236. The graphics multiprocessor 234 shown is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures can be included within processing cluster 214. One or more instances of graphics multiprocessor 234 can be included within processing cluster 214. Graphics multiprocessor 234 can process data, and data crossover switch 240 can be used to distribute the processed data to one of several possible destinations, including other shader units. Pipeline manager 232 can facilitate the distribution of processed data by specifying a destination for the processed data to be distributed via data crossover switch 240.

[0068] Each graphics multiprocessor 234 within the processing cluster 214 may include a set of identical functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). The functional execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions are completed. The functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In one embodiment, the same functional unit hardware can be used to perform different operations, and any combination of functional units may exist.

[0069] Instructions transmitted to processing cluster 214 constitute threads. A collection of threads executing across a set of parallel processing engines is a thread group. Thread groups execute the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. A thread group may also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be performed in consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0070] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 may forgo the internal cache and instead use a cache memory within the processing cluster 214 (e.g., L1 cache 308). Each graphics multiprocessor 234 is also able to access an L2 cache within a partition unit (e.g., partition units 220A-220N of FIG. 2) that is shared among all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. Any memory outside of the parallel processing unit 202 may be used as global memory. Embodiments where the processing cluster 214 includes multiple instances of the graphics multiprocessor 234 may share common instructions and data that can be stored in the L1 cache 308.

[0071] Each processing cluster 214 may include an MMU 245 (Memory Management Unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG2. The MMU 245 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles (more on chunks) and optionally to cache line indices. The MMU 245 may include address translation back buffers (TLBs) or caches that may reside within the graphics multiprocessor 234 or the L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality to allow efficient request interleaving between partition units. Cache line indices can be used to determine whether a request for a cache line is a hit or a miss.

[0072] In graphics and computing applications, processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within graphics multiprocessor 234 and from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs a processed task to data crossover switch 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via memory crossover switch 216. Pre-ROP 242 (Pre-Raster Operation Unit) is configured to receive data from graphics multiprocessor 234 and direct the data to ROP units, which may be located alongside partitioning units as described herein (e.g., partitioning units 220A-220N of FIG. 2). The preROP 242 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0073] It will be understood that the core architecture described herein is illustrative and variations and modifications are possible. Any number of processing units, such as graphics multiprocessors 234, texture units 236, preROP 242, etc., can be included within processing cluster 214. Furthermore, although only one processing cluster 214 is shown, the parallel processing units as described herein can include any number of instances of processing cluster 214. In one embodiment, each processing cluster 214 can be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0074] Figure 2D A graphics multiprocessor 234 according to one embodiment is illustrated. In such embodiments, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0075] In one embodiment, instruction cache 252 receives a stream of instructions to be executed from pipeline manager 232. The instructions are cached in instruction cache 252 and dispatched for execution by instruction unit 254. Instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread in the warp is assigned to a different execution unit within GPGPU core 262. Instructions can access any address space in the local, shared, or global address space by specifying an address within a unified address space. Address mapping unit 256 can be used to translate addresses in the unified address space into different memory addresses accessible by load / store unit 266.

[0076] Register file 258 provides a set of registers for the functional units of graphics multiprocessor 324. Register file 258 provides temporary storage for operands on data paths connected to functional units of graphics multiprocessor 324 (e.g., GPGPU core 262, load / store unit 266). In one embodiment, register file 258 is partitioned between each functional unit such that each functional unit is allocated a dedicated portion of register file 258. In another embodiment, register file 258 is partitioned between different thread bundles being executed by graphics multiprocessor 324.

[0077] Each GPGPU core 262 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. According to embodiments, the GPGPU core 262 may be similar in architecture or may differ in architecture. For example, and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units for performing specific functions such as copying rectangles or pixel blending operations. In one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0078] In one embodiment, GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or can be automatically generated when executing programs written and compiled for Single Program Multiple Data (SPMD) or SIMT architectures. Multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0079] The memory and cache interconnect 268 is an interconnect network that connects each functional unit of the graphics multiprocessor 324 to the register file 258 and shared memory 270. In one embodiment, the memory and cache interconnect 268 is a cross-switch interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, thus data transfers between the GPGPU core 262 and the register file 258 have very low latency. The shared memory 270 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 234. For example, the cache memory 272 can be used as a data cache to cache texture data transferred between functional units and texture units 236. The shared memory 270 can also be used as a cached, managed program. In addition to automatically cached data stored in the cache memory 272, threads executing on the GPGPU core 262 can also programmatically store data in the shared memory.

[0080] Figures 3A-3B An additional graphics multiprocessor according to an embodiment is shown. The illustrated graphics multiprocessors 325, 350 are... Figure 2C Variants of the graphics multiprocessor 234. The graphics multiprocessors 325 and 350 shown can be configured as streaming multiprocessors (SM) capable of executing a large number of execution threads simultaneously.

[0081] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 includes... Figure 2DThe graphics multiprocessor 234 may include multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture units (multiple) 344A-344B. The graphics multiprocessor 325 may also include multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple sets of load / store units 340A-340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0082] Various components can communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more cross switches to enable communication between various components of the graphics multiprocessor 325. In one embodiment, interconnect structure 327 is a separate high-speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. Components of the graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B can each communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation among components.

[0083] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is illustrated. This graphics processor includes multiple sets of execution resources 356A-356D, each set of execution resources including multiple instruction units, register files, GPGPU cores, and load memory units, such as… Figure 2D and Figure 3A As shown, execution resources 356A-356D can operate in harmony with texture units(s) 360A-360D for texture operations, while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D can share instruction cache 354, shared memory 362, and multiple instances of texture and / or data cache memories 358A-358B. Various components can be connected via... Figure 3A The interconnect structure 327 communicates with the similar interconnect structure 352.

[0084] Those skilled in the art will understand that Figure 1 , 2AThe architectures described in -2D and 3A-3B are descriptive and not restrictive within the scope of embodiments of the invention. Therefore, the techniques described herein can be implemented on any appropriately configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as parallel processing unit 202 of FIG. 2), and one or more graphics processors or dedicated processing units, without departing from the scope of the embodiments described herein.

[0085] In some embodiments, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect, such as a high-speed interconnect like PCIe or NVLink. In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0086] Technologies for GPU-to-host processor interconnects

[0087] Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, the high-speed links 440-443 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher, depending on the implementation. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the invention are not limited to any particular communication protocol or throughput.

[0088] Additionally, in one embodiment, two or more of GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as those used for high-speed links 440-443. Similarly, two or more of multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, Figure 4A All communication between the various system components shown can be accomplished using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the invention are not limited to any particular type of interconnect technology.

[0089] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memories 401-402 via memory interconnects 430-431, and each GPU 410-413 is communicatively coupled to GPU memories 420-423 via GPU memory interconnects 450-453. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 401-402 and GPU memories 420-423 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-Ram. In one embodiment, one portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0090] As described below, although the various processors 405-406 and GPUs 410-413 can be physically coupled to specific memories 401-402 and 420-423 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the “effective address” space) is distributed across all the various physical memories. For example, each of the processor memories 401-402 can include 64GB of system memory address space, and each of the GPU memories 420-423 can include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0091] Figure 4B Additional details of the interconnection between a multi-core processor 407 and a graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0092] The processor 407 shown includes multiple cores 460A-460D, each having translational backstops 461A-461D and one or more caches 462A-462D. The cores may include various other components for executing instructions and processing data (e.g., instruction fetch units, branch prediction units, decoders, execution units, reordering buffers, etc.), which are not shown to avoid obscuring the basic principles of the invention. Caches 462A-462D may include Level 1 (L1) and Level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by the set of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and graphics accelerator integrated module 446 are connected to the system memory 441, which may include processor memories 401-402.

[0093] Data and instructions stored in various caches 462A-462D, 456 and system memory 441 are maintained in consistency via inter-core communication through a coherence bus 464. For example, each cache may have associated cache coherence logic / circuit to communicate via the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented via the coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the invention.

[0094] In one embodiment, proxy circuitry 425 communicatively couples graphics acceleration module 446 to coherence bus 464, thereby allowing graphics acceleration module 446 to participate in cache coherence protocols as a peer of the core. Specifically, interface 435 provides connectivity to proxy circuitry 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to high-speed link 440.

[0095] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 431, 432, and N of the graphics acceleration module 446. Each of the graphics processing engines 431, 432, and N may include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, and N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and bit-block transfer engines. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431-432, and N, or the graphics processing engines 431-432, and N may be separate GPUs integrated in a common package, line card, or chip.

[0096] In one embodiment, accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and memory access protocols for accessing system memory 441. MMU 439 may also include a translation back buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 438 stores commands and data for efficient access by graphics processing engines 431-432, N. In one embodiment, data stored in cache 438 and graphics memories 433-434, N is kept consistent with core caches 462A-462D, 456 and system memory 411. As mentioned, this can be accomplished via proxy circuit 425, which represents cache 438 and memories 433-434, N in participating in cache coherency mechanisms (e.g., sending updates to cache 438 related to modifications / accesses to cache lines on processor caches 462A-462D, 456 and receiving updates from cache 438).

[0097] A set of registers 445 stores context data for threads executed by graphics processing engines 431-432, N, and context management circuitry 448 manages the thread context. For example, context management circuitry 448 can perform save and restore operations to save and restore the context of various threads during context switching (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, context management circuitry 448 can store the current register value to a designated area in memory (e.g., identified by a context pointer). It can then restore the register value upon returning to that context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0098] In one implementation, the MMU 439 translates the virtual / effective address from the graphics processing engine 431 into a real / physical address in system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executing on processor 407, or it may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). Resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0099] Therefore, the accelerator integrated circuit acts as a bridge to the system of the graphics acceleration module 446, and provides address translation and system memory caching services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage the virtualization of the graphics processing engine, interrupts, and memory management.

[0100] Because the hardware resources of graphics processing engines 431-432, N are explicitly mapped to the actual address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of graphics processing engines 431-432, N, so that they appear as independent units to the system.

[0101] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are coupled to each of the graphics processing engines 431-432, N, respectively. Graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. Graphics memories 433-434, M can be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0102] In one embodiment, to reduce data traffic on the high-speed link 440, a biasing technique is used to ensure that the data stored in the graphics memories 433-434, M is the data that will be most frequently used by the graphics processing engines 431-432, N and that the cores 460A-460D preferably do not use (or at least not frequently use). Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not the graphics processing engines 431-432, N) within the core caches 462A-462D, 456 and system memory 411.

[0103] Figure 4C Another embodiment in which the accelerator integrated circuit 436 is integrated within the processor 407 is shown. In this embodiment, the graphics processing engines 431-432, N communicate directly with the accelerator integrated circuit 436 via a high-speed link 440 through interfaces 437 and 435 (again, which can utilize any form of bus or interface protocol). The accelerator integrated circuit 436 can perform operations related to... Figure 4B The operations described are the same, but given their close proximity to the coherence bus 462 and caches 462A-462D, 426, they may be performed with higher throughput.

[0104] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The shared programming model may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0105] In one embodiment of the dedicated process model, graphics processing engines 431-432, N are dedicated to a single application or process within a single operating system. This single application can aggregate requests from other applications to graphics engines 431-432, N, thereby providing virtualization within a VM / partition.

[0106] In a dedicated process programming model, the graphics processing engines 431-432,N can be shared by multiple VM / application partitions. This shared model requires the hypervisor to virtualize the graphics processing engines 431-432,N to allow access by each operating system. For single-partition systems without a hypervisor, the graphics processing engines 431-432,N are owned by the operating system. In both cases, the operating system can virtualize the graphics processing engines 431-432,N to provide access to each process or application.

[0107] For a shared programming model, the graphics acceleration module 446 or the separate graphics processing engines 431-432, N use a process handle to select a process element. In one embodiment, the process element is stored in system memory 411 and can be addressed using the effective address to actual address translation techniques described herein. The process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engines 431-432, N (i.e., invoking system software to add a process element to the process element list). The lower 16 bits of the process handle may be the offset of the process element within the process element list.

[0108] Figure 4D An example accelerator integration slice 490 is shown. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application-effective address space 482 within system memory 411 stores process elements 483. In one embodiment, process element 483 is stored in response to a GPU call 481 from an application 480 executing on processor 407. Process element 483 contains the process state for the corresponding application 480. The job descriptor (WD) 484 contained in process element 483 may be a single job requested by the application, or it may contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the application's address space 482.

[0109] The graphics acceleration module 446 and / or separate graphics processing engines 431-432, N can be shared by all or a subset of processes in the system. Embodiments of the invention include infrastructure for establishing process states and sending WD484 to the graphics acceleration module 446 to initiate work in a virtualized environment.

[0110] In one implementation, the dedicated process programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 446 or a separate graphics processing engine 431. Because the graphics acceleration module 446 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 436 for the owned partition, and the operating system initializes the accelerator integrated circuit 436 for the owning process when the graphics acceleration module 446 is assigned.

[0111] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an instruction for a task to be performed by one of the graphics processing engines in the graphics acceleration module 446. Data from the WD 484 can be stored in register 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 448, as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuitry for accessing segment / page tables 486 within the OS virtual address space 485. The interrupt management circuitry 447 can handle interrupt events 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engines 431-432,N is translated into an actual address by the MMU 439.

[0112] In one embodiment, the same set of registers 445 is copied for each graphics processing engine 431-432, N, and / or graphics acceleration module 446, and this same set of registers 445 can be initialized by a hypervisor or operating system. Each of these copied registers can be included in the accelerator integration slice 490. Table 1 shows example registers that can be initialized by a hypervisor.

[0113] Table 1 - Registers initialized by the supervisor

[0114]

[0115] Table 2 shows example registers that can be initialized by the operating system.

[0116] Table 2 - Registers initialized by the operating system

[0117]

[0118] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information required for the graphics processing engine 431-432, N to do its work, or it may be a pointer to a memory location of a command queue that has been set up to perform the work.

[0119] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor physical address space 498 in which a list of process elements 499 is stored. The hypervisor physical address space 498 is accessible via a hypervisor 496, which is used for virtualization of the graphics acceleration module engine of operating system 495.

[0120] The shared programming model allows all or a subset of processes from all or a subset of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time-slice sharing and graphics-oriented sharing.

[0121] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization performed by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) Application job requests must be autonomous (i.e., no state maintenance is required between jobs), or the graphics acceleration module 446 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 446 guarantees completion of application job requests within a specified timeframe, including any transition failures, or the graphics acceleration module 446 provides the ability to preemptively process jobs. 3) When operating in a directed shared programming model, fairness of the graphics acceleration module 446 must be guaranteed between processes.

[0122] In one embodiment, for the shared model, application 480 is required to make an operating system call 495 using the graphics acceleration module 446 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can take the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing the work to be performed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state for the current process. The value passed to the operating system is similar to that set by the application. If the implementation of the accelerator integrated circuit 436 and the graphics acceleration module 446 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Before placing the AMR in process element 483, hypervisor 496 may optionally apply the Current Privilege Mask Overwrite Register (AMOR) value. In one embodiment, CSRP is one of the registers 445 that contains the effective address of a region in the applied address space 482 for use by enabling graphics acceleration module 446 to save and restore context state. This pointer is optional if saving state between jobs or when a job is preempted is not required. The context save / restore region may be pinned system memory.

[0123] Upon receiving a system call, the operating system 495 can verify that application 480 has been registered and granted permission to use the graphics acceleration module 446. The operating system 495 then uses the information shown in Table 3 to invoke the hypervisor 496.

[0124] Table 3 - Parameters for OS to Call the Management Program

[0125]

[0126] Upon receiving a hypervisor call, hypervisor 496 verifies that operating system 495 has been registered and granted permission to use graphics acceleration module 446. Hypervisor 496 then places process element 483 into a linked list of process elements corresponding to the graphics acceleration module 446 type. Process elements may include the information shown in Table 4.

[0127] Table 4 - Process Element Information

[0128]

[0129] In one embodiment, the hypervisor initializes multiple accelerator integration slice 490 registers 445.

[0130] like Figure 4F As shown, one embodiment of the invention employs a unified memory addressable via a shared virtual memory address space for accessing physical processor memories 401-402 and GPU memories 420-423. In this implementation, operations performed on GPUs 410-413 utilize the same virtual / effective memory address space to access processor memories 401-402, and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion to second processor memory 402, a third portion to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 401-402 and GPU memories 420-423, allowing any processor or GPU to access that memory using virtual addresses mapped to any physical memory.

[0131] In one embodiment, the bias / coherence management circuitry 494A-494E within one or more of the MMUs 439A-439E ensures cache coherence between the host processor (e.g., 405) and the cache of the GPUs 410-413, and implements biasing techniques that indicate the physical memory where certain types of data should be stored. While in Figure 4FSeveral instances of bias / coherence management circuitry 494A-494E are shown, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0132] One embodiment allows GPU-attached memories 420-423 to be mapped as a portion of system memory and accessed using shared virtual memory (SVM) technology without suffering the typical performance drawbacks associated with system-wide cache coherence. The ability to access GPU-attached memories 420-423 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are inefficient compared to simple memory access. Meanwhile, the ability to access GPU-attached memories 420-423 without cache coherence overhead can be critical for the execution time of offloading computations. For example, in scenarios with heavy streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410-413. The efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offloading.

[0133] In one implementation, the choice between GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a 1- or 2-bit page-granular structure per GPU-attached memory page (i.e., controlled at the memory page level). The bias table can be implemented within the stolen memory range of one or more GPU-attached memories 420-423, with or without a bias cache in GPUs 410-413 (e.g., caching frequently / recently used entries of the bias table). Alternatively, the entire bias table can be maintained within the GPU.

[0134] In one implementation, the bias table entries associated with each access to GPU-attached memory 420-423 are accessed prior to the actual access to GPU memory, resulting in the following operations: First, local requests from GPUs 410-413 that have found their pages in the GPU bias are forwarded directly to the corresponding GPU memory 420-423. (E.g., via a high-speed link as discussed above) Local requests from GPUs that have found their pages in the host bias are forwarded to processor 405. In one embodiment, a request from processor 405 that has found the requested page in the host processor bias completes like a normal memory read. Alternatively, requests involving GPU bias pages can be forwarded to GPUs 410-413. If the GPU is not currently using the page, the GPU can then translate the page into a host processor bias.

[0135] The page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, for a limited set of cases, purely hardware-based mechanisms.

[0136] One mechanism for changing the bias state involves an API call (such as OpenCL), which in turn invokes the GPU's device driver. The device driver then sends a message to the GPU instructing it to change the bias state (or enqueues a command descriptor). For certain transitions, a cache dump clearing operation is performed on the host machine. This cache dump clearing operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0137] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 405 cannot cache. To access these pages, the processor 405 may request access from the GPU 410, which may or may not grant access immediately, depending on the implementation. Therefore, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are those required by the GPU but not by the host processor 405, and vice versa.

[0138] Graphics processing pipeline

[0139] Figure 5 A graphics processing pipeline 500 according to an embodiment is shown. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included within a parallel processing subsystem as described herein (such as the parallel processor 200 of FIG. 2), which in one embodiment is... Figure 1Variations of the (multiple) parallel processors 112. Various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of parallel processing units (e.g., parallel processing unit 202 of FIG. 2) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3) can be configured to perform the functions of one or more of the vertex processing unit 504, tessellation control processing unit 508, tessellation evaluation processing unit 512, geometry processing unit 516, and fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 can also be performed by other processing engines and corresponding partitioning units (e.g., partitioning units 220A-220N of FIG. 2) within a processing cluster (e.g., processing cluster 214 of FIG. 3). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., parallel processor memory 222 in FIG2) via a memory interface 528, which may be an instance of memory interface 218 of FIG2.

[0140] In one embodiment, the data assembler 502 is a processing unit that collects vertex data of surfaces and primitives. The data assembler 502 then outputs vertex data, including vertex attributes, to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to light and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data and can be programmed to transform the vertex data from an object-based coordinate representation to world space coordinate space or a normalized device coordinate space.

[0141] The first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphical primitives for processing by the tessellation control processing unit 508. Graphical primitives include elements such as triangles, line segments, points, patches, etc., supported by various graphics processing application programming interfaces (APIs).

[0142] The tessellation control processing unit 508 treats input vertices as control points for a geometric patch. These control points are transformed from an input representation of the patch (e.g., the patch's basis) into a representation suitable for use in a surface evaluation performed by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 can also calculate a tessellation factor for the edges of the geometric patch. The tessellation factor is applied to a single edge and quantifies the view-dependent level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factor for the edges of the patch and subdivide the patch into multiple geometric primitives, such as lines, triangles, or quadrilaterals, which are then transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate vertex attributes and a surface representation for each vertex associated with the geometric primitives.

[0143] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphical primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphical primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphical primitives into one or more new graphical primitives and calculate parameters for rasterizing the new graphical primitives.

[0144] In some embodiments, the geometry processing unit 516 can add or delete elements in the geometry flow. The geometry processing unit 516 outputs parameters and vertices specifying new graphic primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphic primitives for processing by the viewport scaling, cull, and clip unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometry data. The viewport scaling, cull, and clip unit 520 performs clipping, cull, and viewport scaling and outputs the processed graphic primitives to the rasterizer 522.

[0145] Rasterizer 522 can perform depth picking and other depth-based optimizations. Rasterizer 522 also performs scan transformations on new graphic primitives to generate fragments and outputs those fragments and associated overlay data to fragment / pixel processing unit 524. Fragment / pixel processing unit 524 is a programmable execution unit configured to execute fragment shader programs or pixel shader programs. Fragment / pixel processing unit 524 transforms fragments or pixels received from rasterizer 522 as specified by the fragment or pixel shader program. For example, fragment / pixel processing unit 524 can be programmed to perform operations including but not limited to texture mapping, shading, blending, texture correction, and perspective correction to produce shaded fragments or pixels output to raster operation unit 526. Fragment / pixel processing unit 524 can read data stored in parallel processor memory or system memory for use when processing fragment data. Fragment or pixel shader programs can be configured to shade at sample, pixel, tile, or other granularities according to a sampling rate configured for the processing unit.

[0146] The raster operation unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-checking, blending, etc., and outputs pixel data as processed graphic data for storage in a graphics memory (e.g., the parallel processor memory 222 in Figure 2, and / or such as...). Figure 1 The data is stored in system memory 104 for display on one or more display devices 110 or for further processing by one or more processors 102 or one of parallel processors 112. In some embodiments, raster operation unit 526 is configured to compress z-or color data written to memory and decompress z-or color data read from memory.

[0147] Machine Learning Overview

[0148] Machine learning algorithms are algorithms that can learn from a set of data. Implementations of machine learning algorithms can be designed to model high-level abstractions within a dataset. For example, image recognition algorithms can be used to determine which of several categories a given input belongs to; regression algorithms can output numerical values ​​given input; and pattern recognition algorithms can be used to generate translated text or perform text-to-speech and / or speech recognition.

[0149] A demonstrative type of machine learning algorithm is the neural network. Many types of neural networks exist; a simple type is the feedforward network. A feedforward network can be implemented as a non-cyclic graph, where nodes are arranged in layers. Typically, a feedforward network topology includes an input layer and an output layer, separated by at least one hidden layer. The hidden layer transforms the input received by the input layer into a representation useful for generating the output in the output layer. Network nodes are fully connected to nodes in adjacent layers via edges, but there are no edges between nodes within a single layer. Data received at the nodes in the input layer of the feedforward network is propagated (i.e., “feedforward”) to the nodes in the output layer via activation functions that compute the state of nodes in each consecutive layer of the network based on coefficients (“weights”), each coefficient associated with one of the edges connecting those layers. Depending on the specific model represented by the algorithm being executed, the output from a neural network algorithm can take various forms.

[0150] Before a machine learning algorithm can be used to model a specific problem, it is trained using a training dataset. Training a neural network involves choosing a network topology, using a set of training data representing the problem being modeled by the network, and adjusting the weights until the network model exhibits minimal error across all instances of the training dataset. For example, during supervised learning training for a neural network, the output generated by the network in response to an input representing an instance in the training dataset is compared to the “correct” labeled output for that instance. An error signal representing the difference between the output and the labeled output is calculated, and the weights associated with the connections are adjusted to minimize the error as the error signal is backpropagated through the layers of the network. The network is considered “trained” when the error of each output generated based on instances of the training dataset is minimized.

[0151] The accuracy of a machine learning algorithm can significantly impact the quality of the dataset used to train it. The training process can be computationally intensive and may take a considerable amount of time on a conventional general-purpose processor. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, as the computations performed when adjusting the coefficients in the neural network naturally facilitate parallel implementation. Specifically, many machine learning algorithms and software applications have been adapted to use parallel processing hardware within general-purpose graphics processing devices.

[0152] Figure 6This is a generalized diagram of the machine learning software stack 600. The machine learning application 602 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 602 may include specialized software that can be used to train the neural network prior to deployment and / or the training and inference capabilities of the neural network. The machine learning application 602 can implement any type of machine intelligence, including but not limited to image recognition, mapping and localization, autonomous navigation, speech synthesis, medical imaging, or language translation.

[0153] Hardware acceleration for machine learning applications 602 can be enabled via the machine learning block 604. The machine learning block 604 provides a library of machine learning primitives. Machine learning primitives are the fundamental operations typically performed by machine learning algorithms. Without the machine learning block 604, developers of machine learning algorithms would be required to create and optimize the main computational logic associated with their algorithms, and then re-optimize that logic when a new parallel processor is developed. Instead, machine learning applications can be configured to use the primitives provided by the machine learning block 604 to perform the necessary computations. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed when training convolutional neural networks (CNNs). The machine learning block 604 can also provide primitives to implement basic linear algebra subroutines performed by many machine learning algorithms, such as matrix and vector operations.

[0154] Machine learning module 604 can process input data received from machine learning application 602 and generate appropriate input for compute module 606. Compute module 606 can abstract the basic instructions provided to GPGPU driver 608, enabling machine learning module 604 to utilize hardware acceleration via GPGPU hardware 610 without requiring machine learning module 604 to be very familiar with the architecture of GPGPU hardware 610. Furthermore, compute module 606 enables hardware acceleration for machine learning module 604 across various types and generations of GPGPU hardware 610.

[0155] GPGPU Machine Learning Acceleration

[0156] Figure 7 The illustration shows a highly parallel general-purpose graphics processing unit 700 according to an embodiment. In one embodiment, the general-purpose processing unit (GPGPU) 700 can be configured to be particularly efficient in handling computational workloads associated with training deep neural networks. Additionally, the GPGPU 700 can be directly linked to other instances of GPGPUs to create a multi-GPU cluster, thereby improving the training speed of particularly deep neural networks.

[0157] The GPGPU 700 includes a host interface 702 for enabling connectivity with a host processor. In one embodiment, the host interface 702 is a PCI Express interface. However, the host interface can also be a provider-specific communication interface or communication structure. The GPGPU 700 receives commands from the host processor and uses a global scheduler 704 to distribute the execution threads associated with those commands to a group of compute clusters 706A-706H. The compute clusters 706A-706H share a cache memory 708. The cache memory 708 can act as an advanced cache within the cache memory of the compute clusters 706A-706H.

[0158] The GPGPU 700 includes memories 714A-714B, which are coupled to the computing cluster 706A-H via a set of memory controllers 712A-712B. In various embodiments, memories 714A-714B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM) (including graphics double data rate (GDDR) memory) or 3D stacked memory (including, but not limited to, high bandwidth memory (HBM)).

[0159] In one embodiment, each computing cluster 706A-706H includes a set of graphics multiprocessors, such as Figure 4A The graphics multiprocessor 400 of the computing cluster includes multiple types of integer and floating-point logic units that can perform computational operations at a range of precisions, including precision suitable for machine learning computations. For example, in one embodiment, at least a subset of the floating-point units in each of the computing clusters 706A-H can be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units can be configured to perform 64-bit floating-point operations.

[0160] Multiple instances of GPGPU 700 can be configured to operate as a computing cluster. The communication mechanisms used by the computing cluster for synchronization and data exchange vary across embodiments. In one embodiment, multiple instances of GPGPU 700 communicate via host interface 702. In one embodiment, GPGPU 700 includes an I / O hub 709 that couples GPGPU 700 to GPU link 710, which enables direct connections to other instances of GPGPU. In one embodiment, GPU link 710 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 700. In one embodiment, GPU link 710 is coupled to a high-speed interconnect to transfer data to and receive data from other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 700 reside in a separate data processing system and communicate via a network device accessible via host interface 702. In one embodiment, GPU link 710 may be configured to enable connections to a host processor, in addition to or as an alternative to host interface 702.

[0161] While the illustrated configuration of the GPGPU 700 can be configured to train neural networks, one embodiment provides an alternative configuration of the GPGPU 700 that can be configured for deployment within a high-performance or low-power inference platform. In the inference configuration, the GPGPU 700 includes fewer compute clusters 706A-H compared to the training configuration. Additionally, the memory technology associated with the memories 714A-714B may differ between the inference and training configurations. In one embodiment, the inference configuration of the GPGPU 700 may support inference-specific instructions. For example, the inference configuration may provide support for one or more 8-bit integer dot product instructions, which are typically used during inference operations against a deployed neural network.

[0162] Figure 8 The illustration shows a multi-GPU computing system 800 according to an embodiment. The multi-GPU computing system 800 may include a processor 802 coupled to a plurality of GPGPUs 806A-806D via a host interface switch 804. In one embodiment, the host interface switch 804 is a PCI express switch device that couples the processor 802 to a PCI express bus through which the processor 802 can communicate with the group of GPGPUs 806A-D. Each of the plurality of GPGPUs 806A-806D may be... Figure 7An example of a GPGPU 700. GPGPU 806A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 816. High-speed GPU-to-GPU links can be via dedicated GPU links (such as... Figure 7 The P2P GPU link 816 is connected to each of the GPGPUs 806A-806D. The P2P GPU link 816 enables direct communication between each of the GPGPUs 806A-806D without requiring communication via the host interface bus to which the processor 802 is connected. In cases where GPU-to-GPU traffic involves the P2P GPU link, the host interface bus can still be used for system memory access or, for example, communication with other instances of the multi-GPU computing system 800 via one or more network devices. While in the illustrated embodiment the GPGPUs 806A-806D are connected to the processor 802 via the host interface switch 804, in one embodiment the processor 802 includes direct support for the P2P GPU link 816 and can be directly connected to the GPGPUs 806A-806D.

[0163] Machine learning neural network implementation

[0164] The computational architectures provided by the embodiments described herein can be configured to perform parallel processing of a type particularly well-suited for training and deploying neural networks for machine learning. Neural networks can be generalized as networks with graph-like relationships. As is well known in the art, there are various types of neural network implementations used in machine learning. An exemplary type of neural network is the feedforward network as previously described.

[0165] The second exemplary type of neural network is the Convolutional Neural Network (CNN). CNNs are specialized feedforward neural networks designed for processing data with known grid-like topologies, such as image data. Therefore, CNNs are commonly used in computational vision and image recognition applications, but they can also be used in other types of pattern recognition, such as speech and language processing. Nodes in the input layer of a CNN are organized into a set of "filters" (feature detectors excited by receptive fields found in the retina), and the output of each set of filters is propagated to nodes in successive layers of the network. The computation for a CNN involves applying convolutional mathematics to each filter to produce its output. Convolution is a specialized kind of mathematical operation performed by two functions to produce a third function, which is a modified version of one of the two original functions. In convolutional network terminology, the first function of the convolution can be called the input, and the second function can be called the convolution kernel. The output can be called a feature map. For example, the input to a convolutional layer can be a multidimensional array of data that defines various color components of the input image. The convolution kernel can be a multidimensional array of parameters, which are adapted through a training process for the neural network.

[0166] Recurrent Neural Networks (RNNs) are a class of feedforward neural networks that include feedback connections between layers. RNNs enable modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture of an RNN includes recurrent loops. A loop represents the effect of a variable's current value on its own value at future times, because at least a portion of the output data from the RNN is used as feedback to process subsequent inputs in the sequence. This feature makes RNNs particularly useful for language processing due to the variable nature that language data can include.

[0167] The following diagrams illustrate exemplary feedforward, CNN, and RNN networks, and describe the general process for training and deploying each of those types of networks, respectively. It will be understood that these descriptions are illustrative and non-limiting with respect to any particular embodiment described herein, and that the concepts illustrated can generally be applied to deep neural networks and machine learning techniques.

[0168] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning performed using deep neural networks. In contrast to shallow neural networks that contain only a single hidden layer, the deep neural networks used in deep learning are artificial neural networks composed of multiple hidden layers. Training deeper neural networks is generally more computationally intensive. However, the additional hidden layers of the network enable multi-step pattern recognition, which results in reduced output error compared to shallow machine learning techniques.

[0169] Deep neural networks used in deep learning typically include a front-end network that performs feature recognition coupled to a back-end network representing a mathematical model. This mathematical model can perform operations (e.g., object classification, speech recognition, etc.) based on the feature representations provided to it. Deep learning enables machine learning to be performed without requiring hand-crafted feature engineering on the model. Instead, deep neural networks can learn features based on statistical structure or correlations within the input data. The learned features can be fed to a mathematical model, which can map the detected features to its output. The mathematical models used by the network are generally specialized for the specific task to be performed, and different models will be used to perform different tasks.

[0170] Once a neural network is structured, a learning model can be applied to it to train it to perform a specific task. The learning model describes how to adjust the weights within the model to reduce the network's output error. Backpropagation of error is a common method used to train neural networks. An input vector is presented to the network for processing. The network's output is compared to the expected output using a loss function, and an error value is calculated for each neuron in the output layer. The error values ​​are then backpropagated until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from those errors using algorithms such as stochastic gradient descent to update the neural network's weights.

[0171] Figures 9A-9B The diagram illustrates a demonstration convolutional neural network. Figure 9A The diagram illustrates the various layers within a CNN. (Example:) Figure 9A As shown, the exemplary CNN used for modeling image processing can receive input 902, which describes the red, green, and blue (RGB) components of an input image. Input 902 can be processed by multiple convolutional layers (e.g., convolutional layer 904, convolutional layer 906). The output from the multiple convolutional layers can optionally be processed by a set of fully connected layers 908. Neurons in a fully connected layer have full connections to all activation functions in the previous layer, as previously described for feedforward networks. The output from the fully connected layer 908 can be used to generate an output from the network. Matrix multiplication can be used instead of convolution to compute activations within the fully connected layer 908. Not all CNN implementations use fully connected layers 908. For example, in some implementations, convolutional layers 906 can generate the CNN output.

[0172] Convolutional layers are sparsely connected, unlike the traditional neural network configuration found in fully connected layers (908). Traditional neural network layers are fully connected, so that each output unit interacts with each input unit. However, convolutional layers are sparsely connected because the output of a convolution of a domain (rather than the corresponding state value of each node in the domain) is fed to nodes in subsequent layers, as illustrated. The kernels associated with the convolutional layers perform convolution operations, the output of which is sent to the next layer. Dimensionality reduction performed within convolutional layers is one aspect that enables CNNs to scale to handle large images.

[0173] Figure 9B The diagram illustrates a demonstration computation phase within a convolutional layer of a CNN. The input 912 to the CNN's convolutional layer can be processed in three stages within convolutional layer 914. These three stages may include a convolutional stage 916, a detector stage 918, and a pooling stage 920. Convolutional layer 914 can then output the data to successive convolutional layers. The final convolutional layer of the network can generate output feature map data or provide input to fully connected layers, for example, to generate classification values ​​for the input to the CNN.

[0174] Several convolutions are performed in parallel within convolution stage 916 to produce a set of linear activations. Convolution stage 916 may include affine transformations, which are any transformations that can be specified as a linear transformation plus translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage computes the output of a function (e.g., a neuron) connected to a specific region in the input, which can be determined as a local region associated with the neuron. The neuron computes the dot product between the neuron's weights and the region in the local input to which the neuron is connected. The output from convolution stage 916 defines a set of linear activations processed by successive stages of convolutional layer 914.

[0175] Linear activations can be processed by detector stage 918. In detector stage 918, each linear activation is processed by a nonlinear activation function. The nonlinear activation function adds nonlinearity to the overall network without affecting the receptive field of the convolutional layer. Several types of nonlinear activation functions can be used. One particular type is the Modified Linear Unit (ReLU), which uses an activation function defined as f(x) = max(0,x) such that the activation is thresholded at zero.

[0176] Pooling stage 920 uses a pooling function that replaces the output of convolutional layer 906 with a generalized statistic of the nearby output. The pooling function can be used to introduce translation invariance into the neural network, such that small translations of the input do not change the pooling output. Local translation invariance can be useful in scenarios where the presence of a feature in the input data is more important than the precise location of that feature. Various types of pooling functions can be used during pooling stage 920, including max pooling, average pooling, and l2-norm pooling. Additionally, some CNN implementations do not include a pooling stage. Instead, such implementations substitute and add convolutional stages with increased strides relative to the previous convolutional stages.

[0177] The output from convolutional layer 914 can then be processed by the next layer 922. The next layer 922 can be either an additional convolutional layer or a fully connected layer 908. For example, Figure 9A The first convolutional layer 904 can output to the second convolutional layer 906, and the second convolutional layer can output to the first layer in the fully connected layer 908.

[0178] Figure 10The diagram illustrates a demonstrative recurrent neural network 1000. In a recurrent neural network (RNN), the network's previous state influences the output of the network's current state. RNNs can be constructed in various ways using a variety of functions. The use of RNNs generally revolves around using mathematical models to predict the future based on previous input sequences. For example, an RNN can be used to perform statistical language modeling to predict an upcoming word given a previous sequence of words. The illustrated RNN 1000 can be described as having an input layer 1002 that receives an input vector, a hidden layer 1004 that implements a recursive function, a feedback mechanism 1005 that enables a 'memory' of previous states, and an output layer 1006 that outputs the result. The RNN 1000 operates based on time steps. The feedback mechanism 1005 influences the RNN's state at a given time step based on previous time steps. For a given time step, the state of the hidden layer 1004 is defined by the previous state and the input at the current time step. The initial input (x1) at the first time step can be processed by the hidden layer 1004. The second input (x2) can be processed by hidden layer 1004 using the state information determined during the processing of the initial input (x1). The given state can be computed as... ,in U and W It is a parameter matrix. Function f Generally, it is nonlinear, such as the hyperbolic tangent function (Tanh) or a correction function. Variations of the RNN 1004. However, the specific mathematical functions used in hidden layer 1004 can vary depending on the specific implementation details of the RNN 1000.

[0179] In addition to the basic CNN and RNN networks described, variations of those networks can be enabled. An example RNN variant is the Long Short-Term Memory (LSTM) RNN. LSTM RNNs are capable of learning long-term dependencies that may be necessary for processing longer language sequences. A variant of CNN is the Convolutional Deep Belief Network (DBN), which has a similar structure to CNNs and is trained in a similar manner to DBNs. A DBN is a generative neural network consisting of multiple layers of random (random) variables. A DBN can be trained layer by layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal set of initial weights for the neural network.

[0180] Figure 11 The training and deployment of a deep neural network are illustrated. Once a given network has been structured for a task, it is trained using a training dataset 1102. Various training block frameworks 1104 have been developed to enable hardware acceleration of the training process. For example, Figure 6The machine learning block 604 can be configured as a training block 604. The training block 604 can be hooked to an untrained neural network 1106 and enables the use of the parallel processing resources described herein to train the untrained neural network to generate a trained neural network 1108.

[0181] To begin the training process, initial weights can be selected randomly or by pre-training using a deep belief network. Training loops are then performed in a supervised or unsupervised manner.

[0182] Supervised learning is a learning method in which training is performed as a mediating operation, such as when the training dataset 1102 includes the input paired with the expected output, or when the training dataset includes inputs with known outputs and the outputs of the neural network are manually graded. The network processes the input and compares the resulting output with a set of expected or desired outputs. The error is then backpropagated through the system. The training block 1104 can be tuned to adjust the weights controlling the untrained neural network 1106. The training block 1104 can provide tools to monitor how well the untrained neural network 1106 converges toward a model suitable for generating correct answers based on known input data. The training process occurs repeatedly as the network weights are adjusted to improve the outputs generated by the neural network. The training process can continue until the neural network reaches the statistically expected accuracy associated with the trained neural network 1108. The trained neural network 1108 can then be deployed to implement any number of machine learning operations.

[0183] Unsupervised learning is a learning method in which a network attempts to train itself using unlabeled data. Therefore, for unsupervised learning, the training dataset 1102 will include input data without any associated output data. The untrained neural network 1106 can learn groupings within the unlabeled inputs and can determine how individual inputs relate to the overall dataset. Unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1107 capable of performing operations useful in reducing data dimensionality. Unsupervised training can also be used to perform anomaly detection, which allows identifying data points in the input dataset that deviate from normal data patterns.

[0184] Variations in supervised and unsupervised training can also be employed. Semi-supervised learning is a technique in which the training dataset 1102 comprises a mixture of labeled and unlabeled data with the same distribution. Incremental learning is a variant of supervised learning in which the input data is continuously used to further train the model. Incremental learning enables the trained neural network 1108 to adapt to new data 1112 without forgetting the knowledge instilled within the network during initial training.

[0185] Whether supervised or unsupervised, training very deep neural networks can be computationally too intensive for a single computing node. A distributed network of computing nodes can be used instead of a single node to accelerate the training process.

[0186] Figure 12 This is a block diagram illustrating distributed learning. Distributed learning uses multiple distributed computing nodes to train models for supervised or unsupervised training of neural networks. Each distributed computing node can include one or more host processors and one or more general-purpose processing nodes, such as... Figure 7 The system features a highly parallel general-purpose graphics processing unit 700. As illustrated, distributed learning can perform model parallelism 1202, data parallelism 1204, or a combination of model and data parallelism 1204.

[0187] In model parallelism 1202, different computing nodes in a distributed system can perform training computations on different parts of a single network. For example, each layer of a neural network can be trained by different processing nodes in a distributed system. Benefits of model parallelism include the ability to scale to particularly large models. Splitting the computations associated with different layers of a neural network makes it possible to train very large neural networks where the weights of all layers are not packed into the memory of a single computing node. In some instances, model parallelism can be particularly useful in performing unsupervised training of large neural networks.

[0188] In data parallelism 1204, different nodes in a distributed network have complete instances of the model, and each node receives a different portion of the data. The results from the different nodes are then combined. While different approaches to data parallelism are possible, all data-parallel training methods require techniques for combining results and synchronizing model parameters across each node. Exemplary methods for combining data include parameter averaging and update-based data parallelism. Parameter averaging trains each node on a subset of the training data and sets global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server to maintain the parameter data. Update-based data parallelism is similar to parameter averaging, except that updates to the model are transmitted instead of parameters from nodes to a parameter server. Alternatively, update-based data parallelism can be performed in a distributed manner, where updates are compressed and transmitted between nodes.

[0189] For example, combined model and data parallelism can be implemented in a distributed system where each compute node includes multiple GPUs. Each node can have a complete instance of the model, with a separate GPU within each node used to train different parts of the model.

[0190] Distributed training incurs increased overhead compared to training on a single machine. However, the parallel processors and GPGPUs described in this paper can each implement various techniques for reducing the overhead of distributed training, including techniques for enabling and accelerating high-bandwidth GPU-to-GPU data transfers and remote data synchronization.

[0191] Demonstration of machine learning applications

[0192] Machine learning can be applied to solve a wide range of technical problems, including but not limited to computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range from reproducing human visual abilities (such as face recognition) to creating new categories of visual abilities. For example, a computer vision application can be configured to identify sound waves from vibrations induced in objects visible in a video. Parallel processor-accelerated machine learning enables the training of computer vision applications using significantly larger training datasets than previously feasible, and allows the deployment of inference systems using low-power parallel processors.

[0193] Parallel processor-accelerated machine learning has applications in autonomous driving, including lane and road sign recognition, obstacle avoidance, navigation, and driving control. Accelerated machine learning techniques can be used to train driving models based on datasets that define appropriate responses to specific training inputs. The parallel processors described in this paper enable the rapid training of increasingly sophisticated neural networks for autonomous driving solutions and allow the deployment of low-power inference processors in mobile platforms suitable for integration into autonomous vehicles.

[0194] Parallel processor-accelerated deep neural networks have enabled machine learning methods for Automatic Speech Recognition (ASR). ASR involves creating functions that compute the most probable language sequence given an input speech sequence. Accelerated machine learning using deep neural networks has made it possible to replace Hidden Markov Models (HMMs) and Gaussian Mixture Models (GMMs) previously used for ASR.

[0195] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automatic learning programs can use statistical inference algorithms to generate models robust to erroneous or unfamiliar inputs. Exemplary natural language processor applications include automatic machine translation between human languages.

[0196] Parallel processing platforms for machine learning can be divided into training platforms and deployment platforms. Training platforms are typically highly parallel and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include... Figure 7 The highly parallel general-purpose graphics processing unit 700 and Figure 8 The multi-GPU computing system 800. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0197] Figure 13 The illustration shows a demonstrative inference system-on-a-chip (SOC) 1300 suitable for performing inference using a trained model. SOC 1300 may integrate processing units including a media processor 1302, a vision processor 1304, a GPGPU 1306, and a multi-core processor 1308. SOC 1300 may additionally include on-chip memory 1305, which enables a shared on-chip data pool accessible by each of the processing units. The processing units can be optimized for low-power operation to enable deployment to a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, one implementation of SOC 1300 can be used as part of a main control system for an autonomous vehicle. When SOC 1300 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the deployment jurisdiction.

[0198] During operation, the media processor 1302 and the vision processor 1304 can work in concert to accelerate computer vision operations. The media processor 1302 enables low-latency decoding of multiple high-resolution (e.g., 4K, 8K) video streams. The decoded video stream can be written to a buffer in on-chip memory 1305. The vision processor 1304 can then parse the decoded video and perform preliminary processing operations on the frames of the decoded video in preparation for processing them using a trained image recognition model. For example, the vision processor 1304 can accelerate convolutional operations for CNNs used to perform image recognition on high-resolution video data, while the back-end model computation is performed by the GPGPU 1306.

[0199] The multi-core processor 1308 may include control logic to assist in the sequencing and synchronization of shared memory operations and data transfers performed by the media processor 1302 and the vision processor 1304. The multi-core processor 1308 may also act as an application processor to execute software applications that can utilize the inference computing power of the GPGPU 1306. For example, at least a portion of navigation and driving logic may be implemented in software executing on the multi-core processor 1308. Such software may directly publish computational workloads to the GPGPU 1306, or may publish computational workloads to the multi-core processor 1308, which may offload at least a portion of those operations to the GPGPU 1306.

[0200] The GPGPU 1306 may include compute clusters, such as low-power configurations of compute clusters 706A-706H within a highly parallel general-purpose graphics processing unit 700. The compute clusters within the GPGPU 1306 may support instructions specifically optimized for performing inference computations on trained neural networks. For example, the GPGPU 1306 may support instructions for performing low-precision computations, such as 8-bit and 4-bit integer vector operations.

[0201] Reduced accuracy of dynamic floating-point units used for machine learning operations

[0202] The IEEE 754 single-precision binary floating-point format specifies a 32-bit binary representation with 1 sign bit, 8 exponent bits, and 24 significant bits, of which 23 bits are explicitly stored. The IEEE 754 half-precision binary floating-point format specifies a 16-bit binary representation with 1 sign bit, 5 exponent bits, and 11 significant bits, of which 10 bits are explicitly stored. The implicit significant bit is defined as 1 for non-zero exponent values ​​and as 0 when all exponent bits are zero. Floating-point units capable of performing arithmetic operations in single-precision and half-precision are known in the art. For example, existing floating-point units can perform 32-bit single-precision floating-point operations (FP32) or dual 16-bit half-precision floating-point operations (FP16).

[0203] The embodiments described herein extend this capability by providing support for instructions and associative logic to enable variable-precision operations. Floating-point instructions that allow variable-precision operations can dynamically increase throughput by performing operations with lower precision when possible. In one embodiment, associative logic and a set of instructions are provided, wherein throughput is increased by performing floating-point operations with the lowest possible precision without significant data loss. In another embodiment, associative logic and a set of instructions are provided, wherein the floating-point logic validates lower-precision results against results performed with higher precision to determine whether any significant data loss has occurred.

[0204] Figure 14Components of a dynamic precision floating-point unit 1400 according to an embodiment are shown. In one embodiment, the dynamic precision floating-point unit 1400 includes a control unit 1402, an internal register set 1404, an exponent block 1406, and a significant bit block 1408. In addition to floating-point control logic known in the art, in one embodiment, the control unit 1402 additionally includes precision tracking logic 1412 and a value transformation unit 1422.

[0205] In one embodiment, precision tracking logic 1412 is hardware logic configured to track the number of available precision bits of computational data associated with a target precision. Precision tracking logic 1412 may track precision registers within exponent block 1406 and significant bit block 1408 to track precision metrics, such as storing the minimum number of precision bits required for computational values ​​generated by exponent block 1406 and significant bit block 1408. In one embodiment, the precision metric includes a running average representing the numerical precision required by data on a computation set. In one embodiment, the precision metric includes the maximum required precision within a given data set. In one embodiment, dynamic precision floating-point unit 1400 supports instructions for reading or resetting register data used by precision tracking logic 1412 to generate the precision metric described herein. In one embodiment, the computation unit housing the dynamic precision floating-point unit supports instructions for setting or resetting register data used by precision tracking logic 1412. In one embodiment, precision tracking logic 1412 monitors an error accumulator 1434 in an internal set of registers 1404. The error accumulator may be used to track accumulated errors (e.g., rounding errors) on a set of floating-point operations. In one embodiment, the dynamic precision floating-point unit 1400 supports a set of instructions including instructions for resetting the error accumulator 1434 and instructions for reading the error accumulator 1434. In one embodiment, the error accumulator may be reset in response to a bit or flag supplied to an instruction as an operand.

[0206] In one embodiment, the numerical transformation unit 1422 can be used to perform intermediate numerical transformations on data when performing low-precision operations to prevent or mitigate the possibility of overflow or underflow during the operation. For example, when approaching the precision limit of a given data type, the numerical transformation unit 1422 can perform multiplication or division operations using logarithms and transform the resulting value via exponentiation. Further details regarding the precision tracking logic 1412 and the numerical transformation unit 1422 are provided in... Figure 22 Provided by China.

[0207] Internal register 1404 includes a set of operand registers 1414 that store input values ​​for the dynamic precision floating-point unit 1400. In one embodiment, operand registers 1414 include two operands (A, B). For floating-point input data, the input data value may be divided into an exponent portion (EXA, EXB) and a significant digit portion (SIGA, SIGB). In various embodiments, operand registers 1414 are not limited to supporting two floating-point inputs. In one embodiment, operand registers 1414 include three input operands, for example to support fused multiply-add, multiply-subtract, multiply-accumulate, or correlated operations. In one embodiment, operand registers 1414 may also store integer values, as in one embodiment the dynamic precision floating-point unit supports 32-bit, 16-bit, and 8-bit integer operations. In one embodiment, specific data types and baseline precision are configurable via inputs to control unit 1402.

[0208] In one embodiment, floating-point operations are performed with dynamic precision using exponent block 1406 and significant bit block 1408. In one embodiment, integer operations can be performed via significant bit block 1408. In one embodiment, dual 8-bit integer operations can be performed using exponent block 1406 and significant bit block 1408.

[0209] In one embodiment, exponent block 1406 includes a comparator 1416 and a dynamic precision exponent adder 1426. The comparator determines the difference between the exponents and identifies the smaller of the two exponents. During floating-point addition, the exponent of the smaller number is adjusted to match the exponent of the larger number. The dynamic precision exponent adder 1426 can be used to add the exponent value for FP16 or FP32 values. Significant bit block 1408 includes a dynamic precision multiplier 1418, a shift unit 1428, a dynamic precision significant bit adder 1438, and an accumulator register 1448.

[0210] In one embodiment, the operation can be specified as either FP16 or FP32 data type. When FP16 is specified, the dynamic precision floating-point unit 1400 can provide power to gate elements that are unnecessary for performing FP32 operations, while maintaining logic to track precision loss or errors (e.g., via error accumulator 1434). For example, and in one embodiment, the error accumulator 1434 can be used to track multiple rounding operations within an instruction cycle. In one embodiment, the error accumulator holds the value of the total accumulated rounding error over the instruction set. The dynamic precision floating-point unit 1400 can enable support for instructions that clear or read the error accumulator 1434 from software. When FP32 is specified, the dynamic precision floating-point unit 1400 can attempt to perform FP32 operations with FP16 precision, while providing power to gate elements and components that exceed the requirements for performing operations with FP16 precision. Based on input or intermediate values, when the dynamic precision floating-point unit 1400 is requested to perform an operation in FP32, it can initially attempt to perform the operation in FP16 and expand the precision up to FP32 as needed. With FP32 operations possible at FP16 precision, the power consumption per operation is reduced, allowing a larger number of compute elements to be enabled simultaneously. For example, dynamic capacitance and / or power budget constraints for a given configuration (such as a battery-powered configuration or a passively cooled configuration only) may not allow all floating-point units or other compute elements within the GPGPU to be enabled simultaneously. By enabling dynamic lower-precision computations to reduce the dynamic power of the floating-point unit set, the overall throughput of the GPGPU's compute units within a given power envelope can be increased because a larger number of threads can be processed on a per-cycle basis without exceeding dynamic power limits.

[0211] Figure 15 Provided according to embodiments relative to Figure 14 Additional details regarding the dynamic precision floating-point unit 1400. In one embodiment, the dynamic precision multiplier 1418 includes a set of input buffers 1302 to store significant bit data. In one embodiment, the set of input buffers includes two buffers to store two input values ​​for a multiplication or division operation. For fused operations (e.g., multiply-add, multiply-subtract), the product of the operations may be added to a third input via an adder and / or stored in an accumulator register.

[0212] In one embodiment, some configurations of the dynamic precision multiplier 1418 include an input buffer that is a 24-bit input (which may explicitly store 24 significant bits of data for single-precision floating-point inputs or 11 significant bits of data for half-precision floating-point values). In some configurations, the input buffer 1302 may also be a 32-bit buffer to enable multiplication of 32-bit integer values. In one embodiment, there is a single configuration of the input buffer 1302 that is selectable or configurable between 32 bits and 24 bits. In one embodiment, the output buffer 1310 is similarly configurable or selectable between 24 bits and 32 bits to selectively enable storage of 24-bit and / or 11-bit significant bits of 32-bit or 16-bit floating-point values ​​or full-precision 32-bit integers.

[0213] In one embodiment, the dynamic precision multiplier 1418 includes a multiplier 1306 and an overflow multiplier 1304. Multiplier 1306 can be configured to perform multiplication or division operations with half precision for data types. For example, multiplier 1306 can perform 11-bit multiplication operations for the significant number of bits of an FP16 floating-point value and / or 16-bit multiplication operations for 16-bit integer operations. Multiplier 1306 can also perform 8-bit multiplication operations for INT8 integer values. For 32-bit floating-point or 32-bit integer values, multiplier 1306 can perform multiplication operations with 11 bits (e.g., FP16 precision) on 24 significant bits. If needed, multiplier 1306 can perform multiplication values ​​with 16 significant bit precision on 24 FP16 significant bits. In one embodiment, the required and obtained precision of operations on a given set of inputs can be tracked via precision register 1308. In one embodiment, the required and obtained precision can be represented in the precision register 1308 by the resulting loss of precision if the output of multiplier 1306 is output via output buffer 1310. In such embodiments, the precision register 1308 can track the precision loss associated with the use of lower precision data types and the precision loss associated with performing operations with a precision lower than the requested precision.

[0214] In one embodiment, the control logic associated with the dynamic precision multiplier 1418 (e.g., in...) Figure 14 Within the control unit 1402, the precision loss associated with operations performing higher precision (e.g., FP32, INT32) operations with lower precision (e.g., FP16, INT16, INT8) can be monitored. If the precision loss would be significant, the control logic can cause the overflow multiplier 1304 to perform an operation on the additional precision bits. Furthermore, if the control logic determines that an overflow or underflow will occur based on the current input, it enables the overflow multiplier 1304 and performs a multiplication operation using both the overflow multiplier 1304 and multiplier 1306.

[0215] Similar control operations are performed on the dynamic precision exponent adder 1426 and the dynamic precision significant digit adder 1438. The dynamic precision exponent adder 1426 includes an 8-bit input buffer set that can store exponent data for FP32 (8 bits) and FP16 (5 bits). The 8-bit input buffer 1312 can also store an INT-8 input set. The output buffer 1320 for the dynamic precision exponent adder 1426 can be configured similarly. The dynamic precision significant digit adder 1438 includes an input buffer set 1322 that can be selected from a 24-bit and a 32-bit buffer set, or can be dynamically configurable to store 24-bit or 32-bit input data. In one embodiment, the input buffer 1322 is simply a 32-bit buffer, which can also store 24-bit input data. The output buffer 1330 for the dynamic precision significant digit adder 1438 can be configured similarly. The precision register 1318 within the dynamic precision exponential adder 1426 and the precision register 1328 within the dynamic precision significant bit adder 1438 can be configured to track the precision loss of the performed operation. The control logic can enable the overflow adder 1314 and / or the overflow adder 1324 as needed to prevent overflow or underflow conditions or to prevent the precision loss from exceeding a threshold.

[0216] return Figure 14 In one embodiment, the dynamic precision floating-point unit 1400 can perform dual INT8 operations using a dynamic precision exponent adder 1426 and a dynamic precision significant bit adder 1438. For example, instead of disabling the exponent block 1406 during integer operations, the exponent block 1406 can be configured to perform operations on a first set of 8-bit integer operands, while the significant bit block 1408 can be configured to perform operations on a second set of 8-bit operands. To enable dual 8-bit multiplication, dual fused multiply-add, dual fused multiply-subtract, and / or other multiplication-based operations, in one embodiment, the exponent block 1406 may include an additional multiplier 1436. The multiplier can be a fixed 8-bit multiplier to enable simultaneous dual 8-bit multiplication operations using the exponent block 1406 and the significant bit block 1408.

[0217] Figure 16The diagram illustrates thread assignment for a dynamic precision processing system 1600 according to an embodiment. In one embodiment, the dynamic precision processing system 1600 includes a set of dynamic floating-point units 1608A-1608D. The dynamic floating-point units 1608A-1608D can execute a set of operation threads 1606A-1606D, which can perform mixed-precision operations and generate output data with variable precision. In one embodiment, a first operation (e.g., addition, subtraction, multiplication, division, etc.) can be performed on a first dynamic floating-point unit 1608A by a first operation thread 1606A, wherein the first operation thread 1606A accepts two 16-bit floating-point values ​​1602A-1602B as input and outputs a 16-bit floating-point value FP16. The first operation can be executed as a double operation, wherein a single instruction executed by the GPGPU allows mixed-precision FP16 / FP32 double operations. The second operation of the double operation can be executed by a second operation thread 1606B, which is executed by a second dynamic floating-point unit 1608B. The second dynamic floating-point unit 1608B can generate a second output 1612 as a 32-bit floating-point output. The second operation thread 1606B configures the second dynamic floating-point unit 1608B to receive two 32-bit floating-point input values ​​1603A-1603B. In one embodiment, the operation on the two 32-bit floating-point operations can be performed with 16-bit precision if it can be performed without excessive loss of precision, underflow, or overflow by performing the operation with lower precision.

[0218] In one embodiment, the dynamic precision processing system 1600 can execute a single instruction having a 16-bit operand 1604A and a 32-bit operand 1604B. The operation thread 1606C can execute on the dynamic floating-point unit 1608C. The dynamic floating-point unit 1608C will attempt to perform mixed-precision 16-bit / 32-bit operations with 16-bit precision unless significant precision loss or error occurs. In one embodiment, the dynamic precision processing system 1600 can also be configured to perform integer operations. For example, operations on a pair of 8-bit integer inputs 1605A-1605B can be performed via the operation thread 1606D using the dynamic floating-point unit 1608D to generate an 8-bit integer output 1616. In one embodiment, the dynamic floating-point unit 1608D can be configured to perform dual 8-bit integer operations, where two 8-bit integer operations can be performed in a single cycle.

[0219] Figure 17 Logic 1700 is illustrated according to an embodiment, which performs numerical operations with less than the requested precision. In one embodiment, logic 1700 is integrated with... Figure 14 The dynamic precision floating-point unit 1400 is implemented in hardware. In one embodiment, the logic 1700 is partially implemented via... Figure 14The control unit 1402 within the dynamic precision floating-point unit 1400 executes the commands.

[0220] In one embodiment, logic 1700 may receive a request to perform a numerical operation with a first precision, as shown in block 1702. The numerical operation may be a floating-point operation or an integer operation. The first precision may be, for example, 32-bit precision. In one embodiment, the numerical operation may be an operation with the first precision performed on an operation with mixed precision. Logic 1700 may then perform the numerical operation using a plurality of bits associated with a second precision lower than the first precision, as shown in block 1704. For example, and in one embodiment, the number of bits used to perform the operation may be a plurality of bits associated with a 16-bit operation, while the first precision is 32-bit precision. In block 1706, logic 1700 may generate an intermediate result with the second precision. Logic 1700 may then determine the precision loss of the intermediate result associated with the first precision. The precision loss may be read from a register that stores a precision loss indicator stored during the operation.

[0221] In block 1709, logic 1700 can determine whether the precision loss is less than a threshold. In one embodiment, the threshold associated with the precision loss can be software-configurable, although a hardware default threshold is used in some embodiments. In one embodiment, the degree of precision loss can also be determined by performing a full-precision operation in parallel on unused computational units. The reduced precision result can then be compared with the full-precision result. If the precision loss is less than the threshold, logic 1700 can output the result with a second precision, as shown in block 1712. If the precision loss in block 1709 is not less than the threshold, then in block 1710, logic 1700 can compute the remaining bits of the result and output the result with a first precision, as shown in block 1714. In one embodiment, this can be achieved via an overflow logic unit (such as, as shown in...). Figure 15 The overflow multiplier 1304, overflow adder 1314 and / or overflow adder 1324 in block 1710 are used to perform the calculation on the remaining bits of the result.

[0222] Vertical stacking of 16-bit floating-point operations

[0223] When performing Single Instruction Multiple Thread (SIMT) operations with lower precision, maintaining full utilization of the underlying Single Instruction Multiple Data (SIMD) logic can be difficult in some cases due to the large number of elements required to fill all SIMD channels. For example, a SIMD logic unit configured for FP32 operations on 128-bit input registers can perform a single operation on four sets of input data. If the logic unit is configured to perform FP16 operations on the same four sets of input data, the underlying throughput of the operation may increase due to the lower operational precision, but the SIMD utilization is halved. One solution to underutilizing SIMD is to perform the operation on eight sets of input data. However, the software executing on the logic unit may not require as much parallelism as the underlying hardware can provide.

[0224] For example, a loop that performs iterative operations on an input array can be vectorized, allowing each iteration of the array to be executed in parallel as a separate SIMT thread. A separate SIMT thread can execute on the underlying SIMD / vector logic within a single computational unit in a single operation. When executing parallel instructions derived via compiler-generated loop vectorization logic, loops shorter than 8 iterations will not fill all eight SIMD channels available for execution on the threads that produce those operations, reducing the overall utilization of the computational unit. Furthermore, in cases where the underlying hardware has N SIMD channels, any number of vectorized iterations that are not multiples of N will require the remainder iterations to be performed on fewer than all SIMD units. Additionally, vectorization may require a separate peel loop to be executed before the body of the vectorized operation.

[0225] Some embodiments described herein can increase SIMD utilization by stacking multiple unrelated FP16 operations into a single SIMD unit for execution. With the SIMD unit having eight channels available for execution, the thread scheduling logic can dispatch threads in units of N / 2 or N / 4, allowing unrelated sets of threads performing the same or compatible operations to share a single SIMD unit. Furthermore, one embodiment enables SIMD channel scheduling, which allows for a mix of dynamically assembled SIMT thread groups and vectorized SIMD threads.

[0226] Figure 18Loop vectorization for a SIMD unit according to an embodiment is illustrated. In one embodiment, the software logic may include loops automatically vectorized by compiler software executed on a data processing system. The loop may include a stripping loop 1802, a vectorized main loop 1804, and a remainder loop 1806. In some configurations, loop vectorization is most efficient when performing on data accessed to memory aligned to the specified memory. For example, a GPGPU may be configured such that vector memory accesses can be performed most efficiently in 64-byte blocks 1801A-1801F. In such a configuration, the stripping loop 1802 includes a subset of loop iterations stripped from the main loop to allow unaligned memory accesses to be isolated from the main loop. The vectorized main loop 1804 includes most of the loop iterations. Each iteration of the vectorized main loop can be executed in parallel, and memory accesses for each element are aligned on specific memory boundaries. The remainder loop 1806 includes a set of iterations following the vectorized main loop 1804. Iterations in the remainder loop 1806 can generally not be executed in parallel as efficiently as the main loop.

[0227] In one embodiment, stripping loop 1802 and remainder loop 1806 can also be vectorized. In one embodiment, each of stripping loop 1802, main loop 1804, and remainder loop 1806 can be executed on an FP16 SIMD8 unit, where eight instances of the same operation can be executed in parallel. Loop iterations can be executed in parallel on SIMD hardware (e.g., FP16 SIMD8 units 1801A-1808C) using execution masks 1812, 1814, and 1816 (each enabling and disabling SIMD channels for an operating cycle). For the illustrated stripping loop 1802 and remainder loop 1806, a subset of elements is selected in execution masks 1812 and 1816. All channels are selected in execution mask 1814 for the vectorized main loop 1804.

[0228] In one embodiment, a SIMD unit with inactive channels can be configured to perform other operations on those inactive channels. For a given period, where the scheduling logic configures a set of inactive channels for a SIMD unit (e.g., FP16 SIMD8 1808A, FP16SIMD8 108C) instead of leaving those channels idle during the period, the scheduler can stack other multi-element SIMD threads or assign SIMT threads to SIMD channels that are otherwise idle.

[0229] Figure 19A thread processing system 1900 according to an embodiment is illustrated. In one embodiment, the thread processing system 1900 includes a SIMD computing unit, such as a SIMD8 floating-point unit 1920 comprising a plurality of dynamic floating-point units 1922A-1922H. Depending on the operation, the SIMD8 floating-point unit 1920 can perform eight or more identical or similar operations in a single cycle. For example, and in one embodiment, each of the eight dynamic floating-point units 1922A-1922H can perform a single operation with FP16 precision. In one embodiment, each of the eight dynamic floating-point units 1922A-1922H can perform two paired INT8 operations in a single cycle.

[0230] In some cases, such as having Figure 18 The stripping or remainder cycle shown does not represent the activity of all channels of the SIMD floating-point unit during the cycle. To increase utilization, SIMD slots can be assigned at a smaller granularity to enable additional unused SIMD channels to be utilized. For example, a SIMD8 floating-point unit 1920 would typically be assigned threads or operations at an eight-operation granularity, where fewer than eight operations presents a potential computational efficiency penalty. In one embodiment, a SIMD channel can be occupied by a single vector of SIMD threads, which includes an execution mask that selects at least eight elements or a group of SIMT threads with at least eight elements.

[0231] To increase SIMD utilization, one embodiment divides eight SIMD channels into two SIMD4 slots (e.g., SIMD4 slot 1910, SIMD4 slot 1912). SIMD4 slots can be filled in various ways. In one embodiment, two separate SIMD threads (SIMD thread 1902, SIMD thread 1904) combined to cover a total of four SIMD channels are assigned to a SIMD4 slot (e.g., SIMD4 slot 1910). In one embodiment, a SIMT thread group 1906 can be assigned to SIMD4 slot 1912. The SIMT thread group 1906 can include any number of threads that are multiples of four threads (e.g., 4, 8, 12, 16, etc.). Threads within the SIMT thread group 1906 can be processed in four-thread-at-a-time manner, wherein the number of cycles required to process all threads within the SIMT thread group 1906 depends on the number of threads in the group.

[0232] Figure 20 The illustration shows logic 2000 for assigning threads for computation according to an embodiment. In one embodiment, logic 2000 is configured via, for example... Figure 19The thread processing system 1900 in the SIMD unit performs the execution. In one embodiment, logic 2000 may receive a first set of threads at a SIMD unit having a first number of channels, as shown in block 2002. Logic 2000 may then determine whether the first set of threads fills all the SIMD channels of the SIMD unit, as shown in block 2003. If the first set of threads includes enough SIMD threads or the threads in the first set of threads include enough SIMD vector elements to fill all the SIMD channels, then logic 2000 may assign the first set of threads to the SIMD unit, as shown in block 2004.

[0233] As determined in block 2003, if the first set of threads does not fill all SIMD channels, then in block 2006, logic 2000 can assign the first set of threads to a second number of channels, which is less than the first number of channels. Assignment can be performed by assigning SIMD threads to SIMD units and masking inactive channels. Assignment can also be performed by assigning a set of SIMD threads to SIMD units. As shown in block 2008, the logic can then stack one or more additional set of threads to fill all SIMD channels. Additional set of threads can specify active SIMD channels that occupy channels not initially occupied by the threads.

[0234] Systems that enable normalization and transformation of low-precision data

[0235] When performing operations using low-precision data types, care must be taken to avoid data overflow or underflow during numerical operations. This responsibility typically falls to the data scientists who develop low-precision algorithms. Due to the limitations of low-precision arithmetic, many neural networks have been adapted to use binary and / or ternary values ​​(each element occupying only one or two bits). However, there is a need for integer and floating-point arithmetic logic units that can enable N-bit low-precision arithmetic with protection logic to warn or attempt to prevent significant loss of precision during arithmetic operations. In one embodiment, the dynamically precision floating-point unit described herein includes logic that warns when numerical computation approaches the limits of low-precision computation.

[0236] like Figure 14As shown, the dynamic precision floating-point unit 1400 may include precision tracking logic 1412 and a numerical transformation unit 1422. In one embodiment, the precision tracking logic 1412 tracks the available bits of precision retained for the calculated data in relation to a target precision. The available bits of precision can be tracked for intermediate data to determine whether an intermediate value (which in one embodiment is calculated with higher precision in relation to the input or output data) can be stored with output precision without significant loss of precision or rounding error. For example, and in one embodiment, a particular low-precision operation can be performed efficiently with higher precision, and the precision tracking logic 1412 can determine whether the result of the calculation will overflow a given output precision. In one embodiment, the logic unit described herein can output status information indicating the degree of precision loss due to rounding error. In one embodiment, the logic unit can perform an intermediate numerical transformation on the data to prevent significant data loss. The logic unit can then output the transformed value. In one embodiment, a full-precision or near-full-precision output value can be programmatically derived based on the output and status information provided with the output.

[0237] Figure 21 A deep neural network 2100 is illustrated that can be processed using the computational logic provided by the embodiments described herein. A deep neural network (DNN) is an artificial neural network comprising multiple neural network layers 2102A-2102N. Each layer represents a set of nonlinear computational operations to perform feature extraction and transformation in a manner consistent with the machine learning neural networks described herein. Each successive layer uses the output from the previous layer as input. In the case of a convolutional neural network, fused multiply-accumulate logic (e.g., FMA logic 2104A, 2104B) can be used to compute the dot product between feature maps and filter data to generate activation map data provided as input to successive layers.

[0238] Low-precision neural networks can be implemented using binary or ternary weights combined with binary, ternary, or N-bit feature maps. Some neural networks can still benefit from the added computational precision of using N-bit feature maps and N-bit filters. In some implementations, the N-bit features and weights of a neural network can be processed with low precision without significantly reducing output error. However, data scientists implementing low-precision N-bit neural networks (e.g., FP16, INT8) should generally be aware of potential rounding errors or out-of-bounds data due to continuous computation with low precision. If the precision tracking logic in the FMA logic 2104A-2106B (e.g., ...) Figure 14If the precision tracking logic 1412 determines that the weight or feature map data is approaching the limit of the available precision for the data type, the status bit can be set by the FMA logic 2104A-2015B. The status bit can act as an indicator for data scientists developing neural network models existing within neural network layers 2102A-2012N, alerting them to potential optimizations or higher numerical precision requirements.

[0239] In one embodiment, before providing the feature map data to the next neural network layer as input, the normalization and transformation logics 2106A-2106B can perform weight normalization or numerical transformation on the feature map data. The application of the normalization and transformation logics 2106A-2106B is optional at each stage and can only be performed if significant loss of accuracy, overflow, or underflow conditions are likely during the processing of the upcoming layer. In one embodiment, the weights or feature maps output from the layers of the neural network can be automatically normalized via instances of the normalization and transformation logics 2106A-2106B.

[0240] In one embodiment, the normalization and transformation logic 2106A-2016B can be used Figure 14 The numerical transformation unit 1422 transforms the feature map data or weight data. The feature map data output from the neural layer may be based on a data set output from the function set. In such embodiments, a specific set of low-precision instructions is provided, which enables automatic adjustment of the N-bit neural network data to prevent catastrophic loss of precision. Exemplary transformations or normalizations that can be performed by normalization and transformation logic 2106A-2016B include weight normalization over a set or range of values ​​of continuous and reversible feature data transformations. In one embodiment, weight normalization may be performed to compress the dynamic range of the filter weight set to a predetermined range. The weight data may be normalized, for example, within the range of [-1, 1], which can preserve the relative differences between weight values ​​while reducing the overall magnitude of the weight values. In one embodiment, the neural network weights or feature map data may be normalized by means of the average value of the dataset.

[0241] In one embodiment, neural network computation using data close to the range limits of the data type can be transformed before the data is used for computation. For example, a multiplication operation using large values ​​that might cause overflow can be performed as a logarithmic addition instead of a multiplication operation. Although such transformation may cause some degree of precision loss, the computation will be able to be performed without overflowing the number of bits allocated for performing the operation. For example, a series of operations can be presented as in equation (1).

[0242]

[0243] If the precision tracking logic within the computation unit determines that such an operation may overflow or underflow, then the operation can be transformed into equation (2).

[0244]

[0245] Equation (2) can be executed to produce a result without triggering a data type overflow. In one embodiment, before using the values ​​described herein for machine learning computation, the normalization and transformation logic 2106A-2016B can transform the output value into a logarithmic value for storage and transform the value by means of exponentiation.

[0246] Figure 22 This is a flowchart of logic 2200 according to an embodiment, which prevents errors or significant loss of precision when performing low-precision operations for machine learning. In one embodiment, logic 2200 may be implemented via, for example... Figure 14 The numerical transformation unit 1422 and precision tracking logic 1412 within the dynamic precision floating-point unit 1400 are used to implement this.

[0247] In one embodiment, logic 2200 may compute activation maps based on filter and feature map data associated with layers of the neural network, as shown in block 2202. Logic 2200 may then track the precision loss that occurs during the computation of activation maps for neural network layers. Logic 2200 may then determine in block 2205 whether the precision loss is close to a threshold. If the precision loss is not close to a default or configured threshold in block 2205, logic 2200 may continue to compute activation maps (and apply activation functions) for successive layers until and unless the precision loss approaches the threshold in block 2205. When the precision loss approaches the threshold, logic 2200 may determine in block 2207 whether automatic numerical transformation is enabled. If automatic transformation is enabled in block 2207, for example via instructions for performing a set of numerical operations, logic 2200 may transform the neural network data in block 2208 to reduce errors due to precision loss. Logic 2200 may perform any numerical transformation described herein, including data normalization by means of averages or ranges. Regardless of whether automatic transformation is enabled in block 2207, logic 2200 in block 2210 can output a state indicating that the accuracy loss is approaching a threshold. As a result of the executed operation, the state can be output as a state flag from the computation unit. Programmers can configure the software logic to respond to such states by adjusting the algorithm executed by the executor or by modifying the neural network model used to perform machine learning.

[0248] Additional demonstration graphics processing system

[0249] The details of the embodiments described above can be incorporated into the graphics processing systems and devices described below. Figures 23 to 36The graphics processing systems and devices described herein illustrate alternative systems and graphics processing hardware that can implement any and all of the techniques described above.

[0250] Additional Exemplary Graphics Processing System Overview

[0251] Figure 23 This is a block diagram of a processing system 2300 according to an embodiment. In various embodiments, system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2302 or processor cores 2307. In one embodiment, system 2300 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile devices, handheld devices, or embedded devices.

[0252] Embodiments of system 2300 may include a server-based gaming platform, a game console including a game and media console, a mobile game console, a handheld game console, or an online game console, or integrated therein. In some embodiments, system 2300 is a mobile phone, smartphone, tablet computing device, or mobile internet device. Data processing system 2300 may also include wearable devices (such as smartwatches, smart glasses, augmented reality devices, or virtual reality devices), coupled to said wearable device, or integrated within said wearable device. In some embodiments, data processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0253] In some embodiments, each of the one or more processors 2302 includes one or more processor cores 2307 for processing instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 2307 is configured to process a particular instruction set 2309. In some embodiments, the instruction set 2309 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). Multiple processor cores 2307 may each process a different instruction set 2309, which may include instructions for facilitating emulation of other instruction sets. The processor cores 2307 may also include other processing devices, such as digital signal processors (DSPs).

[0254] In some embodiments, processor 2302 includes cache memory 2304. Depending on the architecture, processor 2302 may have a single internal cache or multiple internal cache levels. In some embodiments, cache memory is shared among various components of processor 2302. In some embodiments, processor 2302 also uses an external cache (e.g., a Level 3 (L3) cache or a Last Level Cache (LLC)) (not shown), which can be shared among processor cores 2307 using known cache coherence techniques. Register file 2306 is additionally included in processor 2302 and may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general-purpose registers, while others may be specific to the design of processor 2302.

[0255] In some embodiments, processor 2302 is coupled to processor bus 2310 to transmit communication signals, such as address, data, or control signals, between processor 2302 and other components in system 2300. In one embodiment, system 2300 uses an exemplary 'central' system architecture including a memory controller central hub 2316 and an input / output (I / O) controller central hub 2330. Memory controller central hub 2316 facilitates communication between memory devices and other components of system 2300, while I / O controller central hub (ICH) 2330 provides connectivity to I / O devices via a local I / O bus. In one embodiment, the logic of memory controller central hub 2316 is integrated within the processor.

[0256] Memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance to act as process memory. In one embodiment, memory device 2320 may operate as system memory of system 2300 to store data 2322 and instructions 2321 for use by the one or more processors 2302 when executing an application or process. Memory controller hub 2316 is also coupled to an optional external graphics processor 2312, which may communicate with the one or more graphics processors 2308 in processor 2302 to perform graphics and media operations.

[0257] In some embodiments, ICH 2330 enables peripheral devices to connect to memory device 2320 and processor 2302 via a high-speed I / O bus. I / O peripheral devices include, but are not limited to, an audio controller 2346, a firmware interface 2328, a wireless transceiver 2326 (e.g., Wi-Fi, Bluetooth), a data storage device 2324 (e.g., a hard disk drive, flash memory, etc.), and a legacy I / O controller 2340 for coupling legacy devices (e.g., Personal System 2 (PS / 2)) to the system. One or more Universal Serial Bus (USB) controllers 2342 connect input devices, such as a keyboard and mouse combination 2344. A network controller 2334 may also be coupled to ICH 2330. In some embodiments, a high-performance network controller (not shown) is coupled to processor bus 2310. It will be understood that the illustrated system 2300 is exemplary and not limiting, as other types of data processing systems with different configurations may also be used. For example, the I / O controller hub 2330 may be integrated within one or more processors 2302, or the memory controller hub 2316 and the I / O controller hub 2330 may be integrated into a discrete external graphics processor (such as external graphics processor 2312).

[0258] Figure 24 This is a block diagram of an embodiment of processor 2400, which has one or more processor cores 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408. Figure 24 Those elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. Processor 2400 may include, and include, additional cores 2402N, indicated by the dashed block. Each of processor cores 2402A-2402N includes one or more internal cache units 2404A-2404N. In some embodiments, each processor core may also have access to one or more shared cache units 2406.

[0259] Internal cache units 2404A-2404N and shared cache unit 2406 represent the cache memory hierarchy within processor 2400. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest-level cache preceding external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 2406 and 2404A-2404N.

[0260] In some embodiments, the processor 2400 may further include a system agent core 2410 and a collection of one or more bus controller units 2416. The one or more bus controller units 2416 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 2410 provides management functions for various processor components. In some embodiments, the system agent core 2410 includes one or more integrated memory controllers 2414 for managing access to various external memory devices (not shown).

[0261] In some embodiments, one or more of processor cores 2402A-2402N include support for simultaneous multithreading. In such embodiments, system agent core 2410 includes components for coordinating and operating processor cores 2402A-2402N during multithreaded processing. System agent core 2410 may additionally include a power control unit (PCU) including logic and components for regulating the power states of processor cores 2402A-2402N and graphics processor 2408.

[0262] In some embodiments, processor 2400 additionally includes a graphics processor 2408 for performing graphics processing operations. In some embodiments, graphics processor 2408 is coupled to a set of shared cache units 2406 and a system proxy core 2410, the system proxy core 2410 including the one or more integrated memory controllers 2414. In some embodiments, display controller 2411 is coupled to graphics processor 2408 to drive graphics processor output to one or more coupled displays. In some embodiments, display controller 2411 may be a separate module coupled to graphics processor via at least one interconnect, or it may be integrated within graphics processor 2408 or system proxy core 2410.

[0263] In some embodiments, the ring-based interconnect unit 2412 is used to couple internal components of the processor 2400. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art, may be used. In some embodiments, the graphics processor 2408 is coupled to the ring interconnect 2412 via I / O link 2413.

[0264] The exemplary I / O link 2413 represents at least one of a variety of I / O interconnects, including on-package I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2418 (such as eDRAM modules). In some embodiments, each processor core in processor cores 2402A-2402N and graphics processor 2408 uses embedded memory module 2418 as a shared final-level cache.

[0265] In some embodiments, processor cores 2402A-2402N are homogeneous cores executing the same instruction set architecture. In another embodiment, processor cores 2402A-2402N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 2402A-2402N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled to one or more power cores with lower power consumption. Additionally, processor 2400 may be implemented on one or more chips or as a SoC integrated circuit having, among other components, the shown components.

[0266] Figure 25 This is a block diagram of a graphics processor 2500, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed in processor memory. In some embodiments, the graphics processor 2500 includes a memory interface 2514 for accessing memory. The memory interface 2514 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0267] In some embodiments, the graphics processor 2500 further includes a display controller 2502 for driving display output data to a display device 2520. The display controller 2502 includes hardware for one or more overlapping planes of the display and a composition of multi-layer video or user interface elements. In some embodiments, the graphics processor 2500 includes a video codec engine 2506 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and SMPTE 421 M / VC-1 and Joint Group of Picture Experts (JPEG) formats (such as JPEG and Motion JPEG (MJPEG)).

[0268] In some embodiments, the graphics processor 2500 includes a block image transfer (BLIT) engine 2504 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2510. In some embodiments, the GPE 2510 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0269] In some embodiments, GPE 310 includes a 3D pipeline 2512 for performing 3D operations such as rendering 3D images and scenes using processing functions that act on the shapes of 3D primitives (e.g., rectangles, triangles, etc.). The 3D pipeline 2512 includes programmable and fixed functional elements that perform various tasks within the elements and / or generate a large number of execution threads for the 3D / media subsystem 2515. While the 3D pipeline 2512 can be used to perform media operations, embodiments of GPE 2510 also include a media pipeline 2516 specifically designed for performing media operations such as video post-processing and image enhancement.

[0270] In some embodiments, the media pipeline 2516 includes fixed-function or programmable logic units to perform one or more specialized media operations, such as video decoding acceleration, video deinterleaving, and video encoding acceleration, in place of or on behalf of the video codec engine 2506. In some embodiments, the media pipeline 2516 additionally includes a thread mass generation unit to mass-generate threads for execution on the 3D / media subsystem 2515. The mass-generated threads perform computations for media operations on one or more graphics execution units included in the 3D / media subsystem 2515.

[0271] In some embodiments, the 3D / media subsystem 2515 includes logic for executing threads massed by the 3D pipeline 2512 and the media pipeline 2516. In one embodiment, the pipelines send thread execution requests to the 3D / media subsystem 2515, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 2515 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data and storing output data among threads.

[0272] Demonstration of additional graphics processing engine

[0273] Figure 26 This is a block diagram of a graphics processing engine 2610 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 2610 is... Figure 25 The image shows a version of GPE 2510. Figure 26 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein. For example, shown Figure 25 The 3D pipeline 2512 and the media pipeline 2516. The media pipeline 2516 is optional in some embodiments of the GPE 2610 and may not be explicitly included within the GPE 2610. For example, and in at least one embodiment, a separate media and / or image processor is coupled to the GPE 2610.

[0274] In some embodiments, GPE 2610 is coupled to or includes command streamer 2603, which provides a command stream to 3D pipeline 2512 and / or media pipeline 2516. In some embodiments, command streamer 2603 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamer 2603 receives commands from memory and sends commands to 3D pipeline 2512 and / or media pipeline 2516. The commands are instructions obtained from a ring buffer that stores commands for 3D pipeline 2512 and media pipeline 2516. In one embodiment, the ring buffer may additionally include a batch command buffer that stores batches of multiple commands. Commands for 3D pipeline 2512 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2512 and / or image data and memory objects for media pipeline 2516. The 3D pipeline 2512 and the media pipeline 2516 process commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 2614.

[0275] In various embodiments, the 3D pipeline 2512 can execute one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2614. The graphics core array 2614 provides a unified block of execution resources. The multipurpose execution logic (e.g., execution units) within the graphics core array 2614 includes support for various 3D API shader languages ​​and can execute multiple concurrent execution threads associated with multiple shaders.

[0276] In some embodiments, the graphics core array 2614 further includes execution logic for performing media functions such as video and / or image processing. In one embodiment, in addition to graphics processing operations, the execution unit additionally includes general-purpose logic programmable to perform parallel general-purpose computing operations. The general-purpose logic may be related to… Figure 23 (Multiple) processor cores 2307 or such Figure 24 The processor cores 2402A-2402N or any processor described herein perform processing operations in parallel or in combination using general-purpose logic.

[0277] Output data generated by threads executing on the graphics core array 2614 can be output to memory in a uniform return buffer (URB) 2618. The URB 2618 can store data for multiple threads. In some embodiments, the URB 2618 can be used to send data between different threads executing on the graphics core array 2614. In some embodiments, the URB 2618 can also be used for synchronization between fixed-function logic within shared-function logic 2620 and threads on the graphics core array.

[0278] In some embodiments, the graphics core array 2614 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 2610. In one embodiment, the execution resources are dynamically scalable, allowing execution resources to be enabled or disabled as needed.

[0279] The graphics core array 2614 is coupled to shared function logic 2620, which includes multiple resources shared among the graphics cores in the graphics core array. Shared functions within the shared function logic 2620 are hardware logic units that provide specialized supplementary functionality to the graphics core array 2614. In various embodiments, the shared function logic 2620 includes, but is not limited to, sampler 2621, math 2622, and inter-thread communication (ITC) 2623 logic. Additionally, some embodiments implement one or more caches 2625 within the shared function logic 2620. Shared functions are implemented when the requirement for a given specialized function is insufficient to be included within the graphics core array 2614. Alternatively, a single instance of the specialized function is implemented as a separate entity within the shared function logic 2620 and shared among execution resources within the graphics core array 2614. The exact set of functions shared among and included within the graphics core array 2614 varies between embodiments.

[0280] Figure 27 This is a block diagram of another embodiment of the graphics processor 2700. Figure 27 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0281] In some embodiments, the graphics processor 2700 includes a ring interconnect 2702, a pipeline front-end 2704, a media engine 2737, and graphics cores 2780A-2780N. In some embodiments, the ring interconnect 2702 couples the graphics processor to other processing units, which include other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated within a multi-core processing system.

[0282] In some embodiments, the graphics processor 2700 receives multiple batches of commands via a ring interconnect 2702. Incoming commands are interpreted by a command streamer 2703 in a pipeline front-end 2704. In some embodiments, the graphics processor 2700 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores(a plurality of) 2780A-2780N. For 3D geometry processing commands, the command streamer 2703 supplies commands to a geometry pipeline 2736. For at least some media processing commands, the command streamer 2703 supplies commands to a video front-end 2734, which is coupled to a media engine 2737. In some embodiments, the media engine 2737 includes a video quality engine (VQE) 2730 for video and image post-processing and a multi-format encoding / decoding (MFX) engine 2733 for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2736 and the media engine 2737 each generate execution threads for thread execution resources provided by at least one graphics core 2780A.

[0283] In some embodiments, the graphics processor 2700 includes scalable thread execution resources featuring modular cores 2780A-2780N (sometimes referred to as core slices), each of which has multiple sub-cores 2750A-550N, 2760A-2760N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2700 may have any number of graphics cores 2780A to 2780N. In some embodiments, the graphics processor 2700 includes a graphics core 2780A, which has at least a first sub-core 2750A and a second sub-core 2760A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2750A). In some embodiments, the graphics processor 2700 includes multiple graphics cores 2780A-2780N, each including a set of first sub-cores 2750A-2750N and a set of second sub-cores 2760A-2760N. Each of the first sub-cores 2750A-2750N in this group includes at least a first set of execution units 2752A-2752N and media / texture samplers 2754A-2754N. Each of the second sub-cores 2760A-2760N in this group includes at least a second set of execution units 2762A-2762N and samplers 2764A-2764N. In some embodiments, each sub-core 2750A-2750N and 2760A-2760N shares a set of shared resources 2770A-2770N. In some embodiments, the shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0284] Demonstration Additional Execution Unit

[0285] Figure 28 Thread execution logic 2800 is shown, which includes an array of processing elements employed in some embodiments of GPE. Figure 28 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0286] In some embodiments, thread execution logic 2800 includes a shader processor 2802, a thread dispatcher 2804, an instruction cache 2806, a scalable array of execution units including a plurality of execution units 2808A-2808N, a sampler 2810, a data cache 2812, and a data port 2814. In one embodiment, the scalable array of execution units can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 2808A, 2808B, 2808C, 2808D to 2808N-1 and 2808N) based on workload computational requirements. In one embodiment, the included components are interconnected via an interconnect structure linking to each of the components. In some embodiments, thread execution logic 2800 includes one or more connections to memory (such as system memory or cache memory) via the instruction cache 2806, the data port 2814, the sampler 2810, and one or more of the execution units 2808A-2808N. In some embodiments, each execution unit (e.g., 2808A) is an independent, programmable, general-purpose computing unit capable of executing multiple concurrent hardware threads to process multiple data elements in parallel for each thread. In various embodiments, the array of execution units 2808A-2808N is scalable to include any number of individual execution units.

[0287] In some embodiments, execution units 2808A-2808N are primarily used to execute shader programs. Shader processor 2802 can handle various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2804. In one embodiment, the thread dispatcher includes logic for arbitrating thread requests from the graphics and media pipeline and instantiating the requested thread on one or more execution units in execution units 2808A-2808N. For example, a geometry pipeline (e.g., Figure 27 (2736) can dispatch vertex, surface tessellation, or geometry shader to thread execution logic 2800 ( Figure 28 This is used for processing. In some embodiments, the thread dispatcher 2804 can also handle a large number of requests generated by runtime threads executing shader programs.

[0288] In some embodiments, execution units 2808A-2808N support instruction sets including native support for many standard 3D graphics shader instructions, enabling the execution of shader programs from graphics libraries (e.g., Direct3D and OpenGL) with minimal translation. Execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., computation and media shaders). Each of the execution units 2808A-2808N has the capability for multi-issue single-instruction multiple-data (SIMD) execution, and multi-threaded operation enables an efficient execution environment in the face of memory accesses with high latency. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. For pipelines with integer, single- and double-precision floating-point operations, SIMD branching capabilities, logical operations, transcendental operations, and other miscellaneous operation capabilities, execution is multi-issue per clock cycle. While waiting for data from either memory or a shared function, the dependency logic within the execution units 2808A-2808N causes the waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be dedicated to processing other threads. For example, during the latency associated with vertex shader operations, the execution unit may execute operations on the pixel shader, fragment shader, or another type of shader program that includes different vertex shaders.

[0289] Each execution unit in the 2808A-2808N operates on an array of data elements. The number of data elements is the "execution size," or the number of channels used for instructions. An execution channel is a logical unit used for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2808A-2808N support both integer and floating-point data types.

[0290] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compressed data types, and the execution unit will process these elements based on their data size. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (four times the word length (QW) size), eight separate 32-bit compressed data elements (double word (DW) size), sixteen separate 16-bit compressed data elements (word (W) size), or thirty-two separate 8-bit data elements (byte (B) size). However, different vector widths and register sizes are possible.

[0291] One or more internal instruction caches (e.g., 2806) are included in the thread execution logic 2800 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2812) are included to cache thread data during thread execution. In some embodiments, sampler 2810 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, sampler 2810 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0292] During execution, the graphics and media pipeline sends thread initiation requests to thread execution logic 2800 via thread mass production and dispatch logic. Once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2802 is invoked to further compute output information and write the results to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic within shader processor 2802 then executes a pixel or fragment shader program provided by an application programming interface (API). To execute the shader program, shader processor 2802 dispatches threads to execution units (e.g., 2808A) via thread dispatcher 2804. In some embodiments, pixel shader 2802 uses texture sampling logic in sampler 2810 to access texture data in a texture map stored in memory. Arithmetic operations on texture data and input geometry data calculate pixel color data for each geometric fragment, or discard one or more pixels to avoid further processing.

[0293] In some embodiments, data port 2814 provides a memory access mechanism for thread execution logic 2800 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2814 includes or is coupled to one or more cache memories (e.g., data cache 2812) to cache data via the data port for memory access.

[0294] Figure 29This is a block diagram illustrating a graphics processor instruction format 2900 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set having instructions employing multiple formats. Solid lines indicate components generally included in the execution unit instructions, while dashed lines include optional components or those only included in a subset of the instructions. In some embodiments, the instruction format 2900 described and illustrated are macro instructions, as they are instructions supplied to the execution unit, as opposed to the micro-operations caused by instruction decoding once the instruction is processed.

[0295] In some embodiments, the graphics processor execution unit natively supports instructions using the 128-bit instruction format 2910. A 64-bit compressed instruction format 2930 may be available for some instructions, depending on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 2910 provides access to all instruction options, while some options and operations are restricted to the 64-bit format 2930. The native instructions available in the 64-bit format 2930 vary depending on the embodiment. In some embodiments, instructions are partially compressed using a set of index values ​​in the index field 2913. The execution unit hardware references a set of compression tables based on the index values ​​and uses the output of the compression tables to reconstruct the native instructions using the 128-bit instruction format 2910.

[0296] For each format, the instruction opcode 2912 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel, where each color channel represents a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2914 enables control over certain execution options, such as channel selection (e.g., prediction) and data channel ordering (e.g., mixing). For instructions employing the 128-bit instruction format 2910, the execution size field 2916 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 2916 is not available for use in the 64-bit compressed instruction format 2930.

[0297] Some execution unit instructions have up to three operands, including two source operands—src0 2920 and src12 922—and one destination 2918. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2924), where the instruction opcode 2912 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed using the instruction.

[0298] In some embodiments, the 128-bit instruction format 2910 includes an access / addressing mode field 2926 that specifies, for example, whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction.

[0299] In some embodiments, the 128-bit instruction format 2910 includes an access / addressing mode field 2926 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes that include 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction may use byte-aligned addressing for both the source and destination operands, and in a second mode, the instruction may use 16-byte aligned addressing for both the source and destination operands.

[0300] In one embodiment, the addressing mode portion of the access / addressing mode field 2926 determines whether the instruction should use direct or indirect addressing. When using direct register addressing mode, bits in the instruction directly provide the register addresses of one or more operands. When using indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0301] In some embodiments, instructions are grouped based on the 2912-bit opcode field to simplify opcode decoding 2940. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely illustrative. In some embodiments, the move and logic opcode group 2942 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2942 shares five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. The flow control instruction group 2944 (e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2946 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0x30). Parallel math instruction group 2948 includes component-based arithmetic instructions (e.g., addition, multiplication (mul)) in the form of 0100xxxxb (e.g., 0x40). Parallel math group 2948 performs arithmetic operations in parallel across data channels. Vector math group 2950 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Vector math group performs arithmetic on vector operands, such as dot product calculations.

[0302] Demonstration of additional graphic pipeline

[0303] Figure 30 This is a block diagram of another embodiment of the graphics processor 3000. Figure 30 Elements having the same reference numerals (or names) as elements in any other figure herein may operate or function in any manner similar to, but not limited to, those described elsewhere herein.

[0304] In some embodiments, the graphics processor 3000 includes a graphics pipeline 3020, a media pipeline 3030, a display engine 3040, thread execution logic 3050, and a rendering output pipeline 3070. In some embodiments, the graphics processor 3000 is a graphics processor within a multi-core processing system including one or more general-purpose processing cores. The graphics processor is controlled by writing to registers to one or more control registers (not shown) or via commands issued to the graphics processor 3000 through a ring interconnect 3002. In some embodiments, the ring interconnect 3002 couples the graphics processor 3000 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 3002 are interpreted by a command streamer 3003, which supplies instructions to individual components of the graphics pipeline 3020 or the media pipeline 3030.

[0305] In some embodiments, command streamer 3003 guides the operation of vertex acquirer 3005, which reads vertex data from memory and executes vertex processing commands provided by command streamer 3003. In some embodiments, vertex acquirer 3005 provides vertex data to vertex shader 3007, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex acquirer 3005 and vertex shader 3007 execute vertex processing instructions by dispatching execution threads to execution units 3052A-3052B via thread dispatcher 3031.

[0306] In some embodiments, execution units 3052A-3052B are arrays of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution units 3052A-3052B have attached L1 cache 3051, which is array-specific or shared between arrays. This cache can be configured as a data cache, an instruction cache, or a single cache, which is partitioned to contain data and instructions in different partitions.

[0307] In some embodiments, the graphics pipeline 3020 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable shell shader 811 configures the tessellation operation. A programmable domain shader 817 provides back-end evaluation of the tessellation output. A tessellation unit 3013 operates in the direction of the shell shader 3011 and includes dedicated logic for generating a set of detailed geometric objects based on a coarse geometry model, which is provided as input to the graphics pipeline 3020. In some embodiments, the tessellation component (e.g., shell shader 3011, tessellation unit 3013, and domain shader 3017) can be bypassed if tessellation is not used.

[0308] In some embodiments, the complete geometry object may be processed by the geometry shader 3019 via one or more threads dispatched to execution units 3052A-3052B, or it may proceed directly to the clipper 3029. In some embodiments, the geometry shader operates on the entire geometry object rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 3019 receives input from the vertex shader 3007. In some embodiments, the geometry shader 3019 may be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0309] Prior to rasterization, clipper 3029 processes vertex data. Clipper 3029 can be a fixed-function clipper or a programmable clipper with clipping and geometry shader capabilities. In some embodiments, the rasterizer and depth testing unit 3073 in the rendering output pipeline 3070 dispatch pixel shaders to convert geometric objects into their per-pixel representations. In some embodiments, pixel shader logic is included in thread execution logic 3050. In some embodiments, an application can bypass the rasterizer and depth testing unit 3073 and access unrasterized vertex data via outgoing unit 3023.

[0310] The graphics processor 3000 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be transferred between the main components of the processor. In some embodiments, execution units 3052A-3052B and(multiple) associated caches 3051, texture and media samplers 3054, and texture / sampler cache 3058 are interconnected via data port 3056 to perform memory accesses and communicate with the processor's rendering output pipeline components. In some embodiments, samplers 3054, caches 3051, 3058, and execution units 3052A-3052B each have a separate memory access path.

[0311] In some embodiments, the rendering output pipeline 3070 includes a rasterizer and a depth testing unit 3073 that converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / mask unit for performing fixed-function triangle and line rasterization. Associated rendering cache 3078 and depth cache 3079 are also available in some embodiments. Pixel manipulation unit 3077 performs pixel-based operations on the data; however, in some instances, pixel operations associated with 2D operations (e.g., using mixed bit-block image transfer) are performed by the 2D engine 3041, or alternatively by the display controller 3043 using an overlay display plane at display time. In some embodiments, a shared L3 cache 3075 is available for all graphics components, allowing data to be shared without using main system memory.

[0312] In some embodiments, the graphics processor media pipeline 3030 includes a media engine 3037 and a video front-end 3034. In some embodiments, the video front-end 3034 receives pipeline commands from a command streamer 3003. In some embodiments, the media pipeline 3030 includes a separate command streamer. In some embodiments, the video front-end 3034 processes a media command before sending it to the media engine 3037. In some embodiments, the media engine 3037 includes a thread mass production function to mass-produce threads for dispatch to thread execution logic 3050 via a thread dispatcher 3031.

[0313] In some embodiments, the graphics processor 3000 includes a display engine 3040. In some embodiments, the display engine 3040 is external to the processor 3000 and coupled to the graphics processor via a ring interconnect 3002 or some other interconnect bus or structure. In some embodiments, the display engine 3040 includes a 2D engine 3041 and a display controller 3043. In some embodiments, the display engine 3040 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 3043 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0314] In some embodiments, the graphics pipeline 3020 and media pipeline 3030 may be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for OpenGL, OpenCL, and / or Vulkan graphics and computing APIs, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, combinations of these libraries may be supported. Support may also be provided for the open-source computer vision library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a pipeline mapping from future APIs to the graphics processor pipeline can be made.

[0315] Graphical Pipeline Programming

[0316] Figure 31A This is a block diagram illustrating a graphics processor command format 3100 according to some embodiments. Figure 31B This is a block diagram illustrating a graphics processor command sequence 3110 according to an embodiment. Figure 31ASolid lines in the diagram indicate components that are generally included in the drawing command, while dashed lines indicate optional components or components that are included only in a subset of the drawing command. Figure 31A The example graphics processor command format 3100 includes data fields for identifying the target client 3102 of the command, the command operation code (opcode) 3104, and the command's associated data 3106. Some commands also include a sub-opcode 3105 and a command size 3108.

[0317] In some embodiments, client 3102 specifies a client unit of a graphics device that processes command data. In some embodiments, a graphics processor command parser examines the client field of each command to adjust further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads opcode 3104 and sub-opcode 3105 (if present) to determine the operation to be performed. The client unit uses information in data field 3106 to execute the command. For some commands, an explicit command size 3108 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some commands in the command based on the command opcode. In some embodiments, commands are aligned via multiples of double words.

[0318] Figure 31B The flowchart illustrates an exemplary graphics processor command sequence 3110. In some embodiments, software or firmware of a data processing system featuring an embodiment of the graphics processor uses a version of the illustrated command sequence to establish, execute, and terminate a set of graphics operations. Sample command sequences are shown and described for illustrative purposes only, as embodiments are not limited to these specific commands or this command sequence. Moreover, the commands may be issued as a batch of commands in a command sequence, such that the graphics processor will process the sequence of commands at least partially simultaneously.

[0319] In some embodiments, the graphics processor command sequence 3110 may begin with a pipeline dump clearing command 3112 to cause any active graphics pipeline to complete its current pending commands. In some embodiments, the 3D pipeline 3122 and the media pipeline 3124 do not operate simultaneously. Pipeline dump clearing is performed to cause any pending commands to be completed by the active graphics pipeline. In response to pipeline dump clearing, the command parser for the graphics processor will pause command processing until the active graphics engine completes its pending operations and the associated read cache is invalidated. Optionally, any data marked as 'dirty' in the render cache may be dumped to memory. In some embodiments, pipeline dump clearing command 3112 may be used for pipeline synchronization or before placing the graphics processor into a low-power state.

[0320] In some embodiments, a pipeline selection command 3113 is used when a sequence of commands requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline selection command 3113 is only required once within the execution context before a pipeline command is issued, unless the context is issuing commands for two pipelines. In some embodiments, a pipeline dump clearing command 3112 is required immediately preceding the pipeline switch via the pipeline selection command 3113.

[0321] In some embodiments, pipeline control command 3114 configures a graphics pipeline for operation and programs the 3D pipeline 3122 and the media pipeline 3124. In some embodiments, pipeline control command 3114 configures pipeline states for active pipelines. In one embodiment, pipeline control command 3114 is used for pipeline synchronization and for clearing data from one or more caches within an active pipeline before processing a batch of commands.

[0322] In some embodiments, the return buffer state command 3116 is used to configure a set of return buffers for corresponding pipeline write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers that write intermediate data to the one or more return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 3116 includes selecting the size and number of return buffers to be used for a set of pipeline operations.

[0323] The remaining commands in the command sequence vary depending on the active pipeline used for the operation. Based on pipeline determination 3120, the command sequence is suitable for either the 3D pipeline 3122 starting at 3D pipeline state 3130 or the media pipeline 3124 starting at media pipeline state 3140.

[0324] Commands for configuring 3D pipeline states 3130 include 3D state setting commands for vertex buffer states, vertex element states, constant color states, depth buffer states, and other state variables to be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 3130 commands can also selectively disable or bypass certain pipeline elements if those elements will not be used.

[0325] In some embodiments, the 3D primitive 3132 command is used to submit 3D primitives to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 3132 command are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitive 3132 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 3132 command is used to perform vertex operations on the 3D primitives via a vertex shader. To process the vertex shader, the 3D pipeline 3122 dispatches shader execution threads to the graphics processor execution unit.

[0326] In some embodiments, the 3D pipeline 3122 is triggered by executing command 3134 or an event. In some embodiments, register writing triggers command execution. In some embodiments, execution is triggered by a 'go' or 'kick' command in a command sequence. In one embodiment, pipeline synchronization commands are used to trigger command execution to dump and clear the command sequence through the graphics pipeline. The 3D pipeline performs geometric processing on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands for controlling pixel coloring and pixel backend operations may also be included for those operations.

[0327] In some embodiments, when performing media operations, a sequence of graphics processor commands 3110 follows the media pipeline 3124 path. Generally, the specific use and manner of programming for the media pipeline 3124 depends on the media or computational operation to be performed. During media decoding, specific media decoding operations can be offloaded to this media pipeline. In some embodiments, the media pipeline can also be bypassed, and media decoding can be performed wholly or partially using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly associated with rendering graphics primitives.

[0328] In some embodiments, the media pipeline 3124 is configured in a manner similar to that of the 3D pipeline 3122. A set of commands for configuring media pipeline states 3140 is dispatched or placed in a command queue before the media object commands 3142. In some embodiments, the media pipeline state commands 3140 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the media pipeline state commands 3140 also support the use of one or more pointers to "indirect" state elements that contain a set of state settings.

[0329] In some embodiments, media object command 3142 supplies pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object command 3142. Once the pipeline states are configured and media object command 3142 is queued, media pipeline 3124 is triggered via execution command 3144 or an equivalent execution event (e.g., register write). The output from media pipeline 3124 can then be post-processed by operations provided by 3D pipeline 3122 or media pipeline 3124. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0330] Graphical software architecture

[0331] Figure 32 An exemplary graphics software architecture of a data processing system 3200 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 3210, an operating system 3220, and at least one processor 3230. In some embodiments, the processor 3230 includes a graphics processor 3232 and one or more general-purpose processor cores 3234. The graphics application 3210 and the operating system 3220 each execute in the system memory 3250 of the data processing system.

[0332] In some embodiments, the 3D graphics application 3210 includes one or more shader programs including shader instructions 3212. The shader language instructions may be in a high-level shader language, such as High-Level Shading Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 3214 in machine language suitable for execution by a general-purpose processor core 3234. The application also includes graphics objects 3216 defined by vertex data.

[0333] In some embodiments, the operating system 3220 is a Microsoft product from Microsoft Corporation. ® Windows ® The operating system 3220 may be a proprietary UNIX-like operating system or an open-source UNIX-like operating system using a variant of the Linux kernel. The operating system 3220 may support graphics APIs 3222, such as the Direct3D API, OpenGL API, or Vulkan API. When the Direct3D API is in use, the operating system 3220 uses a front-end shader compiler 3224 to compile any shader instructions 3212 in HLSL into a lower-level shader language. This compilation may be just-in-time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application 3210. In some embodiments, the shader instructions 3212 are provided in an intermediate form, such as a version of the standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0334] In some embodiments, the user-mode graphics driver 3226 includes a back-end shader compiler 3227 for translating shader instructions 3212 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 3212 in the GLSL high-level language are passed to the user-mode graphics driver 3226 for compilation. In some embodiments, the user-mode graphics driver 3226 uses operating system kernel-mode functionality 3228 to communicate with the kernel-mode graphics driver 3229. In some embodiments, the kernel-mode graphics driver 3229 communicates with the graphics processor 3232 to dispatch commands and instructions.

[0335] IP core implementation

[0336] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within a processor. When read by a machine, these instructions can cause the machine to manufacture logic for performing the techniques described herein. Such a representation (referred to as an "IP core") is a reusable unit of logic for an integrated circuit that can be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model can be supplied to various consumer or manufacturing facilities that load the hardware model onto a manufacturing machine that manufactures the integrated circuit. Integrated circuits can be manufactured such that the circuit performs the operations described in association with any embodiment of the embodiments described herein.

[0337] Figure 33 This is a block diagram illustrating an IP core development system 3300 that can be used to fabricate integrated circuits to perform operations, according to an embodiment. The IP core development system 3300 can be used to generate modular, reusable designs that can be incorporated into larger designs or used to build entire integrated circuits (e.g., SOC integrated circuits). Design facility 3330 can generate software simulations 3310 of the IP core designs using high-level programming languages ​​(e.g., C / C++). Software simulation 3310 can be used to design, test, and verify the behavior of IP cores using simulation model 3312. Simulation model 3312 can include functional, behavioral, and / or timing simulations. Register transfer level (RTL) designs 3315 can then be created or synthesized from simulation model 3312. RTL design 3315 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including associated logic performed using the modeled digital signals. In addition to RTL design 3315, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Therefore, specific details of the initial design and simulation may vary.

[0338] The RTL design 3315 or an equivalent can be further synthesized into a hardware model 3320 by the design facility. This hardware model 3320 can be represented using a hardware description language (HDL) or some other representation of the physical design data. The HDL can be further simulated or tested to verify the IP core design. The IP core design can be stored in non-volatile memory 3340 (e.g., hard disk, flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 3365. Alternatively, the IP core design can be transmitted via a wired connection 3350 or a wireless connection 3360 (e.g., via the Internet). The manufacturing facility 3365 can then manufacture an integrated circuit at least partially based on the IP core design. The manufactured integrated circuit can be configured to perform operation according to at least one embodiment described herein.

[0339] Demonstration System-on-Chip Integrated Circuit

[0340] Figures 34-36 Exemplary integrated circuits and associated graphics processors that can be fabricated using one or more IP cores according to various embodiments described herein are shown. In addition to those shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0341] Figure 34This is a block diagram illustrating an exemplary system-on-a-chip integrated circuit 3400 that can be fabricated using one or more IP cores according to an embodiment. The exemplary integrated circuit 3400 includes one or more application processors 3405 (e.g., CPUs), at least one graphics processor 3410, and may additionally include an image processor 3415 and / or a video processor 3420, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 3400 includes peripheral or bus logic, including a USB controller 3425, a UART controller 3430, an SPI / SDIO controller 3435, and an I2S / I2C controller 3440. Additionally, the integrated circuit may include a display device 3445 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 3450 and a Mobile Industry Processor Interface (MIPI) display interface 3455. Storage may be provided by a flash memory subsystem 3460 including flash memory and a flash memory controller. A memory interface may be provided via a memory controller 3465 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 3470.

[0342] Figure 35 This is a block diagram illustrating an exemplary graphics processor 3510, a system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3510 may be... Figure 34 A variant of the graphics processor 3410. The graphics processor 3510 includes a vertex processor 3505 and one or more fragment processors 3515A-3515N (e.g., 3515A, 3515B, 3515C, 3515D to 3515N-1 and 3515N). The graphics processor 3510 can execute different shader programs via separate logic, such that the vertex processor 3505 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 3515A-3515N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processor 3505 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors (multiple) 3515A-3515N use the primitive and vertex data generated by the vertex processor 3505 to produce frame buffers displayed on a display device. In one embodiment, the fragment processors (multiple) 3515A-3515N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs as provided in the Direct3D API.

[0343] The graphics processor 3510 additionally includes one or more memory management units (MMUs) 3520A-3520B, caches 3525A-3525B, and circuit interconnects 3530A-3530B. The one or more MMUs 3520A-3520B, as part of the graphics processor 3510, provide virtual-to-physical address mappings for vertex processors 3505 and / or / or (multiple) fragment processors 3515A-3515N. These virtual-to-physical address mappings can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 3525A-3525B. In one embodiment, the one or more MMUs 3520A-3520B can be synchronized with other MMUs within the system, including those related to... Figure 34 The one or more application processors 3405, image processor 3415, and / or video processor 3420 are associated with one or more MMUs, enabling each processor 3405-3420 to participate in a shared or unified virtual memory system. According to an embodiment, the one or more circuit interconnects 3530A-3530B enable the graphics processor 3510 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0344] Figure 36 This is a block diagram illustrating an additional exemplary graphics processor 3610 of a system-on-a-chip integrated circuit that can be fabricated using one or more IP cores according to an embodiment. The graphics processor 3610 may be... Figure 34 A variant of the graphics processor 3410. The graphics processor 3610 includes... Figure 35 The integrated circuit 3500 includes one or more MMUs 3520A-3520B, caches 3525A-3525B, and interconnects 3530A-3530B.

[0345] The graphics processor 3610 includes one or more shader cores 3615A-3615N (e.g., 3615A, 3615B, 3615C, 3615D, 3615E, 3615F to 3615N-1 and 3615N), which provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present can vary in embodiments and implementations. Additionally, the graphics processor 3610 includes an inter-core task manager 3605, which acts as a thread dispatcher for assigning execution threads to one or more shader cores 3615A-3615N, and a chunking unit 3618 for accelerating chunking operations for tile-based rendering, wherein rendering operations for a scene are subdivided in the image space, for example for utilizing local spatial coherence within the scene or for optimizing the use of internal caches.

[0346] The present invention also provides a set of technical solutions as follows:

[0347] 1. A general-purpose graphics processing unit, comprising:

[0348] The system includes a dynamic precision floating-point unit for a control unit, the control unit having precision tracking hardware logic to track the available number of precision bits of computed data related to a target precision, wherein the dynamic precision floating-point unit includes computational logic to output data at multiple precisions.

[0349] 2. The general-purpose graphics processing unit as described in technical solution 1, wherein the dynamic precision floating-point unit includes a set of registers to store input data and intermediate data in multiple precisions.

[0350] 3. The general-purpose graphics processing unit as described in technical solution 2, wherein the register set includes an error accumulator to track accumulated errors on the floating-point operation set.

[0351] 4. The general-purpose graphics processing unit as described in technical solution 1, wherein the dynamic precision floating-point unit includes a significant bit block for performing floating-point calculations, the significant bit block including a dynamic precision adder, the dynamic precision adder being configurable to add or subtract input data with multiple precisions.

[0352] 5. The general-purpose graphics processing unit as described in technical solution 4, wherein the effective bit block includes a dynamic precision multiplier, the dynamic precision multiplier being configurable to add to, multiply, or divide the input data with multiple precisions.

[0353] 6. The general-purpose graphics processing unit as described in technical solution 5, wherein the dynamic precision floating-point unit includes an exponent block for performing floating-point calculations, the exponent block including a dynamic precision adder, the dynamic precision adder being configurable to add or subtract the exponent of input data with multiple precisions.

[0354] 7. The general-purpose graphics processing unit as described in technical solution 6, wherein the exponent block and the significant bit block are used to perform a first floating-point operation to output a first output value with 16-bit precision.

[0355] 8. The general-purpose graphics processing unit as described in technical solution 7, wherein the exponent block and the significant bit block are used to perform a second operation to output a second output value with 32-bit precision.

[0356] 9. The general-purpose graphics processing unit as described in technical solution 8, wherein the exponent block and the significant bit block are used to perform a third floating-point operation on input data having a 32-bit value to output a third output value having a 32-bit data type, the third output value being generated with 16-bit precision.

[0357] 10. The general-purpose graphics processing unit as described in technical solution 9, wherein the exponent block includes an 8-bit multiplier, and wherein the exponent block and the effective bit block are configurable to perform dual 8-bit integer operations.

[0358] 11. A method for performing variable-precision operations within the hardware of a general-purpose graphics processing unit, the method comprising:

[0359] Receive a request to perform numerical operations with first precision;

[0360] The numerical operation is performed using a plurality of bits associated with a second precision that is lower than the first precision;

[0361] Intermediate results are generated using the second level of precision;

[0362] Determine the accuracy loss of the intermediate results; and

[0363] When the accuracy loss of the intermediate result is less than the threshold, the result is output with the second accuracy.

[0364] 12. The method of claim 11, wherein the threshold is configurable via software logic.

[0365] 13. The method as described in technical solution 11, wherein the threshold is a default hardware value.

[0366] 14. The method of claim 11, further comprising:

[0367] The remaining bits of the calculation result when the precision loss of the intermediate result is greater than the threshold; and

[0368] The result is output with the first level of precision.

[0369] 15. The method of claim 14, wherein performing the numerical operation using a plurality of bits associated with a second precision lower than the first precision includes performing the numerical operation using a first set of logic units and calculating the remaining bits of the result, and when the precision loss of the intermediate result is greater than the threshold, includes calculating the remaining bits of the result using a second set of logic units.

[0370] 16. A data processing system, comprising:

[0371] A non-transitory machine-readable medium for storing instructions for execution by one or more processors of the data processing system; and

[0372] A general-purpose graphics processing unit including a dynamic precision floating-point unit, the dynamic precision floating-point unit including a control unit, the control unit having precision tracking hardware logic to track the available number of precision bits of computed data related to a target precision, wherein the dynamic precision floating-point unit includes computation logic to output data in multiple precisions.

[0373] 17. The data processing system of claim 16, wherein the dynamic precision floating-point unit includes a set of registers to store input data and intermediate data in multiple precisions.

[0374] 18. The data processing system of claim 17, wherein the register set includes an error accumulator to track accumulated errors on the set of floating-point operations.

[0375] 19. The data processing system of claim 16, wherein the dynamic precision floating-point unit includes a block of significant bits for performing floating-point calculations, the block of significant bits including a dynamic precision adder, the dynamic precision adder being configurable to add or subtract input data with multiple precisions.

[0376] 20. The data processing system of claim 19, wherein the effective bit block includes a dynamic precision multiplier, which can be configured to add, multiply, or divide the input data with multiple precisions.

[0377] The following terms and / or examples relate to specific embodiments or examples thereof. Specific details in the examples may be used anywhere in one or more embodiments. Various features of different embodiments or examples may be combined in various ways with some of the included features and others that are excluded to suit a wide variety of different applications. Examples may include subjects such as methods, components for performing actions of methods, at least one machine-readable medium including instructions that, when executed by a machine, cause the machine to perform actions of a method, apparatus, or system according to the embodiments and examples described herein. Various components may be components for performing the described operations or functions.

[0378] The embodiments described herein refer to specific configurations of hardware (e.g., application-specific integrated circuits (ASICs)) configured to perform certain operations or have predetermined functionality. Such electronic devices typically include a collection of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touchscreens, and / or displays), and network connectivity. The coupling of the processor collection and its other components is typically via one or more buses and bridges (also known as bus controllers). Storage devices and signals carrying network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Therefore, the storage devices of a given electronic device typically store code and / or data for execution on the one or more processors of that electronic device.

[0379] Of course, one or more parts of the embodiments may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that embodiments may be practiced without some of these specific details. In some instances, well-known structures and functions have not been described in exhaustive detail to avoid obscuring the inventive subject matter of the embodiments. Accordingly, the scope and spirit of the invention should be determined based on the following claims.

Claims

1. A multi-chip module accelerator for performing tensor data processing operations, the multi-chip module accelerator comprising: Multi-chip module, including: Memory stack, comprising multiple memory dies; and A parallel processor circuit module is communicatively coupled to the memory stack, the parallel processor circuit module including multiple processor cores to perform matrix multiplication and accumulation operations; in: The matrix multiplication and accumulation operations include floating-point operations; The floating-point arithmetic is configured to include two-dimensional matrix multiplication and accumulation operations involving inputs with different floating-point precisions; The floating-point arithmetic includes a first operation with a first precision and a second operation with a second precision; and The first operation includes multiplication with at least one 16-bit floating-point input and the second operation includes accumulation with 32-bit floating-point input.

2. The multi-chip module accelerator as described in claim 1, wherein, The memory stack includes high-bandwidth memory.

3. The multi-chip module accelerator as described in claim 1, wherein, The memory stack is included in the same physical package as the parallel processor circuit module.

4. The multi-chip module accelerator as described in claim 1, wherein, The first operation is performed with 16-bit precision, and the second operation is performed with 32-bit precision.

5. The multi-chip module accelerator as described in claim 1, wherein, The first operation involves two or more 16-bit floating-point inputs.

6. The multi-chip module accelerator as described in claim 1, wherein: The multi-chip module accelerator will be communicatively coupled to at least one accelerator cluster; and The accelerator cluster comprises identical parallel processors that are communicatively coupled together.

7. The multi-chip module accelerator as described in claim 1, wherein: The multiprocessor cores will use a unified memory space associated with the memory stack.

8. An accelerator cluster, comprising: The same parallel processors are communicatively coupled together; as well as The multi-chip module accelerator according to any one of claims 1 to 7, which is communicatively coupled to the same parallel processor.

9. A method implemented using a multi-chip module accelerator, the multi-chip module accelerator comprising a memory stack and a parallel processor circuit module, the parallel processor circuit module being communicatively coupled to the memory stack, the memory stack comprising a plurality of memory dies, and the parallel processor circuit module comprising a multiprocessor core, the method comprising: Matrix multiplication and accumulation operations are performed using the multiprocessor cores. in: The matrix multiplication and accumulation operations include floating-point operations; The floating-point arithmetic is configured to include two-dimensional matrix multiplication and accumulation operations involving inputs with different floating-point precisions; The floating-point arithmetic includes a first operation with a first precision and a second operation with a second precision; and The first operation includes multiplication with at least one 16-bit floating-point input and the second operation includes accumulation with 32-bit floating-point input.

10. The method of claim 9, wherein, The memory stack includes high-bandwidth memory.

11. The method of claim 9, wherein, The memory stack is included in the same physical package as the parallel processor circuit module.

12. The method of claim 9, wherein, The first operation is performed with 16-bit precision, and the second operation is performed with 32-bit precision.

13. The method of claim 9, wherein, The first operation involves two or more 16-bit floating-point inputs.

14. The method of claim 9, wherein: The multi-chip module accelerator will be communicatively coupled to at least one accelerator cluster; and The accelerator cluster comprises identical parallel processors that are communicatively coupled together.

15. The method of claim 9, wherein: The multiprocessor cores will use a unified memory space associated with the memory stack.

16. At least one non-transitory machine-readable storage medium storing instructions for execution by at least one machine associated with a multi-chip module accelerator, the multi-chip module accelerator including a memory stack and a parallel processor circuit module communicatively coupled to the memory stack, the memory stack including a plurality of memory dies, the parallel processor circuit module including a multiprocessor core, wherein, when executed by the at least one machine, the instructions cause the multiprocessor core to perform any one of claims 9 to 15.

17. A data processing apparatus comprising components for performing any of the methods of claims 9 to 15.

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