A power mosfet device and method of manufacture
By introducing a vertical slab structure and a source metal field plate into the power MOSFET device, combined with Resurf technology, the electric field distribution is optimized, which solves the performance deficiencies of lateral and vertical power MOSFET devices and achieves a balance between high voltage withstand and high current density.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2023-03-28
- Publication Date
- 2026-08-04
AI Technical Summary
Lateral power MOSFETs have smaller gate-drain capacitance but larger on-resistance, while longitudinal power MOSFETs have smaller on-resistance but lower switching speed. Existing devices struggle to balance high current density and good switching performance.
By combining a vertical wafer structure with a source metal field plate and Resurf technology, a transverse and longitudinal withstand voltage structure is formed, which optimizes the lateral drift region and the electric field distribution of the vertical wafer. The longitudinal electric field is modulated by the polysilicon field plate in the trench structure.
It improves the device's breakdown voltage and current density, reduces the cell size, enhances high current capability, and reduces gate parasitic effects.
Smart Images
Figure CN116417519B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to power semiconductor technology, specifically to a power MOSFET device and its fabrication method. Background Technology
[0002] Power semiconductor devices are devices capable of handling large currents and high voltages; also known as power electronic devices, they are indispensable components in modern electronic systems. Power MOSFET devices have advantages such as high input impedance, low conduction loss, low switching loss, and high reliability, and are often used as electronic switches in power management applications.
[0003] Power MOSFET devices are classified into lateral power MOSFETs and vertical power MOSFETs based on the direction of the current path during conduction. Each type has its own advantages and disadvantages. Lateral power MOSFETs have smaller gate-drain capacitance but larger on-resistance, resulting in larger cell width, lower current density, and poorer overcurrent capability. Vertical power MOSFETs have smaller on-resistance and better overcurrent capability, but significant gate parasitic effects (especially larger gate-drain capacitance), leading to lower switching speed and higher drive power consumption. Summary of the Invention
[0004] The purpose of this invention is to address the aforementioned drawbacks of lateral and vertical power MOSFET devices by proposing a power MOSFET device and its fabrication method.
[0005] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:
[0006] A power MOSFET device includes a drain metal 1, a heavily doped first conductivity type semiconductor substrate 2, a lightly doped second conductivity type semiconductor epitaxial layer 3, a first conductivity type semiconductor vertical wafer 4, a gate dielectric layer 5, a gate polysilicon electrode 6, a second conductivity type semiconductor body region 7, a first conductivity type semiconductor drift region 8, a heavily doped first conductivity type semiconductor source region 9, a heavily doped second conductivity type semiconductor ohmic contact region 11, a first insulating dielectric layer 10, a source metal 12, a trench structure 13, a second insulating dielectric layer 14, and a heavily doped first conductivity type polysilicon 15.
[0007] The heavily doped first conductivity type semiconductor substrate 2 is located above the drain metal 1, the lightly doped second conductivity type semiconductor epitaxial layer 3 is located above the heavily doped first conductivity type semiconductor substrate 2, the first conductivity type semiconductor vertical wafer 4 is located in the lightly doped second conductivity type semiconductor epitaxial layer 3, the bottom of the first conductivity type semiconductor vertical wafer 4 is in direct contact with the heavily doped first conductivity type semiconductor substrate 2, the top of one side of the first conductivity type semiconductor vertical wafer 4 is in direct contact with the first conductivity type semiconductor drift region 8, and the other side is in direct contact with the trench structure 13; the trench structure 13 includes a second insulating dielectric layer 14 and a heavily doped first conductivity type polysilicon 15; inside the trench structure 13, the heavily doped first conductivity type polysilicon 15 and the first conductivity type semiconductor vertical wafer 4, and the heavily doped first conductivity type polysilicon 15 and the heavily doped first conductivity type semiconductor substrate 2 are separated by the second insulating dielectric layer 14, and the heavily doped first conductivity type polysilicon 15 and the source metal 12 are separated by the first insulating dielectric layer 10;
[0008] The second conductivity type semiconductor body region 7 is located on the upper part of the lightly doped second conductivity type semiconductor epitaxial layer 3; the first conductivity type semiconductor drift region 8 is located on the upper part of the lightly doped second conductivity type semiconductor epitaxial layer 3, and its two sides are in direct contact with the first conductivity type semiconductor vertical wafer 4 and the second conductivity type semiconductor body region 7, respectively; the heavily doped first conductivity type semiconductor source region 9 is located on the upper part of the second conductivity type semiconductor body region 7, and its left side is in contact with the source metal 12; the heavily doped second conductivity type semiconductor ohmic contact region 11 is located in the second conductivity type semiconductor body region 7, and its upper part is in contact with the source metal 12; the upper surface of the lightly doped second conductivity type semiconductor epitaxial layer 3 is covered by a first insulating dielectric layer 10, and the first insulating dielectric layer 10 surrounds the gate polysilicon electrode 6; the source metal 12 is located on the upper surface of the first insulating dielectric layer 10 and completely covers the area where the first conductivity type semiconductor drift region 8 is located.
[0009] The heavily doped first conductivity type polysilicon 15 is connected to the source potential; when the device is subjected to reverse breakdown voltage, the first conductivity type semiconductor drift region 8 and the first conductivity type semiconductor vertical substrate 4 are completely depleted.
[0010] As a preferred approach, the heavy doping concentration is greater than 1e19 cm⁻¹. -3 The lightly doped concentration is less than 1e17cm. -3 The doping concentration range of the first conductivity type semiconductor drift region 8 is 1e17 cm⁻¹. -3 -3e17cm -3 The doping concentration range for the first conductivity type semiconductor vertical wafer is 3e17 cm⁻¹. -3 -5e17cm -3 .
[0011] As a preferred embodiment, the first insulating dielectric layer material 10 and the second insulating dielectric layer material 14 are silicon dioxide or high-k materials with dielectric constants higher than silicon dioxide.
[0012] As a preferred embodiment, the source metal 12 extends into the semiconductor material through a contact hole, and its depth is greater than that of the heavily doped first conductivity type semiconductor source region 9.
[0013] As a preferred embodiment, the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
[0014] As a preferred option, the semiconductor material is silicon or silicon carbide.
[0015] The present invention also provides a method for fabricating a power MOSFET device, comprising the following steps:
[0016] (1) A lightly doped second-conductivity semiconductor epitaxial layer 3 is epitaxially grown on a heavily doped first-conductivity semiconductor substrate 2;
[0017] (2) Etch trenches in the lightly doped second conductivity type semiconductor epitaxial layer 3 and deposit the first conductivity type semiconductor vertical wafer 4;
[0018] (3) Thermal oxidation growth of gate dielectric layer 5, deposition of gate polysilicon electrode 6 and etching;
[0019] (4) Ion implantation of the second conductivity type semiconductor body region 7, the first conductivity type semiconductor drift region 8 and the heavily doped first conductivity type semiconductor source region 9 and push-in;
[0020] (5) Etch trenches in the vertical wafer 4 of the first type of conductive semiconductor, grow a second insulating dielectric layer 14 by thermal oxidation in the trenches and deposit heavily doped first type of conductive polysilicon 15, and then etch the polysilicon.
[0021] (6) Deposit the first insulating dielectric layer 10, etch the contact hole, ion implant heavily doped second conductivity type semiconductor ohmic contact region 11 and push it to the junction, and deposit the source metal 12.
[0022] (7) Thin the substrate and form the drain metal 1 on the back gold.
[0023] The beneficial effects of this invention are as follows: Power MOSFET devices with vertical wafers can change the current path from lateral to vertical. While the source metal field plate and Resurf (Reduced Surface Field) technology jointly optimize the surface electric field of the lateral drift region, the bulk polysilicon field plate optimizes the vertical electric field of the vertical wafer. This allows both the lateral drift region and the vertical wafer to bear voltage, forming a lateral and longitudinal withstand voltage structure, further improving the device's withstand voltage characteristics. Furthermore, this structure has low gate parasitic effects and can further reduce the size of the device cell, thereby increasing the current density. Simultaneously, its source and drain are located on the chip surface and back side, respectively, which is beneficial for improving the device's high-current capability. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the structure of a power MOSFET device according to Embodiment 1 of the present invention;
[0025] Figure 2 This refers to the depletion region distribution of the device during the simulated breakdown voltage in Embodiment 1 of the present invention;
[0026] Figure 3 This refers to the lateral electric field distribution in the drift region of the device when simulating the breakdown voltage in Embodiment 1 of the present invention.
[0027] Figure 4 This refers to the vertical electric field distribution of the device when simulating the breakdown voltage in Embodiment 1 of the present invention;
[0028] Figures 5 to 11 This is a key process step in the fabrication of a power MOSFET device according to Embodiment 1 of the present invention.
[0029] The attached diagram lists the components represented by each number as follows:
[0030] 1 is the drain metal, 2 is the heavily doped first conductivity type semiconductor substrate, 3 is the lightly doped second conductivity type semiconductor epitaxial layer, 4 is the first conductivity type semiconductor vertical wafer, 5 is the gate dielectric layer, 6 is the gate polysilicon electrode, 7 is the second conductivity type semiconductor bulk region, 8 is the first conductivity type semiconductor drift region, 9 is the heavily doped first conductivity type semiconductor source region, 11 is the heavily doped second conductivity type semiconductor ohmic contact region, 10 is the first insulating dielectric layer, 12 is the source metal, 13 is the trench structure, 14 is the second insulating dielectric layer, and 15 is the heavily doped first conductivity type polysilicon. Detailed Implementation
[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0032] like Figure 1 As shown, a power MOSFET device of this embodiment includes a drain metal 1, a heavily doped first conductivity type semiconductor substrate 2, a lightly doped second conductivity type semiconductor epitaxial layer 3, a first conductivity type semiconductor vertical wafer 4, a gate dielectric layer 5, a gate polysilicon electrode 6, a second conductivity type semiconductor body region 7, a first conductivity type semiconductor drift region 8, a heavily doped first conductivity type semiconductor source region 9, a heavily doped second conductivity type semiconductor ohmic contact region 11, a first insulating dielectric layer 10, a source metal 12, a trench structure 13, a second insulating dielectric layer 14, and a heavily doped first conductivity type polysilicon 15.
[0033] The heavily doped first conductivity type semiconductor substrate 2 is located above the drain metal 1, the lightly doped second conductivity type semiconductor epitaxial layer 3 is located above the heavily doped first conductivity type semiconductor substrate 2, the first conductivity type semiconductor vertical wafer 4 is located in the lightly doped second conductivity type semiconductor epitaxial layer 3, the bottom of the first conductivity type semiconductor vertical wafer 4 is in direct contact with the heavily doped first conductivity type semiconductor substrate 2, the top of one side of the first conductivity type semiconductor vertical wafer 4 is in direct contact with the first conductivity type semiconductor drift region 8, and the other side is in direct contact with the trench structure 13; the trench structure 13 includes a second insulating dielectric layer 14 and a heavily doped first conductivity type polysilicon 15; inside the trench structure 13, the heavily doped first conductivity type polysilicon 15 and the first conductivity type semiconductor vertical wafer 4, and the heavily doped first conductivity type polysilicon 15 and the heavily doped first conductivity type semiconductor substrate 2 are separated by the second insulating dielectric layer 14, and the heavily doped first conductivity type polysilicon 15 and the source metal 12 are separated by the first insulating dielectric layer 10;
[0034] The second conductivity type semiconductor body region 7 is located on the upper part of the lightly doped second conductivity type semiconductor epitaxial layer 3; the first conductivity type semiconductor drift region 8 is located on the upper part of the lightly doped second conductivity type semiconductor epitaxial layer 3, and its two sides are in direct contact with the first conductivity type semiconductor vertical wafer 4 and the second conductivity type semiconductor body region 7, respectively; the heavily doped first conductivity type semiconductor source region 9 is located on the upper part of the second conductivity type semiconductor body region 7, and its left side is in contact with the source metal 12; the heavily doped second conductivity type semiconductor ohmic contact region 11 is located in the second conductivity type semiconductor body region 7, and its upper part is in contact with the source metal 12; the upper surface of the lightly doped second conductivity type semiconductor epitaxial layer 3 is covered by a first insulating dielectric layer 10, and the first insulating dielectric layer 10 surrounds the gate polysilicon electrode 6; the source metal 12 is located on the upper surface of the first insulating dielectric layer 10 and completely covers the area where the first conductivity type semiconductor drift region 8 is located.
[0035] The heavily doped first conductivity type polysilicon 15 is connected to the source potential; when the device is subjected to reverse breakdown voltage, the first conductivity type semiconductor drift region 8 and the first conductivity type semiconductor vertical substrate 4 are completely depleted.
[0036] In some embodiments, the heavily doped concentration is greater than 1e19 cm⁻¹. -3 The lightly doped concentration is less than 1e17cm. -3 The doping concentration range of the first conductivity type semiconductor drift region 8 is 1e17 cm⁻¹. -3 -3e17cm -3 The doping concentration range for the first conductivity type semiconductor vertical wafer is 3e17 cm⁻¹. -3 -5e17cm -3 .
[0037] In some embodiments, the first insulating dielectric layer material 10 and the second insulating dielectric layer material 14 are silicon dioxide or high-k materials with dielectric constants higher than silicon dioxide.
[0038] In some embodiments, the source metal 12 extends into the semiconductor material through a contact hole, and its depth is greater than that of the heavily doped first conductivity type semiconductor source region 9.
[0039] In some embodiments, the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor; or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor.
[0040] In some embodiments, the semiconductor material is silicon or silicon carbide.
[0041] The working principle of the present invention will be explained below using Example 1 as an example:
[0042] The present invention provides a power MOSFET device, wherein the electrode connection during forward conduction is as follows: the source metal 12 and the heavily doped first conductivity type polysilicon 15 are grounded, the gate polysilicon electrode 6 is connected to a potential higher than the threshold voltage, and the drain metal 1 is connected to a high potential. The electrode connection during reverse blocking is as follows: the gate polysilicon electrode 6, the source metal 12 and the heavily doped first conductivity type polysilicon 15 are grounded, and the drain metal 1 is connected to a high potential.
[0043] When the device is forward-biased, charge carriers first move laterally from the source through the surface of the second conductivity type semiconductor bulk region 7 to the junction of the first conductivity type semiconductor drift region 8 and the first conductivity type semiconductor vertical substrate 4. The lateral movement then changes to longitudinal movement, passing through the first conductivity type semiconductor vertical substrate 4 to the heavily doped first conductivity type semiconductor substrate 2. When the device is reverse-biased, the source metal 12 acts as a field plate, and the first conductivity type semiconductor drift region 8 and the lightly doped second conductivity type semiconductor epitaxial layer 3 form a Resurf structure. The first conductivity type semiconductor drift region 8 is modulated by the combined electric fields of the source metal 12 and the Resurf field, making its lateral electric field closer to a rectangular distribution. Simultaneously, the heavily doped first conductivity type polysilicon 15 inside the trench is grounded, and its bulk field plate structure, formed with the second insulating dielectric layer 14, modulates the longitudinal electric field of the first conductivity type semiconductor vertical substrate 4, enabling the vertical substrate to also bear a portion of the breakdown voltage. Together with the first conductivity type semiconductor drift region 8, it forms a lateral and longitudinal breakdown voltage structure, further improving the device's breakdown voltage. In addition, the structure has a small gate parasitic effect and can further reduce the size of the device cell, thereby increasing the current density. At the same time, its source and drain are located on the chip surface and back side, respectively, which is beneficial to improving the high current capability of the device.
[0044] Figure 2 This is the depletion region distribution of the device when simulating breakdown voltage in the first embodiment of the present invention. When the device is subjected to reverse withstand voltage, the first conductivity type semiconductor drift region 8 and the first conductivity type semiconductor vertical substrate 4 are completely depleted. Figure 3 The first embodiment of the present invention shows the lateral electric field distribution of the drift region of the device when simulating the breakdown voltage. Compared with the triangular electric field distribution of the PN junction, the lateral electric field of the drift region of the device has a double-peak catenary distribution. This electric field distribution is more uniform than the triangular distribution, so a higher withstand voltage can be obtained. Figure 4 The first embodiment of the present invention shows the vertical electric field distribution of the device when simulating the breakdown voltage. The electric field distribution is approximately triangular, which can effectively bear part of the withstand voltage and further improve the withstand voltage of the device.
[0045] like Figures 5 to 11 As shown, this embodiment also provides a method for fabricating a power MOSFET device, including the following steps:
[0046] (1) A lightly doped semiconductor epitaxial layer 3 of a second conductivity type is epitaxially grown on a heavily doped first conductivity type semiconductor substrate 2; such as Figure 5 As shown;
[0047] (2) Trenches are etched in the lightly doped second-conductivity semiconductor epitaxial layer 3, and a first-conductivity semiconductor vertical wafer 4 is deposited; such as Figure 6 As shown;
[0048] (3) Thermal oxidation growth of the gate dielectric layer 5, deposition and etching of the gate polysilicon electrode 6; as shown in the figure. Figure 7 As shown;
[0049] (4) Ion implantation of the second conductivity type semiconductor bulk region 7, the first conductivity type semiconductor drift region 8, and the heavily doped first conductivity type semiconductor source region 9, followed by bonding; such as Figure 8 As shown;
[0050] (5) Trenches are etched within the vertical wafer 4 of the first conductivity type semiconductor. A second insulating dielectric layer 14 is grown by thermal oxidation within the trenches, and heavily doped first conductivity type polysilicon 15 is deposited. The polysilicon is then etched again. Figure 9 As shown;
[0051] (6) Deposit the first insulating dielectric layer 10, etch contact holes, ion implant heavily doped second conductivity type semiconductor ohmic contact region 11 and push it to the junction, deposit source metal 12; as shown Figure 10 As shown;
[0052] (7) Thin the substrate and form the drain metal 1 on the back gold. For example... Figure 11 As shown;
[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A power MOSFET device, characterized in that: It includes a drain metal (1), a heavily doped first conductivity type semiconductor substrate (2), a lightly doped second conductivity type semiconductor epitaxial layer (3), a first conductivity type semiconductor vertical wafer (4), a gate dielectric layer (5), a gate polysilicon electrode (6), a second conductivity type semiconductor body region (7), a first conductivity type semiconductor drift region (8), a heavily doped first conductivity type semiconductor source region (9), a heavily doped second conductivity type semiconductor ohmic contact region (11), a first insulating dielectric layer (10), a source metal (12), and a trench structure (13). The heavily doped first conductivity type semiconductor substrate (2) is located above the drain metal (1), the lightly doped second conductivity type semiconductor epitaxial layer (3) is located above the heavily doped first conductivity type semiconductor substrate (2), the first conductivity type semiconductor vertical wafer (4) is located in the lightly doped second conductivity type semiconductor epitaxial layer (3), the bottom of the first conductivity type semiconductor vertical wafer (4) is in direct contact with the heavily doped first conductivity type semiconductor substrate (2), and the top of one side of the first conductivity type semiconductor vertical wafer (4) is in direct contact with the first conductivity type semiconductor drift region (8). The other side is in direct contact with the trench structure (13); the trench structure (13) includes a second insulating dielectric layer (14) and heavily doped first conductivity type polysilicon (15); inside the trench structure (13), the heavily doped first conductivity type polysilicon (15) and the first conductivity type semiconductor vertical wafer (4) are separated by the second insulating dielectric layer (14), and the heavily doped first conductivity type polysilicon (15) and the heavily doped first conductivity type semiconductor substrate (2) are separated by the first insulating dielectric layer (10); The second type of conductive semiconductor body region (7) is located on the upper part of the lightly doped second type of conductive semiconductor epitaxial layer (3); the first type of conductive semiconductor drift region (8) is located on the upper part of the lightly doped second type of conductive semiconductor epitaxial layer (3), and its two sides are in direct contact with the first type of conductive semiconductor vertical wafer (4) and the second type of conductive semiconductor body region (7), respectively; the heavily doped first type of conductive semiconductor source region (9) is located on the upper part of the second type of conductive semiconductor body region (7), and its left side is in contact with the source metal (12); the heavily doped second type of conductive semiconductor ohmic contact region (11) is located in the second type of conductive semiconductor body region (7), and its upper part is in contact with the source metal (12); the upper surface of the lightly doped second type of conductive semiconductor epitaxial layer (3) is covered with a first insulating dielectric layer (10), and the first insulating dielectric layer (10) surrounds the gate polysilicon electrode (6); the source metal (12) is located on the upper surface of the first insulating dielectric layer (10) and completely covers the area where the first type of conductive semiconductor drift region (8) is located; The heavily doped first conductivity type polysilicon (15) is connected to the source potential; when the device is subjected to reverse breakdown voltage, the first conductivity type semiconductor drift region (8) and the first conductivity type semiconductor vertical substrate (4) are completely depleted.
2. The power MOSFET device according to claim 1, characterized in that: Heavy doping concentration greater than 1e19 cm -3 The lightly doped concentration is less than 1e17 cm⁻¹ -3 The doping concentration range of the first conductivity type semiconductor drift region (8) is 1e17 cm⁻¹. -3 -3e17cm -3 The doping concentration range of the first conductivity type semiconductor vertical wafer (4) is 3e17 cm⁻¹. -3 -5e17cm -3 .
3. A power MOSFET device according to claim 1, characterized in that: The first insulating dielectric layer (10) and the second insulating dielectric layer (14) are made of silicon dioxide or high-K material.
4. A power MOSFET device according to claim 1, characterized in that: The source metal (12) extends into the second conductivity type semiconductor body region (7) through the contact hole, and its depth is deeper than the heavily doped first conductivity type semiconductor source region (9).
5. A power MOSFET device according to claim 1, characterized in that: The first type of semiconductor is an N-type semiconductor, and the second type of semiconductor is a P-type semiconductor; or the first type of semiconductor is a P-type semiconductor, and the second type of semiconductor is an N-type semiconductor.
6. A method for fabricating a power MOSFET device according to any one of claims 1 to 5, characterized in that... Includes the following steps: (1) A lightly doped second-conductivity semiconductor epitaxial layer (3) is epitaxially grown on a heavily doped first-conductivity semiconductor substrate (2); (2) Etch trenches in the lightly doped second conductivity type semiconductor epitaxial layer (3) and deposit a first conductivity type semiconductor vertical wafer (4); (3) Thermal oxidation growth of gate dielectric layer (5), deposition of gate polysilicon electrode (6) and etching; (4) Ion implantation of the second conductivity type semiconductor body region (7), the first conductivity type semiconductor drift region (8) and the heavily doped first conductivity type semiconductor source region (9) and push-in; (5) Etch trenches in the vertical wafer (4) of the first conductivity type semiconductor, grow a second insulating dielectric layer (14) by thermal oxidation in the trenches and deposit heavily doped first conductivity type polysilicon (15), and then etch the polysilicon; (6) Deposit the first insulating dielectric layer (10), etch the contact hole, ion implant heavily doped second conductivity type semiconductor ohmic contact region (11) and push junction, deposit source metal (12). (7) Thin the substrate and metallize the back side of the semiconductor wafer to form the drain metal (1).