A high-voltage packaging process for 5kV silicon carbide Schottky devices

Abstract

This invention relates to the field of semiconductor device packaging technology, and particularly to a high-voltage packaging process for 5kV silicon carbide Schottky devices. First, the chip is soldered to a plasma-cleaned DBC substrate using Sn96.5-Ag3.5 solder, and then ultrasonically wedge-bonded using 12mil aluminum wire. Subsequently, a core PI film double-layer passivation process is implemented: high-viscosity PI liquid is coated twice, followed by low-temperature baking and plasma treatment between the layers. Finally, complete imidization is achieved through gradient heating, constructing a dense passivation layer with a thickness ≥60μm, effectively solving the problem of thick film cracking. Vacuum encapsulation and segmented curing are performed using modified epoxy resin containing SiC filler. The nonlinear conductivity of the filler is used to homogenize the electric field and suppress partial discharge. Devices prepared by this process exhibit a reverse breakdown voltage ≥5000V and a leakage current ≤100μA at 25℃, significantly improving the insulation reliability and withstand voltage level of high-voltage SiC devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device packaging technology, and in particular to a high-voltage packaging process for 5kV silicon carbide Schottky devices. Background Technology

[0002] Silicon carbide power devices, due to their high breakdown field strength, high thermal conductivity, and high operating temperature, have shown great application potential in high-voltage fields above 5kV, such as smart grids, rail transportation, and HVDC transmission. However, with the increase in voltage levels, packaging technology has become a key bottleneck restricting the performance of these devices.

[0003] Traditional high-voltage device packaging processes have the following main drawbacks: 1. After traditional aluminum wire bonding, the electric field at the three bonding points where the chip surface connects to the leads is extremely concentrated. Under 5kV high voltage, if the surface insulation layer has insufficient withstand voltage, partial discharge is very likely to occur, leading to aging or even breakdown of the insulation material.

[0004] 2. Ordinary epoxy resin or silicone potting materials cannot simultaneously meet the requirements of high insulation strength, high heat resistance, and low thermal stress at 5kV. Single materials are prone to electrical tree growth under high electric fields.

[0005] 3. Polyimide is a commonly used passivation material, but the thickness of a single PI film in existing processes is usually limited to less than 15 μm. If the coating is too thick in a single application, solvent evaporation and volume shrinkage during the curing process will cause huge internal stress in the film layer, leading to cracking or delamination, which cannot meet the requirements of ultra-high voltage devices for thick insulating layers.

[0006] To address the aforementioned issues, this invention proposes a multilayer composite passivation and gradient insulation packaging process, which significantly improves the packaging reliability of 5kV SiC devices through specific process flows and material systems. Summary of the Invention

[0007] To overcome the shortcomings of existing technologies, this invention proposes a packaging process method for 5kV silicon carbide Schottky devices, comprising the following steps: Step 1: Device substrate pretreatment; Select AlN or Al2O3 ceramic direct copper clad (DBC) board as substrate and perform plasma cleaning on the substrate surface; Use Sn96.5-Ag3.5 solder to solder the 5kV silicon carbide Schottky chip to the DBC substrate; Step 2: Aluminum wire bonding; using 12mil diameter aluminum bonding wires, the chip electrodes are connected to the copper layer of the DBC substrate through ultrasonic wedge bonding process to form an electrical interconnect; Step 3: Double-layer passivation treatment of PI film; plasma cleaning of the surface of the bonded device; drop-coating the first layer of PI coating liquid onto the metal leads and chip pads (PADs), allowing it to stand and level before staged baking to form the first layer of PI film; then drop-coating the second layer of PI coating liquid onto the first layer of PI film, allowing it to stand and level before staged baking to form the second layer of PI film; finally, gradient temperature curing under a nitrogen atmosphere to completely imidize the double-layer PI film, forming a passivation layer with a total thickness ≥60μm; Step 4: Epoxy resin encapsulation; Using a modified silicon carbide-bisphenol A epoxy resin composite system, after vacuum degassing, the device is immersed in the epoxy resin system for encapsulation, with a coating thickness ≥200μm, covering the PI film and lead connector area; then, it is cured in sections under a nitrogen-hydrogen mixed atmosphere. Step 5: Post-processing and testing; Solder the packaged device to the metal heat sink and perform a withstand voltage test.

[0008] Furthermore, in order to better realize the present invention, in step 1, the ceramic layer thickness of the DBC substrate is 0.38 mm, and the thickness of the upper and lower copper layers is 0.3 mm; the plasma cleaning uses Ar / O2 mixed gas with a power of 100 W and a processing time of 5 min; the welding process is as follows: the temperature is raised to 240°C in a vacuum pressure furnace for 60 s, held for 10 min, and then cooled to room temperature, and the welding layer thickness is controlled at 8~10 μm.

[0009] Furthermore, in order to better realize the present invention, in step 2, the parameters of the ultrasonic wedge welding process are set as follows: bonding pressure 40psi, ultrasonic power 150W, bonding temperature 200℃, and lead arc height controlled at 150~200μm.

[0010] Furthermore, in order to better realize the present invention, in step 3, the viscosity of the PI coating liquid is 15000cp; the staged baking process after the first layer of PI film is: baking at 60°C for 10 min, followed by baking at 100°C for 15 min, to form a first layer of PI film with a thickness of about 30 μm; after the first layer of PI film is formed, its surface is subjected to plasma treatment to enhance the interfacial adhesion.

[0011] Furthermore, in order to better realize the present invention, in step 3, the staged baking process after the second PI film coating is as follows: baking at 60°C for 15 minutes, followed by baking at 100°C for 30 minutes, to form a second PI film with a thickness of about 35 μm.

[0012] Furthermore, in order to better realize the present invention, in step 3, the specific process of gradient temperature curing is as follows: curing at 80℃ for 30 min, heating to 150℃ for 30 min, heating to 200℃ for 30 min, and finally heating to 350℃ for 1 h; the breakdown field strength of the cured PI passivation layer is ≥300V / μm.

[0013] Furthermore, to better realize the present invention, in step 4, in the modified silicon carbide-bisphenol A epoxy resin composite system, the mass ratio of modified SiC to epoxy resin is 1:2, and the mass ratio of epoxy resin to curing agent is 3:1; the volume resistivity of the modified epoxy system is ≥1×10¹ 6 Ω·cm, glass transition temperature (Tg) ≥180℃.

[0014] Furthermore, in order to better realize the present invention, in step 4, the vacuum degassing treatment is carried out in a vacuum environment of -0.1MPa for 15 minutes; the segmented curing process is: curing at 90℃ for 2 hours, followed by curing at 100℃ for 1 hour; the dielectric strength of the cured coating layer is ≥20kV / mm.

[0015] Furthermore, in order to better realize the present invention, in step 5, Sn96.5-Ag3.5 solder is used for welding the metal base plate; the standard for withstand voltage test is: at 25°C, the reverse breakdown voltage of the device is ≥5000V and the leakage current is ≤100μA.

[0016] Furthermore, in order to better realize the present invention, the device has a composite passivation layer with a total thickness of ≥60μm composed of a first PI film and a second PI film, and a modified epoxy resin coating layer with a thickness of ≥200μm covering the outside of the composite passivation layer.

[0017] The beneficial effects of this invention are as follows: The composite insulation structure, which uses double-layer passivation of PI film and epoxy resin encapsulation, improves the withstand voltage characteristics of the device to over 5kV; the PI film thickness is ≥60μm, and combined with the epoxy resin encapsulation layer, it effectively suppresses partial discharge and insulation failure; the process is compatible with existing silicon carbide device packaging production lines, with controllable cost and high reliability. Attached Figure Description

[0018] Figure 1 This is a process flow diagram of the present invention; Figure 2 This is a schematic diagram of the packaging structure of the present invention; Figure 3 This is a schematic diagram of an existing packaging structure. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] Figures 1-3 As a specific embodiment of the present invention, such as Figure 2 As shown, this embodiment provides a packaging structure for a 5kV silicon carbide Schottky device, including a DBC substrate, a SiC chip soldered to the substrate, aluminum bonding wires connecting the chip and the substrate, a double-layer PI passivation layer covering the bonding points, and an outermost modified epoxy resin encapsulation layer.

[0022] The specific manufacturing process is as follows: Figure 1 As shown, it includes the following steps: Step 1: Device Substrate Pretreatment A high thermal conductivity AlN ceramic DBC substrate was selected, with a ceramic layer thickness of 0.38 mm and a double-sided copper cladding layer thickness of 0.3 mm. First, the substrate was placed in a plasma cleaner, and an Ar / O2 mixed gas (flow ratio 1:1) was introduced for 5 minutes at 100 W. This step not only removed organic contaminants from the copper surface but also increased the surface's micro-roughness and activity. Subsequently, a 5kV SiC Schottky chip was positioned on the DBC substrate using a Sn96.5-Ag3.5 solder preform matched to the chip size. The substrate was then placed in a vacuum reflow oven for soldering, with a heating rate set to reach 240°C within 60 seconds and a holding time of 10 minutes to ensure sufficient solder wetting and intermetallic compound (IMC) formation. During the melting phase, a vacuum was applied to below 10 Pa to eliminate air bubbles. After soldering, the substrate was allowed to cool naturally. X-ray inspection showed that the solder layer thickness was uniformly controlled at 8–10 μm, with a void ratio of less than 1%.

[0023] Step 2: Aluminum wire bonding Wire bonding was performed using an automated wedge bonding machine. 99.999% high-purity aluminum wire with a diameter of 12 mil (approximately 305 μm) was selected. For 5kV high-voltage applications, to reduce the electric field intensity on the lead surface and withstand high current, the bonding parameters were set as follows: pressure 40 psi, ultrasonic power 150 W, and platform heating temperature 200℃. The lead arc height was specifically controlled between 150 and 200 μm to ensure sufficient insulation distance from the chip edge and to provide stress buffer space for subsequent thermal expansion and contraction.

[0024] Step 3: PI film double-layer passivation treatment This is the core step of the present invention. (1) Cleaning: The bonded device is subjected to O2 plasma desizing (80W, 3min) again to remove organic residues that may be generated during the bonding process and improve the adhesion of PI. (2) First layer coating: Take a photosensitive polyimide (PI) precursor liquid with a viscosity of 15000cp, drop 0.5mL onto the bonding point and chip surface, and let it stand for 30s to allow it to flow naturally. (3) First layer pre-baking: Place it in an oven and bake at 60℃ for 10min, then raise the temperature to 100℃ for 15min. At this time, the solvent partially evaporates, forming a semi-cured film with a thickness of about 30μm. (4) Intermediate treatment: Perform a short-time (30s) weak plasma treatment on the surface of the first layer semi-cured film to introduce hydrophilic groups. (5) Second layer coating and pre-baking: Repeat the dropping of the same type of PI liquid, let it stand, and then pre-bake at 60℃ / 15min → 100℃ / 30min to form a second layer of film with a thickness of about 35μm. (6) Gradient curing: The device was placed in a nitrogen-filled high-temperature oven and subjected to a strict gradient temperature program: 80℃ / 30min → 150℃ / 30min → 200℃ / 30min → 350℃ / 1h. This process completely converted polyamic acid into polyimide, and the solvent was released slowly without bubbles or cracks. Finally, a dense passivation layer with a total thickness of approximately 65μm was obtained, covering the chip surface and the root of the bonding wires.

[0025] Step 4: Epoxy resin encapsulation Preparation of modified epoxy resin: Micron-sized SiC powder treated with silane coupling agent was mixed with bisphenol A epoxy resin at a mass ratio of 1:2, and then an anhydride curing agent was added (resin:curing agent = 3:1), and the mixture was stirred at high speed until homogeneous. The mixture was placed in a vacuum chamber and degassed at -0.1 MPa for 15 min until no bubbles overflowed. The device treated in step 3 was immersed in the resin and pulled out to form a coating layer with a thickness of approximately 250 μm. It was placed in a curing oven and cured at 90°C for 2 hours under nitrogen-hydrogen mixed gas protection, followed by curing at 100°C for 1 hour. The cured resin layer effectively homogenized the high electric field near the bonding points by utilizing the nonlinear conductivity characteristics of the SiC filler.

[0026] Step 5: Post-processing and testing The packaging unit was soldered to a nickel-plated copper substrate using Sn96.5-Ag3.5 solder. A withstand voltage test was conducted at room temperature (25°C). The device prepared according to this invention maintained a reverse leakage current below 100μA at 5000V, with no partial discharge and no breakdown. In contrast, devices using traditional single-layer PI technology exhibited a sharp increase in leakage current around 3000V.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Any other modifications or equivalent substitutions made by those skilled in the art to the technical solutions of the present invention, as long as they do not depart from the spirit and scope of the technical solutions of the present invention, should be covered within the scope of the claims of the present invention.

Claims

1. A packaging process for 5kV silicon carbide Schottky devices, characterized in that, Includes the following steps: S1: Device substrate pretreatment; AlN or Al2O3 ceramic direct copper clad laminate is selected as the substrate, and the substrate surface is plasma cleaned; 5kV silicon carbide Schottky chip is soldered to DBC substrate using Sn96.5-Ag3.5 solder; S2: Aluminum wire bonding; using 12mil diameter aluminum bonding wires, the chip electrodes are connected to the copper layer of the DBC substrate through ultrasonic wedge bonding process to form an electrical interconnect; S3: Double passivation treatment of PI film; plasma removal and cleaning of the surface of the bonded device; drop-coating the first layer of PI coating liquid onto the metal leads and chip pads, allowing it to stand and level before staged baking to form the first layer of PI film. Subsequently, a second PI coating liquid was drop-coated onto the first PI film. After standing and leveling, it was baked in stages to form the second PI film. Finally, it was cured by gradient heating under a nitrogen atmosphere to completely imidize the double PI film and form a passivation layer with a total thickness of ≥60μm. S4: Epoxy resin coating; A modified silicon carbide-bisphenol A epoxy resin composite system was used. After vacuum degassing, the device was immersed in the epoxy resin system for encapsulation, with a coating thickness of ≥200μm, covering the PI film and lead connector area; then, it was cured in stages under a nitrogen-hydrogen mixed atmosphere. S5: Post-processing and testing; Solder the packaged device to the metal heat sink and perform a withstand voltage test.

2. The packaging process for 5kV silicon carbide Schottky devices according to claim 1, characterized in that: In S1, the ceramic layer thickness of the DBC substrate is 0.38 mm, and the thickness of the upper and lower copper layers is 0.3 mm; the plasma cleaning uses an Ar / O2 mixed gas with a power of 100 W and a processing time of 5 min; the welding process is as follows: the temperature is raised to 240°C in a vacuum pressure furnace for 60 s, held for 10 min, and then cooled to room temperature, with the welding layer thickness controlled at 8~10 μm.

3. The packaging process for 5kV silicon carbide Schottky devices according to claim 1, characterized in that: In S2, the parameters of the ultrasonic wedge welding process are set as follows: bonding pressure 40psi, ultrasonic power 150W, bonding temperature 200℃, and lead wire arc height controlled at 150~200μm.

4. The packaging process for 5kV silicon carbide Schottky devices according to claim 1, characterized in that: In S3, the viscosity of the PI coating solution is 15000cp; the staged baking process after coating the first PI film is as follows: baking at 60℃ for 10 min, followed by baking at 100℃ for 15 min, to form a first PI film with a thickness of about 30μm. After the first PI film is formed, its surface is subjected to plasma treatment to enhance interfacial adhesion.

5. The packaging process for 5kV silicon carbide Schottky devices according to claim 1, characterized in that: In S3, the staged baking process after the second PI film is coated is as follows: baking at 60°C for 15 minutes, followed by baking at 100°C for 30 minutes to form a second PI film with a thickness of about 35 μm.

6. The packaging process for 5kV silicon carbide Schottky devices according to claim 1, characterized in that: In S3, the specific process of gradient temperature curing is as follows: curing at 80℃ for 30 min, curing at 150℃ for 30 min, curing at 200℃ for 30 min, and finally curing at 350℃ for 1 h; the breakdown field strength of the cured PI passivation layer is ≥300V / μm.

7. The packaging process for 5kV silicon carbide Schottky devices according to claim 1, characterized in that: In step S4, the modified silicon carbide-bisphenol A epoxy resin composite system has a mass ratio of modified SiC to epoxy resin of 1:2 and a mass ratio of epoxy resin to curing agent of 3:1; the volume resistivity of the modified epoxy system is ≥1×10⁻⁶. 16 Ω·cm, glass transition temperature (Tg) ≥180℃.

8. The packaging process for 5kV silicon carbide Schottky devices according to claim 1, characterized in that: In step S4, the vacuum degassing treatment is performed for 15 minutes in a -0.1 MPa vacuum environment; the segmented curing process is: curing at 90℃ for 2 hours, followed by curing at 100℃ for 1 hour; the dielectric strength of the cured coating layer is ≥20 kV / mm.

9. The packaging process for 5kV silicon carbide Schottky devices according to claim 1, characterized in that: In S5, the metal base plate is welded using Sn96.5-Ag3.5 solder; the standard for the withstand voltage test is: at 25℃, the reverse breakdown voltage of the device is ≥5000V and the leakage current is ≤100μA.

10. A 5kV silicon carbide Schottky device fabricated using a packaging process according to any one of claims 1-9, characterized in that: The device has a composite passivation layer with a total thickness of ≥60μm, consisting of a first PI film and a second PI film, and a modified epoxy resin coating layer with a thickness of ≥200μm covering the outside of the composite passivation layer.

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