Wafer level chip verification method

Abstract

The present application relates to a kind of wafer level chip verification methods, applied to wafer level chip, the wafer level chip includes multiple interconnected dies, the wafer level chip verification method includes: each die is as master chip, and the die interconnected therewith is as slave chip, and is arranged into connection relationship table;Through script analysis connection relationship table, obtain configuration file, as the environmental configuration information of verification environment;Build the first verification sub-environment env1 of any two dies connected together, then the environmental configuration information corresponding to the remaining dies and its connection relationship is transmitted to the first verification sub-environment env1 by configuration file, corresponding verification sub-environment is built;Die-to-die verification is carried out.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a wafer-level chip verification method. Background Technology

[0002] Chiplet technology is a new chip design approach that emerged after SoC integration reached a certain level. It divides the SoC into smaller dies, interconnects these modular chips, and uses new packaging technologies to package chips with different functions and manufactured using different processes together to form a heterogeneous integrated chip (wafer-level chip).

[0003] Currently, the verification methods for heterogeneous integrated chips in the market are limited, the verification platforms are complex, have low reusability, and are inefficient.

[0004] Wafer-level chips are generally made up of many smaller dies connected together. The more dies there are, the larger the number of connection paths to verify, making it difficult to verify them all in a limited time. Summary of the Invention

[0005] To address at least some of the problems mentioned above in the prior art, the present invention provides a wafer-level chip verification method, applied to a wafer-level chip, wherein the wafer-level chip comprises multiple interconnected dies, and the wafer-level chip verification method includes:

[0006] Each die is designated as the master chip, and the dies interconnected with it are designated as slave chips, and the connection relationships are organized into a table.

[0007] The script parses the connection relationship table to obtain the configuration file, which serves as the environment configuration information for the verification environment.

[0008] Build a first verification sub-environment env1 by connecting any two bare dies together, and then transmit the environment configuration information of the remaining bare dies and their connection relationships to the first verification sub-environment env1 through the configuration file to build the corresponding verification sub-environment;

[0009] Perform null-to-null verification.

[0010] Furthermore, it also includes classifying the dies based on the number of dies connected.

[0011] Furthermore, the connection relationship table includes the connection relationships of parallel connection paths, mutually exclusive connection paths, and multi-die matrices.

[0012] Furthermore, each of the verification sub-environments includes a verification module and a configuration information module, wherein the verification module is used to perform data comparison and report results.

[0013] Furthermore, in the verification sub-environment, the master chip sends random data to the connected slave chip. After receiving the data sent by the master chip, the slave chip compares it with the original data in the verification module. The accuracy of the connection between the bare dies is verified by the comparison result, and the verification module reports the accuracy result.

[0014] Furthermore, if the data received from the chip is the same as the original data, then the connection between the master chip and the slave chip is accurate.

[0015] Furthermore, the master chips on multiple parallel connection paths can simultaneously send random data to the connected slave chips for verification.

[0016] Furthermore, multiple different types of master chips simultaneously send random data to connected slave chips for verification.

[0017] Furthermore, a master chip sends random data in parallel to its connected slave chips for verification, thereby simultaneously verifying all connection paths associated with the master chip.

[0018] Furthermore, each verification sub-environment is a verification environment consisting of two bare dies connected together.

[0019] The present invention has at least the following beneficial effects: The wafer-level chip verification method disclosed in the present invention reuses the verification environment, facilitates environment iteration, enables parallel verification of die-to-die interconnects, saves verification time, has high verification efficiency, and can fully verify the die-to-die connections in the wafer-level chip. Attached Figure Description

[0020] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the various embodiments of the present invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope.

[0021] Figure 1 A schematic diagram of a wafer-level chip die distribution according to an embodiment of the present invention is shown;

[0022] Figure 2 The flowchart of a wafer-level chip verification method according to an embodiment of the present invention is shown;

[0023] Figure 3 A schematic diagram of a verification environment according to an embodiment of the present invention is shown; and

[0024] Figure 4 A schematic diagram of a 2x2 die matrix according to an embodiment of the present invention is shown. Detailed Implementation

[0025] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0026] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0027] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0028] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0029] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0030] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0032] Figure 1 A schematic diagram of a wafer-level chip die distribution according to an embodiment of the present invention is shown. Figure 2 The flowchart of a wafer-level chip verification method according to an embodiment of the present invention is shown. Figure 3 A schematic diagram of a verification environment according to an embodiment of the present invention is shown.

[0033] like Figure 1As shown, a wafer-level chip contains multiple interconnected dies, each die being connected to multiple dies. For example, one die can be connected to two, three, or four dies. Each die can be a logic chip such as a CPU, DSP, GPU, or FPGA, a memory chip such as DRAM or Flash, or other types of chips such as a SOC or a sensor (such as a MEMS sensor).

[0034] like Figure 2 As shown, a wafer-level chip verification method includes:

[0035] Step 1: Classify the dies according to the number of dies connected. Dies connected to two dies are classified as Class 1 dies, dies connected to three dies are classified as Class 2 dies, dies connected to four dies are classified as Class 3 dies, and so on.

[0036] Step 2: Designate each die as a master chip and the dies interconnected with it as slave chips, and organize them into a connection relationship table. The connection relationship table includes parallel connection paths, mutually exclusive connection paths, and multi-die matrix connection relationships. Parallel connection paths are those that can be verified simultaneously. Mutually exclusive connection paths are those that cannot be verified simultaneously. The multi-die matrix connection relationships refer to the connection relationships between multiple dies.

[0037] Step 3: Parse the connection relationship table using a script to obtain the configuration file, which serves as the environment configuration information for the verification environment. Different die types and their interconnection relationships result in different environment configurations in the corresponding configuration files.

[0038] Step 4: Build a first verification sub-environment (env1) by connecting any two bare dies together. Then, transfer the environment configuration information of the remaining bare dies and their corresponding connections to the first verification sub-environment (env1) via a configuration file to build the corresponding verification sub-environments. For example, a second verification sub-environment (env2), a third verification sub-environment (env3), a fourth verification sub-environment (env4), and so on. Figure 3 As shown, all verification sub-environments constitute the wafer-level chip verification environment, ChipEnv. This step enables the reuse of verification environments. Each verification sub-environment includes a verification module and a configuration information module, where the verification module is used for data comparison and result reporting. Each verification sub-environment consists of two bare dies connected together.

[0039] Step 5: Perform die-to-die verification. Specifically, the master chip in the verification sub-environment sends random data to the connected slave chip. After receiving the data from the master chip, the slave chip compares it with the original data in the verification module. The accuracy of the connection between the dies is verified by the comparison result, and the verification module reports the accuracy result. If the data received by the slave chip is the same as the original data, the connection between the master chip and the slave chip is accurate; otherwise, the connection between the dies is inaccurate. Each die will act as a master chip to send data.

[0040] Multiple master chips on parallel connection paths can simultaneously send random data to connected slave chips for verification; or multiple master chips of different types can simultaneously send random data to connected slave chips for verification; or a master chip can send random data to its connected slave chips in parallel for verification, so as to simultaneously verify all connection paths related to this master chip.

[0041] All three parallel verification methods described above can improve verification efficiency.

[0042] The above verification method first classifies the bare dies in order to effectively extract which connections can be used as parallel connection paths and which connections are mutually exclusive connection paths, making it easier to organize a connection relationship table. The reuse of the verification environment is configured based on the information in the connection relationship table. Therefore, classifying the bare dies can effectively improve the reusability of the verification environment.

[0043] The following examples illustrate parallel connection paths and mutually exclusive connection paths.

[0044] Figure 4 A schematic diagram of a 2x2 die matrix according to an embodiment of the present invention is shown.

[0045] Use a 2x2 bare die matrix as an example to illustrate parallel connection paths and mutually exclusive connection paths. For example... Figure 4 As shown, die 11 is connected to die 12 and die 21, die 21 is connected to die 11 and die 22, die 12 is connected to die 11 and die 22, and die 22 is connected to die 12 and die 21.

[0046] Mutually exclusive connection paths: Die 11->Die 12 and Die 21->Die 11, Die 21->Die 22 and Die 11->Die 21, Die 12->Die 22 and Die 11->Die 12, Die 22->Die 12 and Die 21->Die 22. When a die acts as a master chip sending data to its connected slave chip, that die cannot act as a slave chip receiving data. For example, Die 11->Die 12 and Die 21->Die 11 are mutually exclusive connection paths, meaning that while die 11 is sending data to die 12, die 21 cannot send data to die 11.

[0047] Parallel connection paths: Die 11->Die 12 and Die 21->Die 22, Die 11->Die 21 and Die 12->Die 22. When the dies in different connection paths are not connected simultaneously, these connection paths can be used as parallel connection paths, enabling the master chip to send data to its connected slave chip simultaneously. For example, Die 11->Die 12 and Die 21->Die 22 are parallel connection paths, meaning that Die 11 can send data to Die 12, and simultaneously Die 21 can send data to Die 22.

[0048] The connections between multiple dies in the connection relationship table, such as die 11, die 21, and die 22, can be interpreted as connection paths of a multi-die matrix. Not all connection paths are listed here; only examples are provided.

[0049] The following example illustrates parallel verification from bare die to bare die.

[0050] like Figure 1 As shown, the following seven methods can all enable simultaneous verification of interconnections between multiple bare dies, effectively improving verification efficiency.

[0051] 1) Parallel verification of bare film 11->bare film 12, bare film 14->bare film 13, bare film 41->bare film 42, bare film 44->bare film 43;

[0052] 2) Parallel verification of bare film 11->bare film 21, bare film 41->bare film 31, bare film 14->bare film 24, bare film 44->bare film 34;

[0053] 3) Parallel verification of bare film 11->bare film 12, bare film 21->bare film 22, bare film 31->bare film 32, bare film 41->bare film 42;

[0054] 4) Parallel verification of bare film 11->bare film 21, bare film 12->bare film 22, bare film 13->bare film 23, bare film 14->bare film 24;

[0055] 5) Parallel verification of bare film 11->bare film 21, bare film 12->bare film 22, bare film 31->bare film 41, bare film 32->bare film 42;

[0056] 6) Parallel verification of bare film 22->bare film 21, bare film 32->bare film 31, bare film 23->bare film 24, bare film 33->bare film 34;

[0057] 7) Parallel verification of bare film 22->bare film 12, bare film 23->bare film 13, bare film 32->bare film 42, bare film 33->bare film 43.

[0058] The embodiments may be provided as computer program products that may include one or more machine-readable media on which machine-executable instructions are stored, which, when executed by one or more machines such as a computer, computer network, or other electronic equipment, may cause one or more machines to perform operations according to the embodiments of the invention. Machine-readable media may include, but are not limited to, floppy disks, optical disks, CD-ROMs (compact disc read-only memory) and magneto-optical disks, ROMs (read-only memory), RAMs (random access memory), EPROMs (erasable programmable read-only memory), EEPROMs (electrically erasable programmable read-only memory), magnetic or optical cards, flash memory, or other types of media / machine-readable media suitable for storing machine-executable instructions.

[0059] Furthermore, various embodiments can be downloaded as computer program products, wherein the program can be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem and / or a network connection) using one or more data signals implemented and / or modulated by a carrier wave or other propagation medium. Therefore, the machine-readable medium used herein may include such a carrier wave, but is not required to do so.

[0060] The aforementioned wafer-level chip verification method reuses the verification environment, facilitates environment iteration, enables parallel die-to-die interconnect verification, saves verification time, has high verification efficiency, and can fully verify die-to-die connections in wafer-level chips. It provides a new approach to verifying connection relationships in the wafer-level chip field. Combined with the high execution efficiency of software development, it can be fully applied in the verification field to accelerate the implementation of chiplet connection relationship verification.

[0061] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A wafer-level chip verification method, characterized in that, Applied to wafer-level chips, wherein the wafer-level chip comprises multiple interconnected dies, the wafer-level chip verification method includes: The dies are classified according to the number of dies connected; Each die is designated as a master chip, and the dies interconnected with it are designated as slave chips. These are then organized into a connection relationship table. The connection relationship table includes parallel connection paths, mutually exclusive connection paths, and connection relationships of multiple die matrices. The script parses the connection relationship table to obtain the configuration file, which serves as the environment configuration information for the verification environment. A first verification sub-environment env1 is built by connecting any two bare dies together. Then, the environment configuration information of the remaining bare dies and their connection relationships is transmitted to the first verification sub-environment env1 through a configuration file to build the corresponding verification sub-environment. Each verification sub-environment includes a verification module and a configuration information module, wherein the verification module is used to perform data comparison and report results. Perform bare-film-to-bare-film verification; The master chip in the verification sub-environment sends random data to the connected slave chip. After receiving the data sent by the master chip, the slave chip compares it with the original data in the verification module. The accuracy of the connection between the bare dies is verified by the comparison result, and the verification module reports the accuracy result. Multiple master chips on parallel connection paths can simultaneously send random data to connected slave chips for verification; or multiple master chips of different types can simultaneously send random data to connected slave chips for verification; or a master chip can send random data to its connected slave chips in parallel for verification, so as to simultaneously verify all connection paths related to the master chip.

2. The wafer-level chip verification method according to claim 1, characterized in that, If the data received from the chip is the same as the original data, then the connection between the master chip and the slave chip is accurate.

3. The wafer-level chip verification method according to claim 1, characterized in that, Each verification sub-environment consists of two bare dies connected together.

Images