Storage device and data access method

Abstract

The present invention provides a storage device and a data access method. The storage device includes a main storage unit and at least one additional unit. The main storage unit includes a main memory element configured to store secret data, and a main access unit configured to receive an external access command. Each additional unit is configured to receive the external access command. Each additional unit includes an additional memory element configured to store non-specific data, a local access generation element configured to trigger generation of an internal access command based on the external access command, and an additional access unit configured to receive the local access command. The main storage unit and each additional unit are coupled to the same power rail, and coupled to a connection line to receive the external access command simultaneously to access the secret data and the non-specific data stored by each additional unit in parallel (simultaneously).

Description

Technical Field

[0001] This invention relates to a storage device and a data access method, and in particular to a storage device and a data access method that can protect confidential data stored in the storage device from power attacks. Background Technology

[0002] In many electronic systems, critical confidential data is stored in the electronic device's storage. This confidential data may include passwords, decryption keys, version control information, media licenses, personal information, or financial data. To protect this confidential data, access to the storage device is typically restricted to entities with special access rights (such as certain central processing units). Despite these precautions, many attackers still attempt to access the confidential data stored in the storage device. One common attack method is power supply voltage analysis. In this type of attack, the power supply voltage is monitored at the microvolt level. When the central processing unit performs access to the confidential data on the storage device, these access operations produce tiny power supply voltage shifts. These tiny power supply voltage shifts provide a weak indication of the data being written / read. Repeated access to the confidential data can separate these weak spikes from other system noise reflected in the power supply noise, allowing the confidential data to be recovered. Summary of the Invention

[0003] In view of this, the present invention provides a storage device and a data access method to improve the problems of the prior art.

[0004] An embodiment of the present invention provides a storage device. The storage device includes a main storage unit and at least one additional unit. The main storage unit includes a main memory element and a main access unit. The main memory element is configured to store secret data. The main access unit is configured to receive external access commands. Each additional unit is configured to receive external access commands. Each additional unit includes an additional memory element, a local access generation element, and an additional access unit. The additional memory element is configured to store non-specific data. The local access generation element is configured to trigger the generation of an internal access command based on the external access command. And the additional access unit is configured to receive local access commands. The main storage unit and each additional unit are coupled to the same power rail and coupled to a connection line to simultaneously receive external access commands and access the secret data and the non-specific data stored in each additional unit in parallel (simultaneously).

[0005] An embodiment of the present invention provides a data access method applicable to a storage device, the storage device comprising a main storage unit and at least one additional unit. The main storage unit stores confidential data. Each additional unit stores non-specific data. The main storage unit and each additional unit are coupled to a power rail and to a connection line so that the main storage unit and each additional unit simultaneously receive external access commands. The data access method includes the following steps: receiving an external access command; receiving a non-specific number; generating access-related data based on the non-specific number, triggered by the external access command; generating an internal access command corresponding to at least one additional unit based on the access-related data; and accessing the main storage unit in parallel (simultaneously) according to the external access command and accessing each additional unit according to the internal access command.

[0006] One embodiment of the present invention provides a single-chip system including the aforementioned storage device.

[0007] Based on the above, some embodiments of the present invention provide a storage device and a data access method. By setting the main storage unit and each additional unit to have the same structure, and by allowing the main storage unit and each additional unit to access secret data and non-specific data stored in each additional unit in parallel (simultaneously), it can be ensured that power noise caused by reading or writing to the main storage unit and each additional unit is simultaneously injected into the power rail, and that the power noise injection characteristics are the same and that the power noise is generated at the same intensity. This makes it difficult for an attacker to separate the signal of the main storage unit from that of other additional units from the signal analysis of the power rail in order to analyze and obtain the secret data of the main storage unit. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a storage device and an external read / write interface according to an embodiment of the present invention.

[0009] Figure 2 This is a block diagram of memory cells and connection lines drawn according to an embodiment of the present invention.

[0010] Figure 3 This is a flowchart illustrating a data access method according to some embodiments of the present invention.

[0011] Figure 4 This is a flowchart illustrating a data access method according to some embodiments of the present invention.

[0012] Figure 5 This is a flowchart illustrating a data access method according to an embodiment of the present invention.

[0013] Figure 6 This is a flowchart illustrating a data access method according to an embodiment of the present invention.

[0014] Figure 7This is a flowchart illustrating a data access method according to an embodiment of the present invention.

[0015] Figure 8 This is a flowchart illustrating a data access method according to an embodiment of the present invention.

[0016] Figure 9 This is a block diagram of a single-chip system drawn according to an embodiment of the present invention. Detailed Implementation

[0017] The foregoing and other technical contents, features, and effects of this invention will be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings. The thickness or dimensions of the elements in the drawings are exaggerated, omitted, or approximated for the understanding and reading of those skilled in the art. Furthermore, the dimensions of each element are not exactly their actual dimensions and are not intended to limit the implementation of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention. The same reference numerals will be used to denote the same or similar elements in all the drawings.

[0018] Figure 1 This is a block diagram illustrating a storage device and an external read / write interface according to an embodiment of the present invention. Please refer to... Figure 1 The storage device 100 includes a main storage unit 101 and at least one additional unit 102-1 to 102-5. The main storage unit 101 and each additional unit 102-1 to 102-5 are memory units. The main storage unit 101 is configured to store confidential data, and each additional unit 102-1 to 102-5 stores non-specific data, which may be randomly generated and meaningless random data. The main storage unit 101 and each additional unit 102-1 to 102-5 are coupled to the same power rail 105 and connection line 103, such that the main storage unit 101 and each additional unit 102-1 to 102-5 simultaneously receive external access commands issued from the external read / write interface 104.

[0019] It should be noted here that, although Figure 1Only five additional units 102-1 to 102-5 are shown; however, this is merely for illustrative purposes. In reality, the storage device 100 can contain any number of additional units, and the present invention is not limited to five additional units. Furthermore, this embodiment also includes an implementation with only one additional unit. Additionally, the main storage unit 101 and each additional unit 102-1 to 102-5 are designed to have substantially the same or similar noise generation characteristics, such that the main storage unit 101 and each additional unit 102-1 to 102-5 have substantially the same or similar power supply noise injection characteristics when accessed. The power supply noise injection characteristics refer to the noise characteristics injected by the power rail 105 supplying power to the memory elements such as the main storage unit 101 and each additional unit 102-1 to 102-5 when they are accessed. In some embodiments of the present invention, the aforementioned noise characteristics refer to the power spectral density of the noise. It should be noted that the aforementioned setting of the main storage unit 101 and each of the additional units 102-1 to 102-5 having the same power noise injection characteristics when accessed refers to being theoretically identical. In a preferred embodiment, to achieve the aforementioned setting of the main storage unit 101 and each of the additional units 102-1 to 102-5 having the same or similar power noise injection characteristics when accessed, the main storage unit 101 and each of the additional units 102-1 to 102-5 have identical structures. The aforementioned identical structures of the main storage unit 101 and each of the additional units 102-1 to 102-5 mean that the main storage unit 101 and each of the additional units 102-1 to 102-5 have the same type, size, and configuration. Here, type refers to the type of memory, such as Static Random Access Memory (SRAM) or Read-Only Memory (ROM), etc. Size refers to the size of the memory. Configuration refers to the internal configuration of the memory. Taking static random access memory (SRAM) as an example, identical configuration of SRAM means that the configurations of rows and columns, decoders and multiplexers within the SRAM are identical. Setting the main storage unit 101 and each of the supplementary units 102-1 to 102-5 to have the same structure ensures that the main storage unit 101 and each of the supplementary units 102-1 to 102-5 have substantially the same or similar power supply noise injection characteristics when accessed.Since they have the same structure, their power noise injection characteristics should be the same. However, due to actual manufacturing process errors, even if they have the same structure, the power noise injection characteristics of the main storage cell 101 and each of the additional cells 102-1 to 102-5 may have slight differences when accessed. Alternatively, if their structures are only slightly different, but their power noise injection characteristics are substantially similar—in other words, if the power noise injection characteristics of the main storage cell 101 and each of the additional cells 102-1 to 102-5 are similar when accessed—then this invention can be applied.

[0020] The following is a detailed description, with reference to the accompanying drawings, of some embodiments of the data access methods of the present invention and how the various components of the storage device 100 cooperate to operate.

[0021] Figure 3 This is a flowchart illustrating a data access method according to some embodiments of the present invention. Please also refer to [the relevant documentation]. Figure 1 and Figure 3 In step S301, the main storage unit 101 and each additional unit 102-1 to 102-5 simultaneously access the secret data and the non-specific data stored in each additional unit 102-1 to 102-5. The so-called parallel (simultaneous) access means that any access operation of the main storage unit 101 to its stored secret data is accompanied by a corresponding access operation of each additional unit 102-1 to 102-5 to its respective stored non-specific data.

[0022] In this embodiment, since the main storage unit 101 and each of the additional units 102-1 to 102-5 are connected to the same power rail 105, this ensures that any power noise caused by reading or writing to the main storage unit 101 and each of the additional units 102-1 to 102-5 will be injected into the power rail 105 simultaneously. Furthermore, since the main storage unit 101 and each of the additional units 102-1 to 102-5 have the same structure, their power noise injection characteristics are the same, and they all generate power noise with the same intensity. This makes it difficult for an attacker to separate the signal of the main storage unit 101 from the signals of the additional units 102-1 to 102-5 from the signal analysis of the power rail 105 in order to analyze and obtain the secret data of the main storage unit 101.

[0023] Figure 2 This is a block diagram of memory cells and connection lines drawn according to an embodiment of the present invention. Figure 4 This is a flowchart illustrating a data access method according to some embodiments of the present invention. Please also refer to [the relevant documentation]. Figure 2 and Figure 4In one embodiment of the present invention, the aforementioned main storage unit 101 and each additional unit 102-1 to 102-5 each have Figure 2 The diagram illustrates the structure of memory unit 200. Memory unit 200 includes memory element 201, access unit 202, random number generation unit 203, and local access generation unit 204. Local access generation unit 204 is coupled to random number generation unit 203, and access unit 202 is coupled to memory element 201 and local access generation unit 204. Random number generation unit 203 is configured to generate multiple non-specific numbers upon receiving a trigger signal.

[0024] The memory element 201 of the main storage unit 101 is used to store the aforementioned confidential data, while the memory element 201 of each additional unit 102-1 to 102-5 is used to store randomly generated and meaningless non-specific data. The local access generation unit 204 and the access unit 202 are simultaneously coupled to the connection line 103 and are configured to simultaneously receive external access commands issued by the external read / write interface 104.

[0025] In this embodiment, step S301 further includes steps S401 to S404. In step S401, the local access generation unit 204 and access unit 202 of the main storage unit 101 and each of the additional units 102-1 to 102-5 receive an external access command from the external read / write interface 104 during the access cycle of the storage device 100. The main storage unit 101 and each of the additional units 102-1 to 102-5 receiving the external access command indicates that an authorized external device (such as a central processing unit) wants to access the secret data stored in the main storage unit 101. Generally, the external access command usually includes both read and write commands. However, for read-only memory (ROM), it may not include write commands. The fact that external access commands typically include both read and write commands will be further explained in other embodiments below.

[0026] In step S402, in response to the local access generation unit 204 and the access unit 202 receiving an external access command during the access cycle of the storage device 100, the main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 send trigger signals to their respective random number generation units 203 based on the external access command, causing each random number generation unit 203 to generate multiple non-specific numbers. After receiving these non-specific numbers, the main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 generate access-related data based on the received non-specific numbers.

[0027] In step S403, the main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 generate internal access commands based on access-related data and transmit the internal access commands to the access unit 202. The format of the internal access commands is the same as that of the external access commands, except that the internal access commands are generated based on access-related data generated from non-specific numbers. In step S404, the access unit 202 receives the internal access commands generated by the local access generation units 204 and accesses the memory element 201 based on both the external and internal access commands. Specifically, the access unit 202 of the main storage unit 101 accesses its memory element 201 based on the external access commands, while the access units 202 of each of the supplementary units 102-1 to 102-5 access their respective memory elements 201 based on their internal access commands.

[0028] It should be noted that the functions of the aforementioned access unit 202 can be implemented based on a finite state machine or a combinational logic circuit.

[0029] As mentioned above, external access commands typically include read commands and write commands. The following explanations of steps S401 to S404 will use read commands and write commands as examples.

[0030] Figure 5 This is a flowchart illustrating a data access method according to an embodiment of the present invention. Please also refer to [the relevant documentation]. Figure 1 , Figure 2 and Figure 5When the external access command is an external read command, step S401 includes step S501, step S402 includes step S502, step S403 includes step S503, and step S404 includes step S504. The external read command includes a read location indicating the data stored at the read location of the memory element 201 to be read. In step S501, the main storage unit 101 and the local access generation unit 204 and access unit 202 of each of the supplementary units 102-1 to 102-5 receive the external read command from the external read / write interface 104 during the access cycle of the storage device 100. In step S502, in response to the local access generation unit 204 and the access unit 202 receiving an external read command during the access cycle of the storage device 100, the main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 send trigger signals to their respective random number generation units 203 based on the external read command, causing each random number generation unit 203 to generate multiple non-specific numbers. The main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 then receive these non-specific numbers to generate random read positions.

[0031] In step S503, the local access generation units 204 of the main storage unit 101 and each of the supplementary units 102-1 to 102-5 generate internal read commands based on their respective random read locations and transmit the internal read commands to the access unit 202. The format of the internal read commands is the same as that of the external read commands, except that the internal read commands include random read locations generated based on non-specific numbers. In step S504, the access unit 202 of the main storage unit 101 reads the data stored at the read locations in the memory elements 201 of the main storage unit 101 based on the external read commands. Meanwhile, the access units 202 of each of the supplementary units 102-1 to 102-5 read the data stored at the random read locations in their respective memory elements 201 based on their respective internal read commands.

[0032] In one embodiment of the invention, each additional unit 102-1 to 102-5 is configured not to be coupled to a data bus outside the storage device 100. This configuration ensures that data read from random read locations in the respective memory elements 201 of each additional unit 102-1 to 102-5 is not transmitted back. Only data read from read locations in the memory elements 201 of the main storage unit 101 is transmitted back.

[0033] Figure 6 This is a flowchart illustrating a data access method according to an embodiment of the present invention. Please also refer to [the relevant documentation]. Figure 1 , Figure 2 and Figure 6When the external access command is an external write command, step S401 includes step S601, step S402 includes step S602, step S403 includes step S603, and step S404 includes step S604. The external write command includes a write location and write data, indicating that the aforementioned write data should be written to the aforementioned write location in the memory element 201. In step S601, the main storage unit 101 and the local access generation unit 204 and access unit 202 of each of the supplementary units 102-1 to 102-5 receive the external write command from the external read / write interface 104 during the access cycle of the storage device 100. In step S602, in response to the local access generation unit 204 and the access unit 202 receiving an external write command during the access cycle of the storage device 100, the local access generation units 204 of the main storage unit 101 and each of the supplementary units 102-1 to 102-5 send trigger signals to their respective random number generation units 203 based on the external write command, causing each random number generation unit 203 to generate multiple non-specific numbers. The local access generation units 204 of the main storage unit 101 and each of the supplementary units 102-1 to 102-5 then receive these non-specific numbers to generate random write locations and random write data.

[0034] In step S603, the local access generation units 204 of the main storage unit 101 and each of the supplementary units 102-1 to 102-5 generate internal write commands based on their respective random write locations and random write data, and transmit the internal write commands to the access unit 202. The format of the internal write commands is the same as that of the external write commands, except that the internal write commands include random write locations and random write data generated based on non-specific numbers. In step S604, the access unit 202 of the main storage unit 101 writes the write data of the external write command into the memory element 201 within the main storage unit 101 based on the write location of the external write command. Meanwhile, the access units 202 of each of the supplementary units 102-1 to 102-5 write random write data into their respective memory elements 201 based on their respective internal write commands.

[0035] In the aforementioned embodiments, if the main storage unit 101 is performing a read operation, each additional unit 102-1 to 102-5 corresponds to the read operation of the main storage unit 101 and performs a read of its own memory element 201 based on a random read location. These additional parallel (simultaneous) read operations inject noise into the power rail 105, thereby masking any information content that can be obtained by analyzing the noise. If the main storage unit 101 is performing a write operation, the actual external write data and write location are used to write to the memory element 201 of the main storage unit 101. The memory elements 201 of the additional units 102-1 to 102-5 perform write operations according to the random write locations and random write data generated by their respective local access generation units 204 based on the random number generation unit 203. This has the effect of masking voltage changes on the power rail 105, which are visible during the write operation process of the memory element 201 of the main storage unit 101.

[0036] Since the random number generation units 203 of all additional units 102-1 to 102-5 are independent of each other, this means that each time specific secret data is accessed from the memory element 201 of the main storage unit 101, different non-specific data will be read from the additional units 102-1 to 102-5. This ensures that repeated readings of the same secret data do not lead to repeatable power noise injection characteristics. This further thwarts any attacker attempting to isolate the secret data characteristics. The implementation of the random number generation unit 203 will be described in more detail in subsequent embodiments.

[0037] Figure 7 This is a flowchart illustrating a data access method according to an embodiment of the present invention. Please also refer to [the relevant documentation]. Figure 1 , Figure 2 and Figure 7 In some embodiments of the present invention, the aforementioned step S301 further includes steps S701 and S702. In step S701, the local access generation unit 204 and access unit 202 of the main storage unit 101 and each of the additional units 102-1 to 102-5 do not receive an external access command from the external read / write interface 104 during the access cycle of the storage device 100. In step S702, in response to the fact that the local access generation unit 204 and access unit 202 do not receive an external access command from the external read / write interface 104 during the access cycle of the storage device 100, the local access generation unit 204 of the main storage unit 101 and each of the additional units 102-1 to 102-5 sends a trigger signal to their respective random number generation units 203, causing their respective random number generation units 203 to generate multiple non-specific numbers. The main storage unit 101 and the local access generation unit 204 of each of the additional units 102-1 to 102-5 then receive these non-specific numbers to generate random read locations.

[0038] In step S703, the main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 generate internal read commands based on their respective random read locations and transmit the internal read commands to their respective access units 202. In step S704, the main storage unit 101 and the access units 202 of each of the supplementary units 102-1 to 102-5 read the data stored in the random read locations of their respective memory elements 201 based on their respective internal read commands.

[0039] Figure 8 This is a flowchart illustrating a data access method according to an embodiment of the present invention. Please also refer to [the relevant documentation]. Figure 1 , Figure 2 and Figure 8 In some embodiments of the present invention, the aforementioned step S301 further includes performing steps S801, S802, and S803 outside the access cycle. In step S801, the main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 send trigger signals to their respective random number generation units 203, causing each of the random number generation units 203 to generate a plurality of non-specific numbers. The main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 then receive these non-specific numbers to generate random read positions. In step S802, the main storage unit 101 and the local access generation units 204 of each of the supplementary units 102-1 to 102-5 generate internal read commands based on their respective random read positions and transmit the internal read commands to their respective access units 202. In step SS03, the main storage unit 101 and the access units 202 of each of the additional units 102-1 to 102-5 read the data stored in the random read position of their respective memory elements 201 based on their respective internal read commands.

[0040] In some of the aforementioned embodiments, when no external access operation occurs (e.g., no external access command is received from the external read / write interface 104 or outside the access cycle), the main storage unit 101 and each of the supplementary units 102-1 to 102-5 will continuously perform read operations. Therefore, an attacker cannot detect when an actual read operation occurs. This makes it more difficult for an attacker to carry out a successful attack.

[0041] The following embodiments illustrate the implementation of the random number generation unit 203. In some embodiments of the present invention, the random number generation unit 203 utilizes a true random number generator (TRNG) to generate these non-specific numbers. A true random number generator is also known as a hardware random number generator. It is a device that generates random numbers through physical processes rather than computer programs. Such devices are typically based on microscopic phenomena that generate low statistically random "noise" signals, such as thermodynamic noise, the photoelectric effect, and quantum phenomena. These physical processes are theoretically completely unpredictable and have been experimentally verified. A true random number generator typically includes a converter that converts certain aspects of the physical phenomenon into electrical signals, an amplifier that amplifies the amplitude of random fluctuations to a measurable level, and some type of analog-to-digital converter that converts the output into a simple binary digit 0 or 1. By repeatedly sampling the randomly varying signal, a series of random numbers can be obtained.

[0042] In some embodiments of the present invention, the random number generation unit 203, a pseudo-random number generator (PRNG) or a cryptographically secure pseudo-random number generator (CSPRNG), generates these non-specific numbers. The pseudo-random number generator, also known as a deterministic random bit generator (DRBG), is an algorithm for generating number sequences. Its characteristics approximate those of a random sequence. The cryptographically secure pseudo-random number generator is a pseudo-random number generator capable of deriving cryptographically secure pseudo-random numbers through computation. The cryptographically secure pseudo-random numbers generated by the cryptographically secure pseudo-random number generator possess additional pseudo-random properties.

[0043] In some embodiments of the present invention, the main storage unit 101 and the supplementary units 102-1 to 102-5 are all static random access memories. In some embodiments of the present invention, the main storage unit 101 and the supplementary units 102-1 to 102-5 are all read-only memories.

[0044] Figure 9 This is a block diagram of a single-chip system according to an embodiment of the present invention. Please refer to... Figure 9The single-chip system 900 includes a central processing unit 901, an external read / write interface 104, a static random access memory (SRAM) element 902, and a read-only memory (ROM) element 903. The single-chip system 900 is coupled to the external read / write interface 104, which is coupled to the SRAM element 902 and the ROM element 903. In some embodiments, the SRAM element 902 is the storage device 100 described in any of the foregoing embodiments, and the main storage unit 101 and the supplementary units 102-1 to 102-5 are SRAMs. In some embodiments, the ROM element 903 is the storage device 100 described in any of the foregoing embodiments, and the main storage unit 101 and the supplementary units 102-1 to 102-5 are ROMs. The central processing unit 901 accesses the SRAM element 902 and the ROM element 903 through the external read / write interface 104.

[0045] It should be noted that, in the aforementioned Figure 9 In the illustrated embodiments, the storage device 100 described in the foregoing embodiments is implemented in a single-chip system. That is, the storage device 100 described in the foregoing embodiments is integrated into the integrated circuit of a single chip. However, the storage device 100 described in the foregoing embodiments can also be independently packaged on a separate chip to serve as an external storage chip for other systems. The present invention does not limit the storage device 100 to be integrated into the integrated circuit of a single chip.

[0046] [Symbol Explanation]

[0047] 100: Storage device

[0048] 101: Main Storage Unit

[0049] 102-1~102-5: Additional Units

[0050] 103: Connection Line

[0051] 104: External Read / Write Interface

[0052] 105: Power Rail

[0053] 200: Memory Unit

[0054] 201: Memory element

[0055] 202: Access Unit

[0056] 203: Random Number Generation Unit

[0057] 204: Local Access Generation Unit

[0058] 900: Single-chip system

[0059] 901: Central Processing Unit

[0060] 902: Static Random Access Memory Element

[0061] 903: Read-Only Memory Element

[0062] S301, S401~S404, S501~S504, S601~S604, S701~S704, S801~S803: Steps

Claims

1. A storage device comprising: One main storage unit, comprising: A main memory element configured to store secret data; and A main access unit configured to receive an external access command and access the main memory element according to the external access command; and At least one additional unit is configured to receive the external access command, wherein each of the at least one additional unit includes: An additional memory element, configured to store non-specific data; A local access generation element, configured to trigger the generation of an internal access command based on the external access command; and An additional access unit is configured to receive the internal access command and access the additional memory element based on the internal access command; in, The main storage unit and each of the at least one additional unit are coupled to a power rail and to a connection line to simultaneously receive an external access command to access the main storage unit and each of the at least one additional unit.

2. The storage device of claim 1, wherein the local access generating element comprises: A random number generation unit, configured to generate a random number based on a trigger signal; and A local access generation unit is coupled to the random number generation unit, which is configured to generate the internal access command based on the random number.

3. The storage device of claim 2, wherein when the external access command is an external read command and the internal access command is an internal read command, the internal read command includes a random read location, wherein the random read location is generated based on the random number generated by the random number generation unit.

4. The storage device of claim 2, wherein when the external access command is an external write command and the internal access command is an internal write command, the internal write command includes a random write location and a random write data, wherein the random write location and the random write data are generated based on the random number generated by the random number generation unit.

5. The storage device as claimed in claim 1, 2, 3 or 4, wherein the noise generation characteristics of the main storage unit and the at least one additional unit are substantially similar.

6. The storage device as claimed in claim 1, 2, 3 or 4, wherein the main storage unit is substantially similar or identical in structure to each of the at least one additional unit.

7. The storage device of claim 1, 2, 3 or 4, wherein the local access generating element and the additional access unit are configured to perform a read operation simultaneously during an access cycle when the external access command is not received and at least one of them is received outside the access cycle.

8. A data access method applicable to a storage device, the storage device comprising a main storage unit and at least one additional storage unit; wherein, The main storage unit and each of the at least one additional unit are coupled to a power rail and to a connection line; This data access method includes the following steps: An external access command is simultaneously received in the main storage unit and in each of the at least one additional unit; In each of the at least one additional unit, an internal access command is generated based on a nonspecific number and the triggering of the external access command; as well as Simultaneous access to the main storage unit and each of the at least one additional unit, wherein the main storage unit is accessed according to the external access command and each of the at least one additional unit is accessed according to the internal access command.

9. The data access method as described in claim 8, wherein, The primary storage unit and each of the at least one additional unit are configured to perform a read operation simultaneously if the external access command is not received during an access cycle and if at least one of the external access commands is received outside the access cycle.

10. The data access method of claim 8 or 9, wherein the noise generation characteristics of the main storage unit and the at least one additional unit are substantially similar.

11. The data access method of claim 8 or 9, wherein the main storage unit is substantially similar or identical in structure to each of the at least one additional unit.

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