Display panel

Abstract

Disclosed is a display panel, comprising: a display area configured to have a curve and comprising a pixel array having a plurality of pixel rows; and a non-display area disposed at a periphery of the display area and configured to comprise a plurality of gate blocks arranged along the curve, wherein a plurality of connection lines are provided to connect the gate blocks with the pixel rows, the connection lines are configured in a multi-stage arrangement to minimize a size of the non-display area, and at least one dummy block is provided between the gate blocks. Thus, the space waste in the frame provided with the connection lines can be reduced, thereby reducing the size of the non-display area in the display panel.

Description

[0001] This application is a divisional application of the invention patent application filed on October 15, 2019, with application number 201910979029.1 and invention title "Display Panel".

[0002] Cross-reference to related applications

[0003] This application claims the benefit of Korean Patent Application No. 10-2018-0128714, filed on October 26, 2018, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0004] The present invention relates to a display panel which is configured to have a different shape than a rectangular shape and includes driving circuitry. Background Technology

[0005] Wearable devices, flexible devices, and vehicle displays require deformable (or non-rectangular) display panels that can be configured to replace existing rectangular shapes. For example, a disc-shaped display panel can be used in watches, while a rectangular display panel with curved corners can be used in smartphones.

[0006] The driving circuitry of the display panel includes: a pixel array configured to display an image, a data driver configured to provide data signals to the data lines of the pixel array, a gate driver configured to sequentially provide gate signals to the gate lines of the pixel array, and a timing controller configured to control the data driver and the gate driver.

[0007] In the prior art, display devices are implemented by connecting an additional gate driver IC to the display panel. However, this method increases the cost of the display device due to the cost of the IC, and also increases the width of the non-display area due to the increased number of interconnects configured to connect the gate driver to the gate line.

[0008] Recently, a technique has been applied that integrates gate drivers and pixel arrays into display panels. The gate driver integrated into the display panel is known to be a gate-in-panel (GIP) circuit. The GIP circuit includes a shift register. The shift register comprises multiple stages connected in slave configuration. Each stage generates an output in response to a start pulse and shifts the output according to a shift clock. The shift register is provided with a start pulse, a shift clock, a drive voltage, etc.

[0009] In cases where the GIP circuitry is integrated into the display panel, the number of interconnects can be reduced; however, it is difficult to reduce the size of the non-display area. To ensure space for lines configured to provide start pulses, shift clocks, and drive voltages to each stage of the GIP circuitry, the GIP circuitry extends in the left-right direction. Furthermore, multiple interconnects arranged in the display panel, including deformable portions (or non-rectangular portions), extend from the gate lines and are configured in a straight line shape, so that multiple interconnects are not connected to the gate drivers. Therefore, depending on the interconnection structure, the size of the non-display area increases.

[0010] To overcome these problems, various methods have been investigated for reducing non-display areas in deformable (or non-rectangular) display panels with gate drivers. Summary of the Invention

[0011] As described above, when the gate driver is integrated within the display panel, the gate driver occupies a portion of the non-display area, increasing the size of the non-display area. Methods for reducing the size of the non-display area may include optimizing the layout of the gate driver or optimizing the design of the wiring that connects the gate driver and the pixel array to each other to reduce the area occupied by the gate driver. Hereinafter, methods for optimizing the wiring design will be described with reference to this invention.

[0012] The gate driver includes a shift register comprising multiple slave-connected stages, each connected to a pixel array. The anamorphic (or non-rectangular) display panel includes a curve such that the gate driver embedded in the anamorphic (or non-rectangular) portion of the display panel is arranged along the curve. Therefore, the multiple stages arranged in the anamorphic portion are not each located on the same axis as the pixel array connecting the multiple stages. The connections configured to connect the gate driver and the pixel array to each other can be curved or angled along the curve. In this case, if a portion of the area is wasted due to the suboptimal arrangement of the connections, or if the connections are designed to increase the size of the non-display area, the size of the non-display area of ​​the display panel increases.

[0013] Therefore, the inventors recognized the above problems and invented a wiring structure and a display panel using the wiring structure, which is beneficial to reduce the size of the non-display area, especially the size of the non-display area in the deformed part.

[0014] The present invention was made in view of the above problems. The object of the present invention is to provide a wiring structure that is advantageous for reducing the size of the non-display area and a display panel using the wiring structure.

[0015] In addition to the objectives of the invention as described above, those skilled in the art will clearly understand additional objectives of the invention from the following description.

[0016] According to one aspect of the present invention, the above and other objectives can be achieved by providing a display panel comprising: a display area configured to have a curve and including a pixel array having a plurality of pixel rows; and a non-display area disposed around the periphery of the display area and configured to include a plurality of gate blocks arranged along the curve, wherein a plurality of connecting lines are provided to connect the gate blocks to the pixel rows, the connecting lines being configured in a multi-level arrangement to minimize the size of the non-display area, and at least one virtual block is provided between the gate blocks. Therefore, space wastage in the bezel with connecting lines can be reduced, thereby reducing the size of the non-display area in the display panel.

[0017] According to another aspect of the present invention, a display panel is provided, including a deformable portion divided into at least two regions, a first region and a second region. The display panel includes: an "x" number of gate lines arranged in the first region and a "y" number of gate lines arranged in the second region (where "x" > y, and each of "x" and "y" is an integer); a gate driver configured to transmit gate signals to the gate lines; and interconnects configured to connect the gate driver and the gate lines to each other, wherein the interconnects closest to the second region connect the gate lines and the gate driver by a straight line, and dummy gate blocks are provided in some portions of the second region closest to the first region. Therefore, space wastage in the bezel with interconnects can be reduced, thereby reducing the size of the non-display area in the display panel.

[0018] According to another aspect of the present invention, a display panel is provided, the display panel being divided into a general portion and a deformable portion, wherein the display panel includes: a display area having a plurality of pixels, a circuit area having gate drivers, and a bezel with interconnects configured to connect the gate drivers to the plurality of pixels, the interconnects in the general portion being formed by a single line, the interconnects in the deformable portion being formed by multiple lines, and the deformable portion including a plurality of dummy gate drivers. Therefore, space wastage in the bezel with interconnects can be reduced, thereby reducing the size of the non-display area in the display panel.

[0019] Details of other implementation methods are included in the detailed description and accompanying drawings.

[0020] According to one or more embodiments of the present invention, at least one virtual block can be provided between gate blocks, thereby enabling a multi-level arrangement of interconnects and thus reducing the size of the non-display area.

[0021] According to one or more embodiments of the present invention, there may be gate blocks from the first gate block to the (m)th gate block, the number of pixels connected to the first gate block may be greater than the number of pixels connected to the (m)th gate block, and virtual blocks may be arranged adjacent to the first gate block, thereby realizing a multi-level arrangement of interconnections and thus reducing the size of the non-display area.

[0022] According to one or more embodiments of the present invention, each of the lines may include a first line, a second line and a third line, the second lines may connect the first line and the third line to each other, and the number of second lines "m" may be parallel to each other, thereby realizing a multi-level arrangement of the lines and thus reducing the size of the non-display area.

[0023] According to one or more embodiments of the present invention, the angle between the gate line and the virtual line obtained by connecting the centers of the second connection, or the angle between the first connection and the virtual line obtained by connecting the centers of the second connection, can be an acute angle, thereby enabling a multi-level arrangement of the connections and thus reducing the size of the non-display area.

[0024] According to one or more embodiments of the present invention, the angle between the first interconnect and the gate line can be an obtuse angle, thereby enabling a multi-level arrangement of interconnects and thus reducing the size of the non-display area.

[0025] According to one or more embodiments of the present invention, the first and second connecting lines may be perpendicular to each other, and the second and third connecting lines may be perpendicular to each other, thereby enabling a multi-level arrangement of the connecting lines and thus reducing the size of the non-display area.

[0026] According to one or more embodiments of the present invention, the angle between the second connection and the first connection or the angle between the second connection and the gate line can be a right angle or an obtuse angle, thereby enabling a multi-level arrangement of the connections and thus reducing the size of the non-display area.

[0027] According to one or more embodiments of the present invention, the third connection may be parallel to the first connection or the gate line, and the third connection may be perpendicular to the gate block, thereby enabling a multi-level arrangement of the connections and thus reducing the size of the non-display area.

[0028] The above-described objects, means, and effects of the present invention do not specify the features of the claims, and the scope of the claims is not limited to the specific description of the present invention. Attached Figure Description

[0029] The above and other objects, features and advantages of the invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0030] Figure 1 A display panel according to one embodiment of the present invention is illustrated;

[0031] Figure 2 The diagram illustrates the structure of the gate stage included in a gate driver;

[0032] Figure 3 and Figure 4 The diagram illustrates various connection methods between the gate driver and the gate line;

[0033] Figure 5 and Figure 6 The diagram illustrates various implementations of a display panel including curves;

[0034] Figure 7 It is a diagram Figure 5 or Figure 6 An enlarged view of the curved portion of the display panel in the first embodiment;

[0035] Figure 8 The diagram illustrates the situation where the curved section is located in the lower part of the display panel;

[0036] Figure 9 It is a diagram Figure 5 or Figure 6 An enlarged view of the curved portion of the display panel in the second embodiment;

[0037] Figure 10 It is a diagram Figure 5 or Figure 6 An enlarged view of the curved portion of the display panel in the third embodiment;

[0038] Figure 11 It is a diagram Figure 5 or Figure 6 An enlarged view of the curved portion of the display panel in the fourth embodiment. Detailed Implementation

[0039] The advantages and features of the invention, and its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0040] The shapes, dimensions, proportions, angles, and quantities disclosed in the accompanying drawings for the purpose of describing embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. Similar reference numerals denote similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0041] In the context of the use of the terms "including", "having", and "comprising" in this application, additional parts may be added unless "only" is used.

[0042] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0043] When describing positional relationships, such as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0044] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “exactly” or “directly” is used.

[0045] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish elements from one another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0046] It should be understood that the term "at least one" includes all combinations relating to any one item. For example, "at least one of the first element, the second element, and the third element" can include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0047] As will be fully understood by those skilled in the art, the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The embodiments of the present invention can be implemented independently of each other or jointly in an interdependent relationship.

[0048] The following description, with reference to the accompanying drawings, details the interconnection structure according to an embodiment of the present invention and the display panel using the interconnection structure. In the following description, the display panel may be implemented as a liquid crystal display panel, a field emission display panel, an organic light-emitting diode display panel, a quantum dot display panel, or the like.

[0049] Figure 1 The illustration shows a display panel according to one embodiment of the present invention.

[0050] Reference Figure 1The display panel 100 can be divided into a pixel region 120 and other regions besides the pixel region 120. The pixel region 120 is configured to include a pixel array with pixel rows and is used to display images; the pixel region 120 may be referred to as the display region. In the display panel 100, the other regions besides the pixel region 120 may correspond to non-display regions, where gate drivers 110 for applying signals to pixels, various lines, and pads are arranged. Figure 1 In this configuration, the data driver 200 is located outside the display panel 100; however, the location of the data driver 200 is not limited to this.

[0051] The data driver 200 outputs a data signal in response to a data timing control signal provided by a timing controller. The data driver 200 samples and latches the digital data signal provided by the timing controller, and then converts the digital data signal into an analog data signal based on a gamma reference voltage. The output data signal is provided to the data lines in the pixel region 120 via data connection 211. For example, the data driver 200 may be formed on the display panel 100 as an integrated circuit (IC) type or a chip-on-glass (COG) type, or it may be formed in the display panel 100 as a chip-on-film (COF) type. Furthermore, depending on the product, the timing controller may be integrated or combined with the data driver 200, thus implementing it as a single chip.

[0052] The gate driver 110 outputs a gate signal in response to a gate timing control signal provided from a timing controller. For example, the gate timing control signal includes a gate clock signal (GCLK1_L, GCLK2_L, GCLK1_R, GCLK2_R), a start signal, etc. The gate driver 110 provides the gate signal to the gate line in the pixel region 120 via gate interconnect 111. The gate driver 110 may be formed as an integrated circuit (IC). However, in this invention, the gate driver 110 is formed as a gate-in-panel (GIP) type, which is built into or disposed in the display panel 100. The gate driver 110 may be arranged in the left and right regions of the display panel 100, or in either the left or right region of the display panel 100. For example, the gate driver 110 may include a first gate driver 110a (or left gate driver) arranged in the left region of the display panel 100, and a second gate driver 110b (or right gate driver) arranged in the right region of the display panel 100.

[0053] As described above, the display panel 100 displays an image based on the gate signal provided from the gate driver 110, the data signal provided from the data driver 200, and the power supply voltage provided from the power supply section.

[0054] Figure 2The diagram illustrates the structure of the gate stage included in a gate driver.

[0055] Reference Figure 1 and Figure 2 The gate driver 110 includes a shift register. The shift register includes, for example, Figure 2 The diagram shows gate stages G(k-1), G(k), and G(k+1) connected in a slave configuration. Gate stages G(k-1), G(k), and G(k+1) begin outputting gate signals in response to a start signal Vst, and shift their outputs according to gate clock signals GCLK1 and GCLK2. Gate stages G(k-1), G(k), and G(k+1) are connected to gate lines. The output signals GVout(k-1), GVout(k), and GVout(k+1) of gate stages G(k-1), G(k), and G(k+1) are gate signals and are provided to gate lines GL1 to GLn of pixel region 120. The output signal of each of gate stages G(k-1), G(k), and G(k+1) can be provided as a start signal to a subsequent gate stage; furthermore, the output signal of each of gate stages G(k-1), G(k), and G(k+1) can be provided as a reset signal to a previous gate stage. In addition to the gate signal, the gate stages G(k-1), G(k), and G(k+1) also output additional carry signals and provide the carry signal used as the start signal to another stage. In this case, "k" is an integer satisfying 2 ≤ k < (n-1). Figure 2 The (k-1)th gate level G(k-1), the (k)th gate level G(k), and the (k+1)th gate level G(k+1) are shown.

[0056] The connection lines between gate stages G(k-1), G(k), and G(k+1) transmit the start signal Vst, gate clock signals GCLK1 and GCLK2, and drive voltages as carry and reset signals. The drive voltages include the high and low voltages of the gate signals. The input carry signal serves as the start signal in the subsequent gate stage, and the reset signal discharges at the output of the previous gate stage.

[0057] Gate driver 110 may include a scan driver and a light-emitting driver. The scan driver provides a scan signal to the gate line, and the light-emitting driver provides a light-emitting signal (or light-emitting control signal) to the gate line. The gate line may include a scan line to which a scan signal is provided and a light-emitting line to which a light-emitting signal is provided. Each of the scan driver and the light-emitting driver can be configured as follows: Figure 2 The gate stage structure described herein is implemented. Furthermore, depending on the type of pixel driving circuitry included in the pixel, the gate driver 110 may include a reference voltage driver. The reference voltage driver provides a reference voltage to a reference voltage line.

[0058] Figure 3 and Figure 4 The diagram illustrates various connection methods between the gate driver and the gate line.

[0059] Reference Figure 3 The gate driver includes a first gate driver 330a disposed on one edge region (or left side) of the display panel 100 and a second gate driver 330b disposed on another edge region (or right side) of the display panel 100. Each of the first gate driver 330a and the second gate driver 330b is connected to gate lines GL1 to GLn, which are connected to all pixel rows disposed in the display area 120. A single gate line can be connected to at least two pixel rows.

[0060] The first gate driver 330a and the second gate driver 330b simultaneously receive the start signal Vst and simultaneously output gate signals. Therefore, the gate signals output from the first gate driver 330a and the second gate driver 330b are simultaneously applied to both ends of the gate line. For example, when the pixels of pixel region 120 are equally divided into two regions, that is, divided into two regions corresponding to the left and right regions, the first gate driver 330a applies a gate signal to the pixel arranged in the left region, and the second gate driver 330b applies a gate signal to the pixel arranged in the right region. Therefore, pixels can be driven by rapidly applying gate signals to the pixels in the high-resolution display panel.

[0061] Reference Figure 4 The first gate driver 440a is connected to the gate lines included in the first group and sequentially provides gate signals to the gate lines of the first group. The second gate driver 440b is connected to the gate lines included in the second group and sequentially provides gate signals to the gate lines of the second group.

[0062] The first group of gate lines can be odd-numbered gate lines GL1, GL3, ..., GLn-1. The second group of gate lines can be even-numbered gate lines GL2, GL4, ..., GLn. In this case, the start signal Vst can be applied to each of the first gate driver 440a and the second gate driver 440b with a time difference. Therefore, a time difference can exist between the output timing of the gate signal and the carry signal of the first gate driver 440a and the output timing of the gate signal and the carry signal of the second gate driver 440b. For example, after the first gate signal is applied from the first gate driver 440a to the first gate line GL1, the second gate signal can be provided from the second gate driver 440b to the second gate line GL2 after approximately one horizontal cycle. This design structure, in which the first gate driver 440a and the second gate driver 440b are respectively arranged in the left and right regions of the display panel, ensures available space during arrangement, allowing the layout of the gate drivers to be changed in various ways.

[0063] Figure 5 and Figure 6 The diagram illustrates various implementations of a display panel that includes curves.

[0064] Reference Figure 5 and Figure 6 Display panels 500 and 600, including curved sections, can be referred to as deformable display panels or non-rectangular display panels. Deformable display panels can be manufactured with curves having a predetermined curvature in at least a portion of their area. Display panels 500 and 600 can be divided into deformable portions (or non-rectangular portions) with curved sections and general portions without curves. Figure 5 In this case, a display panel 500 with only a deformable portion is shown, the deformable portion being displayed as a semi-circular shape, but it can be applied to a circular display panel. Figure 6 In this case, a display panel 600 with deformable portions and general portions is displayed, wherein the deformable portions are formed in the upper left portion (or upper left corner portion) and the upper right portion (or upper right corner portion) of the display panel 600, however, the deformable portions can be applied to the lower left portion (or lower left corner portion) and the lower right portion (or lower right corner portion) of the display panel 600.

[0065] Reference Figure 5The display panel 500 is divided into a pixel area 520, which is provided with pixels and gate lines GL1, ..., GLn, and a non-display area, which is provided with gate drivers 510a and 510b and other lines. The non-display area corresponds to the areas other than the pixel area 520. In the non-display area, the gate levels G(1), ..., G(k), ..., G(n) of the gate drivers 510a and 510b are arranged along the curve of the display panel 500. The gate levels G(1), ..., G(k), ..., G(n) are arranged radially at fixed intervals on a line extending from the center C of the circle. The center of the minor axis of the gate levels G(1), ..., G(k), ..., G(n) intersects the line extending from the center C of the circle. At this time, the first gate level G(1) and the nth gate level G(n) are located on the extension line obtained by connecting one end of the first gate line GL1 to the center C of the circle, and the extension line obtained by connecting one end of the nth gate line GLn to the center C of the circle, respectively. In this case, the connecting lines obtained by connecting the centers of the short axis lengths of the gate classes G(1), ..., G(k), ..., G(n) can have a concentric circle shape relative to the center C of the circle.

[0066] Reference Figure 6 The display panel 600 is divided into a pixel area 620, which is provided with pixels and gate lines GL1, ..., GLn, and other areas other than the pixel area 620, which are provided with gate drivers 610a and 610b and other lines. Furthermore, the display panel 600 includes a modified portion and a general portion.

[0067] In the modified section, gate lines from the first gate line GL1 to the (k)th gate line GLk are provided, and the gate classes G(1), ..., G(j), ..., G(k) of the gate drivers 610a and 610b are arranged along the curve of the display panel 600 in the non-display area excluding the pixel area 620. The gate classes G(1), ..., G(j), ..., G(k) are arranged radially at fixed intervals on a line extending from the center C of the circle. The center of the minor axis of the gate classes G(1), ..., G(j), ..., G(k) intersects the line extending from the center C of the circle. At this time, the first gate class G(1) and the (k)th gate class G(k) are located on the extension line obtained by connecting one end of the first gate line GL1 to the center C of the circle, and on the extension line obtained by connecting one end of the (k)th gate line GLk to the center C of the circle, respectively. In this case, the connecting lines obtained by connecting the centers of the short axis lengths of the gate classes G(1), ..., G(j), ..., G(k) can have a concentric circle shape relative to the center C of the circle.

[0068] In the general section, gate lines are provided from the (k+1)th gate line GL1 to the (n)th gate line GLn, and the gate levels G(k+1), ..., G(n) of the gate drivers 610a and 610b are arranged along a straight line of the display panel in the non-display area. The gate levels G(k+1), ..., G(n) are arranged on the extension lines of the gate lines GLk+1, ..., GLn. The connections in the general section can be formed by a single line.

[0069] Figure 7 It is a diagram Figure 5 or Figure 6 An enlarged view of the curved portion of the display panel in the first embodiment.

[0070] Figure 7 The image shows a distorted portion of the curve in the upper left part of the display panel. The display panel is divided into a display area DA and a non-display area NDA surrounding the display area DA. The non-display area NDA is divided into a circuit area CA and a bezel BZ. The circuit area CA has a gate driver configured to apply a signal to the gate line of the display area DA, and the bezel BZ has wiring configured to connect the gate driver and the gate line to each other.

[0071] Multiple pixels in the display area DA form multiple pixel rows. As the display moves from the bottom to the top of the display panel, the number of pixels arranged in each of the multiple pixel rows gradually decreases.

[0072] Reference Figure 7The modified portion includes "m" pixel rows, and multiple pixels are arranged in each of the "m" pixel rows. Since the length of the display area DA in which "1P1" is arranged is greater than the length of the display area DA in which "1Pm" is arranged, the number of pixels arranged in "1P1" is greater than the number of pixels arranged in "1Pm". In this case, "1Pm" can be a group of gate lines connected to the pixels included in one pixel row, or it can be a group of gate lines connected to two pixel rows. If needed, "1Pm" can be a group of gate lines connected to the pixels included in three or more pixel rows. Hereinafter, "1Pm" is referred to as the (m)th gate line group. Therefore, the modified portion includes gate line groups from the (1)th gate line group 1P1 to the (m)th gate line group 1Pm, and there may be fewer than "m" gate line groups above the (m)th gate line group 1Pm. For example, in the case where the deformed portion is divided into two regions, a first region and a second region, the first region includes a group of gate lines from the (1)th gate line group 1P1 to the (m)th gate line group 1Pm, and the second region corresponds to the region above the first region, wherein the second region may include a group of gate lines from the (1)th gate line group 2P1 to the (r)th gate line group 2Pr of the second region. In this case, "m>r" is satisfied, and each of "m" and "r" is an integer. This case shows that the deformed portion is divided into two regions. However, the deformed portion may be divided into three or more regions.

[0073] A gate driver that provides a signal to a group of gate lines can be defined as a gate block. A gate block comprises multiple gate stages, and multiple gate blocks constitute a gate driver. (As mentioned above...) Figure 5 and Figure 6 As described above, the aforementioned gate levels G(1), G(j), G(k), and G(n) can be implemented in the form of gate blocks.

[0074] As described above, the gate lines connected to the pixels included in a pixel row can include scan lines, light-emitting lines, and reference voltage lines. For example, a group of gate lines connected to the pixels included in a pixel row can include five lines: a first scan line, a second scan line, a light-emitting line, a reference voltage line, and an initial voltage line. When the (m)th gate line group 1Pm corresponds to a group of gate lines connected to the pixels included in two pixel rows, the (m)th gate line group 1Pm can include ten gate lines. In other words, the number of gate lines included in a gate line group and the number of connections used to connect the gate block to the gate line group can be multiples of "m". In this case, the pixel driving circuit used to provide signals to the pixel can be an internal compensation circuit, such as "7T1C" or "8T1C". In "7T1C" or "8T1C", "T" represents a thin-film transistor and "C" represents a capacitor.

[0075] The circuit region CA corresponds to the area where the gate driver, used to provide gate signals to the pixel, is located. As described above, multiple gate stages are arranged along the curve. Figure 7 In this context, a gate block is represented as a gate block and connected to a gate line group. Since a gate signal is output to a gate level, a gate block comprises multiple gate levels. Each of the gate blocks 1GB(1), 1GB(2), ..., 1GB(m) is connected to each of the gate line groups 1P1, 1P2, ..., 1Pm, and each of the gate blocks 1GB(1), 1GB(2), ..., 1GB(m) provides a gate signal to the pixel connected to the gate line group (1P1, 1P2, ..., 1Pm). For example, when the gate line group is a group of gate lines connected to pixels included in two pixel rows, a gate block can provide a gate signal to the gate line connected to the pixel included in two pixel rows.

[0076] The frame BZ corresponds to the area between the display area DA and the circuit area CA, wherein the wiring for connecting the gate block and the gate line group is disposed in the frame BZ. The wiring (or "m"-numbered" wiring) may be formed by extensions of the gate lines, and each wiring (or "m"-numbered) may include a first wiring, a second wiring, and a third wiring. The first wiring LL1 for connecting the first (1) gate line group 1P1 and the first (1) gate block 1GB(1) to each other may include a first wiring LL1a (or a first sub-wiring), a second wiring LL1b (or a second sub-wiring), and a third wiring LL1c (or a third sub-wiring), and the first wiring LLm for connecting the (m) gate line group 1Pm and the (m) gate block 1GB(m) to each other may include a first wiring LLma (or a first sub-wiring), a second wiring LLmb (or a second sub-wiring), and a third wiring LLmc (or a third sub-wiring).

[0077] The (0) gate line group P0, located below the (1) gate line group 1P1, is included in the general portion of the display panel, and the connection line to the (0) gate block GB (0) is formed by a straight line. In this case, the gate line group above the (0) gate line group P0 is included in a deformed portion, and is thus referred to as the (1) gate line group 1P1. The (0) gate line group P0 is connected to a connection line formed by extensions of the gate lines and is formed by a straight line without any bends. The (1) gate line group 1P1 is not connected to the gate block adjacent to the (0) gate block GB (0), but is connected to the (1) gate block GB (1) corresponding to the next gate block. Therefore, there is a virtual gate block DGB, which is arranged between the (0) gate block GB (0) and the (1) gate block 1GB (1) and is not connected to the gate line group. The virtual gate block DGB may be referred to as a virtual block or a virtual gate driver, but the terminology is not limited thereto. Therefore, since the virtual gate block DGB causes the first gate block 1GB(1) to be not located on the extension line of the first gate line group 1P1, the first connection LL1 used to connect the first gate line group 1P1 and the first gate block 1GB(1) to each other can be designed to include a bend (or a bend). In the case where the connections LL1, ..., LLm included in the deformed portion form a straight line shape without any bends, the connections are concentrated in the area adjacent to the display area DA, thereby short circuits can occur between each connection in the area adjacent to the display area DA depending on the resolution of the display panel and the spacing between each connection. Since the connections LL1, ..., LLm included in the deformed portion include bends, short circuits between each connection can be prevented and the size (or width) of the bezel BZ can be reduced.

[0078] Each of the lines LL1, ..., LLm includes a first line (LL1a, ..., LLma), a second line (LL1b, ..., LLmb), and a third line (LL1c, ..., LLmc). The first line (LL1a, ..., LLma) connects the gate line group (1P1, ..., 1Pm) to the second line (LL1b, ..., LLmb), the second line (LL1b, ..., LLmb) connects the first line (LL1a, ..., LLma) to the third line (LL1c, ..., LLmc), and the third line (LL1c, ..., LLmc) connects the second line (LL1b, ..., LLmb) to the gate block (1GB(1), ..., 1GB(m)). The third line may be located on a virtual line obtained by connecting the gate block to the center of the curved boundary of the non-display area. The first line (LL1a, ..., LLma) and the second line (LL1b, ..., LLmb) are perpendicular to each other, and the second line (LL1b, ..., LLmb) and the third line (LL1c, ..., LLmc) are also perpendicular to each other. The first line (LL1a, ..., LLma) are parallel to each other, the second line (LL1b, ..., LLmb) are parallel to each other, and the third line (LL1c, ..., LLmc) are parallel to each other. In this case, the virtual line VLLb obtained by connecting the centers of the second lines (LL1b, ..., LLmb) is formed in a direction in which the size of the border BZ does not increase. Specifically, the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second lines (LL1b, ..., LLmb) is an acute angle. In this scenario, assuming the intersection of the first line (LL1a, ..., LLma) and the second line (LL1b, ..., LLmb) is called the first bend point, and the intersection of the second line (LL1b, ..., LLmb) and the third line (LL1c, ..., LLmc) is called the second bend point, the virtual line obtained by connecting the first bend point or the second bend point is formed in a direction in which the size of the border BZ does not increase, and the angle between the gate line and the virtual line obtained by connecting the first bend point or the second bend point is an acute angle. Since a virtual gate block DGB is provided between the (0) gate block GB (0) and the (1) gate block 1GB (1), the virtual line VLLb obtained by connecting the centers of the second lines (LL1b, ..., LLmb) can be formed in a direction in which the size of the border BZ does not increase.In the case where the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second connecting lines (LL1b, ..., LLmb) corresponds to an obtuse angle, the virtual line obtained by connecting the centers of the second connecting lines (LL1b, ..., LLmb) is formed in the direction in which the size of the bezel BZ increases, thereby virtually increasing the size of the bezel BZ. Therefore, since the virtual gate block DGB is located on the boundary between the deformed portion and the general portion of the display panel, the connecting lines included in the deformed portion are configured to include bending points, thereby turning the angle between the gate line and the virtual line obtained by connecting the centers of the second connecting lines (LL1b, ..., LLmb) into an acute angle, thereby reducing the size of the bezel BZ.

[0079] The length of the second connection (LL1b, ..., LLmb) used to connect the (m)th gate block 1GB(m) to the last gate line (or the uppermost gate line) of the (m)th gate line group 1Pm is shortened to 0 or close to 0. In this case, the (1)th gate line group 2P1 located above the (m)th gate line group 1Pm and included in the second region is not connected to the gate block adjacent to the (m)th gate block 1GB(m), but is connected to the (1)th gate block 2GB(1) corresponding to the next gate block. Thus, the dummy gate block DGB, which is not connected to the gate line group, is located between the (m)th gate block 1GB(m) of the first region and the (1)th gate block 2GB(1) of the second region. Due to the dummy gate block DGB, the (1)th gate block 2GB(1) is not located on the extension line of the (1)th gate line group 2P1 of the second region, so that the connection used to connect the (1)th gate line group 2P1 of the second region to the (1)th gate block 2GB(1) can be designed to include a bend. Similarly, the connection used to connect the gate block to the gate line group located above the first (1) gate line group 2P1 in the second region is configured to include a second connection, and the angle between the gate line and the virtual line obtained by connecting the centers of the second connection is configured as an acute angle, so that the size of the bezel BZ can be reduced. In this case, the angle between the gate line and the virtual line obtained by connecting the centers of the second connection in the second region may be different from the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second connection in the first region. According to one embodiment of the invention, the angle between the gate line and the virtual line obtained by connecting the centers of the second connection in the second region is smaller than the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second connection in the first region. Therefore, the angle between the gate line and the virtual line obtained by connecting the centers of the second connection is configured as an acute angle, so that the size of the non-display area NDA of the display panel can be reduced.

[0080] Figure 8 Diagram Figure 7The curved portion is located in the lower part of the display panel. Therefore, it will be briefly shown or omitted. Figure 7 Repeated descriptions of the same parts.

[0081] Figure 8 The image shows a distorted portion of the curve in the lower right part of the display panel. The display panel is divided into a display area DA with pixels and a non-display area NDA surrounding the display area DA. The non-display area NDA is divided into a circuit area CA and a bezel BZ. The circuit area CA has a gate driver configured to apply signals to the gate lines of the display area DA, and the bezel BZ has wiring configured to connect the gate driver and the gate lines to each other.

[0082] exist Figure 7 and Figure 8 In the diagram, the curves representing each of the display area DA, the border BZ, and the circuit area CA are shown as curves with the same curvature relative to the center C of the circle. However, the curvature of the curve defining the display area DA may differ from the curvature of the curves defining the border BZ and the circuit area CA, thus the size of the border BZ formed in the deformed portion may not be constant. Furthermore, due to... Figure 7 The curvature of the curve in the circuit region CA is shown. Figure 8 The curves showing the circuit region CA have different curvatures, therefore Figure 8 This explains the case where "i" pixel rows are set in the deformable portion of the display panel. In this case, each of "i" and "m" is an integer, where "i" is different from "m", and each of "i" and "m" is less than "n".

[0083] As it moves toward the lower part of the display panel, the number of pixels arranged in each of the multiple pixel rows in the deformed portion gradually decreases. The deformed portion includes "i" pixel rows, and multiple pixels are arranged in the "i" pixel rows. Since the length of the display area DA of the first (1) gate line group 1P1 where the first region is arranged is greater than the length of the display area DA of the (i) gate line group 1Pi, the number of pixels arranged in the first (1) gate line group 1P1 is greater than the number of pixels arranged in the (i) gate line group 1Pi. Figure 8 The modified portion includes gate line groups from the first gate line group 1P1 to the first gate line group 1Pi, and may include a number of gate line groups smaller than the number of the first gate line group 1P1 to the first gate line group 1Pi in the second region below the first gate line group 1Pi.

[0084] The circuit region CA corresponds to the region where the gate driver, used to provide gate signals to the pixel, is located. As described above, multiple gate stages are arranged along the curve. Figure 7 In the same way, Figure 8In this case, it manifests as a gate block and is connected to a gate line group. Since each of the gate blocks (1GB(1), 1GB(2), ..., 1GB(i)) is connected to each of the gate line groups (1P1, 1P2, ..., 1Pi), each of the gate blocks (1GB(1), 1GB(2), ..., 1GB(i)) provides a gate signal to the pixel connected to the gate line group (1P1, 1P2, ..., 1Pi).

[0085] The frame BZ corresponds to the area between the display area DA and the circuit area CA, wherein the wiring for connecting the gate block and the gate line group is disposed in the frame BZ. The wiring may be formed by extensions of the gate lines, and each wiring may include a first wiring, a second wiring, and a third wiring. The first wiring LL1 for connecting the first (1) gate line group 1P1 and the first (1) gate block 1GB(1) to each other may include a first wiring LL1a (or a first sub-wiring), a second wiring LL1b (or a second sub-wiring), and a third wiring LL1c (or a third sub-wiring). The first wiring LLi for connecting the first (i) gate line group 1Pi and the first (i) gate block 1GB(i) to each other includes a first wiring (LLia) (or a first sub-wiring), a second wiring (LLib) (or a second sub-wiring), and a third wiring (LLic) (or a third sub-wiring).

[0086] The (0) gate line group P0, located above the (1) gate line group 1P1, is included in the general portion of the display panel, and the connection line to the (0) gate block GB (0) is formed by a straight line. In this case, the gate line group located below the (0) gate line group P0 is included in a deformed portion, and the (0) gate line group P0 is connected to a connection line formed by extensions of the gate lines and formed by a straight line without any bends. The (1) gate line group 1P1 is not connected to the gate block adjacent to the (0) gate block GB (0), but is connected to the (1) gate block GB (1) corresponding to the next gate block. Therefore, there is a virtual gate block DGB, which is arranged between the (0) gate block GB (0) and the (1) gate block 1GB (1) and is not connected to the gate line group. Therefore, since the virtual gate block DGB causes the first gate block 1GB(1) to be not located on the extension line of the first gate line group 1P1, the first connection LL1 used to connect the first gate line group 1P1 and the first gate block 1GB(1) to each other can be designed to include a bend.

[0087] Each of the interconnects (LL1, ..., LLi) includes a first interconnect (LL1a, ..., LLia), a second interconnect (LL1b, ..., LLib), and a third interconnect (LL1c, ..., LLic). The first interconnect (LL1a, ..., LLia) connects the gate line group (1P1, ..., 1Pi) to the second interconnect (LL1b, ..., LLib), the second interconnect (LL1b, ..., LLib) connects the first interconnect (LL1a, ..., LLia) to the third interconnect (LL1c, ..., LLic), and the third interconnect (LL1c, ..., LLic) connects the second interconnect (LL1b, ..., LLib) to the gate block (1GB(1), ..., 1GB(i)). The first line (LL1a, ..., LLia) and the second line (LL1b, ..., LLib) are perpendicular to each other, and the second line (LL1b, ..., LLib) and the third line (LL1c, ..., LLic) are also perpendicular to each other. The first line (LL1a, ..., LLia) are parallel to each other, the second line (LL1b, ..., LLib) are parallel to each other, and the third line (LL1c, ..., LLic) are parallel to each other. In this case, the virtual line VLLb obtained by connecting the centers of the second lines (LL1b, ..., LLib) is formed in a direction in which the size of the border BZ does not increase. Specifically, the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second lines (LL1b, ..., LLib) becomes an acute angle. Since a virtual gate block DGB is provided between the (0)th gate block GB(0) and the (1)th gate block GB(1), a virtual line VLLb obtained by connecting the centers of the second connecting lines (LL1b, ..., LLib) can be formed in a direction in which the size of the bezel BZ does not increase. If the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second connecting lines (LL1b, ..., LLib) corresponds to an obtuse angle, then the virtual line VLLb obtained by connecting the centers of the second connecting lines (LL1b, ..., LLib) is formed in a direction in which the size of the bezel BZ increases, thereby virtually increasing the size of the bezel BZ. Therefore, since the virtual gate block DGB is located on the boundary between the deformed portion and the general portion of the display panel, the connecting lines included in the deformed portion are configured to include bending points, thereby making the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second connecting lines (LL1b, ..., LLib) an acute angle, thereby reducing the size of the bezel BZ.

[0088] The length of the second connection used to connect the (i)th gate block 1GB(i) to the last gate line (or the lowest gate line) of the (i)th gate line group 1Pi is shortened to 0 or close to 0. In this case, the (1)th gate line group 2P1 located below the (i)th gate line group 1Pi in the first region and included in the second region is not connected to the gate block adjacent to the (i)th gate block 1GB(i), but is connected to the (1)th gate block 2GB(1) corresponding to the next gate block. Thus, the dummy gate block DGB, which is not connected to the gate line group, is arranged between the (i)th gate block 1GB(i) in the first region and the (1)th gate block 2GB(1) in the second region. Due to the dummy gate block DGB, the (1)th gate block 2GB(1) is not located on the extension line of the (1)th gate line group 2P1, so that the connection used to connect the (1)th gate line group 2P1 and the (1)th gate block 2GB(1) in the second region can be designed to include a bent portion. Similarly, the connection used to connect the gate block to the gate line group located below the first (1) gate line group 2P1 in the second region is configured to include a second connection, and the angle between the gate line and the virtual line obtained by connecting the centers of the second connection is configured to be an acute angle, so that the size of the bezel BZ can be reduced. Therefore, the angle between the gate line and the virtual line obtained by connecting the centers of the second connection is configured to be an acute angle, so that the size of the non-display area NDA of the display panel can be reduced.

[0089] Figure 9 It is a diagram Figure 5 or Figure 6 An enlarged view of the curved portion of the display panel in the second embodiment. Apart from the structure of the second connecting line among the connecting lines, Figure 9 The remaining structure is the same as in the first embodiment, therefore it will be briefly shown or omitted. Figure 7 Repeated descriptions of the same parts.

[0090] With Figure 7 In the same way, Figure 9 This shows the distorted portion of the curve in the upper left part of the display panel. The display panel is divided into the display area DA and the non-display area NDA. The non-display area NDA is further divided into the circuit area CA and the bezel BZ.

[0091] exist Figure 9 In the diagram, the curves for each of the display area DA, the border BZ, and the circuit area CA are shown as curves with the same curvature relative to the center C of the circle. However, the curvature of the curve used to define the display area DA may be different from the curvature of the curves used to define each of the border BZ and the circuit area CA.

[0092] The modified portion comprises "m" pixel rows, and multiple pixels are arranged in "m" pixel rows. The number of pixels arranged in the (1) gate line group 1P1 is greater than the number of pixels arranged in the (m) gate line group 1Pm. The modified portion may include gate line groups from the (1) gate line group 1P1 to the (m) gate line group 1Pm in the first region, and gate line groups from the (1) gate line group 2P1 to the (M) gate line group in the second region above the (m) gate line group 1Pm. In this case, "M" is an integer, where "M" is different from "m", and "M" is less than "m".

[0093] The circuit region CA corresponds to the region where the gate driver, used to provide gate signals to the pixel, is located. As described above, multiple gate stages are arranged along the curve. Figure 7 In the same way, Figure 9 In this case, it manifests as a gate block and is connected to a gate line group. Since each of the gate blocks (1GB(1), 1GB(2), ..., 1GB(m)) is connected to each of the gate line groups (1P1, 1P2, ..., 1Pm), each of the gate blocks (1GB(1), 1GB(2), ..., 1GB(m)) provides a gate signal to the pixel connected to the gate line group (1P1, 1P2, ..., 1Pm).

[0094] The frame BZ corresponds to the area between the display area DA and the circuit area CA, wherein the wiring for connecting the gate block and the gate line group is disposed in the frame BZ. The wiring (or the number of wirings "m") may be formed by extensions of the gate lines, and each of the wirings (or the number of wirings "m") may include a first wiring, a second wiring, and a third wiring. The first wiring LL1 for connecting the first (1) gate line group 1P1 and the first (1) gate block 1GB(1) to each other may include a first wiring LL1a (or a first sub-wiring), a second wiring LL1b (or a second sub-wiring), and a third wiring LL1c (or a third sub-wiring), and the first wiring LLm for connecting the (m) gate line group 1Pm and the (m) gate block 1GB(m) to each other may include a first wiring LLma (or a first sub-wiring), a second wiring LLmb (or a second sub-wiring), and a third wiring LLmc (or a third sub-wiring).

[0095] With Figure 7Similarly, the first gate line group 1P1 is not connected to the gate block adjacent to the first gate block GB (0), but is connected to the first gate block 1GB (1) corresponding to the next gate block. Therefore, there is a dummy gate block DGB, which is arranged between the first gate block GB (0) and the first gate block 1GB (1) and is not connected to the gate line group. Therefore, since the first gate block 1GB (1) is not located on the extension line of the first gate line group 1P1 due to the dummy gate block DGB, the first connection LL1 used to connect the first gate line group 1P1 and the first gate block 1GB (1) to each other can be designed to include a bent portion.

[0096] Each of the interconnects (LL1, ..., LLm) includes a first interconnect (LL1a, ..., LLma), a second interconnect (LL1b, ..., LLmb), and a third interconnect (LL1c, ..., LLmc). The first interconnect (LL1a, ..., LLma) connects the gate line group (1P1, ..., 1Pm) to the second interconnect (LL1b, ..., LLmb), the second interconnect (LL1b, ..., LLmb) connects the first interconnect (LL1a, ..., LLma) to the third interconnect (LL1c, ..., LLmc), and the third interconnect (LL1c, ..., LLmc) connects the second interconnect (LL1b, ..., LLmb) to the gate block (1GB(1), ..., 1GB(m)).

[0097] The first connecting lines (LL1a, ..., LLma) and the third connecting lines (LL1c, ..., LLmc) are parallel to the gate lines, and the angle between the gate lines and the second connecting lines (LL1b, ..., LLmb) becomes an obtuse angle. When the angle θb between the gate lines and the second connecting lines (LL1b, ..., LLmb) is an obtuse angle, compared to the case where the gate lines and the second connecting lines (LL1b, ..., LLmb) are at right angles, the spacing between each of the connecting lines (LL1, ..., LLm) is formed in a direction in which the size of the border BZ does not increase. Therefore, the angle θb between the gate lines and the second connecting lines (LL1b, ..., LLmb) is an obtuse angle, which allows for a reduction in the size of the border BZ. The first connecting lines (LL1a, ..., LLma) are parallel to each other, the second connecting lines (LL1b, ..., LLmb) are parallel to each other, and the third connecting lines (LL1c, ..., LLmc) are parallel to each other. In this case, the virtual line VLLb obtained by connecting the centers of the second lines (LL1b, ..., LLmb) is formed in a direction in which the size of the border BZ does not increase. Specifically, the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second lines (LL1b, ..., LLmb) is an acute angle. Since a virtual gate block DGB is provided between the (0) gate block GB (0) and the (1) gate block 1GB (1), the virtual line VLLb obtained by connecting the centers of the second lines (LL1b, ..., LLmb) can be formed in a direction in which the size of the border BZ does not increase. Therefore, since the virtual gate block DGB is located on the boundary between the deformed portion and the general portion of the display panel, the wiring included in the deformed portion is configured to include a curved portion, thereby making the angle between the gate line and the virtual line VLLb obtained by connecting the center of the second wiring (LL1b, ..., LLmb) an acute angle, and the angle between the gate line and the second wiring (LL1b, ..., LLmb) an obtuse angle, thereby reducing the size of the bezel BZ, and thus reducing the size of the non-display area NDA in the display panel.

[0098] With Figure 7Similarly, in the second region, the first gate line group 2P1 located above the first gate line group 1Pm in the first region is not connected to the gate block adjacent to the first gate block 1GB(m), but is connected to the first gate block 2GB(1) in the second region corresponding to the next gate block. Thus, the dummy gate block DGB, which is not connected to the gate line group, is arranged between the first gate block 1GB(m) in the first region and the first gate block 2GB(1) in the second region. Due to the dummy gate block DGB, the first gate block 2GB(1) is not located on the extension line of the first gate line group 2P1 in the second region, so that the connection used to connect the first gate line group 2P1 and the first gate block 2GB(1) in the second region can be designed to include a bent portion. In the same manner, the connection used to connect the gate block to the gate line group located above the first (1) gate line group 2P1 in the second region is configured to include a second connection, the angle between the gate line and the virtual line obtained by connecting the center of the second connection becomes an acute angle, and the angle θb between the gate line and the second connection becomes an obtuse angle, so that the size of the border BZ can be reduced.

[0099] Figure 10 It is a diagram Figure 5 or Figure 6 An enlarged view of the curved portion of the display panel in the third embodiment. Apart from the structure of the third connecting line, Figure 10 The remaining structure is the same as in the first embodiment, therefore it will be briefly shown or omitted. Figure 7 Repeated descriptions of the same parts.

[0100] With Figure 7 In the same way, Figure 10 This shows the distorted portion of the curve in the upper left part of the display panel. The display panel is divided into the display area DA and the non-display area NDA. The non-display area NDA is further divided into the circuit area CA and the bezel BZ.

[0101] exist Figure 10 In the diagram, the curves for each of the display area DA, the border BZ, and the circuit area CA are shown as curves with the same curvature relative to the center C of the circle. However, the curvature of the curve used to define the display area DA may be different from the curvature of the curves used to define each of the border BZ and the circuit area CA.

[0102] The deformed portion includes "m" pixel rows, wherein multiple pixels are arranged in the "m" pixel rows, and the deformed portion includes gate line groups from the (1) gate line group 1P1 to the (m) gate line group 1Pm. The number of pixels arranged in the (1) gate line group 1P1 is greater than the number of pixels arranged in the (m) gate line group 1Pm. The deformed portion may include the gate line groups from the (1) gate line group 1P1 to the (m) gate line group 1Pm in the first region, and the gate line groups from the (1) gate line group 2P1 to the (M) gate line group in the second region above the (m) gate line group 1Pm. In this case, "M" is an integer, wherein "M" is different from "m", and "M" is less than "m".

[0103] The circuit region CA corresponds to the region where the gate driver, used to provide gate signals to the pixel, is located. As described above, multiple gate stages are arranged along the curve. Figure 7 In the same way, Figure 10 In this case, it manifests as a gate block and is connected to a gate line group. The gate block includes multiple gate stages. Since each of the gate blocks (1GB(1), 1GB(2), ..., 1GB(m)) is connected to each of the gate line groups (1P1, 1P2, ..., 1Pm), each of the gate blocks (1GB(1), 1GB(2), ..., 1GB(m)) provides a gate signal to the pixel connected to the gate line group (1P1, 1P2, ..., 1Pm).

[0104] The frame BZ corresponds to the area between the display area DA and the circuit area CA, wherein the wiring for connecting the gate block and the gate line group is disposed in the frame BZ. The wiring (or "m" number of wirings) may be formed by extensions of the gate lines, and each of the wirings (or "m" number of wirings) may include a first wiring, a second wiring, and a third wiring. The first wiring LL1 for connecting the first (1) gate line group 1P1 and the first (1) gate block 1GB(1) to each other may include a first wiring LL1a (or a first sub-wiring), a second wiring LL1b (or a second sub-wiring), and a third wiring LL1c (or a third sub-wiring). The first wiring (LLm) for connecting the (m) gate line group 1Pm and the (m) gate block 1GB(m) to each other includes a first wiring (LLma) (or a first sub-wiring), a second wiring (LLmb) (or a second sub-wiring), and a third wiring (LLmc) (or a third sub-wiring).

[0105] The first gate line group 1P1 is not connected to the gate block adjacent to the first gate block GB (0), but is connected to the first gate block 1GB (1) corresponding to the next gate block. Therefore, there is a dummy gate block DGB, which is arranged between the first gate block GB (0) and the first gate block 1GB (1) and is not connected to the gate line group. Therefore, since the first gate block 1GB (1) is not located on the extension line of the first gate line group 1P1 due to the dummy gate block DGB, the first connection LL1 used to connect the first gate line group 1P1 and the first gate block 1GB (1) to each other can be designed to include a bent portion.

[0106] Each of the interconnects (LL1, ..., LLm) includes a first interconnect (LL1a, ..., LLma), a second interconnect (LL1b, ..., LLmb), and a third interconnect (LL1c, ..., LLmc). The first interconnect (LL1a, ..., LLma) connects the gate line group (1P1, ..., 1Pm) to the second interconnect (LL1b, ..., LLmb), the second interconnect (LL1b, ..., LLmb) connects the first interconnect (LL1a, ..., LLma) to the third interconnect (LL1c, ..., LLmc), and the third interconnect (LL1c, ..., LLmc) connects the second interconnect (LL1b, ..., LLmb) to the gate block (1GB(1), ..., 1GB(m)).

[0107] The first connection (LL1a, ..., LLma) is an extension of the gate line and is parallel to the gate line. The second connection (LL1b, ..., LLmb) is perpendicular to the first connection (LL1a, ..., LLma). The angle θc between the third connection (LL1c, ..., LLmc) and the gate block (1GB(1), ..., 1GB(m)) is a right angle, and the third connection (LL1c, ..., LLmc) is formed on a line obtained by connecting the gate block (1GB(1), ..., 1GB(m)) and the center C of the circle to each other. In this case, since the third connection (LL1c, ..., LLmc) is arranged in a radial shape, the spacing between each connection is set in such a way that the spacing between the (1)th connection LL1 and the (2)th connection LL2 is the same as the spacing between the (m-1)th connection LLm-1 and the (m)th connection LLm. In each of the connections from the first connection LL1 to the (m-4)th connection LLm-4, as the second connection LL1b from the first connection LL1 to the second connection (LLm-4b) of the (m-4)th connection (LLm-4), the length of each of the second connections (LL1b, ..., LLm-4b) gradually decreases. In the third embodiment of the invention, each of the third connections (LL1c, ..., LLmc) of the connections (LL1, ..., LLm) is formed at a predetermined angle θc and is not parallel to the gate line, thereby no second connections (LL1b, ..., LLmb) appear in the connections from the (m-3)th connection (LLm-3) to the (m)th connection (LLm). For example, a second connection appears in each of the connections from the (1) connection LL1 to the (m-4) connection LLm-4, but not in each of the connections from the (m-3) connection LLm-3 to the (m) connection LLm. Therefore, each connection from the (m-3) connection LLm-3 used to connect the (m-3) gate line group 1Pm-3 and the (m-3) gate block 1GB(m-3) to the (m) connection LLm used to connect the (m) gate line group 1Pm and the (m) gate block 1GB(m) to each other is formed with only a first connection (LLm-3a, ..., LLma) and a third connection (LLm-3c, ..., LLmc).

[0108] The virtual line VLLb, obtained by connecting the centers of the respective second lines (LL1b, ..., LLm-4b) in the lines from the (1) connection LL1 to the (m-4) connection LLm-4, is formed in a direction in which the size of the border BZ does not increase. Specifically, the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the respective second lines (LL1b, ..., LLm-4b) in the lines from the (1) connection LL1 to the (m-4) connection LLm-4 becomes an acute angle. Since a virtual gate block DGB is provided between the (0) gate block GB (0) and the (1) gate block 1GB (1), the virtual line obtained by connecting the centers of the second lines (LL1b, ..., LLm-4b) in the lines from the (1) connection LL1 to the (m-4) connection (LLm-4) can be formed in a direction in which the size of the border BZ does not increase. Therefore, since the virtual gate block DGB is located on the boundary between the deformed portion and the general portion of the display panel, the wiring included in the deformed portion is configured to include a curved portion, thereby making the angle between the gate line and the virtual line VLLb obtained by connecting the center of each of the second lines (LL1b, ..., LLm-4b) in the wiring from the first (1) line LL1 to the second (m-4) line (LLm-4) an acute angle, and the angle between the gate block (1GB(1), ..., 1GB(m)) and the third line (LL1c, ..., LLmc) becomes a right angle, thereby reducing the size of the bezel BZ, and thus reducing the size of the non-display area NDA of the display panel.

[0109] With Figure 7 Similarly, in the second region, the first gate line group 2P1 located above the first gate line group 1Pm in the first region is not connected to the gate block adjacent to the first gate block 1GB(m), but is connected to the first gate block 2GB(1) corresponding to the next gate block. Thus, the dummy gate block DGB, which is not connected to the gate line group, is arranged between the first gate block 1GB(m) in the first region and the first gate block 2GB(1) in the second region. Due to the dummy gate block DGB, the first gate block 2GB(1) is not located on the extension line of the first gate line group 2P1 in the second region, so that the connection used to connect the first gate line group 2P1 and the first gate block 2GB(1) can be designed to include a bent portion. In the same manner, the connection used to connect the gate block to the gate line group located above the first (1) gate line group 2P1 in the second region is configured to include a second connection, the angle between the gate line and the virtual line obtained by connecting the center of the second connection becomes an acute angle, and the angle between the gate block and the third connection becomes a right angle, so that the size of the bezel BZ can be reduced.

[0110] Figure 11It is a diagram Figure 5 or Figure 6 An enlarged view of the curved portion of the display panel in the fourth embodiment. Apart from the structure of the second connecting line among the connecting lines, Figure 11 The remaining structure is the same as in the first embodiment, therefore it will be briefly shown or omitted. Figure 7 Repeated descriptions of the same parts.

[0111] With Figure 7 In the same way, Figure 11 This shows the distorted portion of the curve in the upper left part of the display panel. The display panel is divided into the display area DA and the non-display area NDA. The non-display area NDA is further divided into the circuit area CA and the bezel BZ.

[0112] exist Figure 11 In the diagram, the curves for each of the display area DA, the border BZ, and the circuit area CA are shown as curves with the same curvature relative to the center C of the circle. However, the curvature of the curve used to define the display area DA may be different from the curvature of the curves used to define each of the border BZ and the circuit area CA.

[0113] The deformed portion includes "m" pixel rows, wherein multiple pixels are arranged in the "m" pixel rows, and the deformed portion includes gate line groups from the (1) gate line group 1P1 to the (m) gate line group 1Pm. The number of pixels arranged in the (1) gate line group 1P1 is greater than the number of pixels arranged in the (m) gate line group 1Pm. A second region above the (m) gate line group 1Pm of the first region may include a number of gate line groups less than "m".

[0114] The circuit region CA corresponds to the region where the gate driver, used to provide gate signals to the pixel, is located. As described above, multiple gate stages are arranged along the curve. Figure 7 In the same way, Figure 11 In this case, it manifests as a gate block and is connected to a gate line group. The gate block includes multiple gate stages. Since each of the gate blocks (1GB(1), 1GB(2), ..., 1GB(m)) is connected to each of the gate line groups (1P1, 1P2, ..., 1Pm), each of the gate blocks (1GB(1), 1GB(2), ..., 1GB(m)) provides a gate signal to the pixel connected to the gate line group (1P1, 1P2, ..., 1Pm).

[0115] The frame BZ corresponds to the area between the display area DA and the circuit area CA, wherein the wiring for connecting the gate block and the gate line group is disposed in the frame BZ. The wiring (or "m" number of wirings) may be formed by extensions of the gate lines, and each of the wirings (or "m" number of wirings) may include a first wiring, a second wiring, and a third wiring. The first wiring LL1 for connecting the first (1) gate line group 1P1 and the first (1) gate block 1GB(1) to each other may include a first wiring LL1a (or a first sub-wiring), a second wiring LL1b (or a second sub-wiring), and a third wiring LL1c (or a third sub-wiring), and the first wiring LLm for connecting the (m) gate line group 1Pm and the (m) gate block 1GB(m) to each other may include a first wiring LLma (or a first sub-wiring), a second wiring LLmb (or a second sub-wiring), and a third wiring LLmc (or a third sub-wiring).

[0116] The first gate line group 1P1 is not connected to the gate block adjacent to the first gate block GB (0), but is connected to the first gate block 1GB (1) corresponding to the next gate block. Therefore, there is a dummy gate block DGB, which is arranged between the first gate block GB (0) and the first gate block 1GB (1) and is not connected to the gate line group. Therefore, since the first gate block 1GB (1) is not located on the extension line of the first gate line group 1P1 due to the dummy gate block DGB, the first connection LL1 used to connect the first gate line group 1P1 and the first gate block 1GB (1) to each other can be designed to include a bent portion.

[0117] Each of the interconnects (LL1, ..., LLm) includes a first interconnect (LL1a, ..., LLma), a second interconnect (LL1b, ..., LLmb), and a third interconnect (LL1c, ..., LLmc). The first interconnect (LL1a, ..., LLma) connects the gate line group (1P1, ..., 1Pm) to the second interconnect (LL1b, ..., LLmb), the second interconnect (LL1b, ..., LLmb) connects the first interconnect (LL1a, ..., LLma) to the third interconnect (LL1c, ..., LLmc), and the third interconnect (LL1c, ..., LLmc) connects the second interconnect (LL1b, ..., LLmb) to the gate block (1GB(1), ..., 1GB(m)).

[0118] The third connection (LL1c, ..., LLmc) is parallel to the gate line. The second connection (LL1b, ..., LLmb) is perpendicular to the third connection (LL1c, ..., LLmc) and the gate line. The first connection (LL1a, ..., LLma) is formed on a line obtained by connecting one end of the gate line group to the gate block (1GB(1), ..., 1GB(m)). In this case, the angle θa between the gate line and the first connection (LL1a, ..., LLma) becomes an obtuse angle, wherein the angle between the gate line and each of the first connections (LL1a, ..., LLma) changes for each of the first connections (LL1a, ..., LLma). In each of the connections from the first connection LL1 to the first connection LLm, the angle θa between the gate line and the first connection (LL1a, ..., LLma) is set such that the angle gradually increases from the first connection LL1a of the first connection LL1 to the first connection (LL1m) of the first connection (LLm). In this case, the spacing between each of the first connections (LL1a, ..., LLma) is kept constant to at least the same as the spacing between each gate line in the display area DA, without being concentrated at any one point. The virtual line VLLb obtained by connecting the centers of the second connections (LL1b, ..., LLmb) is formed in a direction in which the size of the bezel BZ does not increase. In detail, the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second connections (LL1b, ..., LLmb) becomes an acute angle. Since a virtual gate block DGB is provided between the (0)th gate block GB (0) and the (1)th gate block 1GB (1), the virtual line VLLb obtained by connecting the centers of the second connecting lines (LL1b, ..., LLmb) can be formed in a direction in which the size of the bezel BZ does not increase. Therefore, since the virtual gate block DGB is located on the boundary between the deformed portion and the general portion of the display panel, the connecting lines included in the deformed portion are configured to include curved portions, thereby making the angle between the gate line and the virtual line VLLb obtained by connecting the centers of the second connecting lines (LL1b, ..., LLmb) an acute angle, and the angle between the gate line and the first connecting lines (LL1a, ..., LLma) an obtuse angle, thereby reducing the size of the bezel BZ, and thus reducing the size of the non-display area NDA of the display panel.

[0119] With Figure 7Similarly, the first gate line group 2P1 in the second region, located above the first gate line group 1Pm in the first region, is not connected to the gate block adjacent to the first gate block 1GB(m) in the first region, but is connected to the first gate block 2GB(1) in the second region corresponding to the next gate block. Therefore, a virtual gate block DGB, not connected to the gate line group, is arranged between the first gate block 1GB(m) in the first region and the first gate block 2GB(1) in the second region. Due to the virtual gate block DGB, the first gate block 2GB(1) is not located on the extension line of the first gate line group 2P1 in the second region, allowing the connection used to connect the first gate line group 2P1 to the first gate block 2GB(1) to be designed to include a bent portion. In the same manner, the connection used to connect the gate block to the gate line group located above the first (1) gate line group 2P1 in the second region is configured to include a second connection, the angle between the gate line and the virtual line obtained by connecting the center of the second connection becomes an acute angle, and the angle θa between the gate line and the first connection becomes an obtuse angle, so that the size of the border BZ can be reduced.

[0120] In the second, third, and fourth embodiments of the present invention, the curved portion is formed in the upper left portion of the display panel, but the invention is not limited to these structures. Figure 8 As shown, the curved portion can be applied to all deformed portions of the display panel formed in the lower left, lower right, or upper right portion.

[0121] Furthermore, the various structures of the wiring described in the first to fourth embodiments of the present invention can be referred to as multi-level arrangements to minimize the size of the non-display area.

[0122] According to an embodiment of the present invention, a display panel includes: a display area configured to have a curve and including a pixel array having a plurality of pixel rows; and a non-display area disposed around the periphery of the display area and configured to include a plurality of gate blocks arranged along the curve, wherein a plurality of connecting lines are provided to connect the gate blocks to the pixel rows, the connecting lines are configured in a multi-level arrangement to minimize the size of the non-display area, and at least one virtual block is provided between the gate blocks. Therefore, space wastage in the bezel with connecting lines can be reduced, thereby reducing the size of the non-display area in the display panel.

[0123] According to one or more embodiments of the present invention, there may be gate blocks from the first gate block to the (m)th gate block, the number of pixels connected to the first gate block may be greater than the number of pixels connected to the (m)th gate block, and the virtual block may be arranged adjacent to the first gate block.

[0124] According to one or more embodiments of the present invention, each of the "m" number of connections arranged in the non-display area to achieve a multi-level arrangement may include a first connection, a second connection, and a third connection, the second connections may connect the first connection and the third connection to each other, and the "m" number of second connections may be parallel to each other.

[0125] According to one or more embodiments of the present invention, the number of connections connected to the gate blocks arranged along the curve of the display panel can be a number corresponding to a multiple of "m". Each connection corresponding to a multiple of "m" may include a first connection, a second connection, and a third connection. The first connection may be connected to a gate line, and the second connection may connect the first connection and the third connection to each other. Furthermore, the angle between the gate line and a virtual line obtained by connecting the centers of the second connection, or the angle between the first connection and a virtual line obtained by connecting the centers of the second connection, can be an acute angle.

[0126] According to one or more embodiments of the present invention, the angle between the first connection line and the gate line can be an obtuse angle.

[0127] According to one or more embodiments of the present invention, the first line and the second line may be perpendicular to each other, and the second line and the third line may be perpendicular to each other.

[0128] According to one or more embodiments of the present invention, the angle between the second connection line and the first connection line or the angle between the second connection line and the gate line can be a right angle or an obtuse angle.

[0129] According to one or more embodiments of the present invention, the third connection may be parallel to the first connection or the gate line, and the third connection may be located on a virtual line obtained by connecting the gate block to the center of the curved boundary of the non-display area.

[0130] According to an embodiment of the present invention, a display panel includes a deformable portion divided into at least a first region and a second region. The display panel includes: an "x" number of gate lines arranged in the first region and a "y" number of gate lines arranged in the second region (where "x" > "y", and each of "x" and "y" is an integer); a gate driver configured to transmit gate signals to the gate lines; and interconnects configured to connect the gate driver and the gate lines to each other. The interconnects located in the first region and closest to the second region are straight lines, and dummy gate blocks are disposed in some portions of the second region closest to the first region. Therefore, space wastage in the bezel with interconnects can be reduced, thereby reducing the size of the non-display area in the display panel.

[0131] According to one or more embodiments of the present invention, the gate driver may include a plurality of gate blocks, and the plurality of gate blocks may be arranged in a radial shape in the deformed portion. Furthermore, the gate blocks may provide signals to a plurality of gate lines, and a single gate line may be connected to at least two pixel rows.

[0132] According to one or more embodiments of the present invention, the connecting line may be disposed in a frame, the connecting line may include a first bending point and a second bending point, and the virtual line obtained by connecting the first bending point or the second bending point of the connecting line in the first region and the second region may be formed in a direction in which the size of the frame does not increase. Furthermore, the angle between the virtual line and the gate line may be an acute angle. Additionally, the angle between the gate line and the connecting line configured to connect the first bending point and the second bending point to each other may be a right angle or an obtuse angle.

[0133] According to an embodiment of the present invention, a display panel is divided into a general portion and a deformable portion, wherein the display panel includes: a display area having a plurality of pixels, a circuit area having gate drivers, and a bezel with interconnections, the interconnections being configured to connect the gate drivers to the plurality of pixels. The interconnections in the general portion are formed by a single line, while the interconnections in the deformable portion are formed by multiple lines, and the deformable portion includes a plurality of virtual gate drivers. Therefore, space wastage in the bezel with interconnections can be reduced, thereby reducing the size of the non-display area in the display panel.

[0134] According to one or more embodiments of the present invention, the deformable portion may be disposed in each of the lower end and the upper end of the display panel.

[0135] According to one or more embodiments of the present invention, the display panel may have a circular shape.

[0136] According to one or more embodiments of the present invention, the size of the border provided in the general portion may be constant, while the size of the border provided in the deformed portion may not be constant.

[0137] According to one or more embodiments of the present invention, the curvature of the deformed portion in the circuit region may be different from the curvature of the display region.

[0138] In addition to the effects of the invention as described above, those skilled in the art will clearly understand additional advantages and features of the invention from the above description.

[0139] It will be apparent to those skilled in the art that the present invention is not limited to the described embodiments and drawings, and various substitutions, modifications, and variations can be made in the present invention without departing from its spirit or scope. Therefore, the scope of the present invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of the present invention.

[0140] The above embodiments can be combined to provide further embodiments. Various aspects of the embodiments can be modified to provide further embodiments.

[0141] These and other variations can be made to the embodiments as described in detail above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments covered by these claims and all equivalents. Therefore, the claims are not limited to the specific embodiments.

Claims

1. A display panel comprising a first portion and a second portion, comprising: Display area; A non-display area located on the periphery of the display area, and the non-display area includes: Border; and Circuit area, The border refers to the area between the display area and the circuit area; A plurality of pixel arrays including pixel rows in the display area; A gate driver is disposed in the circuit region, the gate driver comprising a plurality of gate blocks; Multiple gate lines located in the display area, each gate line connected to the pixel row; and Multiple interconnects located only within the frame, each interconnect connected to each gate line, and each interconnect including at least two corresponding bend points. The at least two corresponding bending points are located within the border outside the circuit region. At least one virtual block is provided between the gate blocks. The first part has a rectangular shape, and the second part has a non-rectangular shape. This includes the plurality of connecting lines of the at least two corresponding bending points being arranged in the second part, and the connecting lines arranged in the first part being formed by straight lines.

2. The display panel according to claim 1, wherein the plurality of connecting lines comprises: First sub-connection; Second sub-connection; and Third child connection, The second sub-connection connects the first sub-connection to the third sub-connection.

3. The display panel according to claim 2, wherein at least one of the third sub-connectors has a width smaller than the size of the circuit area.

4. The display panel according to claim 1, wherein the plurality of gate blocks comprises: From the first gate block to the mth gate block, "m" is an integer; and The number of pixels connected to the first gate block is greater than the number of pixels connected to the m-th gate block.

5. The display panel according to claim 1, wherein the plurality of interconnections includes each of the plurality of interconnections in the non-display area, where "m" is an integer.

6. The display panel according to claim 1, wherein the second portion is located in each of the lower end and the upper end of the display area.

7. The display panel according to claim 1, wherein the gate driver includes a first gate driver disposed on a first side of the display panel and a second gate driver disposed on a second side of the display panel, the first side and the second side being opposite to each other.

8. The display panel of claim 7, wherein the first gate driver and the second gate driver are configured to simultaneously receive a start signal and simultaneously output a gate signal to the gate line.

9. The display panel according to claim 7, wherein the pixels of the display area are equally divided into two areas corresponding to the left and right areas. The first gate driver is configured to apply a gate signal to the pixel in the left-hand region, and The second gate driver is configured to apply a gate signal to the pixel in the right region.

10. The display panel of claim 8, wherein the gate lines are divided into a first group and a second group, the first group corresponding to odd-numbered gate lines and the second group corresponding to even-numbered gate lines. The start signal is applied to each of the first gate driver and the second gate driver with a time difference, and A first gate signal is applied from the first gate driver to the first gate line, and a second gate signal is applied from the second gate driver to the second gate line after one horizontal cycle.

11. The display panel of claim 1, wherein each of the gate blocks is configured to output a carry signal to another gate block.

12. The display panel of claim 11, wherein each of the gate blocks outputs the carry signal to at least one of the rear gate block and the front gate block.

13. The display panel of claim 1, wherein the bezel has a different size than the circuit area.

14. The display panel of claim 1, wherein the virtual block is disposed between a first gate block and a 0th gate block among the plurality of gate blocks, the 0th gate block being located in the first portion of the display panel, and the first gate block being located in the second portion of the display panel.

15. The display panel of claim 1, wherein the second portion of the display panel has a curve, and The gate driver located in the second part is arranged along the curve.

16. The display panel of claim 15, wherein the first portion of the display panel has a rectangular shape and the second portion of the display panel has a semi-circular shape, and The gate blocks are arranged radially at fixed intervals on a line extending from the center of the semi-circular shape.

17. The display panel according to claim 1, wherein the number of pixels arranged in each of the plurality of pixel rows in the second portion gradually decreases from the lower part of the display panel toward the upper part of the display panel.

18. The display panel of claim 1, wherein the gate driver includes a scan driver and a light-emitting driver.

19. The display panel of claim 18, wherein the scan driver comprises a first scan driver disposed on a first side of the display panel and a second scan driver disposed on a second side of the display panel, the first side and the second side being opposite to each other, and The light-emitting driver includes a first light-emitting driver disposed on the first side of the display panel and a second light-emitting driver disposed on the second side of the display panel.

20. The display panel of claim 18, wherein the gate lines comprise scan lines and light-emitting lines. The scan driver is configured to provide a scan signal to the scan line, and The light-emitting driver is configured to provide a light-emitting signal to the light-emitting line.

21. The display panel of claim 18, wherein the gate driver further comprises a reference voltage driver. The gate line further includes a reference voltage line, and The reference voltage driver is configured to provide a reference voltage to the reference voltage line.

22. The display panel of claim 1, wherein the gate line connected to the pixel included in a pixel row has a first scan line, a second scan line, a light-emitting line, a reference voltage line, and an initial voltage line.

23. The display panel of claim 1, wherein the second portion comprises "m" pixel rows and gate line groups from a first gate line group corresponding to the first pixel row to a gate line group corresponding to the m pixel row.

24. The display panel according to claim 23, wherein the number of pixels arranged in the first gate line group is greater than the number of pixels arranged in the mth gate line group.

25. The display panel of claim 24, wherein the second portion comprises a first region and a second region, the first region comprising gate line groups from a first gate line group corresponding to a first pixel row to a m gate line group corresponding to an m pixel row, the second region being disposed above the m gate line group in the first region, and The second region includes a number of gate line groups less than "m".

26. The display panel according to claim 1, further comprising: A pixel driving circuit is set in each pixel.

27. The display panel of claim 1, further comprising a timing controller configured to provide a gate clock signal to the gate driver.

28. A display panel comprising a deformable portion and a general portion, comprising: A display area having a plurality of pixel arrays including pixel rows, the display area comprising: The first part corresponding to the general part; and Corresponding to the second part of the deformed portion, the first part has multiple more pixels than the second part; A non-display area located on the periphery of the display area, and the non-display area includes a circuit area and a border, the border corresponding to the area between the display area and the circuit area; A pixel driving circuit is provided in each pixel, and the pixel driving circuit includes an internal compensation circuit. A gate driver is disposed in the circuit region, the gate driver comprising a plurality of gate blocks; Multiple gate lines located in the display area, each gate line connected to the pixel row; and Multiple interconnects located only within the frame, each interconnect connected to each gate line, and each interconnect including at least two corresponding bend points. The at least two corresponding bending points are located within the border outside the circuit region. At least one virtual block is provided between the gate blocks. The first part has a rectangular shape, and the second part has a non-rectangular shape. This includes the plurality of connecting lines of the at least two corresponding bending points being arranged in the second part, and the connecting lines arranged in the first part being formed by straight lines.

Images