Chip detection method, chip and computer readable storage medium
By reserving contact points on each metal layer of the chip and performing segmented detection, combined with the dichotomy method and failure location analysis, the problem of failure level location in the prior art is solved, achieving efficient failure level location and cost control.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU HAIGUANG MICROELECTRONICS TECH CO LTD
- Filing Date
- 2023-05-22
- Publication Date
- 2026-07-03
AI Technical Summary
Existing yield testing methods cannot directly pinpoint the failure level through test results, as they are limited by metal wire layout and testing constraints.
Contact points are reserved on each metal layer of the chip, and segmented detection is performed using DCM metal lines. The anomaly range is narrowed down using a two-part method, and the anomaly is accurately located by combining it with a failure location analysis instrument.
It improves the efficiency of failure level location, reduces computational overhead, lowers chip cost, and reduces the risk of detection interference.
Smart Images
Figure CN116539959B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and more specifically, to a chip testing method, a chip, and a computer-readable storage medium. Background Technology
[0002] Currently, when designing chips, the wafer foundry's design rules are followed, and a metal line (such as...) is designed around the outermost layer of the chip's circuit layout. Figure 1 As shown, this metal wire is called a DCM (Die Crack Monitor) metal wire. This metal wire is connected in series layer by layer on all the metal layers used in the chip circuit (e.g., Figure 2 As shown, it is used to detect extreme situations where the internal circuitry of a chip is accidentally damaged during dicing.
[0003] In practical use, since this metal line is located at the outermost edge of the chip and is not directly connected to the chip's functional circuitry, it is also used for yield testing (testing the resistance of this metal line and determining whether the chip is abnormal based on the resistance value) to evaluate the process performance of the metal (metal layer) and VIA (structure in the chip used to connect different metal layers) at the wafer's limit position.
[0004] However, existing yield testing methods, after detecting abnormal metal wire resistance, are limited by metal wire layout and testing constraints, and cannot directly locate the failure level through test results. Summary of the Invention
[0005] The purpose of this application is to provide a chip detection method, a chip, and a computer-readable storage medium to solve the above-mentioned problems.
[0006] This application provides a chip testing method, including: performing anomaly detection on the chip through DCM metal lines; the DCM metal lines have reserved contact points on each metal layer of the chip; in the event of a chip anomaly, the resistance value of the DCM metal lines is detected segment by segment through the reserved contact points on each metal layer to determine the metal layer where the DCM metal line segment with the abnormal resistance value is located; the metal layer where the DCM metal line segment with the abnormal resistance value is located is the abnormal metal layer.
[0007] In the above implementation process, when a chip abnormality is detected by the DCM metal line, since the DCM metal line has reserved contact points on each metal layer of the chip, the DCM metal line can be segmented and detected through the reserved contact points on each metal layer, thereby detecting the DCM metal line segment with abnormal resistance. Then, the abnormal metal layer can be located according to the metal layer where the DCM metal line segment with abnormal resistance is located, thus realizing the location of the failure level.
[0008] Further, by using the contact points reserved on each of the metal layers, the resistance value of the DCM metal line is detected segment by segment to determine the metal layer where the DCM metal line segment with abnormal resistance is located. This includes: continuously detecting the DCM metal line segment with abnormal resistance using a binary method to determine the metal layer where the DCM metal line segment with abnormal resistance is located; wherein, the binary method includes: selecting a target contact point from the contact points located on the DCM metal line segment to be tested; detecting whether the resistance value of the DCM metal line segment from the starting point of the DCM metal line segment to be tested to the target contact point is abnormal, and detecting whether the resistance value of the DCM metal line segment from the target contact point to the ending point of the DCM metal line segment to be tested is abnormal; the DCM metal line segment to be tested is the DCM metal line segment with abnormal resistance determined; the initial DCM metal line segment to be tested is the entire DCM metal line.
[0009] In the above method, the range of DCM metal segments with abnormal resistance can be continuously narrowed down by using a two-part distribution method, thereby quickly locating the DCM metal segments with abnormal resistance, improving the location efficiency, and reducing computational overhead.
[0010] Furthermore, the resistance of the DCM metal line is detected in segments through the contact points reserved on each of the metal layers, including: dividing the DCM metal line into non-overlapping DCM metal line segments based on the start and end points of the DCM metal line and each of the contact points; and detecting the resistance of each of the DCM metal line segments to be tested.
[0011] In the above method, by dividing the DCM metal line into non-overlapping DCM metal line segments to be tested separately, the DCM metal line segment with abnormal resistance can be quickly located, thus improving the positioning efficiency.
[0012] Furthermore, after determining the metal layer where the DCM metal segment with abnormal resistance is located, the method further includes: performing failure location analysis on the metal layer where the DCM metal segment with abnormal resistance is located using a failure location analysis instrument.
[0013] In the above implementation process, after locating the abnormal metal layer, a failure location analysis instrument is used to analyze the failure location of the abnormal metal layer, which can further clarify the cause of failure, the specific failure location, and other information. Furthermore, compared to performing failure location analysis on the entire chip, this application can perform failure location analysis only on the abnormal metal layer, resulting in higher analysis efficiency.
[0014] Furthermore, the contact points are embedded within the insulating material of the metal layers; before segmentally detecting the resistance of the DCM metal wire through the contact points reserved on each of the metal layers, the method further includes: drawing out the contact points to be used for detection from the insulating material.
[0015] In the above method, by burying the contact points within the insulating material of the metal layer, the risk of the exposed contact points causing interference or other adverse effects on the chip can be avoided.
[0016] Furthermore, the contact point is smaller than the size of the preset contact metal ball in the chip; the contact metal ball is located at the start and end points of the DCM metal line.
[0017] It's understandable that chips typically have pre-installed contact metal balls (commonly called bumps, used for testing). Bumps are usually placed at the start and end points of DCM metal lines for chip testing. In the above method, the contact points are set to be smaller than the size of the bumps in the chip. This is beneficial because, firstly, smaller contact points mean less space is required, resulting in lower chip costs; secondly, smaller contact point sizes facilitate placement within the metal layer, reducing the risk of contact point placement affecting the functionality of the metal layer itself.
[0018] This application also provides a chip, including: a chip body; DCM metal lines surrounding the chip body, wherein the DCM metal lines are connected in series on all metal layers of the chip body, and the DCM metal lines have reserved contact points on each of the metal layers.
[0019] Based on the chip provided in this application embodiment, since the DCM metal lines have reserved contact points on each metal layer, when a chip abnormality is detected through the DCM metal lines, the DCM metal lines can be segmented and detected through the reserved contact points on each metal layer. This allows for the detection of DCM metal line segments with abnormal resistance values. Furthermore, the abnormal metal layer can be located based on the metal layer where the abnormal DCM metal line segment is located, thus achieving the location of the failure level. In other words, the chip provided in this application embodiment has the ability to locate the failure level through detection, overcoming the shortcomings of existing chips.
[0020] Furthermore, the contact point is embedded within the insulating material of the metal layer.
[0021] Furthermore, the contact point is smaller than the size of the preset contact metal ball in the chip; the contact metal ball is located at the start and end points of the DCM metal line.
[0022] This application also provides a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement any of the chip detection methods described above. Attached Figure Description
[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of the winding of DCM metal wire;
[0025] Figure 2 This is a schematic diagram showing the specific winding method of the DCM metal wires around the chip;
[0026] Figure 3 A cross-sectional view of one side of a chip provided in an embodiment of this application;
[0027] Figure 4 Another cross-sectional view of one side of the chip provided in this application embodiment;
[0028] Figure 5 This is a schematic flowchart of a chip detection method provided in an embodiment of this application. Detailed Implementation
[0029] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0030] Example 1:
[0031] To address the problem that existing yield testing methods, after detecting abnormal metal line resistance, cannot directly pinpoint the failure level based on test results due to limitations in metal line layout and testing, this application provides a chip and a corresponding chip testing method.
[0032] The chip provided in this application embodiment includes a chip body and DCM metal lines surrounding the chip body. The DCM metal lines are connected in series on all metal layers of the chip body. The arrangement of the DCM metal lines can be found in [reference needed]. Figure 1 and Figure 2 As shown, it will not be elaborated further here.
[0033] In the embodiments of this application, the chip body refers to a chip crystal with a metal layer and functional circuits. It can be each die on a wafer or all parts of a chip that has been cut and packaged except for the DCM metal lines.
[0034] See Figure 3 As shown, Figure 3 The diagram shows a cross-sectional view of one side of the chip. M1, M2, and M3 in the diagram are metal layers. It is understandable that, although... Figure 3 Only three metal layers are shown in the illustration, but in actual applications, chips can have more or fewer metal layers, and this application does not impose any restrictions on this.
[0035] In the chip provided in this application embodiment, the DCM metal lines have pre-reserved contact points on each metal layer. It can be understood that the contact points can be metal lines with current transmission capabilities.
[0036] In this embodiment, the contact points are laid out facing outwards from the chip to facilitate their extraction during subsequent testing.
[0037] In some feasible implementations of the embodiments of this application, such as Figure 3 As shown, contact points can be reserved on each metal layer to ensure that a specific metal layer can be located. Of course, in other feasible embodiments of this application, contact points can also be reserved on some metal layers. In this way, after detecting a DCM metal line segment with abnormal resistance, the DCM metal line segment may be located on multiple metal layers, and all of these multiple metal layers can be identified as abnormal metal layers.
[0038] In some feasible embodiments of this application, the contact point can be embedded within the insulating material of the metal layer, for example... Figure 3 As shown ( Figure 3 None of the contact points are exposed outside the metal layer, thus avoiding the risk of interference or other adverse effects on the chip caused by exposed contact points. Of course, in some other feasible embodiments of this application, the contact points can also be directly led out of the chip (for example, led out of the top metal layer to form a small bump).
[0039] In some feasible embodiments of this application, the contact point can be implemented using a small-sized metal wire. In this application embodiment, the size of the contact point refers to its diameter or radius, not its length. For example, the contact point can be a metal wire segment with a diameter smaller than the diameter of a preset bump in the chip. It is understood that bumps are typically placed at the start and end points of the DCM metal line for chip detection. A bump is an exposed metal sphere.
[0040] It's also understandable that the placement of contact points should avoid traces and VIAs within the metal layer to prevent interference with the metal layer's functionality. Since the contact points have a smaller diameter, and their placement may involve passing through multiple metal layers, a smaller diameter reduces the likelihood of damaging traces and VIAs within the metal layer. This facilitates placement within the metal layer and lowers the risk of contact point placement affecting the metal layer's functionality. Furthermore, a smaller contact point diameter also means less space is required, resulting in lower chip costs.
[0041] In some feasible embodiments of this application, only one contact point may be provided on a metal layer. In other feasible embodiments of this application, multiple contact points may be provided on a metal layer. This application does not impose any limitations on this aspect.
[0042] In feasible implementations of providing multiple contact points on a metal layer, in addition to... Figure 2 As shown, besides a single series connection on one side of the chip body, multiple series connections can also be used for deployment, for example... Figure 4 As shown. This is understandable. Figure 4 The diagram illustrates a scenario where the chip body is divided into left and right sections on one side, and DCM metal lines are connected in series for each section. In addition, this embodiment may involve three or more series connections, and this application does not impose any limitations on this.
[0043] When multiple contact points are set on a metal layer, after identifying the abnormal metal layer, the location of the abnormal point on the abnormal metal layer can be further narrowed down based on the location of the DCM metal line segment with abnormal resistance. For example, Figure 4 If the resistance of the DCM metal segment between the two contact points A and B on the right side of the M3 metal layer is abnormal, then the M3 metal layer can be determined to be an abnormal metal layer, and the abnormal point should be located in the right region of the M3 metal layer.
[0044] See Figure 5 As shown, Figure 5 The flowchart of the chip detection method provided in the embodiments of this application is shown, including:
[0045] S501: Performs anomaly detection on the chip via DCM metal lines.
[0046] In this embodiment, the end point of the DCM metal line can be grounded, and a test voltage can be injected from the starting point of the DCM metal line to test the resistance value of the DCM metal line using a testing device. If the resistance value is abnormal, the chip is determined to be faulty; if the resistance value is normal, the chip is determined to be normal.
[0047] As can be understood, the start and end points of DCM metal lines are contact metal balls for testing, often referred to as bumps, that are led out from the top layer of metal on the chip.
[0048] S502: In the event of a chip malfunction, the resistance of the DCM metal lines is detected segment by segment through the pre-reserved contact points on each metal layer to determine the metal layer where the DCM metal line segment with the abnormal resistance is located.
[0049] It is understandable that the metal layer containing the DCM metal segment with abnormal resistance is the abnormal metal layer.
[0050] In some feasible embodiments of this application, the bisection method can be used to continuously detect the DCM metal line segments with abnormal resistance values to determine the metal layer where the DCM metal line segments with abnormal resistance values are located.
[0051] The so-called two-way method refers to: selecting a target contact point from the contact points on the DCM metal segment to be tested; and checking whether the resistance of the DCM metal segment from the starting point of the DCM metal segment to the target contact point is abnormal, and whether the resistance of the DCM metal segment from the target contact point to the ending point of the DCM metal segment to be tested is abnormal.
[0052] Among them, the DCM metal line segment to be tested is the DCM metal line segment with the identified abnormal resistance value. The initial DCM metal line segment to be tested is the entire DCM metal line.
[0053] For example, assuming there are 10 contact points, the 5th contact point can be selected as the target contact point. This divides the DCM metal line into two DCM metal line segments: the first DCM metal line segment from the starting point of the DCM metal line to the 5th contact point, and the second DCM metal line segment from the 5th contact point to the end point of the DCM metal line.
[0054] Ground the target contact point, then inject test voltage from the starting point of the DCM metal wire to test the resistance of the first DCM metal wire segment and determine whether the resistance of the first DCM metal wire segment is abnormal.
[0055] Ground the end of the DCM metal wire, apply a test voltage to the target contact point, test the resistance of the second DCM metal wire segment, and determine whether the resistance of the second DCM metal wire segment is abnormal.
[0056] Assuming the first DCM metal segment is faulty while the second DCM metal segment is not faulty, then we continue to select one of the 1st to 4th contact points as the target contact point, for example, selecting the 3rd contact point. Let the DCM metal segment from the starting point of the DCM metal line to the 3rd contact point be the third DCM metal segment, and the DCM metal segment from the 3rd contact point to the 5th contact point be the fourth DCM metal segment.
[0057] Ground the third contact point, then inject test voltage from the starting point of the DCM metal wire to test the resistance of the third DCM metal wire segment and determine whether the resistance of the third DCM metal wire segment is abnormal.
[0058] Ground the fifth contact point, apply a test voltage to the third contact point, test the resistance of the fourth DCM metal segment, and determine whether the resistance of the fourth DCM metal segment is abnormal.
[0059] Assuming the third DCM metal segment is abnormal while the fourth DCM metal segment is not abnormal, then continue selecting one of the first to third contact points as the target contact point, for example, selecting the first contact point. Let the DCM metal segment from the starting point of the DCM metal line to the first contact point be the fifth DCM metal segment, and the DCM metal segment from the first contact point to the third contact point be the sixth DCM metal segment.
[0060] Ground the first contact point, then inject test voltage from the starting point of the DCM metal wire to test the resistance of the fifth DCM metal wire segment and determine whether the resistance of the fifth DCM metal wire segment is abnormal.
[0061] Ground the third contact point, apply a test voltage to the first contact point, test the resistance of the sixth DCM metal segment, and determine whether the resistance of the sixth DCM metal segment is abnormal.
[0062] Assume the fifth DCM metal segment is abnormal, while the sixth DCM metal segment is not abnormal. Since the fifth DCM metal segment no longer contains any contact points other than the first contact point, it's impossible to further divide it into DCM metal segments; therefore, the binary search ends. The metal layer containing the fifth DCM metal segment is determined to be the abnormal metal layer.
[0063] In other feasible embodiments of this application, the DCM metal line can be divided into non-overlapping DCM metal line segments based on the start and end points of the DCM metal line and each contact point, and then the resistance value of each DCM metal line segment can be detected to determine the abnormal metal layer.
[0064] For example, assuming there are 5 contact points, the DCM metal line can be divided into a first DCM metal line segment from the starting point of the DCM metal line to the first contact point, a second DCM metal line segment from the first contact point to the second contact point, a third DCM metal line segment from the second contact point to the third contact point, a fourth DCM metal line segment from the third contact point to the fourth contact point, a fifth DCM metal line segment from the fourth contact point to the fifth contact point, and a sixth DCM metal line segment from the fifth contact point to the end point of the DCM metal line.
[0065] Then, the resistance of each DCM metal segment was tested. The test method was to ground one end of the DCM metal segment and inject the test voltage into the other end.
[0066] If the resistance of the fifth DCM metal segment is found to be abnormal, then the metal layer containing the fifth DCM metal segment can be determined to be an abnormal metal layer.
[0067] It is understood that the above are only two feasible testing methods exemplified in the embodiments of this application. Other methods can also be used for testing, as long as the metal line segment with abnormal resistance can be found. The above methods are not intended to limit the embodiments of this application.
[0068] In some feasible embodiments of this application, after determining the metal layer where the DCM metal segment with abnormal resistance is located, failure location analysis can be performed on the metal layer using a failure location analysis instrument (such as EMMI (Emission Microscope) or OBIRCH (Optical Beam Induced Resistance Change) instrument). Thus, after locating the abnormal metal layer, failure location analysis using a failure location analysis instrument can further clarify the cause of the failure, the specific failure location, and other information. Furthermore, compared to performing failure location analysis on the entire chip, this application can perform failure location analysis only on the abnormal metal layer, resulting in higher analysis efficiency.
[0069] In some feasible embodiments of this application, if the contact point is buried within the insulating material of the metal layer, the contact point to be used for testing needs to be led out from the insulating material before the resistance value of the DCM metal wire is detected in segments through the contact points reserved on each metal layer.
[0070] For example, contact points can be extracted from insulating materials using, but not limited to, FIB (Focused Ion beam, a technique that uses an electric lens to focus an ion beam into a very small ion beam to bombard the surface of a material to achieve circuit trimming, repair or modification) technology.
[0071] Optionally, all contact points can be pre-exposed from the insulation material for use. Alternatively, the target contact points can be pre-exposed from the insulation material after they have been determined.
[0072] The chip and chip detection method provided in this application, when a chip abnormality is detected by the DCM metal line, can be segmented by the DCM metal line through the contact points reserved on each metal layer of the chip, thereby detecting the DCM metal line segment with abnormal resistance. Then, the abnormal metal layer can be located according to the metal layer where the DCM metal line segment with abnormal resistance is located, thus realizing the location of the failure layer.
[0073] It is understood that each step of the chip testing method provided in this application embodiment can be completed manually by engineers using relevant equipment, or it can be fully automated by configuring corresponding mechanized equipment. This application does not impose any restrictions on this.
[0074] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc. This computer-readable storage medium stores one or more programs that implement the various steps of the above-described chip detection method. These one or more programs can be executed by one or more processors or devices to implement the above-described chip detection method. Further details will not be elaborated here.
[0075] The embodiments described above are merely illustrative. The technical features in each embodiment or real-time mode can be freely combined to obtain new embodiments without conflict, and these new embodiments are also within the protection scope of the embodiments of this application.
[0076] In the embodiments provided in this application, it should be understood that the disclosed methods can be implemented in other ways. Furthermore, the interconnections shown or discussed may be via communication interfaces and may be electrical, mechanical, or other forms.
[0077] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.
[0078] In this article, "multiple" refers to two or more.
[0079] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A chip detection method characterized by, include: Anomaly detection of the chip is performed using DCM metal lines; the DCM metal lines have contact points reserved on each metal layer of the chip. The DCM metal line is located at the outermost edge of the chip and is not directly connected to the chip's functional circuitry. In the event of a chip malfunction, the resistance of the DCM metal lines is detected segment by segment through the contact points reserved on each of the metal layers to determine the metal layer where the DCM metal line segment with the abnormal resistance is located; the metal layer where the DCM metal line segment with the abnormal resistance is located is the abnormal metal layer.
2. The chip detection method of claim 1, wherein, By using the contact points reserved on each of the aforementioned metal layers, the resistance of the DCM metal lines is detected segment by segment to determine the metal layer where the DCM metal line segment with abnormal resistance is located, including: The bisection method is continuously used to detect the DCM metal line segments with abnormal resistance values to determine the metal layer where the DCM metal line segments with abnormal resistance values are located. The dichotomy method includes: selecting a target contact point from the contact points located on the DCM metal line segment to be tested; The resistance of the DCM metal line segment from the starting point of the DCM metal line segment to the target contact point is checked for abnormality, and the resistance of the DCM metal line segment from the target contact point to the ending point of the DCM metal line segment to be tested is checked for abnormality. The DCM metal segment to be tested is the DCM metal segment with an abnormal resistance value that has been identified; the initial DCM metal segment to be tested is the entire DCM metal line.
3. The chip detection method of claim 1, wherein, The resistance of the DCM metal line is detected segment by segment through the contact points reserved on each of the metal layers, including: Based on the starting point and ending point of the DCM metal line and each of the contact points, the DCM metal line is divided into non-overlapping DCM metal line segments to be tested. The resistance of each of the DCM metal segments to be tested is measured.
4. The chip detecting method of claim 1, wherein, After determining the metal layer containing the DCM metal segment with abnormal resistance, the method further includes: The failure location of the DCM metal segment with abnormal resistance was analyzed using a failure location analysis instrument.
5. The chip detection method according to any one of claims 1-4, characterized in that, The contact points are embedded within the insulating material of the metal layer; Before segmentally detecting the resistance of the DCM metal line through the contact points reserved on each of the metal layers, the method further includes: The contact points required for testing are brought out from the insulating material.
6. The chip detection method according to any one of claims 1-4, characterized in that, The contact point is smaller than the size of the preset contact metal ball in the chip; the contact metal ball is located at the start and end points of the DCM metal line.
7. A chip, characterized in that, include: Chip body; The DCM metal lines surround the chip body and are connected in series on all metal layers of the chip body, with contact points reserved on each metal layer; the DCM metal lines are located at the outermost edge of the chip and are not directly connected to the functional circuits in the chip body.
8. The chip as described in claim 7, characterized in that, The contact point is embedded within the insulating material of the metal layer.
9. The chip as described in claim 7 or 8, characterized in that, The contact point is smaller than the size of the preset contact metal ball in the chip; the contact metal ball is located at the start and end points of the DCM metal line.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the chip detection method as described in any one of claims 1-6.