Wiring substrate and manufacturing method thereof

Abstract

To provide a wiring substrate and a manufacturing method of the wiring substrate, and to improve the reliability of a via conductor of the wiring substrate. The manufacturing method of the wiring substrate of the embodiment includes the steps of forming a first conductor layer (22) on a first insulating layer (21); forming a second insulating layer (23) on the first insulating layer (21) so as to cover the first conductor layer; forming a via passage (24) in the second insulating layer so as to expose a part of the first conductor layer; forming a via conductor in the via passage; and forming a second conductor layer (14) on the second insulating layer. The step of forming the via conductor includes the steps of forming a first plating film (11) on the bottom surface and the side surface of the via passage under a first plating condition so as to have a gap portion between the part (11a) on the bottom surface and the part (11b) on the side surface of the via passage; and forming a second plating film (12) that fills the via passage on the gap portion and the first plating film under a second plating condition that is different from the first plating condition.

Description

Technical Field

[0001] This invention relates to wiring substrates and methods for manufacturing wiring substrates. Background Technology

[0002] Patent Document 1 discloses a copper plating solution composition for copper plating of printed circuit boards.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-224304

[0004] In the disclosure of Patent Document 1, sometimes sufficient metal cannot be deposited inside the bottom side of the via, which easily leads to voids and surface depressions in the plated film. In addition, sometimes the electroplating time becomes longer. Summary of the Invention

[0005] The wiring substrate of the present invention comprises: a first insulating layer; a first conductor layer formed on the first insulating layer; a second insulating layer formed on the first insulating layer to cover the first conductor layer; a via path formed on the second insulating layer to expose a portion of the first conductor layer; a seed layer formed on the inner surface of the via path and a first surface in the second insulating layer that is opposite to the surface opposite to the first insulating layer; a via conductor formed inside the via path; and a second conductor layer connected to the via conductor and formed on the first surface. Furthermore, the via conductor comprises: a first plating film formed separately on the bottom and side surfaces of the via path; and a second plating film formed to cover at least a portion of the gaps between the first plating films that are not covered by the first plating film due to the separation of the first plating film and at least a portion of the surface of the first plating film facing the interior of the via path.

[0006] The method for manufacturing a wiring substrate according to the present invention includes the following steps: forming a first conductor layer including a wiring pattern on a first insulating layer; forming a second insulating layer on the first insulating layer such that it covers the first conductor layer; forming a via passage on the second insulating layer such that a portion of the first conductor layer is exposed; forming a via conductor in the via passage; and forming a second conductor layer on the second insulating layer, wherein the step of forming the via conductor includes the following steps: under a first plating condition, forming a first plating film on the bottom surface and the side surface of the via passage such that a gap exists between the portion on the bottom surface and the portion on the side surface; and forming a second plating film filling the via passage on the gap and the first plating film under a second plating condition different from the first plating condition.

[0007] According to embodiments of the present invention, a wiring substrate having highly reliable via conductors and a method for manufacturing such a wiring substrate are provided. Attached Figure Description

[0008] Figure 1A This is a cross-sectional view of the process of forming the first coating film according to one embodiment of the present invention.

[0009] Figure 1B This is a cross-sectional view of the process of forming the second coating film according to one embodiment of the present invention.

[0010] Figure 1C yes Figure 1B The actual SEM image of the state.

[0011] Figure 1D This is a schematic cross-sectional view showing the via passage of one embodiment of the present invention fully embedded.

[0012] Figure 1E yes Figure 1D The actual SEM image of the state.

[0013] Figure 2A This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0014] Figure 2B This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0015] Figure 2C This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0016] Figure 2D This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0017] Figure 2E This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0018] Figure 2F This is a cross-sectional view illustrating an example of a method for manufacturing a wiring substrate according to an embodiment of the present invention.

[0019] Label Explanation

[0020] 11 (11a, 11b, 11c): First plating layer; 12: Second plating layer; 13: Via conductor; 14: Second conductor layer; 21: First insulating layer; 22: First conductor layer; 23: Second insulating layer; 23a: First surface; 24: Via path; 25: Seed layer (metal layer); C: Corner. Detailed Implementation

[0021] In the wiring substrate and wiring substrate manufacturing method of the embodiments, voids, pits, etc., are not generated in the via passages formed on the insulating layer of the wiring substrate after lamination. Instead, the plated metal is embedded by electrolytic plating to form the via conductor. Therefore, the method for forming the via conductor in the wiring substrate manufacturing method of the embodiments will be described first.

[0022] exist Figure 1A The image shows a cross-sectional view of the step of forming the first plating film in a method for manufacturing a wiring substrate according to one embodiment. Figure 1A As shown, in a portion of the stacked layers, a first conductor layer 22 is formed on one side of the first insulating layer 21, and a second insulating layer 23 is formed to cover the first conductor layer 22. Furthermore, a via 24 is formed in the second insulating layer 23 such that a portion of the first conductor layer 22 is exposed. A seed layer 25 for supplying plating current is formed on the inner surface of the via 24 and on the first surface 23a, which is the side of the second insulating layer 23 opposite to the first insulating layer 21. In this state, by electrolytic plating, a via conductor 13 (see reference 12) comprising a first plating film 11 and a second plating film 12 is formed inside the via 24. Figure 1D A second conductor layer 14 is formed on the first surface 23a of the second insulating layer 23 (see reference). Figure 1D ).

[0023] First, such as Figure 1A As shown, a first plating film 11 (11a, 11b, 11c) is formed on the bottom surface of the via passage 24 formed in the second insulating layer 23, that is, on the side surface of the first conductor layer 22 exposed by the formation of the via passage 24, the sidewall of the via passage 24, and above the first surface 23a of the second insulating layer 23, by electrolytic plating with a low current density as the first plating condition. In electrolytic plating with a low current density, less plating metal is deposited, so the plating film does not become too thick in a short time. Therefore, although the first plating films 11a and 11b formed in the via passage 24 are relatively thin, they are formed approximately uniformly except at the corners. However, it is difficult for plating metal to be deposited at the boundary between the bottom surface and the side surface of the via passage 24, that is, at the corners. Therefore, if the plating time is short, the first plating film 11 will not grow at the corner of the boundary between the bottom and side surfaces, which serve as the via passage, and a concave gap will be formed between the first plating film 11a formed on the bottom surface and the first plating film 11b formed on the side surface. At this time, the first plating film 11c is also formed thinly above the first surface 23a of the second insulating layer 23.

[0024] As described later, additives such as inhibitors to suppress plating growth and promoters to promote plating growth are added to the electrolytic plating solution. Their effects will be described later. Through this effect, even at the corner C of the opening of the via 24, the plating film will not concentrate. Furthermore, the plating metal will not deposit in a thick layer on the flat portion above the second insulating layer 23, and a first plating film 11a, 11b will be formed on the inner surface of the via 24, namely the bottom and side surfaces. Figures 1A to 1C In the process, the first plating film 11b on the side of the via 24 and the first plating film 11c above the second insulating layer 23 are formed continuously with the same thickness. However, the first plating film 11c deposited above the first surface 23a of the second insulating layer 23 can be made thinner than the first plating film 11b on the side of the via 24 by means of the inhibitors mentioned above.

[0025] Specifically, the first coated film 11 is formed by electrolytic plating under first plating conditions. The first plating conditions are, for example, 0.5 A / dm². 2 Above 3A / dm 2 The process is performed at a low current density. If the current density is low, as previously mentioned, the amount of deposited plating metal is small, resulting in a thin first plating film 11. Therefore, by shortening the plating time, a concave gap (recess) can be formed between the first plating films 11a and 11b without plating metal depositing at the corners of the bottom surface of the via 24. In electrolytic plating based on this first plating condition, less plating metal is deposited, but because the first plating film 11 is thin, the plating time does not become so long. At this time, on the bottom surface of the via 24, at the center of the bottom surface, the deposition of plating metal is significant, such as... Figure 1A As shown, the first plating film 11a on the bottom surface has a raised shape in the center. In addition, the current tends to concentrate at the corner C of the opening of the via 24, but the plating growth on the corner C and the first surface 23a of the insulating layer 23 is suppressed by the inhibitor described above.

[0026] In other words, the electrolytic plating based on the first plating conditions is completed in such a way that the first plating film 11a on the bottom surface of the via 24 and the first plating film 11b on the side surface are not connected, and the inner surface (seed layer 25) of the via 24 is not covered between them, thus forming a concave gap. As a result, the first plating film 11b formed on the side surface of the via 24 and the first plating film 11c formed on the first surface 23a of the second insulating layer 23 can be formed continuously. In other words, the first plating films 11a and 11b are formed in such a way that the first plating film 11a on the bottom surface and the first plating film 11b on the side surface are not excessively separated and not excessively close, thus forming a concave space between them, but the first plating film 11b on the side surface and the first plating film 11c on the first surface 23a of the second insulating layer 23 can be formed continuously. For example, with the diameter of via 24 being approximately 50 μm and the depth approximately 30 μm, and the current density being 1 A / dm²... 2 In this case, the time is preferably between 1 minute and 5 minutes. The aspect ratio of the via 24 can be formed to be between 0.25 and 0.90.

[0027] The second plating film 12 is formed in the gap between the first plating films 11a and 11b, which are separately formed on the bottom and side surfaces of the via passage 24, in a manner that covers at least a portion of the inner surface of the via passage 24 not covered by the first plating film 11 (the exposed seed layer 25) and the surface of the first plating film 11 facing the center of the via passage 24. Specifically, as Figure 1B sectional view, Figure 1C As shown in the actual scanning electron microscope (SEM) image, under the second plating condition of high current density, a plating film is preferentially grown on the seed layer 25 where the first plating film 11a is not formed, forming a second plating film 12 that fills the via passage 24, in the concave gap between the first plating film 11a formed on the bottom surface of the via passage 24 and the first plating film 11b formed on the side surface.

[0028] The second plating condition is, for example, 4A / dm. 2 Above and 15A / dm 2The following high current density conditions are applied. Electroplating under these high current density conditions results in more deposited metal and a thicker plating film in a shorter time. On the other hand, the recess formed between the first plating film 11a on the bottom surface and the first plating film 11b on the side surface of the via 24 is very narrow, a space relatively narrower than the surface of the first metal films 11a and 11b. Therefore, for example, very little adsorption of inhibitors added to the electroplating solution occurs, and the deposition of plating metal based on electroplating becomes relatively significant compared to the surface of the first plating film 11. Therefore, at the corner of the bottom surface of the via 24, the second plating film 12 preferentially forms at the exposed portion of the seed layer 25. Therefore, in electroplating based on the second plating conditions, more growth begins from the corner of the bottom surface of the via 24 where the first plating films 11a and 11b are not formed. However, the second plating film 12 also grows on the surface of the first plating film 11.

[0029] On the other hand, the seed layer 25 at the corner C on the first surface 23a of the second insulating layer 23 outside the via 24 is further inhibited from growing the second plating film 12 by the action of inhibitors, etc., compared with that inside the via 24. Therefore, by the action of the added inhibitors, the growth of the second plating film 12 is maximized in the concave portion between the first plating films 11a and 11b at the bottom corner of the via 24. Then, the growth of the surface of the first plating film in the via 24 is carried out, and the growth of the second plating film 12 is minimized on the first surface 23a of the second insulating layer 23. As a result, the second plating film 12 grows from the bottom side of the via 24 and does not form voids inside the via 24. In addition, the upper surface of the via conductor 13 formed in the via 24 and the second conductor layer 14 on the second insulating layer 23 (see reference) can be made more uniform. Figure 1D The surface is roughly flush.

[0030] In other words, a first plating film 11 is formed, and a second plating film 12 is formed thereon under second plating conditions of high current density for the second plating film 12. Therefore, as in Figure 1D A schematic cross-sectional view is shown in the figure. Figure 1E As shown in the actual scanning electron microscope (SEM) image, a via conductor 13 comprising a seed layer 25, first plating films 11a and 11b, and a second plating film 12 is formed within the via passage 24. Furthermore, a second conductor layer 14 comprising a metal layer composed of the seed layer 25, a first plating film 11c, and a second plating film 12 is formed on the first surface 23a of the second insulating layer 23. The second conductor layer 14 can be formed, for example, by a semi-additive method, in various conductor patterns including desired wiring patterns, connection pads, and electrode pads.

[0031] exist Figure 1DIn the example shown, the second plating film 12 (which forms the gap between the first plating film 11a on the bottom surface and the first plating film 11b on the side surface of the embedded via 24) Figure 1B After the state is reached, the via conductor 13 and the second conductor layer 14 are formed under the second plating conditions. However, it is also possible to... Figure 1B After the state is reached, electrolytic plating based on the first plating condition, i.e., low current density, can be continued. Alternatively, other plating conditions, such as higher current density than the second plating condition, can be used to embed the remaining portion within the via passage 24.

[0032] Furthermore, by adding growth inhibitors and growth promoters in optimal proportions to the plating solution, the growth of the plating film on the first surface 23a of the second insulating layer 23 is suppressed, thereby promoting growth within the via passage 24 in this embodiment. Figure 1D As shown, the surface of the via conductor 13 and the surface of the second conductor layer 14 can be formed to be approximately flush.

[0033] A seed layer 25 for supplying plating current is formed on the lower surface of the first plating film 11. The seed layer 25 is usually formed by electroless plating (chemical plating), sputtering, vacuum evaporation or other physical evaporation methods, or chemical evaporation methods such as CVD, using a chemical plating solution containing metal ions (most often complexes) and a reducing agent.

[0034] In the wiring substrate of this embodiment, the via conductor 13 and the second conductor layer 14 are formed by a seed layer (metal layer) 25, a first plating film 11, and a second plating film 12. The first plating film 11 is not connected to the bottom and side surfaces of the via passage 24, and a concave gap is formed between them. Therefore, the seed layer 25 is exposed between the first plating film 11a formed on the bottom surface and the first plating film 11b formed on the side surface, and the second plating film 12 is embedded therein. The second plating film 12 can also cover the first plating films 11a and 11b formed on the bottom and side surfaces of the via passage 24, so the second plating film 12 is buried from the bottom of the via passage 24. Therefore, the formation of voids, pits, etc. in the via passage 24 can be suppressed. That is, a wiring substrate containing a via conductor 13 with low resistivity and high reliability can be obtained in a short time.

[0035] The plating solution used to form the via conductor 13 and the second conductor layer 14 of the wiring substrate in this embodiment is a copper plating solution containing copper salt and acid, with added additives such as inhibitors to inhibit plating growth and promoters to promote plating growth. As the copper salt, copper sulfate (CuSO4·5H2O) is used, but it is not limited to copper sulfate; copper nitrate (Cu(NO3)2), copper formate (Cu(HCOO)2), copper chloride (CuCl2·2H2O), etc., can also be used.

[0036] Sulfuric acid (H2SO4·5H2O) is commonly used as an acid, but it is not limited to this; hydrochloric acid (HCl), acetic acid (CH3COOH), and fluoroboric acid (HBF4) can also be used.

[0037] Inhibitors, for example, are composed of high-molecular-weight organic compounds. Due to their large molecular weight and low mobility, they readily adsorb onto the flat areas of the substrate surface, following the diffusion rules, but are difficult to adsorb into narrow regions such as the vias 24. Therefore, in Figure 1A In the illustrated configuration, the flat surface of the first surface 23a of the second insulating layer 23 readily adsorbs inhibitors. Therefore, plating precipitation occurs within the via passage 24, but the flat surface of the first surface 23a of the second insulating layer 23 inhibits the precipitation of plating metal. Similarly, in the concave gaps formed by the first plating films 11a and 11b within the via passage 24, a certain amount of inhibitor is added, but the large molecular weight inhibitor can hardly penetrate the gaps of the first plating films 11a and 11b. Therefore, compared to the surfaces of the first plating films 11a and 11b, the precipitation of plating metal is promoted. As a result, as... Figures 1A to 1C As shown, via conductor 13, which is embedded in via passage 24 without creating voids, and second conductor layer 14, such as wiring, formed on the first surface 23a of the second insulating layer 23, are simultaneously formed by electrolytic plating. Furthermore, the surface of via conductor 13 is easily made approximately flush with the surface of the second conductor layer 14. Additionally, the inhibitor readily adheres to the corner C of the opening of via passage 24 along with the flat surface of the first surface 23a of the second insulating layer 23. Therefore, by adding this inhibitor, the growth of the plating film locally at the corner C can also be suppressed.

[0038] The accelerator, formed from chloride ions (Cl), hydrochloric acid (HCl), sodium chloride (NaCl), etc., promotes the deposition of plating. This accelerator is also generally uniformly adsorbed on the bottom surface, side surface, and planar portion of the via 24 and the second insulating layer 23. During plating, the accelerator becomes denser inside the via 24 as the plating metal grows. Therefore, the plating speed inside the via 24 is faster than on the planar portion of the second insulating layer 23. On the other hand, by also adding the aforementioned inhibitor, the growth of plating metal on the planar portion is suppressed. That is, by adding the accelerator and inhibitor in an appropriate ratio, the surface of the thick via conductor 13 and the surface of the thin second conductor layer 14 are homogenized.

[0039] Typically, these inhibitors and promoters are mixed in a moderate ratio in a plating solution, and through their combined effect, copper is filled into the interior of the via 24. This is because the deposition characteristics of the plated metal vary depending on the diameter, depth, etc. of the via 24.

[0040] As additives, not limited to the inhibitors and promoters mentioned above, flattening agents that are easily adsorbed on flat surfaces but difficult to adsorb within the via 24, gloss agents that adsorb onto the growth points of crystal nuclei and inhibit crystal growth, reducing agents, etc., can be added.

[0041] By adding the aforementioned inhibitor, crystallization can be suppressed at the corner C of the opening of the via 24 and on the first surface 23a of the second insulating layer 23. On the other hand, the inhibitor is difficult to adsorb inside the via 24, and further in the recesses (gap portions) formed within the via 24, thus copper as plating metal precipitates on the bottom and sides of the via 24. However, if the via 24 is uniform, plating metal is relatively difficult to precipitate at the corner of the bottom surface of the via 24. As a result, by controlling the electrolytic plating time based on the first plating conditions for a short period of time, such as... Figure 1A As shown, a first plating film 11a is formed on the bottom surface of the via 24 in a non-connected manner, and a first plating film 11b is formed on the side surface in a non-connected manner. The first plating film 11a formed on the bottom surface is separated from the first plating film 11b formed on the side surface, and the seed layer 25 in the via 24 is exposed in the gap between them.

[0042] The current density under the second plating condition is higher than that under the first plating condition. Specifically, it is preferably 4 A / dm. 2 Above and 15A / dm 2 In other words, the current density is preferably 1.2 times or more and 30 times less than that of the first plating condition. As a result, a second plating film 12 based on the second plating condition is formed in a short time. Moreover, as... Figure 1B As shown, on the bottom surface of the via 24, as described above, the gap between the first metal films 11a and 11b is concave, thus the second coated film 12 preferentially forms from this gap. As a result, voids are not formed, etc. Figure 1D As shown, a via conductor 13 is formed within a short time in the via passage 24, and a second conductor layer 14 is formed on the first surface 23a of the second insulating layer 23.

[0043] Next, refer to Figures 2A to 2F A method for manufacturing a wiring substrate according to one embodiment will be described. Figures 2A-2F Only the portion showing the via conductors during the fabrication of the wiring substrate formed by the multilayer is shown.

[0044] like Figure 2A As shown, a first conductor layer 22 containing a wiring pattern is formed on the first insulating layer 21. The first insulating layer 21 is formed of any insulating resin. Examples of insulating resins include epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin. Although in Figure 2AAlthough not explicitly stated in the example, the first insulating layer 21 may comprise a core material (reinforcing material) formed of glass fiber, aramid fiber, etc. Although in Figure 2A The first insulating layer 21 may contain a core material made of glass fiber or the like, but is not shown in the figure. It may also contain an inorganic filler (not shown) made of particles such as silicon dioxide (SiO2), alumina or mullite.

[0045] The first conductor layer 22 can be a layer in which a metal foil laminated on the first insulating layer 21 has a desired conductor pattern through patterning based on a subtractive method, or it can be a layer formed by a semi-additive method, as described later as the second conductor layer 14. There are no particular limitations on the metal used; any metal such as copper or nickel can be used.

[0046] like Figure 2B As shown, a second insulating layer 23 is formed on a first insulating layer 21 in a manner that covers the first conductor layer 22. Specifically, for example, a film-like epoxy resin is laminated onto the first insulating layer 21 on which the first conductor layer 22 is formed, and then heated and pressurized. As a result, the second insulating layer 23 is formed.

[0047] like Figure 2C As shown, a via 24 is formed in the second insulating layer 23 with a portion of the first conductor layer 22 exposed. Specifically, the via 24, used to form a via conductor 13 for connecting the lower and upper conductor layers of the second insulating layer 23, is formed, for example, by irradiation with a carbon dioxide laser. Since the carbon dioxide laser weakens as it penetrates deeper into the second insulating layer 23, therefore... Figure 2C As shown, the cross-sectional shape of the via 24 is tapered, with the bottom portion being thinner than the opening portion. The surface of the first conductor layer 22 exposed through the formation of the via 24 becomes the bottom surface of the via 24.

[0048] like Figure 2D As shown, a seed layer 25 for supplying plating current is formed on the inner surface of the via 24, including the bottom and side surfaces, and on the first surface 23a of the second insulating layer 23, which is the opposite side to the first insulating layer 21. The seed layer 25 can be formed, for example, by electroless plating or physical evaporation such as sputtering, vacuum evaporation, or chemical evaporation such as CVD. Since the first surface 23a of the second insulating layer 23 and the side surface of the via 24 are insulating layers, current for electrolytic plating cannot flow through them. Therefore, a metal film is formed on approximately the entire surface for power supply. This seed layer 25 is formed as a thin layer that does not produce cracks, as long as current can flow through it.

[0049] After that, as Figure 2EAs shown, according to the first plating conditions, a first plating film 11 is formed on the bottom and side surfaces of the via 24 with a concave gap between the portion 11a on the bottom surface and the portion 11b on the side surface. That is, the portion 11a on the bottom surface and the portion 11b on the side surface are not connected to each other, forming a recess between them, and a portion of the seed layer 25 on the bottom surface side of the via 24 is not covered, thus forming the first plating film 11 (11a, 11b). In other words, the first plating films 11a and 11b are formed with a gap that is neither too large nor too small. Therefore, the first plating film 11 is formed relatively thin, and the first plating film 11b deposited on the side surface of the via 24 does not contact the first plating film 11b deposited on the opposite side surface, thus forming the first plating film 11. As described above, it is believed that if the first plating film 11b deposited on the side surface comes into contact with the first plating film 11b deposited on the opposite side surface, a void may easily form at a position closer to the bottom surface than that portion, but this possibility is not considered. Furthermore, if the first plating film 11a deposited on the bottom surface of the via 24 comes into contact with the first plating film 11b formed on the side surface of the via 24, and the entire inner surface of the via 24 is covered by the first plating film 11, it is possible that sufficient plating growth based on the subsequent second plating conditions may not be possible on the bottom surface, but this possibility is also not considered.

[0050] On the seed layer 25 of the first surface 23a of the second insulating layer 23, for example, by adding the aforementioned inhibitor to the electrolytic plating solution, according to the diffusion rules, the inhibitor is more adsorbed than inside the via 24, thus suppressing the precipitation of plating metal. Unlike inside the via 24, no plating film is precipitated, and a first plating film 11c is formed as a thinner layer. The thickness of this first plating film 11c can be adjusted by the mixing ratio of the added inhibitor, accelerator, etc.

[0051] Next, as Figure 2F As shown, according to the second plating conditions, plating metal (copper) precipitates from the portion of the seed layer 25 not covered by the first plating film 11 between the bottom and side surfaces of the first plating films 11a and 11b formed in the via passage 24. As described above, the inhibitor added to the electrolytic plating solution is difficult to adsorb in narrow areas such as recesses, but is more easily adsorbed in flat areas. Therefore, compared to the surface of the first plating film 11, plating metal precipitation preferentially begins in the concave gap between the first plating films 11a and 11b. On the other hand, plating metal also grows on the surface of the first plating film 11, but since plating growth is dominant on the bottom side of the via passage 24, plating growth from the bottom side of the via passage 24 makes it difficult to form voids, etc., and the second plating film 12 is formed in the via passage 24 in a short time.

[0052] The current density under the second plating condition is approximately 1.2 times to less than 30 times that of the first plating condition. Specifically, at 4 A / dm²... 2 Above and 15A / dm 2 The current density below forms the second plating film 12. As described above, if electroplating is performed under the second plating conditions, plating metal is deposited on the surface of the seed layer 25 that appears in the concave gap between the first plating film 11a formed on the bottom surface of the via 24 and the first plating film 11b formed on the side surface. New plating metal is further deposited in the deposited plating metal, thereby plating growth is performed in a short time.

[0053] As described above, the growth rate of the second plating film 12 decreases sequentially from the gap between the first plating films 11a and 11b, to the first plating film 11, and then to the first surface 23a of the second insulating layer 23. However, it also grows on the first plating film 11, with the plating metal growing sequentially from the bottom side of the via passage 24, and the via conductor 13 is embedded inside the via passage 24. Figure 2E In the diagram, the first plating film 11b, which becomes the side of the via passage 24, and the first plating film 11c on the first surface 23a of the second insulating layer 23 are continuously formed, but their thickness is thinner on the first surface 23a.

[0054] exist Figure 2F In the example shown, the second plating film 12, which is then formed at the bottom of the via 24, continues to grow under the second plating conditions to form the via conductor 13. However, as described above, as... Figure 1B As shown, if the bottom of the via 24 is buried by the second plating film 12, the second plating condition may not be continued, or the remaining part of the via 24 may be buried under other plating conditions.

[0055] According to the wiring substrate manufacturing method of this embodiment, a low current density current, serving as a first plating condition, is used to form a recess between the bottom and side surfaces of the via passage 24 without interconnection, thereby forming a first plating film 11a, 11b such that a portion including the corner of the bottom surface of the via passage 24 is not covered. Then, from the gap between the first plating films 11a, 11b formed on the bottom and side surfaces of the via passage 24, a high current density current, serving as a second plating condition, is used to form a second plating film 12 at least near the bottom surface of the via passage 24. Therefore, since the second plating film 12 is formed from the bottom surface side of the via passage 24 and is formed by high current density electrolytic plating, it is believed that voids, pits, etc., will not be generated in the via conductor 13, and the via conductor 13 will be formed in a short time.

Claims

1. A wiring substrate, comprising: First insulating layer; A first conductor layer is formed on the first insulating layer; A second insulating layer is formed on the first insulating layer in such a way as to cover the first conductor layer; Via passages are formed in the second insulating layer such that a portion of the first conductor layer is exposed; A seed layer is formed on the inner surface of the via and the first surface of the second insulating layer, which is the opposite side of the surface opposite to the first insulating layer. A via conductor, which is formed inside the via passage; as well as A second conductor layer, which is connected to the via conductor and formed on the first surface, is also present. in, The via conductor comprises: The first coating film is formed separately on the bottom and side surfaces of the via; and The second coating is formed in such a way that it covers at least a portion of the gaps between the first coatings that were not covered by the first coating due to the separation of the first coating and at least a portion of the surface of the first coating facing the interior of the via passage.

2. The wiring substrate according to claim 1, wherein, The first plating film and the second plating film are electrolytic plating films.

3. The wiring substrate according to claim 2, wherein, The first coating and the second coating each contain copper as the main component.

4. The wiring substrate according to claim 1, wherein, The first coating film formed on the side of the via is continuous with the first coating film formed on the first surface.

5. The wiring substrate according to claim 1, wherein, The central portion of the first coated film formed on the bottom surface of the via is raised.

6. The wiring substrate according to claim 1, wherein, The aspect ratio of the via is greater than 0.25 and less than 0.

90.

7. The wiring substrate according to claim 1, wherein, The via is filled by the second coating film.

8. A method for manufacturing a wiring substrate, the method comprising the following steps: A first conductor layer containing a wiring pattern is formed on the first insulating layer; A second insulating layer is formed on the first insulating layer in a manner that covers the first conductor layer; A via is formed in the second insulating layer such that a portion of the first conductor layer is exposed; A via conductor is formed within the via passage; and A second conductor layer is formed on the second insulating layer. in, The steps of forming the via conductor include the following steps: Under the first plating condition, a first plating film is formed on the bottom and side surfaces of the via passage in such a way that there is a gap between the portion on the bottom surface and the portion on the side surface. as well as A second plating film is formed on the gap and the first plating film under a second plating condition different from the first plating condition to fill the via passage.

9. The method for manufacturing a wiring substrate according to claim 8, wherein, The first and second plating films are formed by electrolytic plating.

10. The method for manufacturing a wiring substrate according to claim 9, wherein, The current density of the second plating condition is greater than the current density of the first plating condition.

11. The method for manufacturing a wiring substrate according to claim 10, wherein, The current density of the second plating condition is more than 1.2 times and less than 30 times that of the current density of the first plating condition.

12. The method for manufacturing a wiring substrate according to claim 9, wherein, The electroplating process involves applying a direct current.

13. The method for manufacturing a wiring substrate according to claim 8, wherein, The second coating film precipitates at the gap from the inner surface of the via passage that is not covered by the first coating film.

14. The method for manufacturing a wiring substrate according to claim 8, wherein, The first plating condition and the second plating condition involve using a plating solution containing copper salts.

15. The method for manufacturing a wiring substrate according to claim 14, wherein, The copper salt is selected from at least one of the group consisting of copper sulfate, copper nitrate, copper formate, and copper chloride.

16. The method for manufacturing a wiring substrate according to claim 14, wherein, The first plating condition and the second plating condition include adding a plating promoter that promotes plating growth to the plating solution containing copper salt.

17. The method for manufacturing a wiring substrate according to claim 14, wherein, The first plating condition and the second plating condition involve adding a plating inhibitor that inhibits plating growth to the plating solution containing copper salt.

18. The method for manufacturing a wiring substrate according to claim 8, wherein, Before forming the first coating film, a seed layer is formed on the inner surface of the via passage, including the bottom and side surfaces, and on the opposite side of the second insulating layer to the surface opposite to the first insulating layer.

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