A method and system for implementing a sparse fractional fourier transform (FPGA)

Abstract

This invention discloses a sparse fractional Fourier transform (FFT) implementation method and system on FPGA, belonging to the fields of digital signal processing and embedded systems. First, the external input signal f(n) is multiplied by the chirp1 signal to obtain the frequency-modulated signal x(n), and signal x(n) is cached in a DDR3 memory chip for subsequent loop calculations. Next, a sparse Fourier transform is performed on signal x(n). Finally, the result of the sparse Fourier transform is multiplied by the chirp2 signal to obtain the fractional Fourier transform result of the original input signal f(n). Compared to the traditional fractional Fourier transform, this method can perform the fractional Fourier transform more quickly and can reduce the hardware resource consumption of the FPGA device.

Description

Technical Field

[0001] This invention belongs to the field of digital signal processing and embedded systems, and particularly relates to a sparse fractional Fourier transform FPGA implementation method and system. Background Technology

[0002] Fourier transform, as a signal processing method, plays an important role in scientific research and engineering. However, Fourier transform is a global transform, yielding the overall spectrum of the signal, and therefore cannot represent the local time-frequency characteristics of the signal; Fourier transform is suitable for processing stationary signals, but its effectiveness is limited for processing non-stationary signals. To analyze and process non-stationary signals, a series of new signal analysis theories have been proposed and developed, and fractional Fourier transform, as a generalized form of Fourier transform, has gained favor among many researchers due to its unique time-frequency joint representation characteristics.

[0003] The concept of the fractional Fourier transform was proposed as early as 1929 by N. Wiener of MIT. In 1980, V. Namias of Purdue University's Gallimard campus proposed the concept of the fractional Fourier transform in a purely mathematical manner. Subsequently, ACMcBride et al. gave a mathematical expression for the closed-form of the fractional Fourier transform from the perspective of integral form. In 1993, D. Mendlovic and H. Mozaktas proposed the fractional Fourier transform from an optical perspective, gave its optical implementation, and applied it to optical information processing. [The text then abruptly shifts to a different topic:] [A separate, unrelated section explains the physical meaning of the fractional Fourier transform from the perspective of optical information processing, stating that the p-th order fractional Fourier transform is equivalent to a rotation of the Wigner distribution function in phase space by an angle of pπ / 2, and provides fractional Fourier transform results for some common signals.

[0004] Following the proposal by HMOzaktas et al. from Birkenau University in Turkey in 1996 of a discrete algorithm with computational complexity comparable to the Fast Fourier Transform (FFT), the fractional Fourier Transform (FFT) experienced rapid development. Currently, FFT algorithms based on this discrete algorithm are mainly divided into three categories: eigenvalue-based, linear combination-based, and sampling-based. Among them, the sampling-based FFT algorithm directly samples the continuous FFT kernel to obtain the discrete FFT kernel matrix, representing the most direct and simplest definition method for the FFT.

[0005] Compared to the Fourier transform, the fractional Fourier transform is much more complex to calculate. In previous FPGA implementations, the signal first needs preprocessing, performing an FFT calculation, then interpolating and filtering the signal to generate a chirp1 signal. The product of the two chirp1 and chirp2 signals is then linearly convolved with the chirp2 signal. Finally, an IFFT transform and decimation are performed to obtain the fractional Fourier transform result. However, the sparse fractional Fourier transform FPGA implementation proposed in this invention only requires basic multiplication operations and an FFT transform, significantly reducing computation time and improving resource utilization. Summary of the Invention

[0006] The purpose of this invention is to provide an FPGA implementation method and system for sparse fractional Fourier transform, aiming to overcome the problems of computational complexity and high hardware resource consumption in the hardware implementation scheme of traditional fractional Fourier transform algorithms.

[0007] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0008] A method for implementing sparse fractional Fourier transform on FPGA includes the following steps:

[0009] Step 1: Preprocess the signal of length N to convert it into a signal of length B;

[0010] Step 2: Perform FFT / IFFT transformation on the signal of length B;

[0011] Step 3: Perform insertion sort on the data transformed in Step 2 and select the threshold.

[0012] Step 4: Filter candidate frequency points based on the threshold output in Step 3;

[0013] Step 5: Perform insertion sort to determine the amplitude corresponding to each candidate frequency point selected in Step 4. Then sort the candidate frequency points with determined amplitudes according to the amplitude size, filter out the frequency points with large values, and finally tune the filtered results to obtain the final calculation result.

[0014] Thus, from step 1 to step 5, a method for implementing sparse fractional Fourier transform on an FPGA has been completed.

[0015] Preferably, the implementation process of step 1 is as follows:

[0016] Step 1.1: Obtain the input signal f(n), and use the chirp1 signal to perform frequency modulation on the input signal f(n) to obtain the signal x(n), specifically:

[0017] Step 1.1A: Calculate the rotation angle α based on the order p of the sparse fractional Fourier transform input from the host computer, where α = pπ / 2. Then, call the Cordic-IP core in the FPGA to generate the chirp1 signal.

[0018] Step 1.1B: Set an input counter at the input end of the data preprocessing module to control the number of input signals f(n) by counting the number of input signals f(n);

[0019] Step 1.1C: Multiply the input signal f(n) with the chirp1 signal to obtain the signal x(n). The lengths of both the input signal f(n) and the signal x(n) are N.

[0020] Step 1.2: Buffer the signal x(n) obtained in Step 1.1C. Specifically, perform a signed number expansion operation on the signal x(n) to expand the data bit width to the same as the data line bit width of the DDR3 memory chip and send it into the asynchronous FIFO. Then, the DDR3 control module reads the signal x(n) that has completed the expansion operation in the asynchronous FIFO and writes it sequentially into the DDR3 memory chip in the form of burst write.

[0021] Step 1.3: Perform data spectrum rearrangement, filtering, and aliasing on the signal x(n), specifically as follows:

[0022] Step 1.3A: Based on the storage location of signal x(n) in the DDR3 memory chip, calculate the storage location of each point of signal x(n) after rearrangement and the storage location after aliasing;

[0023] Multiply the storage location of signal x(n) by the randomly generated spectral rearrangement coefficient σ, and take the modulus of the result with respect to the length N to obtain the storage location of each point of signal x(n) after rearrangement. Then, take the modulus of the storage location of the rearranged signal x(n) with respect to the length B to obtain the storage location after aliasing.

[0024] Step 1.3B: Recall the RAM to store the signal of length B obtained after the aliasing operation is completed;

[0025] In the L rounds of the SFrFT system's geg loop, the first round buffers the signal x(n) into the DDR3 memory chip while simultaneously performing L / 2 rounds of spectrum rearrangement, filtering, and aliasing operations on the signal x(n) in parallel, resulting in L / 2 data slices of length B. In the second to L / 2-1 rounds of the loop, only the result of the aliasing calculation in the first round is output. In the L / 2 round of the loop, the data in the DDR3 memory chip is read by the DDR3 control module and written into the FIFO. After performing a truncation operation on the signed number, the original bit width signal x(n) is obtained. Then, L / 2 rounds of spectrum rearrangement, filtering, and aliasing operations are performed in parallel, and in the remaining rounds of the loop, only the result of the aliasing calculation in the L / 2 round is output.

[0026] Preferably, the implementation process of step 2 is as follows:

[0027] Perform an FFT / IFFT transformation on the signal of length B stored in RAM in step 1.3B to obtain the calculation result X(k); where the FFT / IFFT transformation is implemented by calling the FFT-IP core.

[0028] Preferably, the implementation process of step 3 is as follows:

[0029] Step 3.1: Obtain two identical amplitude register groups, each containing K registers. Each amplitude register group also corresponds to an indicator signal with a bit width of Kbit, and the bits of the indicator signal correspond one-to-one with the registers in the amplitude register group.

[0030] Step 3.2: The calculation result X(k) and coordinates obtained in Step 2 are serially input into the amplitude register group. After B clock cycles, the calculation result X(k) will be completely input into the amplitude register group. In each clock cycle, the first amplitude register will get a value of the calculation result X(k). At the same time, this value will be compared with the amplitude of the data stored in the first amplitude register group. If the amplitude of this value is greater than the amplitude of the data stored at a certain position in the first amplitude register group, the bit at the corresponding position of the indicator signal will be set to 1; otherwise, it will be set to 0.

[0031] After the comparison is completed, if the indicator signal is not 0, the value is inserted into the first amplitude register group according to the number of 1 bits in the indicator signal, and the value discarded by the first amplitude register group after one comparison is passed to the second amplitude register group; when the indicator signal is 0, the value of X(k) compared with the data stored in the first amplitude register group is passed to the second amplitude register group.

[0032] Within the same clock cycle, the second amplitude register group performs the same comparison operation; the final 2K values ​​left by the two register groups are the largest 2K values ​​arranged from largest to smallest amplitude, which are the high-frequency points selected from the FTT / IFFT calculation result X(k) in this round of the loop;

[0033] Step 3.3: Pass the value with the smallest amplitude in the second amplitude register group as the threshold to the candidate frequency filtering module, and at the same time output the frequency points of all values ​​stored in the two amplitude register groups to the candidate frequency filtering module.

[0034] Preferably, the implementation process of step 4 is as follows:

[0035] Step 4.1: In the first loop, the large frequency points selected from the calculation result X(k) passed from Step 3 are restored to their original frequency points and stored in the frequency point register group of the candidate frequency point selection module;

[0036] Step 4.2: In the second round of the loop, the large frequency points passed from Step 3 are restored to the original frequency points and stored in the circular shift register group of the candidate frequency point screening module. Then, the frequency point register group is compared with the original frequency points stored in the circular shift register group. If there are the same frequency points in the frequency point register group and the circular shift register group, the frequency point at the corresponding storage position in the circular shift register group is cleared and the highest bit of the corresponding storage position in the frequency point register group is pulled high.

[0037] Step 4.3: In the third loop, the original frequency points stored in the frequency point register group and the circular shift register group are mapped to the FFT / IFFT calculation results of step 3 of this loop. The corresponding amplitude is compared with the threshold passed from step 3 of the third loop. The original frequency points with amplitudes less than the threshold and with the highest bit low are eliminated. The filtered frequency points and the corresponding amplitudes generated in each loop are passed to the result calculation module for sorting and estimation.

[0038] Preferably, the sorting in step 5 is as follows:

[0039] Step 5.1: Sort the real and imaginary parts of each frequency point separately, and select the median as the final amplitude of the frequency point;

[0040] Step 5.2: Sort all candidate frequency points with determined amplitudes according to their amplitude values, and select the K largest frequency points as the final high-value frequency points;

[0041] Step 5.3: Based on the final high-frequency point selected, the chirp2 signal generated by the Cordic-IP core is multiplied with it to obtain the final calculation result.

[0042] The present invention also provides a sparse fractional Fourier transform FPGA implementation system, which is used in the sparse fractional Fourier transform FPGA implementation method according to any one of claims 1-5, wherein the implementation device of the system is an FPGA, and the FPGA includes a Cordic-IP core, a data preprocessing module, an asynchronous FIFO, a DDR3 control module, RAM, an amplitude register group, and a candidate frequency point screening module.

[0043] Beneficial effects: Compared with the FPGA implementation scheme of the traditional fractional Fourier transform algorithm, the sparse Fourier transform algorithm proposed in this invention can effectively reduce computational complexity, improve computational efficiency, reduce computation time, and its simpler hardware design structure also greatly reduces the hardware resources required. Attached Figure Description

[0044] Figure 1 This is an overall flowchart of an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0045] Figure 2 This is an overall hardware architecture diagram of an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0046] Figure 3 This is a structural block diagram of the data preprocessing module in an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0047] Figure 4 This is a structural block diagram of the address calculator in an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0048] Figure 5 This is a structural block diagram of the DDR3 control module in an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0049] Figure 6 This is a block diagram of the insertion sorter in an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0050] Figure 7 This is a structural block diagram of the candidate frequency point screening module in an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0051] Figure 8 This is a structural block diagram of the result calculation module in an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0052] Figure 9 These are actual test results from an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform".

[0053] Figure 10 This is the theoretical result of directly performing the fractional Fourier transform in the embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform". Detailed Implementation

[0054] To better understand the purpose, structure, and function of this invention, a sparse fractional Fourier transform FPGA implementation method of this invention will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0055] This embodiment illustrates the implementation process of applying the present invention "A Sparse Fractional Fourier Transform FPGA Implementation Method and System" to perform a 32768-point sparse fractional Fourier transform on an input signal.

[0056] Figure 1 This is a flowchart of an embodiment of the present invention, "An FPGA Implementation Method and System for Sparse Fractional Fourier Transform". Figure 2 This is an overall hardware architecture diagram of an embodiment of the present invention, "A Sparse Fractional Fourier Transform FPGA Implementation Method and System".

[0057] from Figure 1 As can be seen, this method includes the following steps:

[0058] Step A involves preprocessing the input signal, namely, buffering the input signal after frequency modulation and performing spectrum rearrangement, filtering, and aliasing operations on the frequency-modulated signal.

[0059] In the specific implementation of this example, after comprehensively considering the computational accuracy and resource consumption, this embodiment sets the total data length N to 32768, the aliasing length B to 512, the signal sparsity K to 4, and the number of sparse Fourier transform loops to 8. Figure 3 The data preprocessing module architecture diagram in the embodiment is shown; after the SFrFT hardware system starts up, it begins to accept data and starts the input counter; in the first loop, the chirp signal generation module in the data preprocessing module generates the chirp1 signal, and the chirp1 signal is multiplied with the input signal f(n) to obtain the frequency-modulated signal x(n); Figure 5 The structure of the DDR3 control block is shown. In the first loop, the signal x(n) is buffered in a FIFO after the signed number expansion operation is completed. Then it is read out by the DDR3 control module and written to the DDR3 memory chip. In the fifth loop, the DDR3 control module reads the buffered data from the DDR3 memory chip, performs a signed number truncation operation, and writes it into an asynchronous FIFO for the data preprocessing module to read out. Figure 4 The address calculator shown will calculate the storage address of the filter corresponding to the spectrum rearrangement and the storage address after aliasing in the first and fifth loops, thus completing the spectrum rearrangement, filtering and aliasing operations on the signal x(n);

[0060] In this embodiment of the invention, it should be noted that in the first loop, the data preprocessing module performs four rounds of spectrum rearrangement, filtering, and aliasing operations on the signal x(n) in parallel while caching the signal x(n) into the DDR3 memory chip, resulting in four data slices of length B. In the second, third, and fourth loops, the data preprocessing module only outputs the calculation results generated in the first loop and does not perform any other operations. In the fifth loop, the data preprocessing module reads the data from the DDR3 memory chip through the DDR3 control module, and then performs four rounds of spectrum rearrangement, filtering, and aliasing operations in parallel. In the sixth, seventh, and eighth loops, the data preprocessing module only outputs the calculation results generated in the fifth loop and does not perform any other operations.

[0061] Step B: Perform FFT / IFFT transformation on the data processed in Step A, and then select the 2K largest values ​​from the results;

[0062] The parameters of the FFT-IP core are set as follows: FFT type is selected as Radix-4 Burst I / O, rounding type is selected as rounding, the calculation result is not truncated, the input bit width and output bit width are 20 bits and 30 bits respectively, and the data type is selected as fixed-point signed number; the insertion sorter structure is as follows. Figure 4 As shown, the length of the amplitude register group in this example is 4, so the maximum of 8 points can be selected. The register storage method is: the high 9 bits store the frequency, the middle 20 bits store the imaginary part, and the low 20 bits store the real part. After the threshold selection module completes the calculation, it will output the large value frequency points in descending order of amplitude, and take the last output data, i.e. the smallest amplitude, as the threshold.

[0063] Step C: Reconstruct and filter the high-value frequency points to select candidate frequency points;

[0064] Figure 6 To insert a sorting comparator and perform candidate frequency point filtering, the following steps are taken: First, the high-value frequency points selected by the first-round threshold selection module are reconstructed, and the results are stored in a circular shift register group. The storage method is: the highest bit is set to 0, and the low bits store the frequency points. Then, the high-value frequency points selected by the second-round threshold selection module are reconstructed, and the results are stored in a frequency point register group. Next, the data in the circular shift register group and the frequency point register group are compared. If there are the same frequency points in the frequency point register group and the circular shift register group, the corresponding frequency point in the circular shift register group is cleared, and the highest bit of the corresponding frequency point in the frequency point register group is pulled high. In the third loop, the original frequency points in the frequency point register group and the circular shift register group are mapped to the high-value frequency points in the FFT / IFFT calculation results of the third loop. The corresponding amplitude is compared with the threshold passed by the threshold selection module. Frequency points with amplitudes less than the threshold and high bits of 0 are eliminated to obtain candidate frequency points.

[0065] Step D, Figure 8 The structure diagram of the result calculation module is shown below. The real and imaginary parts of each candidate frequency point are inserted and sorted, and the median value is taken as the final amplitude of that frequency point. Then, all candidate frequency points are sorted according to their amplitude, and the four largest ones are selected as the final large value frequency points. At the same time, the chirp2 signal is generated, and the amplitude of the large value frequency points is frequency tuned to obtain the final calculation result.

[0066] Table 1 shows the hardware resource consumption in this embodiment. I / O resource consumption is relatively high, but it does not increase significantly with the increase of N. Meanwhile, using DDR3 memory chips for data caching greatly reduces BRAM resource consumption.

[0067] Table 1:

[0068]

[0069] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A sparse fractional Fourier transform FPGA implementation method, characterized in that: Includes the following steps: Step 1: Preprocess the signal of length N to convert it into a signal of length B; Step 2: Perform FFT / IFFT transformation on the signal of length B; Step 3: Perform insertion sort on the data transformed in Step 2 and select the threshold. Step 4: Filter candidate frequency points based on the threshold output in Step 3; Step 5: Perform insertion sort to determine the amplitude corresponding to each candidate frequency point selected in Step 4. Then sort the candidate frequency points with determined amplitudes according to the amplitude size, filter out the frequency points with large values, and finally tune the filtered results to obtain the final calculation result. Thus, from step 1 to step 5, a method for implementing sparse fractional Fourier transform on an FPGA has been completed. The implementation process of step 1 is as follows: Step 1.1: Acquire the input signal Using the chirp1 signal to analyze the input signal Perform frequency modulation operation to obtain The signal, specifically: Step 1.1A: Calculate the rotation angle based on the order p of the sparse fractional Fourier transform input from the host computer. ,and Then, the Cordic-IP core is called in the FPGA to generate the chirp1 signal; Step 1.1B: Set an input counter at the input terminal of the data preprocessing module, and then use the input signal... The quantity is counted to control the input signal. Quantity; Step 1.1C: Input signal Multiplying the signal by the chirp1 signal yields the signal. Input signal and The length of each signal is N; Step 1.2: Process the signal acquired in Step 1.1C Buffering, specifically: Buffering the signal A signed number extension operation is performed to expand the data bit width to the same as the data bus width of the DDR3 memory chip before it is sent into the asynchronous FIFO. Then, the DDR3 control module reads the signal from the asynchronous FIFO that has completed the extension operation. Then, it is written sequentially to the DDR3 memory chip in the form of burst write; Step 1.3: Signal Data spectrum rearrangement, filtering, and aliasing are performed, specifically as follows: Step 1.3A: Based on the signal The signal is calculated at the storage location of the DDR3 memory chip. The storage location of each point after rearrangement and the storage location after aliasing; Signal The storage location multiplied by the randomly generated spectral rearrangement coefficient The calculation result is modulo the length N to obtain the signal. The storage location of each point after rearrangement, and the signal The storage location after aliasing is obtained by taking the modulo of the length B after rearrangement. Step 1.3B: Recall the RAM to store the signal of length B obtained after the aliasing operation is completed; In the L-round cycle of the SFrFT system, the first round of the cycle will... While caching the signal into the DDR3 memory chip Parallel execution Round-spectrum rearrangement, filtering, and aliasing operations are performed to obtain... A data slice of length B; in the second to the... In the first iteration of the loop, only the result of the aliasing calculation is output; in the second iteration... In the round-robin process, the DDR3 control module reads data from the DDR3 memory chip and writes it into the FIFO. Then, a truncation operation is performed on the signed number to obtain the original bit-width signal. Then execute in parallel The program performs spectrum rearrangement, filtering, and aliasing operations in one round, and outputs only the first digit in the remaining rounds of the loop. The result of the cyclic aliasing calculation.

2. The FPGA implementation method for sparse fractional Fourier transform according to claim 1, characterized in that, The implementation process of step 2 is as follows: Perform an FFT / IFFT transform on the signal of length B stored in RAM from step 1.3B to obtain the calculation result. The FFT / IFFT transformation is implemented by calling the FFT-IP core.

3. The FPGA implementation method for sparse fractional Fourier transform according to claim 2, characterized in that, The implementation process of step 3 is as follows: Step 3.1: Obtain two identical amplitude register groups, each containing K registers. Each amplitude register group also corresponds to an indicator signal with a bit width of Kbit, and the bits of the indicator signal correspond one-to-one with the registers in the amplitude register group. Step 3.2: Calculation results obtained in Step 2 The coordinates are serially input into the amplitude register group, and after B clock cycles, the calculation result is obtained. The values ​​will be fully input into the amplitude register set; the first amplitude register of each clock cycle will receive the calculation result. A value is given, and this value is compared with the magnitude of the data stored in the first magnitude register group. If the magnitude of this value is greater than the magnitude of the data stored at a certain position in the first magnitude register group, the bit at the corresponding position of the indicator signal will be set to 1; otherwise, it will be set to 0. After the comparison is complete, if the indicator signal is not 0, the value is inserted into the corresponding register in the first amplitude register group based on the number of 1 bits in the indicator signal. The value discarded from the first amplitude register group after one comparison is then passed to the second amplitude register group. If the indicator signal is 0, the value is compared with the data stored in the first amplitude register group. The value is passed to the second amplitude register group; Within the same clock cycle, the second amplitude register group performs the same comparison operation; ultimately, the 2K values ​​remaining in the two register groups are the largest 2K values ​​arranged in descending order of amplitude, representing the result of the FTT / IFFT calculation for this round of the loop. The high-frequency points selected from the data; Step 3.3: Pass the value with the smallest amplitude in the second amplitude register group as the threshold to the candidate frequency filtering module, and output the frequency points of all values ​​stored in the two amplitude register groups to the candidate frequency filtering module.

4. The FPGA implementation method for sparse fractional Fourier transform according to claim 3, characterized in that, The implementation process of step 4 is as follows: Step 4.1: In the first loop, the calculation result passed from Step 3 is used... The high-value frequency points selected in the process are restored to their original frequency points and stored in the frequency point register group of the candidate frequency point selection module; Step 4.2: In the second round of the loop, the large frequency points passed from Step 3 are restored to the original frequency points and stored in the circular shift register group of the candidate frequency point screening module. Then, the frequency point register group is compared with the original frequency points stored in the circular shift register group. If there are the same frequency points in the frequency point register group and the circular shift register group, the frequency point at the corresponding storage position in the circular shift register group is cleared and the highest bit of the corresponding storage position in the frequency point register group is pulled high. Step 4.3: In the third loop, the original frequency points stored in the frequency point register group and the circular shift register group are mapped to the FFT / IFFT calculation results of step 3 of this loop. The corresponding amplitude is compared with the threshold passed from step 3 of the third loop. The original frequency points with amplitudes less than the threshold and with the highest bit low are eliminated. The filtered frequency points and the corresponding amplitudes generated in each loop are passed to the result calculation module for sorting and estimation.

5. The FPGA implementation method for sparse fractional Fourier transform according to claim 4, characterized in that, The sorting in step 5 is specifically as follows: Step 5.1: Sort the real and imaginary parts of each frequency point separately, and select the median as the final amplitude of the frequency point; Step 5.2: Sort all candidate frequency points with determined amplitudes according to their amplitude values, and select the K largest amplitude points as the final high-value frequency points; Step 5.3: Based on the final high-frequency point selected, the chirp2 signal generated by the Cordic-IP core is multiplied with it to obtain the final calculation result.

6. A sparse fractional Fourier transform FPGA implementation system, characterized in that, The system is used in any one of the sparse fractional Fourier transform FPGA implementation methods according to claims 1-5, wherein the system is implemented by an FPGA, and the FPGA includes a Cordic-IP core, a data preprocessing module, an asynchronous FIFO, a DDR3 control module, RAM, an amplitude register group, and a candidate frequency point screening module.

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