Miniaturized multi-channel multi-task integrated radio frequency real-time signal processor

Abstract

This invention provides a miniaturized, multi-channel, multi-task integrated real-time radio frequency signal processor, comprising six boards and one backplane. The six boards are divided into two functional types: an integrated radio frequency control and interface card, and an integrated radio frequency acquisition and processing card. This invention employs highly integrated and general-purpose modular SIP design technology. Each integrated radio frequency acquisition and preprocessing card includes one signal acquisition and preprocessing SIP module and one high-performance digital signal processing SIP module, reducing the number and types of components, effectively lowering the number of boards and the power consumption of a single unit. Adopting an integrated radio frequency signal and information processing approach, it can meet the requirements of multiple working modes operating simultaneously. Using multi-source data fusion technology, it achieves information interaction between multiple working modes and fusion-based decision-making. This invention features high hardware integration, integrated multi-source radio frequency signal collaborative processing, stable high-speed signal transmission, easy expansion of the entire unit, and can meet the requirements of simultaneous processing in multiple working modes.

Description

Technical Field

[0001] This invention relates to the field of electrical components technology, specifically to a miniaturized multi-channel, multi-task integrated radio frequency real-time signal processor. Background Technology

[0002] With the rapid development of information technology, the requirements for high-speed signal acquisition and processing are constantly increasing. Due to comprehensive considerations of performance, cost, power consumption, etc., high-speed signal processors are developing towards miniaturization and high integration.

[0003] However, traditional processing systems are characterized by limited functionality, fragmented architecture, high resource consumption, large size, low data processing efficiency, and poor information integration. Therefore, there is an urgent need for an integrated processing system that is compact, multifunctional, and capable of achieving miniaturization, high power density, high bandwidth transmission, and multi-channel processing. Summary of the Invention

[0004] This invention addresses the problems of traditional processing systems, such as limited functionality, fragmented architecture, high resource consumption, large size, low data processing efficiency, and poor information integration. It provides a miniaturized, multi-channel, multi-task integrated real-time radio frequency signal processor. This processor enables multi-channel, high-bandwidth acquisition / processing, multi-channel analog signal transmission, multi-mode big data processing, multi-mode information fusion, and multi-interface, multi-speed data transmission. Through optimized design, it significantly reduces size and weight, substantially improves digital signal processing performance, and thus better meets diverse application needs.

[0005] This invention provides a miniaturized multi-channel multi-task integrated radio frequency real-time signal processor, comprising interconnected first integrated radio frequency acquisition and processing card, second integrated radio frequency acquisition and processing card, third integrated radio frequency acquisition and processing card, fourth integrated radio frequency acquisition and processing card, fifth integrated radio frequency acquisition and processing card, integrated radio frequency control and interface card, and backplane;

[0006] The first, second, third, fourth, and fifth integrated radio frequency acquisition and processing cards all have the same structure, including a signal acquisition and preprocessing SIP module and a high-performance digital signal processing SIP module.

[0007] The signal acquisition and preprocessing SIP module includes a SIP-packaged FPGA bare chip, an ADC bare chip, a DAC bare chip, and a FLASH bare chip; the high-performance digital signal processing SIP module includes two SIP-packaged DSP bare chips, a FLASH bare chip, and at least two DDR bare chips.

[0008] The signal acquisition and preprocessing SIP module converts the intermediate frequency signal received by the RF system into a digital intermediate frequency signal through the ADC bare chip and outputs it to the FPGA bare chip. The FPGA bare chip performs digital down-conversion to form a digital baseband signal and outputs it to the integrated RF control and interface card and the high-performance digital signal processing SIP module on the board. The DAC bare chip generates an intermediate frequency signal based on the received parameter information and outputs it to the RF system.

[0009] The high-performance digital signal processing SIP module uses two bare DSP chips to perform real-time digital processing on the digital baseband signal output from the signal acquisition and preprocessing SIP module, and outputs the processing results to the integrated RF control and interface card through the backplane.

[0010] The miniaturized multi-channel multi-task integrated radio frequency real-time signal processor of the present invention, as a preferred embodiment, includes working mode one, working mode two, working mode three and working mode four;

[0011] In working mode one, the first integrated radio frequency acquisition and processing card performs analog-to-digital conversion and digital down-conversion on the intermediate frequency signal sent by the frequency conversion system to obtain the first digital baseband echo signal. After digital signal processing, the signal is output to the integrated radio frequency control and interface card for result reporting and echo recording and storage.

[0012] In working mode two, the second and third integrated RF acquisition and processing cards work simultaneously. They receive the intermediate frequency signal from the frequency conversion system through the bare ADC chip packaged in the signal acquisition and preprocessing SIP module on the board and output it to the FPGA chip packaged in the module. After digital down-conversion processing, the second and third digital baseband echo signals are generated respectively. The third integrated RF acquisition and processing card fuses the third and second digital baseband echo signals to obtain the fourth digital baseband echo signal. The second integrated RF acquisition and processing card fuses the second and third digital baseband echo signals to obtain the fifth digital baseband echo signal. The fourth and fifth digital baseband echo signals are both output to the integrated RF control and interface card for fusion processing, result reporting, and echo recording storage.

[0013] In working mode three, the integrated RF control and interface card receives the data processing results from working mode one, makes a decision, and outputs the decision results through the backplane to the high-performance digital signal processing SIP module of the fourth integrated RF acquisition and processing card. After signal analysis algorithm processing, the transmission signal parameters are formed and output to the signal acquisition preprocessing SIP module on the fourth integrated RF acquisition and processing card. The FPGA bare chip in the module generates a digital intermediate frequency signal according to the parameters and passes it to the DAC bare chip in the module. After digital-to-analog conversion, the intermediate frequency signal is obtained and output to the frequency conversion system.

[0014] In working mode four, the fifth integrated radio frequency acquisition and processing card waits for the backplane to output instructions and parameter information and forms a transmission signal as required.

[0015] The miniaturized multi-channel, multi-task integrated real-time radio frequency signal processor of this invention, in preferred mode, in operating mode one, the first integrated radio frequency acquisition and processing card receives the intermediate frequency signal sent by the frequency conversion system through the ADC bare chip packaged in the signal acquisition and preprocessing SIP module on the board and outputs it to the FPGA chip packaged in the module. After digital down-conversion processing, the first digital baseband echo signal is obtained. The first digital baseband echo signal is divided into two paths. One path is transmitted to the DSP bare chip packaged in the high-performance digital signal processing SIP module through the SRIO high-speed port on the board for digital signal processing. The processed result is transmitted to the integrated radio frequency control and interface card through the internal interface circuit of the high-performance digital signal processing SIP module, completing the result reporting in operating mode one. The other path is transmitted to the integrated radio frequency control and interface card and sent to the solid-state memory through the photoelectric conversion module on the board, completing the echo recording and storage in operating mode one.

[0016] The miniaturized multi-channel multi-task integrated real-time signal processor of the present invention, in preferred mode two, divides the fourth digital baseband echo signal into two paths. One path is transmitted to the on-board high-performance digital signal processing SIP module for digital signal processing, and the processing result is transmitted through the backplane to the high-performance digital signal processing SIP module of the integrated RF control and interface card for data fusion. The other path is directly transmitted to the FPGA chip of the integrated RF control and interface card for echo storage.

[0017] The fifth digital baseband echo signal is divided into two paths. One path is transmitted to the high-performance digital signal processing SIP module on the board for digital signal processing, and the processing result is transmitted to the high-performance digital signal processing SIP module of the integrated RF control and interface card through the backplane for data fusion. The other path is directly transmitted to the FPGA chip of the integrated RF control and interface card for echo storage.

[0018] The high-performance digital signal processing SIP module of the integrated radio frequency control and interface card receives the processing results reported by the second and third integrated radio frequency acquisition and processing cards, performs data fusion processing, and then reports them to the control system.

[0019] The miniaturized multi-channel multi-task integrated radio frequency real-time signal processor of the present invention, as a preferred embodiment, in working mode one, has 8 intermediate frequency signals output from the frequency conversion system to the first integrated radio frequency acquisition and processing card;

[0020] In working mode two, 12 acquisition channels and 1 upconversion channel are used;

[0021] Working mode 3 and working mode 1 share the same data acquisition channel and use 2 transmission channels; working mode 4 uses 1 transmission channel.

[0022] After power-on, the integrated RF control and interface card receives the wake-up command from the system and outputs it to each board through the interface circuit. Each board reports its self-test results and sends them to the high-performance digital signal processing SIP module. After analysis, if the self-test of each board is normal, the integrated RF control and interface card sends a start command to each board, and each board starts working.

[0023] The miniaturized, multi-channel, multi-task integrated real-time radio frequency signal processor of this invention, as a preferred embodiment, integrates a radio frequency control and interface card to receive instructions from an external control system and perform comprehensive control and overall resource scheduling of the entire machine; performs system power consumption control and generates a system reset signal; sends echo data from various operating modes to a solid-state memory; monitors the operating status of each board and reports abnormal operating states; performs system power consumption control; controls external devices of the system; loads unified programs for each board; receives external analog detection signals; receives echo data from the integrated radio frequency acquisition and processing card; receives processing results from the integrated radio frequency acquisition and processing card; outputs processing results, raw echo information, and self-test information to the control system; and synchronizes with the test equipment in time.

[0024] The miniaturized multi-channel multi-task integrated real-time signal processor of the present invention, as a preferred embodiment, includes an integrated RF control and interface card comprising an FPGA chip and a high-performance digital signal processing SIP module; the FPGA chip receives working instructions and data issued by the control system according to the interface form specified in the protocol and places the data at the address specified in the protocol to realize the transparent transmission of instruction data; the FPGA chip receives echo data from other boards through the backplane and transmits the echo data to the control system according to the requirements of the fiber optic Glink protocol.

[0025] The miniaturized multi-channel multi-task integrated radio frequency real-time signal processor of the present invention, in a preferred embodiment, uses a backplane to transmit signals and perform high- and low-speed data communication between the first integrated radio frequency acquisition and processing card, the second integrated radio frequency acquisition and processing card, the third integrated radio frequency acquisition and processing card, the fourth integrated radio frequency acquisition and processing card, the fifth integrated radio frequency acquisition and processing card, and the integrated radio frequency control and interface card via a VPX connector, and sends the reported data to the control system according to the connector and node definitions of the control system.

[0026] The backplane provides 12V DC power to the first integrated RF acquisition and processing card, the second integrated RF acquisition and processing card, the third integrated RF acquisition and processing card, the fourth integrated RF acquisition and processing card, the fifth integrated RF acquisition and processing card, and the integrated RF control and interface card.

[0027] The miniaturized multi-channel multi-task integrated real-time signal processor of the present invention, as a preferred embodiment, has an ADC bare chip of the signal acquisition and preprocessing SIP module that is a high-bandwidth, high-speed sampling chip with a single-channel sampling rate of not less than 3.2 Gsps and an A / D bit depth of 12 bits; the instantaneous sampling rate of the ADC bare chip is not less than 40 Gsps; and the DAC bare chip has a single-channel 14-bit DAC and a D / A bit depth of 16 bits.

[0028] The signal processor has 40 acquisition channels, 5 transmission channels, a computing power of 1536 GFLOPS, an equivalent total number of logic gates of over 100 million, and a high-speed data transmission rate of ≥20Gbps.

[0029] The miniaturized multi-channel multi-task integrated radio frequency real-time signal processor of the present invention, in a preferred embodiment, further includes a shell connected to the first integrated radio frequency acquisition and processing card, the second integrated radio frequency acquisition and processing card, the third integrated radio frequency acquisition and processing card, the fourth integrated radio frequency acquisition and processing card, the fifth integrated radio frequency acquisition and processing card, the integrated radio frequency control and interface card, and the backplane.

[0030] The integrated radio frequency control and interface card, the first integrated radio frequency acquisition and processing card, the second integrated radio frequency acquisition and processing card, the third integrated radio frequency acquisition and processing card, the fourth integrated radio frequency acquisition and processing card, and the fifth integrated radio frequency acquisition and processing card are arranged from top to bottom in sequence, and the back panel is connected to the side of the first integrated radio frequency acquisition and processing card, the second integrated radio frequency acquisition and processing card, the third integrated radio frequency acquisition and processing card, the fourth integrated radio frequency acquisition and processing card, the fifth integrated radio frequency acquisition and processing card, and the integrated radio frequency control and interface card;

[0031] The backplate is a VPX backplate.

[0032] This invention discloses a miniaturized, multi-mode, multi-channel, multi-task integrated real-time radio frequency signal processor, comprising: 6 boards and 1 backplane. The 6 boards are divided into two functional types: an integrated radio frequency control and interface card and an integrated radio frequency acquisition and processing card. This invention implements signal acquisition and processing functions on a single board, employing highly integrated and general-purpose modular SIP advanced design technology. Each integrated radio frequency acquisition and preprocessing card includes one signal acquisition and preprocessing SIP module and one high-performance digital signal processing SIP module, reducing the number and types of components, effectively lowering the number of boards and single-unit power consumption. Adopting an integrated radio frequency signal and information processing approach, it can meet the requirements of multiple working modes operating simultaneously. Multi-source data fusion technology is used to achieve information interaction between multiple working modes, and the results are fused for decision-making. This invention features high hardware integration, integrated multi-source radio frequency signal collaborative processing, stable high-speed signal transmission, easy expansion of the entire machine, and can meet the requirements of simultaneous processing of multiple working modes.

[0033] This invention provides a miniaturized, multi-mode, multi-channel, multi-tasking integrated real-time radio frequency signal processor. It employs advanced technologies such as SIP microsystem packaging, high-bandwidth multi-channel high-speed analog signal transmission and acquisition, ultra-high-speed direct RF acquisition, high-speed serial data exchange, and hardware-software co-implementation of complex interfaces and algorithms to support multi-channel, multi-tasking, and multi-mode collaborative operation. The system achieves high-speed real-time digital signal processing through a high-performance digital signal processing multi-core array and a large-scale FPGA, and is based on a standard 3U VPX board design, further enhancing compatibility, scalability, and system performance.

[0034] The present invention has the following advantages:

[0035] (1) High-density multi-channel integrated design: It adopts 20 AD acquisition and 5 DA transmission to realize efficient acquisition and transmission of multi-channel, large bandwidth signals, which significantly improves the system processing capability.

[0036] (2) Multi-task parallel processing capability: Supports simultaneous execution of four working modes. Combined with modular board design, it achieves flexible configuration and efficient collaboration, meeting diverse needs in complex scenarios. It enables accurate extraction and efficient fusion of multi-dimensional information in complex environments, and the system possesses high information perception capability and decision-making accuracy.

[0037] (3) By adopting SIP technology, multi-channel, high-bandwidth, and high-density functional integration is achieved, reducing the types of boards, significantly reducing the system size, and improving overall performance. Based on the standard 3U VPX board architecture, the system's compatibility, scalability, and ease of maintenance are enhanced, enabling it to quickly adapt to the needs of various application scenarios. Attached Figure Description

[0038] Figure 1This is an architecture diagram of a miniaturized, multi-channel, multi-task integrated real-time radio frequency signal processor;

[0039] Figure 2 This is a structural diagram of a miniaturized, multi-channel, multi-task integrated real-time radio frequency signal processor.

[0040] Figure 3 A block diagram of a miniaturized, multi-channel, multi-task integrated real-time radio frequency signal processor, comprising a comprehensive radio frequency acquisition and processing card.

[0041] Figure 4 A block diagram of a miniaturized, multi-channel, multi-task integrated real-time signal processor with integrated radio frequency control and interface card (6 blocks).

[0042] Figure 5 This is a block diagram of a signal acquisition and preprocessing SIP module for a miniaturized, multi-channel, multi-task integrated real-time radio frequency signal processor.

[0043] Figure 6 This is a block diagram of a high-performance digital signal processing SIP module for a miniaturized, multi-channel, multi-task integrated radio frequency real-time signal processor;

[0044] Figure 7 This is a schematic diagram of the structure of a miniaturized, multi-channel, multi-task integrated radio frequency real-time signal processor;

[0045] Figure 8 This is a physical image of a miniaturized, multi-channel, multi-task integrated radio frequency real-time signal processor.

[0046] Figure label:

[0047] 1. First integrated RF acquisition and processing card; 2. Second integrated RF acquisition and processing card; 3. Third integrated RF acquisition and processing card; 4. Fourth integrated RF acquisition and processing card; 5. Fifth integrated RF acquisition and processing card; 6. Integrated RF control and interface card; 7. Backplane; 8. Housing. Detailed Implementation

[0048] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Example 1

[0049] like Figures 1-8 As shown, a miniaturized multi-channel multi-task integrated radio frequency real-time signal processor includes one integrated radio frequency control and interface card 6, five integrated radio frequency acquisition and processing cards, a backplane 7 for high-speed signal transmission and power supply between the cards, and a shell 8 that covers all the cards.

[0050] The integrated radio frequency acquisition and processing card includes a first integrated radio frequency acquisition and processing card 1, a second integrated radio frequency acquisition and processing card 2, a third integrated radio frequency acquisition and processing card 3, a fourth integrated radio frequency acquisition and processing card 4, and a fifth integrated radio frequency acquisition and processing card 5.

[0051] Integrated RF Control and Interface Card 6: Receives commands from the external control system and performs comprehensive control and overall resource scheduling of the entire system; controls system power consumption and generates a system reset signal; sends echo data from various operating modes to solid-state storage; monitors the operating status of each board and reports abnormal operating states; controls system power consumption; controls external devices; loads unified programs onto each board; receives external analog signals; receives echo data from the integrated RF acquisition and processing card; receives processing results from the integrated RF acquisition and processing card; outputs processing results, raw echo information, and self-test information to the control system; and synchronizes with the test equipment.

[0052] Integrated RF Acquisition and Processing Card: Receives operating mode commands and parameters; sends operating mode status and self-test results; receives intermediate frequency (IF) signals in operating mode, enabling high-speed acquisition of multiple IF echo signals and performing preprocessing such as digital down-conversion and filtering; receives time alignment signals and performs time synchronization; transmits echo signals to Integrated RF Control and Interface Card 6 via a high-speed interface; generates active radar transmit IF signals; generates and receives multi-channel self-calibrating IF signals; and performs real-time echo signal processing internally to obtain echo signal inversion information.

[0053] Backplane 7 is a VPX standard backplane: it enables high-speed and low-speed data transmission between boards, provides 12V DC power, and powers each board.

[0054] The first integrated RF acquisition and processing card 1, the second integrated RF acquisition and processing card 2, the third integrated RF acquisition and processing card 3, the fourth integrated RF acquisition and processing card 4, and the fifth integrated RF acquisition and processing card 5 all include a signal acquisition and preprocessing SIP module and a high-performance digital signal processing SIP module. The signal acquisition and preprocessing SIP module uses SIP technology to encapsulate an FPGA bare chip, an ADC bare chip, a DAC bare chip, and a FLASH bare chip within a single SIP module. The high-performance digital signal processing SIP module uses SIP technology to encapsulate two DSP bare chips, a DDR bare chip, and a FLASH bare chip within a single SIP module.

[0055] The signal acquisition and preprocessing SIP module uses an ADC bare chip to convert the intermediate frequency (IF) signal received by the RF system into a digital IF signal, which is then transmitted to the FPGA bare chip. The FPGA bare chip performs digital down-conversion to generate a digital baseband signal, which is then transmitted to the integrated RF control and interface card 6 and the high-performance digital signal processing SIP module on the board. The DA chip generates an IF signal based on the received parameter information and outputs it to the RF system.

[0056] The high-performance digital signal processing SIP module uses two bare DSP chips to perform real-time digital processing on the digital baseband signal transmitted from the signal acquisition and preprocessing SIP module, and transmits the processing results to the integrated RF control and interface card 6 through the backplane.

[0057] The integrated RF control and interface card 6 includes an FPGA chip and a high-performance digital signal processing SIP module. The FPGA chip receives operating commands and data from the control system according to the interface format specified in the protocol, and places the data at the addresses specified in the protocol to achieve transparent transmission of commands and data. The FPGA chip receives echo data from other boards through the backplane and transmits the echo data to the control system according to the fiber optic Glink protocol requirements.

[0058] The high-performance digital signal processing SIP module analyzes the instructions issued by the control system through the DSP bare chip, receives the working status and other information reported by each board and reports them to the control system. At the same time, it can perform data fusion on the processing results of each board.

[0059] The signal processing backplane uses VPX connectors to transmit signals and communicate high and low speed data between various boards inside the processor. It also sends the reported data to the control system according to the connector and node definitions of the control system.

[0060] The signal acquisition and preprocessing SIP module's AD bare chip is a high-bandwidth, high-speed sampling chip with a single-channel sampling rate of no less than 3.2Gsps and an A / D bit depth of 12 bits; the ultra-high-speed RF direct sampling AD bare chip has an instantaneous sampling rate of no less than 40Gsps; the DA bare chip is a single-channel 14-bit chip with a D / A bit depth of 16 bits, and the first FPGA chip is a K7 series chip; the high-performance digital signal processing SIP module's DSP bare chip is a TMS320C6678.

[0061] A miniaturized, multi-mode, multi-channel, multi-task integrated real-time radio frequency signal processor has 40 acquisition channels, 5 transmission channels, a computing power of 1536 GFLOPS, an equivalent total number of logic gates of over 100 million, and a high-speed data transmission rate of ≥20Gbps, which can meet the requirements of simultaneous operation of multiple tasks and multiple modes.

[0062] This invention proposes a miniaturized, multi-mode, multi-channel, multi-task integrated real-time radio frequency signal processor. This invention implements signal acquisition and processing functions on a single board, employing advanced general-purpose modular SIP design technology. Each integrated RF acquisition and preprocessing card contains one signal acquisition and preprocessing SIP module and one high-performance digital signal processing SIP module, reducing the number and types of components, effectively lowering the number of boards and the power consumption of a single unit. Adopting an integrated RF signal and information processing approach, it can meet the requirements of multiple operating modes operating simultaneously. Multi-source data fusion technology is used to achieve information interaction between multiple operating modes, and the results are fused for decision-making. It features high hardware integration, integrated multi-source RF signal collaborative processing, stable high-speed signal transmission, and easy expansion, meeting the requirements of simultaneous processing in multiple operating modes.

[0063] Taking four working modes operating simultaneously as an example, working mode one requires 8 acquisition channels; working mode two requires 12 acquisition channels plus 1 upconversion channel; working mode three shares acquisition channel information with working mode one and requires 2 transmission channels; working mode four requires 1 transmission channel. Analysis shows that working mode one operates on integrated RF control and interface card 6 and the first integrated RF acquisition and processing card 1; working mode two operates on integrated RF control and interface card 6, the second integrated RF acquisition and processing card 2 (8 acquisition channels), and the third integrated RF acquisition and processing card 3 (4 acquisition channels); working mode three operates on integrated RF control and interface card 6 and the fourth integrated RF acquisition and processing card 4; and working mode four operates on the fifth integrated RF acquisition and processing card 5.

[0064] After powering on, as Figure 4 As shown, the integrated RF control and interface card 6 receives the "wake-up" command from the system and sends the command to each board through the interface circuit. Each board reports its self-test results and sends them to the high-performance digital signal processing SIP module. After analyzing that each board's self-test is normal, the integrated RF control and interface card 6 sends the "start work" command to each board, and each board starts working.

[0065] Working Mode 1: such as Figure 3 and Figure 5The first integrated RF acquisition and processing card 1 shown receives the intermediate frequency signal from the frequency conversion system through the bare ADC chip packaged in the signal acquisition and preprocessing SIP module on the board. It then transmits the signal to the FPGA chip packaged in the module. After digital down-conversion processing, the first digital baseband echo signal is divided into two paths. One path is transmitted through the SRIO high-speed port on the board to the DSP chip packaged in the high-performance digital signal processing SIP module for digital signal processing. The processed result is transmitted through the internal interface circuit of the high-performance digital signal processing SIP module to the integrated RF control and interface card 6 to complete the result reporting of working mode one. The other path is transmitted to the integrated RF control and interface card 6, which sends the echo signal to the solid-state memory through the photoelectric conversion module on the board to complete the echo recording and storage of working mode one.

[0066] Working Mode Two: (e.g.) Figure 3 and Figure 5 The second integrated RF acquisition and processing card 2 and the third integrated RF acquisition and processing card 3, as shown, work simultaneously. They receive the intermediate frequency signal sent by the frequency conversion system through the ADC bare chip packaged in the signal acquisition and preprocessing SIP module on the board, respectively, and transmit it to the FPGA bare chip packaged in the module. After digital down-conversion processing, they generate the second digital baseband echo signal and the third digital baseband echo signal, respectively.

[0067] The second integrated RF acquisition and processing card 2 sends the second digital baseband echo signal to the signal acquisition and preprocessing SIP module of the third integrated RF acquisition and processing card 3 through the high-speed inter-board port. The third integrated RF acquisition and processing card 3 fuses the third digital baseband echo signal generated within its own card board with the second digital baseband echo signal transmitted through the backplane to generate a fourth digital baseband echo signal. This signal is divided into two paths: one path is transmitted to the high-performance digital signal processing SIP module within the board for digital signal processing, and the processing result is transmitted through the backplane to the high-performance digital signal processing SIP module of the integrated RF control and interface card 6 for data fusion; the other path is directly transmitted to the FPGA chip of the integrated RF control and interface card 6 for echo storage.

[0068] The third integrated RF acquisition and processing card 3 sends the digital baseband echo signal 3 to the signal acquisition and preprocessing SIP module of the second integrated RF acquisition and processing card 2 through the high-speed inter-board port. The second integrated RF acquisition and processing card 2 fuses the digital baseband signal 2 generated within its own board with the digital baseband echo signal 3 transmitted through the backplane to generate the fifth digital baseband signal. This signal is divided into two paths: one path is transmitted to the high-performance digital signal processing SIP module within the board for digital signal processing, and the processing result is transmitted through the backplane to the high-performance digital signal processing SIP module of the integrated RF control and interface card 6 for data fusion; the other path is directly transmitted to the FPGA chip of the integrated RF control and interface card 6 for echo storage.

[0069] The high-performance digital signal processing SIP module of the integrated radio frequency control and interface card 6 receives the processing results reported by the second integrated radio frequency acquisition and processing card 2 and the third integrated radio frequency acquisition and processing card 3. After processing by the data fusion algorithm, it reports to the control system, and finally completes the result reporting and echo storage tasks of working mode two.

[0070] Working Mode 3: The integrated RF control and interface card 6 receives the data processing results from Working Mode 1. After making a decision, it sends the decision results to the high-performance digital signal processing SIP module of the fourth integrated RF acquisition and processing card 4 through the backplane. After signal analysis algorithm processing, the transmission signal parameters are formed and passed to the signal acquisition preprocessing SIP module on the fourth integrated RF acquisition and processing card 4. The FPGA bare chip in the module generates a digital intermediate frequency signal according to the parameters and passes it to the DA bare chip in the module. After digital-to-analog conversion, the intermediate frequency signal is formed and passed to the frequency conversion system.

[0071] Working Mode 4: The fifth integrated radio frequency acquisition and processing card 5 waits for instructions and parameter information sent from the backplane and forms a transmission signal as required.

[0072] The performance metrics of this system are as follows:

[0073] (1) High-speed data transmission rate between boards: ≥20Gbps;

[0074] (2) High-speed data interaction rate between onboard processing chips: ≥20Gbps;

[0075] (3) Real-time computing power: ≥1024 GFLOPS;

[0076] (4) Data caching capacity: ≥124Gbit;

[0077] (5) Number of intermediate frequency acquisition channels: 40 channels;

[0078] (6) Number of intermediate frequency transmission channels: 5 channels;

[0079] (7) ADC single-channel sampling rate: ≥3.2GSPS;

[0080] (8) ADC sampling accuracy: ≥12 bits;

[0081] (9) DAC sampling rate: ≥3.2GHz;

[0082] (10) DAC sampling accuracy: ≥16 bits;

[0083] (11) RF direct sampling AD sampling rate: ≥40GSPS;

[0084] (12) RF direct sampling AD sampling accuracy: 1 bit.

[0085] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A miniaturized, multi-channel, multi-task integrated radio frequency real-time signal processor, characterized in that: The system includes an interconnected first integrated radio frequency acquisition and processing card (1), a second integrated radio frequency acquisition and processing card (2), a third integrated radio frequency acquisition and processing card (3), a fourth integrated radio frequency acquisition and processing card (4), a fifth integrated radio frequency acquisition and processing card (5), an integrated radio frequency control and interface card (6), and a backplane (7). The first integrated radio frequency acquisition and processing card (1), the second integrated radio frequency acquisition and processing card (2), the third integrated radio frequency acquisition and processing card (3), the fourth integrated radio frequency acquisition and processing card (4), and the fifth integrated radio frequency acquisition and processing card (5) all have the same structure, and all include a signal acquisition and preprocessing SIP module and a high-performance digital signal processing SIP module. The signal acquisition and preprocessing SIP module includes a SIP-packaged FPGA bare chip, an ADC bare chip, a DAC bare chip, and a FLASH bare chip; the high-performance digital signal processing SIP module includes two SIP-packaged DSP bare chips, a FLASH bare chip, and at least two DDR bare chips. The signal acquisition and preprocessing SIP module converts the intermediate frequency signal received by the radio frequency system into a digital intermediate frequency signal through the ADC bare chip and outputs it to the FPGA bare chip. The FPGA bare chip performs digital down-conversion to form a digital baseband signal and outputs it to the integrated radio frequency control and interface card (6) and the high-performance digital signal processing SIP module on the board. The bare DAC chip generates an intermediate frequency signal based on the received parameter information and outputs it to the radio frequency system; The high-performance digital signal processing SIP module performs real-time digital processing on the digital baseband signal output by the signal acquisition and preprocessing SIP module through two DSP bare chips and outputs the processing result to the integrated radio frequency control and interface card (6) through the backplane (7). The miniaturized, multi-channel, multi-task integrated real-time RF signal processor adopts 20-channel AD acquisition and 5-channel DA transmission to achieve efficient acquisition and transmission of multi-channel, high-bandwidth signals, and supports simultaneous execution of 4 working modes.

2. The miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 1, characterized in that: The signal processor includes operating mode one, operating mode two, operating mode three, and operating mode four; When working mode one, the first integrated radio frequency acquisition and processing card (1) converts the intermediate frequency signal sent by the frequency conversion system into an analog-to-digital signal and then performs digital down-conversion to obtain the first digital baseband echo signal. After digital signal processing, it outputs the signal to the integrated radio frequency control and interface card (6) for result reporting and echo recording storage. In working mode two, the second integrated radio frequency acquisition and processing card (2) and the third integrated radio frequency acquisition and processing card (3) work simultaneously. They receive the intermediate frequency signal sent by the frequency conversion system through the ADC bare chip packaged in the signal acquisition and preprocessing SIP module on the board and output it to the FPGA bare chip packaged in the module. After digital down-conversion processing, the second digital baseband echo signal and the third digital baseband echo signal are generated respectively. The third integrated radio frequency acquisition and processing card (3) fuses the third digital baseband echo signal with the second digital baseband echo signal to obtain the fourth digital baseband echo signal. The second integrated radio frequency acquisition and processing card (2) fuses the second digital baseband echo signal with the third digital baseband echo signal to obtain the fifth digital baseband echo signal. The fourth digital baseband echo signal and the fifth digital baseband echo signal are both output to the integrated radio frequency control and interface card (6) for fusion processing, result reporting and echo recording storage. In working mode three, the integrated radio frequency control and interface card (6) receives the data processing result of working mode one, makes a decision, and outputs the decision result through the backplane (7) to the high-performance digital signal processing SIP module of the fourth integrated radio frequency acquisition and processing card (4). After processing by the signal analysis algorithm, the transmission signal parameters are formed and output to the signal acquisition preprocessing SIP module on the fourth integrated radio frequency acquisition and processing card (4). The FPGA bare chip in the module generates a digital intermediate frequency signal according to the parameters and transmits it to the DAC bare chip in the module. After digital-to-analog conversion, the intermediate frequency signal is obtained and output to the frequency conversion system. In working mode four, the fifth integrated radio frequency acquisition and processing card (5) waits for the backplane (7) to output instructions and parameter information and forms a transmission signal as required.

3. The miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 2, characterized in that: In working mode one, the first integrated RF acquisition and processing card (1) receives the intermediate frequency signal sent by the frequency conversion system through the ADC bare chip packaged in the signal acquisition and preprocessing SIP module on the board and outputs it to the FPGA bare chip packaged in the module. After digital down-conversion processing, the first digital baseband echo signal is obtained. The first digital baseband echo signal is divided into two paths. One path is transmitted to the DSP bare chip packaged in the high-performance digital signal processing SIP module through the SRIO high-speed port on the board for digital signal processing. The processed result is transmitted to the integrated RF control and interface card (6) through the internal interface circuit of the high-performance digital signal processing SIP module to complete the result reporting of working mode one. The other path is transmitted to the integrated RF control and interface card (6) and the echo signal is sent to the solid-state memory through the photoelectric conversion module on the board to complete the echo recording and storage of working mode one.

4. A miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 2, characterized in that: In working mode two, the fourth digital baseband echo signal is divided into two paths. One path is transmitted to the high-performance digital signal processing SIP module on the board for digital signal processing and the processing result is transmitted through the backplane (7) to the high-performance digital signal processing SIP module of the integrated radio frequency control and interface card (6) for data fusion. The other path is directly transmitted to the FPGA bare chip of the integrated radio frequency control and interface card (6) for echo storage. The fifth digital baseband echo signal is divided into two paths. One path is transmitted to the high-performance digital signal processing SIP module on the board for digital signal processing and the processing result is transmitted to the high-performance digital signal processing SIP module of the integrated radio frequency control and interface card (6) through the backplane (7) for data fusion. The other path is directly transmitted to the FPGA bare chip of the integrated radio frequency control and interface card (6) for echo storage. The high-performance digital signal processing SIP module of the integrated radio frequency control and interface card (6) receives the processing results reported by the second integrated radio frequency acquisition and processing card (2) and the third integrated radio frequency acquisition and processing card (3), performs data fusion processing, and then reports it to the control system.

5. A miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 2, characterized in that: When operating mode 1, the frequency conversion system outputs 8 intermediate frequency signals to the first integrated radio frequency acquisition and processing card (1); In working mode two, 12 acquisition channels and 1 upconversion channel are used; Working mode 3 and working mode 1 share the same data acquisition channel and use 2 transmission channels; working mode 4 uses 1 transmission channel. After power-on, the integrated radio frequency control and interface card (6) receives the wake-up command issued by the system and outputs it to each board through the interface circuit. Each board reports the self-test result and sends it to the high-performance digital signal processing SIP module. After analyzing that each board's self-test is normal, the integrated radio frequency control and interface card (6) issues a start-up command to each board, and each board starts working.

6. A miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 2, characterized in that: The integrated RF control and interface card (6) receives instructions from the external control system and performs integrated control and overall resource scheduling of the entire machine; performs system power consumption control and generates a system reset signal; sends echo data of each working mode to the solid-state memory; monitors the working status of each board and reports abnormal working status; performs system power consumption control; controls external devices of the system; loads unified programs for each board; receives external detection analog quantities; receives echo data from the integrated RF acquisition and processing card; receives processing results from the integrated RF acquisition and processing card; outputs processing results, raw echo information, and self-test information to the control system; and synchronizes with the test equipment time.

7. A miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 1, characterized in that: The integrated radio frequency control and interface card (6) includes an FPGA bare chip and the high-performance digital signal processing SIP module; the FPGA bare chip receives the working instructions and data issued by the control system in accordance with the interface form specified in the protocol and places the data on the address specified in the protocol to realize the transparent transmission of instruction data; the FPGA bare chip receives the echo data of other boards through the backplane (7) and transmits the echo data to the control system in accordance with the requirements of the fiber optic Glink protocol.

8. A miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 1, characterized in that: The backplane (7) transmits signals and performs high- and low-speed data communication between the first integrated radio frequency acquisition and processing card (1), the second integrated radio frequency acquisition and processing card (2), the third integrated radio frequency acquisition and processing card (3), the fourth integrated radio frequency acquisition and processing card (4), the fifth integrated radio frequency acquisition and processing card (5), and the integrated radio frequency control and interface card (6) through the VPX connector, and sends the reported data to the control system according to the control system connector and node definition; The backplane (7) provides 12V DC power to the first integrated radio frequency acquisition and processing card (1), the second integrated radio frequency acquisition and processing card (2), the third integrated radio frequency acquisition and processing card (3), the fourth integrated radio frequency acquisition and processing card (4), the fifth integrated radio frequency acquisition and processing card (5), and the integrated radio frequency control and interface card (6).

9. A miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 1, characterized in that: The ADC bare chip of the signal acquisition and preprocessing SIP module is a high-bandwidth, high-speed sampling chip with a single-channel sampling rate of not less than 3.2 Gsps and an A / D bit depth of 12 bits; the instantaneous sampling rate of the ADC bare chip is not less than 40 Gsps; the DAC bare chip is a single-channel 14-bit chip with a D / A bit depth of 16 bits. The signal processor has 40 acquisition channels, 5 transmission channels, a computing power of 1536 GFLOPS, an equivalent total number of logic gates of over 100 million, and a high-speed data transmission rate of ≥20Gbps.

10. A miniaturized multi-channel multi-task integrated radio frequency real-time signal processor according to claim 1, characterized in that: It also includes a housing (8) connected to the outside of the first integrated radio frequency acquisition and processing card (1), the second integrated radio frequency acquisition and processing card (2), the third integrated radio frequency acquisition and processing card (3), the fourth integrated radio frequency acquisition and processing card (4), the fifth integrated radio frequency acquisition and processing card (5), the integrated radio frequency control and interface card (6), and the backplate (7); The integrated radio frequency control and interface card (6), the first integrated radio frequency acquisition and processing card (1), the second integrated radio frequency acquisition and processing card (2), the third integrated radio frequency acquisition and processing card (3), the fourth integrated radio frequency acquisition and processing card (4), and the fifth integrated radio frequency acquisition and processing card (5) are arranged from top to bottom in sequence, and the back plate (7) is connected to the side of the first integrated radio frequency acquisition and processing card (1), the second integrated radio frequency acquisition and processing card (2), the third integrated radio frequency acquisition and processing card (3), the fourth integrated radio frequency acquisition and processing card (4), the fifth integrated radio frequency acquisition and processing card (5), and the integrated radio frequency control and interface card (6); The backplate (7) is a VPX backplate.

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