A Knowledge Graph-Based FPGA Code Defect Detection Method

Abstract

This invention relates to a knowledge graph-based FPGA code defect detection method, belonging to the field of FPGA verification technology. Compared with traditional FPGA code defect detection methods, the method of this invention has the following advantages: 1. Increased code defect detection rate. By utilizing information such as the software type, module function, and rule violations of the code under test, the knowledge graph can automatically recommend corresponding suspicious defects to testers based on prior knowledge, thereby improving the defect detection capabilities of testers and increasing the code defect detection rate. 2. Strong interpretability and high visualization. The constructed FPGA code defect knowledge graph stores FPGA code defect information in the form of a graph structure, allowing testers to clearly understand the relationships between defects when searching for related defects.

Description

Technical Field

[0001] This invention belongs to the field of FPGA verification technology, specifically relating to an FPGA code defect detection method based on knowledge graphs. Background Technology

[0002] As can be seen from the characteristics of the FPGA design process, the earlier code defects are discovered, the lower the cost of fixing them. Currently, the process for detecting FPGA code defects involves first performing formal verification and rule checks, and then testers further analyzing the software code defects based on the check results. However, the correlation between FPGA code defects and the results of formal verification and rule checks is not clear, so it relies heavily on the testers' testing experience.

[0003] In the era of big data, effectively utilizing massive and chaotic data to transform it into a structured database has become a popular research direction. Knowledge graphs, which represent concepts, entities, and their relationships in the objective world in graph form, possess advantages such as strong interpretability and high search efficiency, and have attracted significant attention from researchers. However, current knowledge graph research in the software field primarily focuses on traditional software, with less attention paid to the area of ​​FPGA code defect detection. Therefore, constructing an FPGA code defect knowledge graph and utilizing it for FPGA code defect detection knowledge retrieval and related defect information recommendation is essential to providing detection experience and knowledge for FPGA code defect detection work. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] The technical problem to be solved by this invention is to construct an FPGA code defect knowledge graph and use the knowledge graph to retrieve FPGA code defect detection knowledge and recommend related defect information, so as to provide detection experience and knowledge for FPGA code defect detection.

[0006] (II) Technical Solution

[0007] To address the aforementioned technical problems, this invention provides a knowledge graph-based FPGA code defect detection method, comprising the following steps:

[0008] Step 1: Construct a knowledge graph of FPGA code defects;

[0009] Step 2: Based on Step 1, perform FPGA code defect detection knowledge retrieval.

[0010] Preferably, in step 1, knowledge extraction is first performed, extracting 10 types of entity data from existing FPGA code defect data, including defect type, severity level, defect description, rule violation, typical case, sample code, software type, module function, development language, and rule number. The entity category is the attribute of the entity. Then, the 10 types of entity data are used to construct an FPGA code defect knowledge graph in the form of (head entity, relation, tail entity) triples. After the construction is completed, it is stored using a graph database.

[0011] Preferably, in step 2, the FPGA code defect knowledge graph is used to help testers identify potential defects based on the characteristics of the test project before formal testing.

[0012] Preferably, in step 2, if the input data is a single entity and the input data exists in the FPGA code defect knowledge graph, then one of the entity data is input: software type, defect type, rule violation, or module function. The FPGA code defect knowledge graph is used to query the data associated with the entity data layer by layer until the entity with the attribute "defect description" is found. The query path is recorded and the knowledge graph formed by the query path is output.

[0013] Preferably, in step 2, the FPGA code defect knowledge graph enables testers to discover unknown defects based on existing defects.

[0014] Preferably, in step 2, if the input data is a single entity but does not exist in the FPGA code defect knowledge graph, then a defect description that does not exist in the FPGA code defect knowledge graph is input based on the actual test results. The key semantics of the input defect description are extracted using natural language processing algorithms. The similarity between the input defect description and all entities in the FPGA code defect knowledge graph is calculated. The entity with the highest similarity and the attribute "defect description" is selected as the mapping of the input statement in the FPGA code defect knowledge graph. Then, the FPGA code defect knowledge graph is used to query the "defect type" associated with the mapped entity, and then other defects associated with the "defect type" are queried. The query path is recorded and the knowledge graph formed by the query path is output.

[0015] Preferably, in step 2, the FPGA code defect knowledge graph is used to recommend suspicious defects and their corresponding typical cases and example code to help testers analyze potential defects and further analyze the FPGA code based on the typical cases and example code.

[0016] Preferably, in step 2, if the input data is a combined entity, FPGA code-related defect information is recommended: based on the information of the test project, multiple data information under the input software type, defect type, rule violation, and module function are combined, and the data associated with each entity data is queried using the FPGA code defect knowledge graph until an entity with the attribute "defect description" is found. The intersection of the defect descriptions corresponding to each entity is taken, and the result is the suspected defect of the input entity combination. Then, the typical cases and example code corresponding to the suspected defect are queried using the FPGA code defect knowledge graph, and the results are saved.

[0017] The present invention also provides a system for implementing the FPFA code defect detection method.

[0018] The present invention also provides an FPGA verification method using the aforementioned FPFA code defect detection method.

[0019] (III) Beneficial Effects

[0020] Compared to traditional FPFA code defect detection methods, the method of this invention has the following advantages:

[0021] 1. Increase code defect detection rate. By utilizing information such as the software type, module function, and rule violations of the code under test, and based on prior knowledge, a knowledge graph can automatically recommend corresponding suspicious defects to testers. This can improve testers' defect detection capabilities and thus increase the code defect detection rate.

[0022] 2. Highly interpretable and visually appealing. The constructed FPGA code defect knowledge graph stores FPGA code defect information in a graph structure, allowing testers to easily understand the relationships between related defects when searching for them. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the knowledge graph structure constructed for this invention;

[0024] Figure 2 This is a schematic diagram illustrating the relevant knowledge of the "interface software" of the present invention;

[0025] Figure 3 This is a schematic diagram illustrating the semantic feedback-related knowledge of the present invention;

[0026] Figure 4 This is a flowchart of the FPGA code defect detection method of the present invention. Detailed Implementation

[0027] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0028] This invention provides a knowledge graph-based FPGA code defect detection method, which is a method for detecting defects in the logic code of programmable devices. The specific steps are as follows:

[0029] 1. Construct a knowledge graph of FPGA code defects.

[0030] First, knowledge extraction is performed. From the existing FPGA code defect data, 10 categories of entity data are extracted, including defect type, severity level, defect description, rule violation, typical case, sample code, software type, module function, development language, and rule number. The entity category is the attribute of the entity.

[0031] Then, the 10 types of entity data are used to construct an FPGA code defect knowledge graph in the form of (head entity, relation, tail entity) triples. The specific knowledge graph structure is as follows: Figure 1 As shown.

[0032] Once constructed, it is stored using a graph database.

[0033] 2. Based on step 1, perform FPGA code defect detection knowledge retrieval.

[0034] If the input data is a single entity and exists in the FPGA code defect knowledge graph, then execute step (1); if the input data is a single entity but does not exist in the FPGA code defect knowledge graph, then execute step (2); if the input data is a combined entity, then execute step (3).

[0035] (1) Input one of the entity data, namely software type, defect type, rule violation, or module function. Use the FPGA code defect knowledge graph to query the data associated with the entity data layer by layer until the entity with the attribute "defect description" is found. Record the query path and output the knowledge graph formed by the query path.

[0036] For example, if a tester inputs data indicating the software type as "interface software," the FPGA code defect knowledge graph can be used to query the path of the FPGA code defect, such as... Figure 2 As shown.

[0037] After the first-level query, the entities associated with "interface software" are divided into three categories: "interface module," "control module," and "timing control module." Since the first-level query does not include entities with the attribute "defect description," a second-level query is performed around these three categories of modules. The query results show that the defects associated with the "timing control module" are "the clock is designed with triple modular redundancy, which is not conducive to timing convergence" and "the module output uses complex combinational logic directly, which may result in unexpected results." The query method for other modules is the same as that for the "timing control module." Since the entity with the attribute "defect description" has been found, the query ends.

[0038] Figure 2 Examples show that using the FPGA code defect knowledge graph, common defects in "interface software" can be found, such as "repeated assignment of the same signal under the same conditions, which can easily cause signal conflicts", "the module output uses complex combinational logic to directly output, which may result in unexpected results", "the use of combinational logic to control tri-state gates can easily cause glitches", and "if statement branches are unreachable". This achieves the goal of helping testers to identify potential defects by understanding the characteristics of the test project before formal testing.

[0039] (2) Input defect descriptions that do not exist in the FPGA code defect knowledge graph based on actual test results. Use natural language processing algorithms to extract the key semantics of the input defect descriptions. Calculate the similarity between the input defect descriptions and all entities in the FPGA code defect knowledge graph. Select the entity with the highest similarity and the attribute "defect description" as the mapping of the input statement in the FPGA code defect knowledge graph. Then use the FPGA code defect knowledge graph to query the "defect type" associated with the mapped entity. Query other defects associated with the "defect type" and record the query path. Output the knowledge graph formed by the query path.

[0040] For example, if the defect description entered by the tester is "data overflow caused program processing error", the entity with the highest similarity and attribute "defect description" calculated using natural language processing algorithm is "data operation overflow situation, calculation result error". According to the FPGA code defect knowledge graph query, its defect type is "data overflow rule". Other defects related to this defect type are "bit width index overflow", "array index overflow", "division by zero operation" and "when using FIFO or RAM to store data, the empty and full storage conditions are not considered". This indicates that the above four defects are other possible suspicious defects in the code.

[0041] Therefore, knowledge graphs can help testers discover unknown defects based on existing defects.

[0042] (3) Recommend information on defects related to FPGA code.

[0043] Based on the information of the test project, multiple data information under the input software type, defect type, rule violation, and module function are combined. The FPGA code defect knowledge graph is used to query the data associated with each entity data until the entity with the attribute "defect description" is found. The intersection of the defect descriptions corresponding to each entity is taken. The result is the suspected defect of the input entity combination. Then, the FPGA code defect knowledge graph is used to query the typical cases and example code corresponding to the suspected defect, and the results are saved.

[0044] For example, if a tester is testing a module whose function is "timing control module", and the rule checking tool results (i.e. rule violation) show that the module violates the rule "it is not advisable to design a triple-mode redundancy clock", the suspected defects recommended by the FPGA code defect knowledge graph and their corresponding typical cases and example code are shown in the table below.

[0045]

[0046] Table 1 Recommended Related Defect Information

[0047] This indicates that the timing control module that violates the rule "it is not advisable to design the clock with triple mode redundancy" may have the defect that "designing the clock with triple mode redundancy is not conducive to timing convergence". Typical cases and example code are shown in Table 1. This can help testers analyze potential defects and further analyze the FPGA code based on typical cases and example code.

[0048] In the example above, "timing control module" corresponds to "module function," and "not suitable for triple-modulus redundancy design of the clock" corresponds to "violation of rules." For example, according to the FPGA code defect knowledge graph query, the defects associated with "timing control module" are "triple-modulus redundancy design of the clock is not conducive to timing convergence" and "the module output uses complex combinational logic directly, which may lead to unexpected results." The defects associated with violating the rule "not suitable for triple-modulus redundancy design of the clock" are "triple-modulus redundancy design of the clock is not conducive to timing convergence" and "an inverter or buffer is inserted in the clock path." Therefore, the intersection of the defect descriptions corresponding to the two entities is "triple-modulus redundancy design of the clock is not conducive to timing convergence." Then, the FPGA code defect knowledge graph is used to query typical cases and example code corresponding to the suspected defect "triple-modulus redundancy design of the clock is not conducive to timing convergence." The query results are shown in Table 1.

[0049] As mentioned above, such as Figure 4As shown, the present invention provides an FPGA code defect detection method based on knowledge graphs, which mainly includes two parts: FPGA code defect detection knowledge retrieval and FPGA code-related defect information recommendation, including the following steps:

[0050] Step [1]: Construct an FPGA code defect knowledge graph and store it using a graph database.

[0051] Step [2]: Testers input data

[0052] If the input is a single item and the input data exists in the knowledge graph:

[0053] Step [3]: Use the knowledge graph to query the data associated with the entity data layer by layer until the entity with the attribute "defect description" is found.

[0054] Step [4]: ​​Output the knowledge graph formed by the query path

[0055] If the input is a single item but the input data does not exist in the knowledge graph:

[0056] Step [3]: Extract key semantics using natural language processing algorithms and calculate the similarity between the input statement and entities in the knowledge graph.

[0057] Step [4]: ​​Select the entity with the highest similarity and the attribute "defect description" as the mapping entity. Step [5]: Use the knowledge graph to query the "defect type" associated with the mapping entity.

[0058] Step [6]: Query other defects associated with the "defect type".

[0059] Step [7]: Output the knowledge graph formed by the query path

[0060] If the input is a combined input:

[0061] Step [3]: Combine multiple data information such as input software type, defect type, rule violation, and module function.

[0062] Step [4]: ​​Use the knowledge graph to query the data associated with each entity until the entity with the attribute "defect description" is found.

[0063] Step [5]: Take the intersection of the defect descriptions corresponding to each item.

[0064] Step [6]: Use the knowledge graph to query typical cases and example code corresponding to the defects.

[0065] Step [7]: Output the defect description, corresponding typical cases, and example code.

[0066] Note: Step [2] requires manual operation by the tester. Different algorithms will be executed depending on the input of the tester.

[0067] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A knowledge graph-based method for detecting defects in FPGA code, characterized in that, Includes the following steps: Step 1: Construct a knowledge graph of FPGA code defects; Step 2: Based on Step 1, perform FPGA code defect detection knowledge retrieval; In step 1, knowledge extraction is first performed. Ten types of entity data are extracted from existing FPGA code defect data: defect type, severity level, defect description, rule violation, typical case, sample code, software type, module function, programming language, and rule number. The entity category is the attribute of the entity. Then, the FPGA code defect knowledge graph is constructed by combining the 10 types of entity data into (head entity, relation, tail entity) triples. After the graph is constructed, it is stored using a graph database. In step 2, if the input data is a single entity but does not exist in the FPGA code defect knowledge graph, then a defect description that does not exist in the FPGA code defect knowledge graph is input based on the actual test results. The key semantics of the input defect description are extracted using natural language processing algorithms. The similarity between the input defect description and all entities in the FPGA code defect knowledge graph is calculated. The entity with the highest similarity and the attribute "defect description" is selected as the mapping of the input statement in the FPGA code defect knowledge graph. Then, the FPGA code defect knowledge graph is used to query the "defect type" associated with the mapped entity, and then other defects associated with the "defect type" are queried. The query path is recorded and the knowledge graph formed by the query path is output. In step 2, if the input data is a composite entity, FPGA code-related defect information is recommended: Based on the test project information, multiple data information under the input software type, defect type, rule violation, and module function are combined. The FPGA code defect knowledge graph is used to query the data associated with each entity data until an entity with the attribute "defect description" is found. The intersection of the defect descriptions corresponding to each entity is taken, and the result is the suspected defect of the input entity combination. Then, the FPGA code defect knowledge graph is used to query the typical cases and example code corresponding to the suspected defect, and the results are saved.

2. The method as described in claim 1, characterized in that, In step 2, the FPGA code defect knowledge graph is used to help testers identify potential defects based on the characteristics of the test project before formal testing.

3. The method as described in claim 1, characterized in that, In step 2, if the input data is a single entity and exists in the FPGA code defect knowledge graph, then input one of the following entity data: software type, defect type, rule violation, or module function. Use the FPGA code defect knowledge graph to query the data associated with the entity data layer by layer until the entity with the attribute "defect description" is found. Record the query path and output the knowledge graph formed by the query path.

4. The method as described in claim 1, characterized in that, In step 2, the FPGA code defect knowledge graph enables testers to discover unknown defects based on existing defects.

5. The method as described in claim 1, characterized in that, In step 2, the FPGA code defect knowledge graph is used to recommend suspicious defects and their corresponding typical cases and sample code to help testers analyze potential defects and further analyze the FPGA code based on the typical cases and sample code.

6. A system for implementing the method as described in any one of claims 1 to 5.

7. An FPGA verification method employing the method described in any one of claims 1 to 5.

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