Misregulated voltage calibration method, comparison device and decision feedback equalization circuit

Abstract

The application discloses a method for calibrating a misadjustment voltage, a comparison device and a decision feedback equalization circuit. The method calibrates the misadjustment voltage by adjusting the voltage of the reference input end of the comparator. The method does not need to short the input end of the comparator, so it does not need to insert a transmission gate in the receiving link, thus not affecting the signal quality of the receiving end. After calibration, the eye diagram of the receiving end of the comparator is obviously larger, and the margin of the whole receiving end is greatly increased. In addition, for two single-ended signal comparators constituting the structure of the decision feedback equalizer, the method for synchronously adjusting the reference voltages of the two comparators is used to calibrate the misadjustment voltage, and the DFE strength is combined, so that the DFE and the misadjustment voltage calibration are simultaneously performed, and the logic complexity of the calibration system is greatly simplified.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and more specifically, to an offset voltage calibration method, a comparison device, and a decision feedback equalization circuit. Background Technology

[0002] An ideal comparator can be considered to have no mismatch between its positive and negative input terminals; that is, the comparator outputs a high voltage when the voltage at the positive input terminal is greater than that at the negative input terminal, and vice versa. However, due to non-ideal factors such as process mismatch, even if the positive and negative input terminals are perfectly matched in the design, the comparator will still have an offset voltage Vos (Voltage Offset). This causes the comparator output flip point to deviate from the voltage difference between the positive and negative terminals by a certain voltage range. This voltage range is called the comparator's input offset voltage Vos. In high-speed signal receivers, as the signal rate increases and the signal amplitude decreases, the impact of the comparator's input offset voltage Vos on the comparator's performance becomes increasingly significant. Typically, Vos for a 3 sigma comparator can reach 20-30mV or even higher. Therefore, before a high-speed comparator can operate normally, it is generally necessary to perform offset voltage calibration (VosCalibration).

[0003] Figure 1 This is a circuit diagram of a traditional comparator offset voltage Vos calibration method; for example... Figure 1 As shown, existing Vos calibration methods typically involve shorting the positive and negative inputs of a comparator using an analog switch, then adjusting the comparator parameters, such as the dimensions of the differential input pair transistors, to cause the comparator output to flip. This is then considered to have calibrated the comparator's offset voltage, Vos. During normal operation, the positive and negative inputs are then disconnected. However, this method requires disconnecting the I / O to the comparator input first, usually by inserting a transmission gate in the input signal path. During normal operation, the transmission gate is in the conducting state, and during calibration, it is in the closed state. In high-speed signal transmission, inserting a transmission gate in the receiving link introduces additional parasitic parameters R and C, significantly impacting the signal bandwidth and directly degrading the signal quality at the receiving end. Summary of the Invention

[0004] To address at least one deficiency or improvement requirement in the prior art, the present invention provides an offset voltage calibration method, a comparator, and a decision feedback equalization circuit. The offset voltage is calibrated by adjusting the voltage at the reference input terminal of the comparator. Since no transmission gate is inserted on the input link of the comparator, the signal quality at the receiving end is not affected.

[0005] To achieve the above objectives, according to a first aspect of the present invention, an offset voltage calibration method is provided, suitable for calibrating the offset voltage of a single-ended signal comparator, the calibration method comprising:

[0006] While keeping the first input voltage at the positive input terminal of the single-ended signal comparator constant, different reference voltages are provided to the negative input terminal of the single-ended signal comparator.

[0007] The output voltage of the single-ended signal comparator is acquired, and a loopback test is performed based on the first input voltage, the reference voltage and the corresponding output voltage to obtain the first two-dimensional test eye diagram.

[0008] The reference voltage corresponding to the middle position of the first two-dimensional test eye diagram is obtained and used as a calibration voltage to cancel the offset voltage of the single-ended signal comparator and fed back to the negative input terminal of the single-ended signal comparator.

[0009] Furthermore, in the above-mentioned offset voltage calibration method, the middle position of the two-dimensional test eye diagram is at half the eye height of the two-dimensional test eye diagram.

[0010] According to a second aspect of the present invention, a comparator with offset voltage self-calibration function is also provided, the comparator comprising a single-ended signal comparator and a calibration circuit; wherein the calibration circuit comprises:

[0011] The reference voltage generation circuit has its input terminal connected to the controller and its output terminal connected to the negative input terminal of a single-ended signal comparator. It is used to provide reference voltages of different magnitudes to the negative input terminal of the single-ended signal comparator according to the reference voltage control signal generated by the controller.

[0012] The sampling circuit has its first input terminal connected to the controller and its second input terminal connected to the output terminal of a single-ended signal comparator; it is used to acquire the output voltage of the single-ended signal comparator according to the sampling phase control signal generated by the controller and feed it back to the controller.

[0013] The controller is configured to provide a fixed first input voltage to the positive input terminal of a single-ended signal comparator, perform a loopback test based on the first input voltage, a reference voltage, and an output voltage to obtain a first two-dimensional test eye diagram; and acquire a reference voltage corresponding to the middle position of the first two-dimensional test eye diagram as a calibration voltage to cancel the offset voltage of the single-ended signal comparator and feed it back to the negative input terminal of the single-ended signal comparator.

[0014] Furthermore, in the above-described comparison device, the sampling circuit includes:

[0015] The sampling clock generation circuit is used to generate a reference clock and send it to the sampling phase adjustment circuit;

[0016] The sampling phase adjustment circuit has its input terminals connected to the controller and the sampling clock generation circuit, respectively, and its output terminal connected to the latch; it is used to adjust the reference clock according to the sampling phase control signal generated by the controller, generate a sampling clock, and send it to the latch.

[0017] A latch, whose input is connected to the output of a single-ended signal comparator and whose output is connected to a controller; is used to acquire the output voltage of the single-ended signal comparator according to the sampling clock generated by the sampling phase adjustment circuit and feed it back to the controller.

[0018] Furthermore, in the above-mentioned comparison device, the controller obtains the midpoint of the eye height of the two-dimensional test eye diagram as the middle position of the two-dimensional test eye diagram.

[0019] According to a third aspect of the present invention, an offset voltage calibration method is also provided, which is applicable to synchronously calibrating the offset voltage and delay feedback strength of two single-ended signal comparators constituting a decision feedback equalizer, the calibration method comprising:

[0020] The same second input voltage is provided to the positive input terminals of the first single-ended signal comparator and the second single-ended signal comparator; a first reference voltage is provided to the negative input terminal of the first single-ended signal comparator, and a second reference voltage higher than the first reference voltage is provided to the negative input terminal of the second single-ended signal comparator.

[0021] While maintaining the input voltage constant, the magnitudes of the first reference voltage and the second reference voltage are adjusted synchronously, and the difference between the first reference voltage and the second reference voltage remains constant during the adjustment process; the output terminals of the first single-ended signal comparator and the second single-ended signal comparator are respectively connected to a multiplexer; the multiplexer selects the output of the first single-ended signal comparator or the second single-ended signal comparator as the output voltage of the current sampling period based on the output result of the previous sampling period;

[0022] The output voltage of each sampling period is obtained, and a loopback test is performed based on the second input voltage, the first reference voltage, the second reference voltage and the corresponding output voltage to obtain the second two-dimensional test eye diagram.

[0023] The first reference voltage and the second reference voltage corresponding to the maximum value of the second two-dimensional test eye diagram are obtained and used as calibration voltages to cancel the offset voltages of the first single-ended signal comparator and the second single-ended signal comparator, respectively, and fed back to their respective negative input terminals.

[0024] Furthermore, in the above offset voltage calibration method, the second two-dimensional test eye diagram is generated as follows:

[0025] Using the first reference voltage as a reference, extract the high-level signal from the second input voltage; using the second reference voltage as a reference, extract the low-level signal from the second input voltage.

[0026] The captured high-level signal and low-level signal are spliced ​​together to form a second two-dimensional test eye diagram.

[0027] Furthermore, in the above-mentioned offset voltage calibration method, the size of the second two-dimensional test eye diagram is determined by its area or eye width.

[0028] Furthermore, in the above offset voltage calibration method, the multiplexer selects the output of either the first single-ended signal comparator or the second single-ended signal comparator as the output voltage for the current sampling period based on the output result of the previous sampling period, specifically as follows:

[0029] When the output of the previous sampling period is low, the output of the second single-ended signal comparator with the second reference voltage is selected as the output voltage of the current sampling period.

[0030] When the output of the previous sampling period is high, the output of the first single-ended signal comparator with the first reference voltage is selected as the output voltage of the current sampling period.

[0031] Furthermore, in the above offset voltage calibration method, the difference between the first reference voltage and the second reference voltage characterizes the delay feedback strength;

[0032] If the first offset voltage of the first single-ended signal comparator is less than the second offset voltage of the second single-ended signal comparator, and the delay feedback strength is less than the difference between the second offset voltage and the first offset voltage, then the delay feedback strength is increased, and the increase is not less than the difference between the second offset voltage and the first offset voltage.

[0033] According to a fourth aspect of the present invention, a decision feedback equalization circuit is also provided, the decision feedback equalization circuit including a calibration circuit and a first single-ended signal comparator, a second single-ended signal comparator, and a multiplexer constituting a decision feedback equalizer; the output terminals of the first single-ended signal comparator and the second single-ended signal comparator are respectively connected to the multiplexer; the multiplexer selects the output of the first single-ended signal comparator or the second single-ended signal comparator as the output voltage of the current sampling period based on the output result of the previous sampling period;

[0034] The calibration circuit includes:

[0035] A reference voltage generation circuit has its input terminal connected to a controller and its output terminals connected to the negative input terminals of a first single-ended signal comparator and a second single-ended signal comparator, respectively. It provides a first reference voltage to the negative input terminal of the first single-ended signal comparator and a second reference voltage higher than the first reference voltage to the negative input terminal of the second single-ended signal comparator based on a reference voltage control signal generated by the controller. It synchronously adjusts the magnitudes of the first and second reference voltages, maintaining a constant difference between them during the adjustment process.

[0036] The sampling circuit has its first input terminal connected to the controller and its second input terminal connected to the output terminal of the multiplexer; it is used to acquire the output voltage of the multiplexer based on the sampling phase control signal generated by the controller and feed it back to the controller.

[0037] The controller is configured to provide the same second input voltage to the positive input terminals of the first single-ended signal comparator and the second single-ended signal comparator, perform a loopback test based on the second input voltage, the first reference voltage, the second reference voltage and the corresponding output voltage to obtain a second two-dimensional test eye diagram; and acquire the first reference voltage and the second reference voltage corresponding to the second two-dimensional test eye diagram reaching its maximum, and use them as calibration voltages to cancel the offset voltages of the first single-ended signal comparator and the second single-ended signal comparator and feed them back to their respective negative input terminals.

[0038] Furthermore, in the aforementioned decision feedback equalization circuit, the controller generates the second two-dimensional test eye diagram in the following way:

[0039] Using the first reference voltage as a reference, extract the high-level signal from the second input voltage; using the second reference voltage as a reference, extract the low-level signal from the second input voltage.

[0040] The captured high-level signal and low-level signal are spliced ​​together to form a second two-dimensional test eye diagram.

[0041] Furthermore, in the aforementioned decision feedback equalization circuit, the sampling circuit includes:

[0042] The sampling clock generation circuit is used to generate a reference clock and send it to the sampling phase adjustment circuit;

[0043] The sampling phase adjustment circuit has its input terminals connected to the controller and the sampling clock generation circuit, respectively, and its output terminal connected to the latch; it is used to adjust the reference clock according to the sampling phase control signal generated by the controller, generate a sampling clock, and send it to the latch.

[0044] A latch, whose input is connected to the output of a multiplexer and whose output is connected to a controller, is used to acquire the output voltage of the multiplexer according to the sampling clock generated by the sampling phase adjustment circuit and feed it back to the controller.

[0045] Furthermore, in the aforementioned decision feedback equalization circuit, the controller obtains the largest second two-dimensional test eye diagram by measuring the area or eye width.

[0046] Furthermore, in the aforementioned decision feedback equalization circuit, the multiplexer selects the output of either the first single-ended signal comparator or the second single-ended signal comparator as the output voltage for the current sampling period based on the output result of the previous sampling period, specifically as follows:

[0047] When the output of the current sampling period is low, the multiplexer selects the output of the second single-ended signal comparator with the second reference voltage as the output voltage of the current sampling period.

[0048] When the output of the current sampling period is high, the multiplexer selects the output of the first single-ended signal comparator with the first reference voltage as the output voltage of the current sampling period.

[0049] Furthermore, in the above-mentioned decision feedback equalization circuit, the difference between the first reference voltage and the second reference voltage characterizes the delay feedback strength;

[0050] If the first offset voltage of the first single-ended signal comparator is less than the second offset voltage of the second single-ended signal comparator, and the delay feedback strength is less than the difference between the second offset voltage and the first offset voltage, then the reference voltage generation circuit increases the delay feedback strength, and the increase is not less than the difference between the second offset voltage and the first offset voltage.

[0051] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:

[0052] (1) The present invention calibrates the offset voltage by adjusting the voltage at the reference input terminal of the comparator. This calibration scheme does not require shorting the input terminal of the comparator, so there is no need to insert a transmission gate in the receiving link, and therefore it will not affect the signal quality of the receiving end. After calibration, the eye diagram of the receiving end of the comparator becomes significantly larger, and the margin of the entire receiving end is greatly increased.

[0053] (2) This invention addresses the two single-ended signal comparators constituting a Decision Feedback Equalizer (DFE) structure by calibrating the offset voltage through synchronous adjustment of the reference voltages of the two comparators. This is combined with the DFE strength, allowing DFE and offset voltage calibration to occur simultaneously, significantly simplifying the logical complexity of the calibration system. After calibration, the eye diagram at the comparator's receiver significantly increases, greatly enhancing the overall receiver margin and achieving the DFE enhancement effect. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 A circuit diagram for a traditional comparator offset voltage Vos calibration method;

[0056] Figure 2 A schematic flowchart illustrating the offset voltage calibration method provided in this application embodiment;

[0057] Figure 3 This is a circuit diagram corresponding to the offset voltage calibration method provided in the embodiments of this application;

[0058] Figure 4 A schematic diagram of a first two-dimensional test eye diagram provided in an embodiment of this application;

[0059] Figure 5 This is a schematic diagram of the structure of a comparator with offset voltage self-calibration function provided in an embodiment of this application;

[0060] Figure 6 A schematic diagram of the circuit structure for implementing a decision feedback equalizer effect using two single-ended signal comparators, provided for an embodiment of this application;

[0061] Figure 7 A schematic diagram of a two-dimensional eye diagram provided in this application embodiment when the DFE is turned on under ideal conditions where there is no offset voltage;

[0062] Figure 8 A schematic flowchart illustrating the offset voltage calibration method provided in this application embodiment;

[0063] Figure 9 This is a schematic diagram of the decision feedback equalization circuit provided in an embodiment of this application. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0065] The terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0066] Furthermore, to avoid obscuring the understanding of the invention by those skilled in the art, well-known or widely used techniques, elements, structures, and processes may not be described or shown in detail. Although the accompanying drawings illustrate exemplary embodiments of the invention, the drawings are not necessarily drawn to scale, and specific features may be enlarged or omitted to better illustrate and explain the invention.

[0067] This embodiment provides an offset voltage calibration method applicable to calibrating the offset voltage of a single-ended signal comparator. Figure 2 This is a flowchart illustrating the offset voltage calibration method provided in this embodiment. Please refer to [link / reference]. Figure 2 The calibration method mainly includes the following steps:

[0068] Step 101: While keeping the first input voltage at the positive input terminal of the single-ended signal comparator constant, provide reference voltages of different magnitudes to the negative input terminal of the single-ended signal comparator;

[0069] Figure 3 This is a circuit diagram corresponding to the offset voltage calibration method provided in this embodiment; please refer to [link / reference]. Figure 3 In this embodiment, the offset voltage Vos of the single-ended signal comparator Comp is treated as a whole. The positive input terminal of the single-ended signal comparator Comp receives the first input voltage Vin, and the negative input terminal receives the reference voltage Vref. During the calibration process, the magnitude of the reference voltage Vref is continuously adjusted. The upper limit of the adjustment of the reference voltage Vref is not lower than the first input voltage Vin. In this embodiment, the adjustment range of the reference voltage is set to 0-Vin. It can be adjusted by gradually increasing or decreasing the reference voltage Vref according to a preset step.

[0070] Step 102: Collect the output voltage of the single-ended signal comparator when it receives different reference voltages, and perform a loopback test based on the first input voltage, reference voltage and output voltage to obtain the first two-dimensional test eye diagram;

[0071] Under different reference voltages Vref, the first input voltage Vin and the corresponding output voltage Vout of the single-ended signal comparator Comp are obtained for loopback testing, thereby depicting the first two-dimensional test eye diagram. This first two-dimensional test eye diagram can be generated in the following way:

[0072] Using the phase of the first input voltage Vin as the abscissa and the reference voltage Vref as the ordinate, a first two-dimensional test eye diagram is formed; or,

[0073] Using the reference voltage Vref as the horizontal axis and the phase of the first input voltage Vin as the vertical axis, a first two-dimensional test eye diagram is formed.

[0074] Step 103: Obtain the reference voltage corresponding to the middle position of the first two-dimensional test eye diagram, use it as the calibration voltage to cancel the offset voltage of the single-ended signal comparator, and feed it back to the negative input terminal of the single-ended signal comparator.

[0075] After drawing the first two-dimensional test eye diagram, the middle position of the first two-dimensional test eye diagram is first determined, and the reference voltage Vref corresponding to the middle position is used as the calibration voltage to offset the offset voltage Vos of Comp.

[0076] When the reference voltage Vref is used as the vertical axis to form the first two-dimensional test eye diagram, the middle position of the first two-dimensional test eye diagram is at half the height of the eye; when the reference voltage Vref is used as the horizontal axis to form the first two-dimensional test eye diagram, the middle position of the first two-dimensional test eye diagram is at half the width of the eye.

[0077] Figure 4 This is a schematic diagram of the first two-dimensional test eye diagram provided in this embodiment, as shown below. Figure 4 As shown, the first two-dimensional test eye diagram is plotted with the reference voltage Vref as the ordinate. The middle position of the first two-dimensional test eye diagram is at half the eye height. When the reference voltage Vref is at the middle position of the eye diagram, there is the maximum sampling margin. It can be considered that the reference voltage Vref at this time has eliminated the influence of the offset voltage Vos of the single-ended signal comparator Comp. The calibration process ends, the reference voltage Vref at this time is locked, and it is fed back to the negative input terminal of the single-ended signal comparator Comp.

[0078] This embodiment targets a comparator for single-ended signals. It calibrates the effect of offset voltage by adjusting the reference voltage at the comparator's negative input. This calibration scheme does not require shorting the comparator's input, thus eliminating the need for a transmission gate in the receiving link. Furthermore, after calibration, the eye diagram at the comparator's receiving end significantly increases, greatly enhancing the overall receiver margin.

[0079] It should be noted that the offset voltage calibration method provided in this embodiment is applicable to all comparators with offset voltage, and is not limited to comparators with a specific circuit structure.

[0080] This embodiment also provides a comparison device with offset voltage self-calibration function, which can be used to implement the offset voltage calibration method in the above embodiments. Figure 5 This is a schematic diagram of the comparator with offset voltage self-calibration function. Please refer to [link / reference]. Figure 5 The comparison device includes a single-ended signal comparator and a calibration circuit; wherein the calibration circuit includes a reference voltage generation circuit, a sampling circuit and a controller;

[0081] The input of the reference voltage generation circuit is connected to the controller, and the output is connected to the negative input of a single-ended signal comparator. It is used to provide reference voltages of different magnitudes to the negative input of the single-ended signal comparator according to the reference voltage control signal generated by the controller.

[0082] The first input terminal of the sampling circuit is connected to the controller, and the second input terminal is connected to the output terminal of the single-ended signal comparator; it is used to acquire the output voltage of the single-ended signal comparator according to the sampling phase control signal generated by the controller and feed it back to the controller.

[0083] The controller provides a fixed first input voltage to the positive input terminal of the single-ended signal comparator. Specifically, the controller transmits the expected data of the first input voltage to its Tx transmitter, which generates the first input voltage and provides it to the positive input terminal of the single-ended signal comparator. Additionally, the controller performs a loopback test based on the first input voltage, reference voltage, and output voltage to obtain a first two-dimensional eye diagram. It then acquires the reference voltage corresponding to the middle position of the first two-dimensional eye diagram, using it as a calibration voltage to compensate for the offset voltage of the single-ended signal comparator, and feeds it back to the negative input terminal of the single-ended signal comparator.

[0084] In this embodiment, during the calibration process, the reference voltage generation circuit continuously adjusts the magnitude of the reference voltage Vref. The upper limit of the adjustment of the reference voltage Vref is not lower than the first input voltage Vin. In a specific example, the adjustment range of the reference voltage is set to 0~Vin, and it can be adjusted by gradually increasing or decreasing the reference voltage Vref according to a preset step.

[0085] Under different reference voltages Vref, the controller performs loopback tests based on the first input voltage Vin and the corresponding output voltage Vout of the single-ended signal comparator Comp, thereby drawing a first two-dimensional test eye diagram. Then, the middle position of this first two-dimensional test eye diagram is determined, and the reference voltage Vref corresponding to this middle position is used as the calibration voltage to cancel the offset voltage Vos of the single-ended signal comparator Comp. After the calibration process is complete, the reference voltage Vref corresponding to the middle position of the eye diagram is locked, and the reference voltage generation circuit is controlled to provide it to the negative input terminal of the single-ended signal comparator Comp.

[0086] Specifically, when the reference voltage Vref is used as the vertical axis to form the first two-dimensional test eye diagram, the center position of the first two-dimensional test eye diagram is at half the eye height; when the reference voltage Vref is used as the horizontal axis to form the first two-dimensional test eye diagram, the center position of the first two-dimensional test eye diagram is at half the eye width. In this embodiment, the first two-dimensional test eye diagram is depicted using the reference voltage Vref as the vertical axis, so the center position of the first two-dimensional test eye diagram is at half the eye height.

[0087] Please continue reading. Figure 5 In one optional implementation, the sampling circuit includes a sampling clock generation circuit, a sampling phase adjustment circuit, and a latch.

[0088] The output of the sampling clock generation circuit is connected to the sampling phase adjustment circuit, which is mainly used to generate a reference clock and send it to the sampling phase adjustment circuit.

[0089] The input terminals of the sampling phase adjustment circuit are connected to the controller and the sampling clock generation circuit, respectively, and the output terminal is connected to the latch. The sampling phase adjustment circuit adjusts the reference clock according to the sampling phase control signal generated by the controller, generates the sampling clock, and sends it to the latch.

[0090] The input of the latch is connected to the output of the single-ended signal comparator, and the output of the latch is connected to the controller. The latch acquires the output voltage of the single-ended signal comparator according to the sampling clock generated by the sampling phase adjustment circuit and feeds it back to the controller.

[0091] This embodiment provides an offset voltage calibration method applicable to the synchronous calibration of the offset voltage and delay feedback strength of two single-ended signal comparators constituting a decision feedback equalizer.

[0092] Figure 6 This is a schematic diagram of a circuit structure that uses two single-ended signal comparators to achieve the effect of a decision feedback equalizer (DFE). Figure 6As shown, when a tap DFE is constructed using a first single-ended signal comparator Comp1 and a second single-ended signal comparator Comp2 with different reference voltages, the sampling result of the previous sampling period determines whether the output result of Comp1 or Comp2 is used in the next sampling period. Taking the example that the reference voltage Vref_h of the second single-ended signal comparator Comp2 is greater than the reference voltage Vref_l of the first single-ended signal comparator Comp1, if the sampling result Vout of the data D0 in the previous cycle is high, the multiplexer (such as a 2-to-1 MUX) switches the output of the data D1 in the next cycle to the second single-ended signal comparator Comp2. The reference voltage Vref_h used by the second single-ended signal comparator Comp2 is relatively higher than the reference voltage Vref_l used by the second single-ended signal comparator Comp1. When sampling the data D1 in the next cycle when the data D0 in the previous cycle is high, due to the influence of inter-symbol interference (ISI), the comparator with a higher reference voltage Vref obviously has a larger sampling margin. Conversely, when the data in the previous sampling cycle is low, the first single-ended signal comparator Comp1, which uses Vref_l as the reference voltage, has a larger sampling margin. Therefore, in an ideal case where the offset voltages of Comp1 and Comp2 are not considered, the reference voltage for low-level data can be Vref_h, and the reference voltage for high-level data can be Vref_l. Both high and low levels have a larger sampling margin compared to the case where DFE is not enabled. Figure 7 This is a schematic diagram of a two-dimensional eye diagram when the DFE is turned on under ideal conditions with no offset voltage. Figure 7 It can be seen that the sampling eye diagram has become significantly larger.

[0093] However, in practical applications, both the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2 will have offset voltages, which complicates the situation. To obtain the optimal two-dimensional eye diagram, it is necessary to first adjust the reference voltages Vref_l and Vref_h to calibrate the offset voltages Vos1 and Vos2 of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2, respectively. At the same time, in order to enable DFE, it is necessary to further adjust the reference voltages Vref_l and Vref_h to achieve the best DFE effect. Compared with the aforementioned embodiment, the adjustment of the reference voltage Vref becomes much more complicated.

[0094] To address this issue, this embodiment employs a method of simultaneously calibrating the offset voltage Vos and DFE. This method only requires adjusting the reference voltage Vref once, thereby simplifying the calibration process.

[0095] Figure 8 This is a flowchart illustrating the offset voltage calibration method provided in this embodiment. Please refer to [link / reference]. Figure 8The calibration method includes the following steps:

[0096] Step 801: Provide the same second input voltage to the positive input terminals of the first single-ended signal comparator and the second single-ended signal comparator; provide a first reference voltage to the negative input terminal of the first single-ended signal comparator, and provide a second reference voltage higher than the first reference voltage to the negative input terminal of the second single-ended signal comparator;

[0097] Please see Figure 6 The positive input terminals of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2 receive the same second input voltage Vin. The negative input terminal of the first single-ended signal comparator Comp1 receives the first reference voltage Vref_l, and the negative input terminal of the second single-ended signal comparator Comp2 receives the second reference voltage Vref_h, and Vref_l is less than Vref_h.

[0098] The outputs of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2 are respectively connected to a multiplexer; the multiplexer selects either the output Vout_1 of the first single-ended signal comparator Comp1 or the output Vout_2 of the second single-ended signal comparator Comp2 as the output voltage for the current sampling period based on the output result of the previous sampling period; specifically:

[0099] When the output result Vout of the previous sampling period is low, the output Vout_2 of the second single-ended signal comparator Comp2 with the second reference voltage Vref_h is selected as the output voltage of the current sampling period.

[0100] When the output result Vout of the previous sampling period is high, the output Vout_1 of the first single-ended signal comparator Comp1 with the first reference voltage Vref_l is selected as the output voltage of the current sampling period.

[0101] Step 802: While keeping the input voltage constant, synchronously adjust the magnitudes of the first reference voltage and the second reference voltage, and keep the difference between the first reference voltage and the second reference voltage constant during the adjustment process;

[0102] In this step, the first reference voltage Vref_l of the first single-ended signal comparator Comp1 and the second reference voltage Vref_h of the second single-ended signal comparator Comp2 are synchronously adjusted, and the difference between the first reference voltage Vref_l and the second reference voltage Vref_h is kept constant throughout the adjustment process. This difference is defined as the delay feedback strength (DFE strength), that is, DFE strength = ΔVref = Vref_h - Vref_l.

[0103] Step 803: Obtain the output voltage of each sampling period, and perform a loopback test based on the second input voltage, the first reference voltage, the second reference voltage and the corresponding output voltage to obtain the second two-dimensional test eye diagram;

[0104] In this step, under different first reference voltages Vref_l and second reference voltages Vref_h, the output voltage Vout of the multiplexer in each sampling period is obtained. A loopback test is performed based on the second input voltage Vin and the corresponding output voltage Vout, thereby depicting the second two-dimensional test eye diagram. This second two-dimensional test eye diagram is similar to the generation method of the first two-dimensional test eye diagram in the above embodiment, the difference being that the formation process of the second two-dimensional test eye diagram uses two voltages, the first reference voltage Vref_l and the second reference voltage Vref_h. Please refer to [link to relevant documentation]. Figure 7 Taking the eye diagram as an example, with different reference voltages as the ordinate, the generation method of this second two-dimensional test eye diagram is as follows:

[0105] Using the first reference voltage Vref_l as a reference, extract the high-level signal from the second input voltage; using the second reference voltage Vref_h as a reference, extract the low-level signal from the second input voltage.

[0106] The captured high-level signal and low-level signal are spliced ​​together to form a second two-dimensional test eye diagram.

[0107] Step 804: Obtain the first reference voltage and the second reference voltage corresponding to the maximum value of the second two-dimensional test eye diagram, and use them as calibration voltages to cancel the offset voltages of the first single-ended signal comparator and the second single-ended signal comparator, respectively, and feed them back to their respective negative input terminals.

[0108] In this step, the size of the second two-dimensional test eye diagram can be determined in various ways, including but not limited to measuring the area or width of the eye diagram, etc. This embodiment does not limit the specific method. When the second two-dimensional test eye diagram reaches its maximum, the first reference voltage Vref_l corresponding to this maximum eye diagram is considered to be the calibration voltage after the first offset voltage Vos1 of the first single-ended signal comparator Comp1 is canceled, and the corresponding second reference voltage Vref_h is considered to be the calibration voltage after the second offset voltage Vos2 of the second single-ended signal comparator Comp2 is canceled. Providing the first reference voltage Vref_l corresponding to the maximum eye diagram to the negative input terminal of the first single-ended signal comparator Comp1, and providing the second reference voltage Vref_h corresponding to the maximum eye diagram to the negative input terminal of the second single-ended signal comparator Comp2, simultaneously completes the calibration of the offset voltages of the two single-ended signal comparators.

[0109] The specific reasons are explained in detail below:

[0110] (1)When Vos1 - Vos2 < 0 and the DFE strength = ΔVref < Vos2 - Vos1, when calibrated to the optimal position, it can be equivalently considered that the DFE strength is not turned on. There is still an equivalent offset voltage offset of |Vos2 - Vos1| - ΔVref that has not been calibrated. At this time, it is necessary to further increase the DFE strength, that is, increase ΔVref. For example, if Vos1 = -10mV, Vos2 = 20mV, and ΔVref = 20mV, when calibrated to the optimal position, Vref_l - Vos1 = 5mV, Vref_h - Vos2 = -5mV, which is equivalent to having 10mV of equivalent offset voltage offset not fully calibrated.

[0111] For this case, that is, when the DFE strength is less than the difference in offset voltages |Vos2 - Vos1| of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2, it is necessary to continue to increase on the basis of the pre-set DFE strength, and the increased part should not be less than the difference in offset voltages |Vos2 - Vos1|, so as to further cancel the equivalent offset voltage offset, so as to ensure that the offset voltage is fully calibrated.

[0112] (2)When Vos1 - Vos2 < 0 and ΔVref > Vos2 - Vos1, when calibrated to the optimal position, it can be considered that the equivalent offset voltage offset is offset by a part of the DFE strength (Vos2 - Vos1). The equivalent offset voltage offsets of the two comparators are fully calibrated. At the same time, the actual DFE strength becomes ΔVref - |Vos2 - Vos1|, which is smaller than the actual set value ΔVref. The reduced part can be fully compensated by continuing to increase ΔVref to (ΔVref + |Vos2 - Vos1|). For example, if Vos1 = -10mV, Vos2 = 20mV, and ΔVref = 40mV, when calibrated to the optimal position, Vref_l - Vos1 = -5mV, Vref_h - Vos2 = +5mV, the equivalent offset voltage offset is calibrated, and an additional 10mV of DFE strength is turned on.

[0113] (3)When Vos1 - Vos2 > 0 and ΔVref = 0, when calibrated to the optimal position, although the DFE strength is set to 0, due to the influence of the equivalent offset voltage offset, it can be equivalently considered that the DFE is turned on and the DFE strength is |Vos1 - Vos2|. For example, if Vos1 = 20mV, Vos2 = -10mV, and ΔVref = 0mV, when calibrated to the optimal position, Vref_l - Vos1 = -15mV, Vref_h - Vos2 = +15mV. The existence of the equivalent offset voltage offset can be considered to have an additional 30mV of DFE strength turned on.

[0114] (4) When Vos1-Vos2>0 and ΔVref>0, when calibrated to the optimal position, the actual DFE intensity can be considered as ΔVref +|Vos1-Vos2|, that is, the equivalent offset voltage increases the DFE intensity. For example, Vos1=20mV, Vos2=-10mV, ΔVref=10mV, when calibrated to the optimal position, Vref_l-Vos1=-20mV, Vref_h-Vos2=+20mV, the existence of the equivalent offset voltage can be considered as an additional 30mV of DFE intensity, plus the set 10mV DFE intensity, the equivalent total DFE intensity is 40mV.

[0115] This embodiment addresses the two single-ended signal comparators constituting the DFE structure. It employs a method of synchronously adjusting the reference voltages of both comparators to calibrate the offset voltage. This is combined with the DFE strength, allowing DFE and input offset calibration to occur simultaneously, significantly simplifying the logic complexity of the calibration system. Furthermore, after calibration, the eye diagram at the comparator's receiver significantly increases, greatly enhancing the overall receiver margin and achieving the DFE enhancement effect.

[0116] It should be noted that the offset voltage calibration method provided in this embodiment is applicable to all comparators with offset voltage, and is not limited to comparators with a specific circuit structure. Furthermore, this calibration method is applicable not only to the calibration of full-rate DFE structure comparators, but also to comparator circuits with half-rate DFE structure.

[0117] This embodiment also provides a decision feedback equalization circuit, which can use the offset voltage calibration method in the above embodiments. Figure 9 This is a schematic diagram of the decision feedback equalization circuit. Please refer to [link / reference]. Figure 9 The decision feedback equalization circuit includes a calibration circuit and a first single-ended signal comparator Comp1, a second single-ended signal comparator Comp2, and a multiplexer constituting the decision feedback equalizer. The outputs of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2 are respectively connected to the multiplexer. The multiplexer selects the output of the first single-ended signal comparator Comp1 or the second single-ended signal comparator Comp2 as the output voltage of the current sampling period based on the output result of the previous sampling period.

[0118] In this embodiment, the calibration circuit includes a reference voltage generation circuit, a sampling circuit, and a controller; wherein,

[0119] The input of the reference voltage generation circuit is connected to the controller, and the output is connected to the negative inputs of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2, respectively. It provides a first reference voltage Vref_l to the negative input of the first single-ended signal comparator Comp1 and a second reference voltage Vref_h, higher than the first reference voltage Vref_l, to the negative input of the second single-ended signal comparator Comp2, based on the reference voltage control signal generated by the controller. During calibration, the reference voltage generation circuit synchronously adjusts the magnitudes of the first reference voltage Vref_l and the second reference voltage Vref_h, maintaining a constant difference between them. This difference is defined as the DFE intensity, i.e., DFE intensity = ΔVref = Vref_h - Vref_l.

[0120] The first input terminal of the sampling circuit is connected to the controller, and the second input terminal is connected to the output terminal of the multiplexer; it is used to acquire the output voltage of the multiplexer based on the sampling phase control signal generated by the controller and feed it back to the controller. Specifically:

[0121] When the output result Vout of the previous sampling period is low, the multiplexer selects the output Vout_2 of the second single-ended signal comparator Comp2, which has a second reference voltage Vref_h, as the output voltage of the current sampling period; that is, the sampling circuit feeds back the output Vout_2 of the second single-ended signal comparator Comp2 as the output voltage of the current sampling period to the controller.

[0122] When the output result Vout of the previous sampling period is high, the multiplexer selects the output Vout_1 of the first single-ended signal comparator Comp1 with the first reference voltage Vref_l as the output voltage of the current sampling period; that is, the sampling circuit feeds back the output Vout_1 of the first single-ended signal comparator Comp1 as the output voltage of the current sampling period to the controller.

[0123] In one optional implementation, the sampling circuit includes a sampling clock generation circuit, a sampling phase adjustment circuit, and a latch; wherein,

[0124] The sampling clock generation circuit is used to generate a reference clock and send it to the sampling phase adjustment circuit;

[0125] The input terminals of the sampling phase adjustment circuit are connected to the controller and the sampling clock generation circuit, respectively, and the output terminal is connected to the latch. The sampling phase adjustment circuit is used to adjust the reference clock according to the sampling phase control signal generated by the controller, generate the sampling clock, and send it to the latch.

[0126] The input of the latch is connected to the output of the multiplexer, and the output is connected to the controller. The latch is used to acquire the output voltage of the multiplexer according to the sampling clock generated by the sampling phase adjustment circuit and feed it back to the controller.

[0127] The controller provides the same second input voltage to the positive input terminals of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2. Specifically, the controller transmits the expected data of the second input voltage to its Tx transmitter, which generates the second input voltage and provides it to the positive input terminals of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2. Additionally, the controller performs a loopback test based on the second input voltage, the first reference voltage Vref_l, the second reference voltage Vref_h, and the corresponding output voltage Vout to obtain a second two-dimensional eye diagram. Furthermore, it acquires the first reference voltage Vref_l and the second reference voltage Vref_h corresponding to the maximum value of the second two-dimensional eye diagram, using them as calibration voltages to cancel the offset voltages of the first single-ended signal comparator Comp1 and the second single-ended signal comparator Comp2, respectively, and feeds them back to their respective negative input terminals.

[0128] In this embodiment, under different first reference voltages Vref_l and second reference voltages Vref_h, the controller acquires the output voltage Vout of the multiplexer in each sampling period, and performs a loopback test based on the second input voltage Vin and the corresponding output voltage Vout, thereby depicting a second two-dimensional test eye diagram. The generation process of this second two-dimensional test eye diagram uses two voltages, the first reference voltage Vref_l and the second reference voltage Vref_h. Taking the different reference voltages as the vertical axis to depict the eye diagram as an example, the generation method of this second two-dimensional test eye diagram is as follows:

[0129] Using the first reference voltage Vref_l as a reference, extract the high-level signal from the second input voltage; using the second reference voltage Vref_h as a reference, extract the low-level signal from the second input voltage.

[0130] The captured high-level signal and low-level signal are spliced ​​together to form a second two-dimensional test eye diagram.

[0131] After generating the second two-dimensional test eye diagram, the controller can determine the size of the second two-dimensional test eye diagram by measuring the area or eye width of the eye diagram; when the second two-dimensional test eye diagram reaches its maximum, the first reference voltage Vref_l corresponding to this maximum eye diagram is considered to be the calibration voltage after the first offset voltage Vos1 of the first single-ended signal comparator Comp1 is cancelled out. The first reference voltage Vref_l corresponding to the maximum eye diagram is provided to the negative input terminal of the first single-ended signal comparator Comp1 through the reference voltage generation circuit; the corresponding second reference voltage Vref_h is the calibration voltage after the second offset voltage Vos2 of the second single-ended signal comparator Comp2 is cancelled out. The second reference voltage Vref_h is provided to the negative input terminal of the second single-ended signal comparator Comp2 through the reference voltage generation circuit, thus completing the calibration of the offset voltages of the two single-ended signal comparators simultaneously.

[0132] A special case needs to be explained. If the first offset voltage Vos1 of the first single-ended signal comparator Comp1 is less than the second offset voltage Vos2 of the second single-ended signal comparator Comp2, and the DFE strength is less than the difference between the second offset voltage and the first offset voltage, that is, ΔVref < Vos2 - Vos1, at this time, the delay feedback strength should be increased by increasing the difference between the first reference voltage Vref_l and the second reference voltage Vref_h, and the increase amplitude is not less than the difference between the second offset voltage and the first offset voltage Vos2 - Vos1, so as to ensure that the offset voltage is completely calibrated.

[0133] It should be noted that although in the above embodiments, the operations of the methods in the embodiments of this specification are described in a specific order, however, this does not require or imply that these operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the steps depicted in the flowchart can change the execution order. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step for execution, and / or one step can be decomposed into multiple steps for execution.

[0134] In the above embodiments, the descriptions of each embodiment have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0135] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program. This program can be stored in a computer-readable memory, and the memory can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disc, etc.

[0136] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

[0137] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An offset voltage calibration method, characterized in that, The calibration method is applicable to calibrating the offset voltage of a single-ended signal comparator, and includes: While keeping the first input voltage Vin at the positive input terminal of the single-ended signal comparator constant, reference voltages of different magnitudes are provided to the negative input terminal of the single-ended signal comparator. The adjustment range of the reference voltage is 0~Vin, and it is gradually increased or decreased according to a preset step. The output voltage of the single-ended signal comparator is acquired, and a loopback test is performed based on the first input voltage Vin, the reference voltage and the corresponding output voltage to obtain the first two-dimensional test eye diagram. The reference voltage corresponding to the middle position of the first two-dimensional test eye diagram is obtained and used as a calibration voltage to cancel the offset voltage of the single-ended signal comparator and fed back to the negative input terminal of the single-ended signal comparator.

2. The offset voltage calibration method as described in claim 1, characterized in that, The center position of the two-dimensional test eye diagram is at half the eye height of the two-dimensional test eye diagram.

3. A comparison device, characterized in that, It includes a single-ended signal comparator and a calibration circuit; the calibration circuit includes a reference voltage generation circuit, a sampling circuit, and a controller. The input terminal of the reference voltage generation circuit is connected to the controller, and the output terminal is connected to the negative input terminal of the single-ended signal comparator; the first input terminal of the sampling circuit is connected to the controller, and the second input terminal is connected to the output terminal of the single-ended signal comparator. The controller is used to provide a fixed first input voltage Vin to the positive input terminal of the single-ended signal comparator and to provide a reference voltage control signal to the reference voltage generation circuit; the reference voltage generation circuit is used to provide reference voltages of different magnitudes to the negative input terminal of the single-ended signal comparator according to the reference voltage control signal, wherein the adjustment range of the reference voltage is 0~Vin, and it is gradually increased or decreased in preset steps; the sampling circuit is used to acquire the output voltage of the single-ended signal comparator according to the sampling phase control signal generated by the controller and feed it back to the controller. The controller is further configured to perform a loopback test based on the first input voltage Vin, the reference voltage, and the output voltage to obtain a first two-dimensional test eye diagram; and to obtain the reference voltage corresponding to the middle position of the first two-dimensional test eye diagram as a calibration voltage to offset the offset voltage of the single-ended signal comparator and feed it back to the negative input terminal of the single-ended signal comparator.

4. The comparison device as claimed in claim 3, characterized in that, The sampling circuit includes a sampling clock generation circuit, a sampling phase adjustment circuit, and a latch. The sampling clock generation circuit is used to generate a reference clock and send it to the sampling phase adjustment circuit; The input terminal of the sampling phase adjustment circuit is connected to the controller and the sampling clock generation circuit respectively, and the output terminal is connected to the latch. Used to adjust the reference clock according to the sampling phase control signal generated by the controller, generate a sampling clock and send it to the latch; The input terminal of the latch is connected to the output terminal of the single-ended signal comparator, and the output terminal is connected to the controller. The sampling phase adjustment circuit is used to acquire the output voltage of the single-ended signal comparator according to the sampling clock generated by the sampling phase adjustment circuit and feed it back to the controller.

5. The comparison device as claimed in claim 3, characterized in that, The controller obtains the midpoint of the eye height of the two-dimensional test eye diagram as the middle position of the two-dimensional test eye diagram.

6. An offset voltage calibration method, characterized in that, A calibration method applicable to the synchronous calibration of the offset voltage and delay feedback strength of two single-ended signal comparators constituting a decision feedback equalizer, the calibration method comprising: The same second input voltage is provided to the positive input terminals of the first single-ended signal comparator and the second single-ended signal comparator; a first reference voltage is provided to the negative input terminal of the first single-ended signal comparator, and a second reference voltage higher than the first reference voltage is provided to the negative input terminal of the second single-ended signal comparator; the output terminals of the first single-ended signal comparator and the second single-ended signal comparator are respectively connected to a multiplexer; the multiplexer selects the output of the first single-ended signal comparator or the second single-ended signal comparator as the output voltage of the current sampling period based on the output result of the previous sampling period. While keeping the second input voltage constant, the magnitudes of the first reference voltage and the second reference voltage are adjusted synchronously, and the difference between the first reference voltage and the second reference voltage is kept constant during the adjustment process; The output voltage of each sampling period is obtained, and a loopback test is performed based on the second input voltage, the first reference voltage, the second reference voltage and the corresponding output voltage to obtain the second two-dimensional test eye diagram. The first reference voltage and the second reference voltage corresponding to the maximum value of the second two-dimensional test eye diagram are obtained and used as calibration voltages to cancel the offset voltages of the first single-ended signal comparator and the second single-ended signal comparator, respectively, and fed back to their respective negative input terminals.

7. The offset voltage calibration method as described in claim 6, characterized in that, The second two-dimensional test eye diagram is generated as follows: Using the first reference voltage as a reference, extract the high-level signal from the second input voltage; using the second reference voltage as a reference, extract the low-level signal from the second input voltage. The captured high-level signal and low-level signal are spliced ​​together to form a second two-dimensional test eye diagram.

8. The offset voltage calibration method as described in claim 6, characterized in that, The size of the second two-dimensional test eye diagram is determined by its area or eye width.

9. The offset voltage calibration method as described in claim 6, characterized in that, The multiplexer selects the output of either the first single-ended signal comparator or the second single-ended signal comparator as the output voltage for the current sampling period based on the output result of the previous sampling period. Specifically: When the output of the previous sampling period is low, the output of the second single-ended signal comparator with the second reference voltage is selected as the output voltage of the current sampling period. When the output of the previous sampling period is high, the output of the first single-ended signal comparator with the first reference voltage is selected as the output voltage of the current sampling period.

10. The offset voltage calibration method as described in claim 6, characterized in that, The difference between the first reference voltage and the second reference voltage characterizes the strength of the delay feedback; If the first offset voltage of the first single-ended signal comparator is less than the second offset voltage of the second single-ended signal comparator, and the delay feedback strength is less than the difference between the second offset voltage and the first offset voltage, then the delay feedback strength should be increased, and the increase should not be less than the difference between the second offset voltage and the first offset voltage.

11. A decision feedback equalization circuit, characterized in that, It includes a calibration circuit and a first single-ended signal comparator, a second single-ended signal comparator, and a multiplexer constituting a decision feedback equalizer; the outputs of the first single-ended signal comparator and the second single-ended signal comparator are respectively connected to the multiplexer; the multiplexer selects the output of the first single-ended signal comparator or the second single-ended signal comparator as the output voltage of the current sampling period based on the output result of the previous sampling period. The calibration circuit includes a reference voltage generation circuit, a sampling circuit, and a controller: The input terminal of the reference voltage generation circuit is connected to the controller, and the output terminal is connected to the negative input terminals of the first single-ended signal comparator and the second single-ended signal comparator, respectively; the first input terminal of the sampling circuit is connected to the controller, and the second input terminal is connected to the output terminal of the multiplexer. The controller is configured to provide the same second input voltage to the positive input terminals of the first single-ended signal comparator and the second single-ended signal comparator, and to provide a reference voltage control signal to the reference voltage generation circuit; the reference voltage generation circuit is configured to provide a first reference voltage to the negative input terminal of the first single-ended signal comparator and a second reference voltage higher than the first reference voltage to the negative input terminal of the second single-ended signal comparator according to the reference voltage control signal, and to synchronously adjust the magnitudes of the first reference voltage and the second reference voltage, while maintaining the difference between the first reference voltage and the second reference voltage unchanged during the adjustment process; The sampling circuit is used to acquire the output voltage of the multiplexer based on the sampling phase control signal generated by the controller and feed it back to the controller. The controller is further configured to perform a loopback test based on the second input voltage, the first reference voltage, the second reference voltage and the corresponding output voltage to obtain a second two-dimensional test eye diagram; and to obtain the first reference voltage and the second reference voltage corresponding to the second two-dimensional test eye diagram reaching its maximum, and to feed them back to their respective negative input terminals as calibration voltages to offset the offset voltages of the first single-ended signal comparator and the second single-ended signal comparator.

12. The decision feedback equalization circuit as described in claim 11, characterized in that, The controller generates the second two-dimensional test eye diagram in the following way: Using the first reference voltage as a reference, extract the high-level signal from the second input voltage; using the second reference voltage as a reference, extract the low-level signal from the second input voltage. The captured high-level signal and low-level signal are spliced ​​together to form a second two-dimensional test eye diagram.

13. The decision feedback equalization circuit as described in claim 11, characterized in that, The sampling circuit includes a sampling clock generation circuit, a sampling phase adjustment circuit, and a latch. The sampling clock generation circuit is used to generate a reference clock and send it to the sampling phase adjustment circuit; The input terminal of the sampling phase adjustment circuit is connected to the controller and the sampling clock generation circuit respectively, and the output terminal is connected to the latch. Used to adjust the reference clock according to the sampling phase control signal generated by the controller, generate a sampling clock and send it to the latch; The input of the latch is connected to the output of the multiplexer, and the output is connected to the controller. The sampling phase adjustment circuit is used to acquire the output voltage of the multiplexer according to the sampling clock generated by the sampling phase adjustment circuit and feed it back to the controller.

14. The decision feedback equalization circuit as described in claim 11, characterized in that, The controller obtains the largest second two-dimensional test eye diagram by measuring the area or eye width.

15. The decision feedback equalization circuit as described in claim 11, characterized in that, The multiplexer selects the output of either the first single-ended signal comparator or the second single-ended signal comparator as the output voltage for the current sampling period based on the output result of the previous sampling period. When the output of the current sampling period is low, the multiplexer selects the output of the second single-ended signal comparator with the second reference voltage as the output voltage of the current sampling period. When the output of the current sampling period is high, the multiplexer selects the output of the first single-ended signal comparator with the first reference voltage as the output voltage of the current sampling period.

16. The decision feedback equalization circuit as described in claim 11, characterized in that, The difference between the first reference voltage and the second reference voltage characterizes the strength of the delay feedback; If the first offset voltage of the first single-ended signal comparator is less than the second offset voltage of the second single-ended signal comparator, and the delay feedback strength is less than the difference between the second offset voltage and the first offset voltage, then the reference voltage generation circuit increases the delay feedback strength, and the increase is not less than the difference between the second offset voltage and the first offset voltage.

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