A software and hardware interaction method and device for accessing logical IP

Abstract

The embodiment of the present application provides a method and device for software and hardware interaction for accessing a logical IP, which relates to the field of chip technology and can reuse software drivers, reduce costs and improve user experience when the logical IP is disassembled. The method includes: a first software driver is used to call the function of the first logical IP, a second software driver is used to call the function of the second logical IP, the first logical IP and the second logical IP are merged into a third logical IP, and the third logical IP includes two interrupt numbers and two groups of task registers, as well as all functions of the first logical IP and the second logical IP. When it is determined to call the same function as the first logical IP, the first software driver is controlled to configure the first group of task registers of the third logical IP, and the first software driver corresponds to the first interrupt number of the third logical IP. When it is determined to call the same function as the second logical IP, the second software driver is controlled to configure the second group of task registers of the third logical IP, and the second software driver corresponds to the second interrupt number of the third logical IP.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and more particularly to a method and device for software and hardware interaction for accessing a logic IP. Background Art

[0002] With the development of chip technology, chips for the same market are divided into high-end, mid-range and low-end according to their performance and function richness. Low-end chips pursue low cost. Since the more logical intellectual property (IP), the higher the cost of the chip, low-end chips usually merge logical IPs, merging the functions of multiple logical IPs with some computing reuse into one logical IP. The merged logical IP includes all the functions of multiple logical IPs before the merger. High-end chips pursue high performance. Since the more logical IPs, the higher the chip's working efficiency, high-end chips usually make multiple logical IPs independent. Mid-range chips look at actual needs and appropriately merge some logical IPs.

[0003] Currently, one logical IP corresponds to one software driver. When the logical IP is split or merged (referred to as splitting and merging), the software driver also needs to be split and reconstructed, resulting in the need to develop and maintain multiple sets of software drivers with different architectures, which is costly. In addition, changes in the architecture of the software driver may cause changes in the application programming interface (API), which in turn will change the way users use it, resulting in a poor user experience. Summary of the invention

[0004] The embodiments of the present application provide a method and device for software-hardware interaction for accessing a logical IP, which can reuse software drivers, reduce costs, and improve user experience when splitting or merging logical IPs.

[0005] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0006] In the first aspect, the embodiment of the present application provides a method for software-hardware interaction for accessing a logic IP, wherein the first software driver is used to call the function of the first logic intellectual property IP, the second software driver is used to call the function of the second logic IP, the third logic IP is obtained by merging the first logic IP and the second logic IP, the third logic IP includes two interrupt numbers and two groups of task registers, the two groups of task registers are the first group of task registers and the second group of task registers, and the third logic IP includes all functions of the first logic IP and the second logic IP; the method includes: when determining to call the same function as the first logic IP, controlling the first software driver to configure the first group of task registers of the third logic IP, wherein the first software driver corresponds to the first interrupt number of the third logic IP. When determining to call the same function as the second logic IP, controlling the second software driver to configure the second group of task registers of the third logic IP, wherein the second software driver corresponds to the second interrupt number of the third logic IP.

[0007] Therefore, the software and hardware interaction method for accessing logical IP provided by the present application can reuse the software driver before the merger when the logical IP is split, so that the merged software driver does not need to develop and maintain a new software architecture. Compared with the prior art that merges logical IPs and requires reconstruction of the software driver, new development and maintenance of a new software architecture, which leads to high costs and changes in user usage methods, the present application effectively reduces costs, and the reuse of software drivers will not cause changes in the API interface, thereby improving the user experience.

[0008] In one possible design, the first operating system includes a first software driver, the second operating system includes a second software driver, and the first software driver is the same as or different from the second software driver. Therefore, the hardware-software interaction method for accessing a logical IP provided by the present application can include two identical software drivers in two operating systems, and the two identical software drivers can call the same logical IP, and the logical IP supports a dual-ear mechanism. As a result, there is no need to call the function of the logical IP through inter-core communication between the two operating systems, which reduces latency and work complexity, and effectively improves the work efficiency of the system. In addition, the hardware-software interaction method for accessing a logical IP provided by the present application can also enable two different software drivers located in different operating systems to call the function of the same logical IP.

[0009] In one possible design, each group of task registers includes multiple sets of task registers, the first software driver corresponds to the first mutex register, and the second software driver corresponds to the second mutex register; controlling the first software driver to configure the first group of task registers of the third logic IP includes: controlling the first software driver to lock the first mutex register, configuring at least one set of task registers in the multiple sets of task registers of the first group of task registers, and controlling the first software driver to unlock the first mutex register; controlling the second software driver to configure the second group of task registers of the third logic IP includes: controlling the second software driver to lock the second mutex register, configuring at least one set of task registers in the multiple sets of task registers of the second group of task registers, and controlling the second software driver to unlock the second mutex register. Therefore, the software and hardware interaction method for accessing the logic IP provided by the present application, under normal working conditions, when the software driver accesses the logic IP, the software driver needs to first lock its corresponding mutex register, and then configure its corresponding task register. That is, before the software driver configures the task register, the condition of locking the corresponding mutex register is added, so that the software driver can control whether it can continue to configure the task register through this condition.

[0010] In a possible design, when the third logic IP is reset, the first software driver is controlled to lock the first mutex register and the second mutex register, and after the third logic IP is reset, the first software driver is controlled to unlock the first mutex register and the second mutex register; or, the second software driver is controlled to lock the first mutex register and the second mutex register, and after the third logic IP is reset, the second software driver is controlled to unlock the first mutex register and the second mutex register. Therefore, the software and hardware interaction method for accessing the logic IP provided by the present application, when the dual-ear logic IP or the multi-ear logic IP is reset, one of the software drivers performs the reset operation, and controls the software driver to lock all the mutex registers. Therefore, other software drivers cannot lock their corresponding mutex registers, that is, they cannot configure their corresponding task registers. Thereby, it can be avoided that other software drivers cannot know whether to perform the reset operation, and continue to configure the task register, resulting in the loss of write configuration and read status error, and the reset operation of the logic IP is reasonably executed.

[0011] In one possible design, the first software driver corresponds to the first clock switch register, the second software driver corresponds to the second clock switch register, and the first clock switch register and the second clock switch register are used to control the logic clock of the third logic IP; the method also includes: when the first clock switch register and the second clock switch register are both closed, the logic clock of the third logic IP is closed; when the first clock switch register or the second clock switch register is opened, the logic clock of the third logic IP is opened. Therefore, the software and hardware interaction method for accessing the logic IP provided by the present application introduces two logic clock registers under the dual-ear logic IP mechanism, and as long as one of the clock switch registers is opened, the logic clock of the logic IP is in the open state, and only when both clock switch registers are closed, the logic clock of the logic IP is in the closed state. Thereby, the switching state of the logic clock can be reasonably controlled.

[0012] In one possible design, each group of task registers includes multiple sets of task registers, each set of task registers includes a task priority register, and the task priority register is used to reflect the priority of a set of task registers; the method also includes: controlling the third logic IP to execute each set of task registers according to the priority corresponding to each set of task registers. Therefore, the software and hardware interaction method for accessing the logic IP provided by the present application is provided with a task priority register in each set of task registers of the logic IP, so that the logic IP determines the order of execution according to the priority of each set of task registers, thereby reasonably arranging the task preemption process.

[0013] In a possible design, controlling the third logic IP to execute each set of task registers according to the priority corresponding to each set of task registers includes: controlling the first software driver to traverse multiple sets of task registers of the first group of task registers to find the first set of task registers in an idle state; controlling the first software driver to configure the first set of task registers, and the first set of task registers changes from an idle state to a waiting state; controlling the second software driver to traverse multiple sets of task registers of the second group of task registers to find the second set of task registers in an idle state; controlling the second software driver to configure the second set of task registers, and the second set of task registers changes from an idle state to a waiting state; controlling the third logic IP to traverse the first set of task registers and the second set of task registers in the waiting state, and comparing the priority of the first set of task registers and the priority of the second set of task registers; when the priority of the first set of task registers is higher than the priority of the second set of task registers, controlling the third logic IP to execute the first set of task registers, and the first set of task registers changes from a waiting state to a busy state; after the third logic IP executes the first set of task registers, the first set of task registers changes from a busy state to an idle state, and controlling the third logic IP to report the interrupt status of task completion to the first software driver according to the first interrupt number. Therefore, the software-hardware interaction method for accessing the logic IP provided by the present application enables the logic IP to compare the priorities of multiple sets of task registers in the waiting state, select the set of task registers with the highest priority for execution first, and thus reasonably arrange the task preemption process.

[0014] In a possible design, the method further includes: when the priority of the first set of task registers is the same as the priority of the second set of task registers, controlling the third logic IP to compare the configuration time of the first set of task registers and the configuration time of the second set of task registers, and when the configuration time of the second set of task registers is earlier than the configuration time of the first set of task registers, controlling the third logic IP to execute the second set of task registers. Thus, in the software and hardware interaction method for accessing the logic IP provided by the present application, the logic IP compares the priorities of multiple sets of task registers in a waiting state, and if multiple sets of task registers have the same priority and are all the highest priority, the logic IP continues to compare the configuration time of the multiple sets of task registers with the same priority, and selects the set of task registers with the earliest configuration time for priority execution, thereby reasonably arranging the task preemption process.

[0015] In one possible design, each group of task registers includes multiple sets of task registers, each set of task registers includes a task cancel register, and the task cancel register is used to instruct the third logic IP to cancel the execution of a set of task registers in the third logic IP. Therefore, the software and hardware interaction method for accessing the logic IP provided by the present application is provided with a task cancel register in each set of task registers of the logic IP. When the scene is switched or a set of task registers needs to be destroyed, the task cancel register can be configured to cancel the execution of the set of task registers, thereby reasonably canceling the task.

[0016] In a possible design, the method further includes: controlling the first software driver to configure a first task cancellation register, the first task cancellation register being located in the first set of task registers; when the first set of task registers is in a busy state, controlling the third logic IP to complete the execution of the first set of task registers, and reporting the interrupt status of task completion to the first software driver according to the first interrupt number; when the first set of task registers is in a waiting state, controlling the third logic IP to cancel the execution of the first set of task registers, and reporting the interrupt status of task cancellation to the first software driver according to the first interrupt number. Therefore, the software and hardware interaction method for accessing the logic IP provided in the present application, after configuring a set of task registers with a task cancellation register, if the set of task registers is being executed by the logic IP, that is, in a busy state, the task cancellation fails, and the logic IP continues to execute the set of task registers. If the set of task registers has not been executed by the logic IP, that is, in a waiting state, the execution of the set of task registers is canceled, that is, the task cancellation is successful, thereby reasonably canceling the task.

[0017] In the second aspect, the embodiment of the present application provides a device for accessing a logical IP, wherein a first software driver is used to call a function of a first logical intellectual property IP, a second software driver is used to call a function of a second logical IP, a third logical IP is obtained by merging the first logical IP and the second logical IP, the third logical IP includes two interrupt numbers and two groups of task registers, the two groups of task registers are a first group of task registers and a second group of task registers, and the third logical IP includes all functions of the first logical IP and the second logical IP; the device includes a first control unit and a second control unit; when determining to call the same function as the first logical IP, the first control unit is used to control the first software driver to configure the first group of task registers of the third logical IP, wherein the first software driver corresponds to the first interrupt number of the third logical IP. When determining to call the same function as the second logical IP, the second control unit is used to control the second software driver to configure the second group of task registers of the third logical IP, wherein the second software driver corresponds to the second interrupt number of the third logical IP. The beneficial effects achieved in the second aspect can refer to the beneficial effects in the first aspect.

[0018] In one possible design, the first operating system includes a first software driver, the second operating system includes a second software driver, and the first software driver is the same as or different from the second software driver.

[0019] In one possible design, each group of task registers includes multiple sets of task registers, the first software driver corresponds to the first mutex lock register, and the second software driver corresponds to the second mutex lock register; the first control unit is specifically used to control the first software driver to lock the first mutex lock register, configure at least one set of task registers in the multiple sets of task registers of the first group of task registers, and control the first software driver to unlock the first mutex lock register; the second control unit is also specifically used to control the second software driver to lock the second mutex lock register, configure at least one set of task registers in the multiple sets of task registers of the second group of task registers, and control the second software driver to unlock the second mutex lock register.

[0020] In one possible design, when the third logic IP is reset, the first control unit is also used to control the first software driver to lock the first mutex lock register and the second mutex lock register, and after the third logic IP is reset, the first control unit is also used to control the first software driver to unlock the first mutex lock register and the second mutex lock register; or, the second control unit is also used to control the second software driver to lock the first mutex lock register and the second mutex lock register, and after the third logic IP is reset, the second control unit is also used to control the second software driver to unlock the first mutex lock register and the second mutex lock register.

[0021] In one possible design, the first software driver corresponds to the first clock switch register, the second software driver corresponds to the second clock switch register, the first clock switch register and the second clock switch register are used to control the logic clock of the third logic IP; when the first control unit controls the first clock switch register to close and the second control unit controls the second clock switch register to close, the logic clock of the third logic IP is closed; when the first control unit controls the first clock switch register to open or the second control unit controls the second clock switch register to open, the logic clock of the third logic IP is opened.

[0022] In one possible design, each group of task registers includes multiple sets of task registers, each set of task registers includes a task priority register, and the task priority register is used to reflect the priority of a set of task registers; the device also includes a third control unit, and the third control unit is used to: control the third logic IP to execute each set of task registers according to the priority corresponding to each set of task registers.

[0023] In a possible design, the first control unit is specifically used to control the first software driver to traverse multiple sets of task registers of the first group of task registers to find the first set of task registers in an idle state; control the first software driver to configure the first set of task registers, and the first set of task registers changes from an idle state to a waiting state; the second control unit is specifically used to control the second software driver to traverse multiple sets of task registers of the second group of task registers to find the second set of task registers in an idle state; control the second software driver to configure the second set of task registers, and the second set of task registers changes from an idle state to a waiting state; the third control unit is specifically used to control the third logic IP to traverse the first set of task registers and the second set of task registers in the waiting state, and compare the priority of the first set of task registers with the priority of the second set of task registers; when the priority of the first set of task registers is higher than the priority of the second set of task registers, control the third logic IP to execute the first set of task registers, and the first set of task registers changes from a waiting state to a busy state; after the third logic IP executes the first set of task registers, the first set of task registers changes from a busy state to an idle state, and control the third logic IP to report the interrupt status of task completion to the first software driver according to the first interrupt number.

[0024] In one possible design, the third control unit is also used to: when the priority of the first set of task registers is the same as the priority of the second set of task registers, control the third logic IP to compare the configuration time of the first set of task registers and the configuration time of the second set of task registers; when the configuration time of the second set of task registers is earlier than the configuration time of the first set of task registers, control the third logic IP to execute the second set of task registers.

[0025] In a possible design, each group of task registers includes multiple sets of task registers, each set of task registers includes a task cancel register, and the task cancel register is used to instruct the third logic IP to cancel the execution of a set of task registers in the third logic IP.

[0026] In one possible design, the first control unit is also used to: control the first software driver to configure a first task cancel register, which is located in the first set of task registers; when the first set of task registers is in a busy state, the third control unit controls the third logic IP to execute the first set of task registers, and reports the interrupt status of task completion to the first software driver according to the first interrupt number; when the first set of task registers is in a waiting state, the third control unit controls the third logic IP to cancel the execution of the first set of task registers, and reports the interrupt status of task cancellation to the first software driver according to the first interrupt number.

[0027] In a third aspect, a computer-readable storage medium stores computer instructions, which, when executed on an electronic device, causes the electronic device to execute the method described in the first aspect and any possible design of the first aspect.

[0028] In a fourth aspect, a computer program product is provided. When the computer program product is run on a computer, the electronic device executes the method described in the first aspect and any possible design of the first aspect.

[0029] The beneficial effects corresponding to the other aspects mentioned above can be found in the description of the beneficial effects of the first aspect and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the merger of logical IP;

[0031] Figure 2 A schematic diagram of accessing logical IP in an AMP deployment scenario;

[0032] Figure 3 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0033] Figure 4 A schematic diagram of a software and hardware interaction method for accessing a logical IP provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of a logical IP merger provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of accessing a logical IP in an AMP deployment scenario provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of operating a mutex register when the logic IP provided in an embodiment of the present application works normally;

[0037] Figure 8 A schematic diagram of operating a mutex register when resetting a logic IP provided in an embodiment of the present application;

[0038] Fig. 9 A schematic diagram of a task preemption process provided in an embodiment of the present application;

[0039] Fig.10 A schematic diagram of a task preemption process provided in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0041] Fig.12 A schematic diagram of the structural composition of a communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] For ease of understanding, some concepts related to the embodiments of the present application are exemplarily described for reference, as shown below:

[0043] Intellectual property (IP): A hardware accelerator integrated into a chip. The logical IP may include multiple sets of task registers. When the software driver writes a value to the task register of the logical IP, it can be understood that when the software driver configures a task in the task register of the logical IP, the logical IP is used to execute the corresponding task in the task register. The corresponding relationship between the value written by the software driver to the task register and the task executed by the logical IP is agreed in advance.

[0044] Symmetric Multi-Processing (SMP): A service deployment method in a chip. The characteristic of SMP deployment is that there is only one operating system instance. All central processing units (CPUs) run one operating system instance together, and all services are deployed on the same operating system instance.

[0045] Asymmetric multi-processing (AMP): A service deployment method in a chip. The characteristic of AMP deployment is that there are multiple CPUs, each running an operating system instance. The services are deployed in multiple operating system instances. The services deployed on each operating system instance can be completely different or partially the same, mainly based on the actual needs of the product.

[0046] Single ear: A logical IP integrates an interrupt number and a set of task registers, and can only be called by a software driver, where a set of task registers can include multiple sets of task registers.

[0047] N ears: A logical IP integrates N interrupt numbers and N groups of task registers, and can be called by N software drivers, where N is an integer greater than 0. When N is an integer greater than or equal to 2, it indicates multiple ears, and when N is equal to 2, it indicates dual ears, that is, a logical IP integrates two interrupt numbers and two groups of task registers, and can be called by two software drivers, and each group of task registers can include multiple sets of task registers.

[0048] In the prior art, there is only a single-ear software and hardware interaction mode. The embodiment of the present application is a solution design for a multi-ear software and hardware interaction mode.

[0049] Mutex register (mutex_reg): In the embodiment of the present application, the mutex register is a system register, that is, a system-side register located outside the logic IP. Therefore, any logic IP reset cannot clear the mutex register, and only the chip system reset can clear the mutex register. When the value of the mutex register is 0, the software driver can write any non-zero value x to the mutex register to lock the mutex register. After the mutex register is locked, the software driver cannot change the value of the mutex register by writing any value other than the non-zero value x to the mutex register. Only when the software driver writes the same non-zero value x to the mutex register again can the value of the mutex register be changed back to 0, that is, the mutex register is unlocked.

[0050] Task register: Task register is a task register integrated in the logic IP. A set of task registers includes multiple sets of task registers, each set of task registers includes multiple registers, and the software driver configures a set of task registers, which can be understood as configuring a task. In the embodiment of the present application, a set of task registers includes a task priority register and a task cancellation register. A set of task registers includes three states: idle, wait, and busy. A set of task registers in an idle state indicates that the set of task registers has not been configured, so it can be found and configured by the software driver. A set of task registers in a wait state indicates that the set of task registers has been configured by the software driver but has not been executed by the logic IP, so it can be found and executed by the logic IP. A set of task registers in a busy state indicates that the set of task registers has begun to be executed by the logic IP. After the logic IP executes the set of task registers, the set of task registers will become idle again.

[0051] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the present embodiment, unless otherwise specified, "multiple" means two or more.

[0052] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, the meaning of "coupled" refers to the direct or indirect connection of two or more circuit elements. For example, the coupling of A and B may mean that A is directly connected to B, or A is connected to B through C.

[0053] At present, a logic IP includes an interrupt number and a set of task registers, corresponding to a software driver, that is, a software driver operates the logic IP and calls the function of the logic IP. Figure 1 As shown, the logic IP (A) includes an interrupt number (A) and a set of task registers (A), corresponding to a software driver (A). Among them, the task register (A) is located in the logic IP (A), and the task register (A) can include multiple sets of task registers. The software driver (A) corresponds to the interrupt number (A) of the logic IP (A), and the logic IP (A) and the software driver (A) interact. The software driver (A) configures the task to any one or more sets of task registers of the task register (A), and calls the function of the logic IP (A), so that the logic IP (A) executes the task configured by the software driver (A). After executing the task, the logic IP (A) reports the interrupt status of the task completion to the software driver (A), so that the software driver (A) knows that the logic IP (A) has completed the task, so that the software driver (A) can perform the interrupt post-processing of the corresponding task. The logic IP (B) includes an interrupt number (B) and a set of task registers (B), corresponding to a software driver (B). The multiple sets of task registers included in the task register (B) may be partially identical to or completely different from the multiple sets of task registers included in the task register (A).

[0054] When merging logical IP (A) and logical IP (B), you need to merge both the logical IP and the software driver corresponding to the logical IP. Figure 1As shown, the logic IP (A) and the logic IP (B) are merged into the logic IP (C), and the software driver (A) and the software driver (B) are merged into the software driver (C). The merged logic IP (C) includes all the functions of the logic IP (A) and the logic IP (B). Similarly, the merged software driver (C) includes all the functions of the software driver (A) and the software driver (B). However, when merging the software driver, a new software architecture needs to be developed and maintained for the merged software driver (C), resulting in high software development and maintenance costs. In addition, changes in the software architecture will cause changes in the application programming interface (API), and thus changes in the way users use the software. Accordingly, when the logic IP is separated, there is also the need to develop and maintain multiple software architectures and a poor user experience.

[0055] At the same time, when the chip's business deployment mode is AMP deployment, in some scenarios, the businesses of multiple systems may need to call the functions of the logical IP (D). However, in order to save the cost of the chip, only one logical IP (D) will be integrated, and the software driver (D) that can call the logical IP (D) function will only be deployed in one system. Other systems need to obtain the capabilities of the software driver (D) through inter-core communication to call the functions of the logical IP (D), but inter-core communication will lead to high CPU usage, high latency, and complex business interactions. Figure 2 As shown, taking a dual system as an example, the services of the master system and the slave system both need to call the capability of the logical IP (D), but the software driver (D) corresponding to the logical IP (D) is only deployed in the slave system. Therefore, the master system can only obtain the capability of the logical IP (D) through the software driver (D) on the slave system by communicating between cores of the slave system.

[0056] Therefore, the present application proposes a method for software-hardware interaction for accessing a logical IP. Considering that in the prior art, when the logical IP is split or merged, it is necessary to develop and maintain multiple sets of software architectures, resulting in high overhead and high cost, and the API interface may change, causing the user's usage mode to change, affecting the user experience. The present application controls the first software driver to call the function of the third logical IP, controls the second software driver to call the function of the third logical IP, and the first software driver is also used to call the function of the first logical IP, and the second software driver is also used to call the function of the second logical IP, and the first logical IP and the second logical IP are merged into the third logical IP. It can be understood that the present application reuses the first software driver and the second software driver corresponding to the first logical IP and the second logical IP before the merger, so that the merged third logical IP corresponds to two software drivers and can be called by the two software drivers in time division multiplexing. Since software drivers with different functions can share the same underlying logical IP, there is no need to develop and maintain multiple sets of different software architectures, which effectively reduces costs, and software driver reuse will not cause changes in the API interface, so the user experience can be improved. In addition, under the AMP deployment mode, when the services of multiple systems need to call the functions of the same logical IP, this application supports the deployment of the same software driver on multiple systems. The software drivers in different systems can share the same underlying logical IP, avoiding the ability to obtain software drivers through inter-core communication, which leads to high CPU usage, large latency and complex business interaction. Therefore, it can reduce latency and work complexity and effectively improve the system's work efficiency.

[0057] The software-hardware interaction method for accessing a logical IP proposed in the embodiment of the present application can be applied to the scenario of splitting and combining logical IPs, such as merging multiple logical IPs into one logical IP, or splitting one logical IP into multiple logical IPs. It can also be applied to the scenario of accessing logical IPs, such as the scenario of software driver and logical IP interaction, wherein the software driver is located in the operating system, and the operating system may include one or more software drivers, and the logical IP is located in the chip, and the chip may include one or more logical IPs, and the software driver executes the corresponding business by calling the function of the logical IP.

[0058] A software and hardware interaction method for accessing a logical IP proposed in an embodiment of the present application is applied to a communication device, such as Figure 3 As shown, it shows a schematic diagram of the structure of a communication device, the communication device includes an operating system and a chip, Figure 3 The communication device 300 is taken as an example of a communication device. The communication device 300 includes a software driver unit 301 and a logic IP unit 302.

[0059] It is to be understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the communication device 300. In other embodiments of the present application, the communication device 300 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0060] The software driver unit 301 may include one or more software drivers, each software driver corresponds to a logical IP, and multiple software drivers may correspond to the same logical IP. The software driver can call the function of the corresponding logical IP, such as configuring the task register in the logical IP. In the embodiment of the present application, the software driver unit 301 includes a first software driver 3011 and a second software driver 3012, wherein the first software driver 3011 and the second software driver 3012 share the same third logical IP 3021 at the bottom layer, and the first software driver 3011 and the second software driver 3012 can call the function of the third logical IP 3021 in time division multiplexing. The software driver unit 301 can configure the task register included in the logical IP unit 302, and the task register includes a task priority register and a task cancellation register, etc., and can also configure the system register outside the logical IP unit 302, and the system register includes a mutex register and a clock switch register, etc.

[0061] The logic IP unit 302 may include one or more logic IPs, each of which may include one or more interrupt numbers and one or more groups of task registers, corresponding to one or more software drivers. After the software driver configures the task to the task register in the logic IP, the logic IP can execute the task configured in the task register and report the interrupt status to the software driver. In the embodiment of the present application, the logic IP unit 302 includes a third logic IP 3021, and the third logic IP 3021 corresponds to the first software driver 3011 and the second software driver 3012. The first software driver 3011 and the second software driver 3012 can use time-division multiplexing to call the function of the third logic IP 3021, and the third logic IP 3021 can serially execute the tasks configured by the first software driver 3011 and the second software driver 3012.

[0062] Using the communication device provided by the present application, the method for accessing the logical IP proposed by the present application for the communication device is introduced below in conjunction with the accompanying drawings. In the process of accessing the logical IP, the software driver is multiplexed when the logical IP is disassembled and assembled, so that multiple software drivers with different functions time-division multiplex the same logical IP.

[0063] like Figure 4As shown, the embodiment of the present application provides a method for software and hardware interaction for accessing a logical IP, which is applied to a communication device. Taking the communication device as a communication device 300 as an example, the communication device 300 includes a software driver unit 301 and a logical IP unit 302. The software driver unit 301 includes a first software driver 3011 and a second software driver 3012, and the logical IP unit 302 includes a third logical IP 3021. The method includes:

[0064] Step 410: When it is determined that the same function as the first logic IP is called, control the first software driver to configure the first group of task registers of the third logic IP.

[0065] like Figure 5 As shown, it shows the process of merging the first logical IP and the second logical IP into the third logical IP3021. Among them, the task register 1 in the first logical IP corresponds to the first group of task registers in the third logical IP3021 after merging, and the task register 2 in the second logical IP corresponds to the second group of task registers in the third logical IP3021 after merging. Task register 1 is not completely the same as the first group of task registers, and task register 2 is not completely the same as the second group of task registers. Before the logical IP is merged, the first software driver 3011 corresponds to the first logical IP, the first software driver 3011 corresponds to the interrupt number 1 of the first logical IP, and the first software driver 3011 is used to call the function of the first logical IP. It can be understood that the first software driver 3011 can configure the task register 1 in the first logical IP. After the logical IP is merged, the merged third logical IP3021 includes all the functions of the first logical IP and the second logical IP. The first software driver 3011 corresponds to the third logic IP 3021, and the first software driver 3011 corresponds to the first interrupt number of the third logic IP. The first software driver 3011 is used to call the function of the third logic IP 3021. It can be understood that the first software driver 3011 is used to call the same function as the first logic IP in the third logic IP 3021, that is, the first software driver 3011 can configure the first group of task registers in the third logic IP 3021.

[0066] Exemplarily, after the logical IPs are merged, when it is determined to call the same function as the first logical IP, the first software driver 3011 is controlled to configure the first group of task registers of the third logical IP 3021 to call the function. The first software driver 3011 corresponds to the first interrupt number of the third logical IP 3021, and the first software driver 3011 is also used to call the function of the first logical IP. Figure 5As shown, it can be understood that before the logical IP is merged, the first software driver 3011 corresponds to the first logical IP and can configure the first group of task registers in the first logical IP. After the logical IP is merged, the first software driver 3011 corresponds to the third logical IP 3021 and can configure the first group of task registers in the third logical IP 3021.

[0067] Step 420: When it is determined that the same function as the second logic IP is called, control the second software driver to configure the second group of task registers of the third logic IP.

[0068] Among them, Figure 5 As shown, before the logical IP is merged, the second software driver 3012 corresponds to the second logical IP, the second software driver 3012 corresponds to the interrupt number 2 of the second logical IP, and the second software driver 3012 is used to call the function of the second logical IP, which can be understood as the second software driver 3012 can configure the task register 2 in the second logical IP. The second software driver 3012 corresponds to the third logical IP 3021, the second software driver 3012 corresponds to the second interrupt number of the third logical IP, and the second software driver 3012 is used to call the function of the third logical IP 3021, which can be understood as the second software driver 3012 is used to call the same function in the third logical IP 3021 as the second logical IP, that is, the second software driver 3012 can configure the second group of task registers in the third logical IP 3021.

[0069] Exemplarily, after the logical IP is merged, when it is determined to call the same function as the second logical IP, the second software driver 3012 is controlled to configure the second group of task registers of the third logical IP 3021 to call the function. The second software driver 3012 corresponds to the second interrupt number of the third logical IP 3021, and the second software driver 3012 is also used to call the function of the second logical IP. Figure 5 As shown, it can be understood that before the logical IP is merged, the second software driver 3012 corresponds to the second logical IP and can configure the second group of task registers in the second logical IP. After the logical IP is merged, the second software driver 3012 corresponds to the third logical IP 3021 and can configure the second group of task registers in the third logical IP 3021.

[0070] The above steps 410 and 420 can be understood as merging the first logical IP and the second logical IP into a third logical IP 3021. The third logical IP 3021 includes two interrupt numbers and two groups of task registers, corresponding to two software drivers. Among them, the two interrupt numbers included in the third logical IP 3021 are the first interrupt number and the second interrupt number, respectively. The first interrupt number and the second interrupt number can be the same as the interrupt number 1 integrated by the first logical IP before the logical IP is merged, and the interrupt number 2 integrated by the second logical IP, or can be different from the interrupt number 1 and the interrupt number 2. This application is not limited. The two interrupt numbers included in the third logical IP 3021 are only used to indicate the third logical IP 3021 in one chip. The two groups of task registers included in the third logical IP 3021 are the first group of task registers and the second group of task registers. The two software drivers corresponding to the third logical IP 3021 are the first software driver 3011 and the second software driver 3012 corresponding to the first logical IP and the second logical IP before the logical IP is merged. Furthermore, among the two groups of task registers included in the third logic IP3021, each group of task registers includes multiple sets of task registers, that is, the third logic IP3021 includes multiple sets of task registers.

[0071] It can be seen that the merged third logic IP 3021 supports being called by two software drivers, and is a dual-ear logic IP, and the third logic IP 3021 reuses the software drivers corresponding to the first logic IP and the second logic IP before the merger. The software drivers are not merged when the logic IPs are merged, and the first software driver 3011 and the second software driver 3012 can time-division multiplex the third logic IP 3021 after the merger. Therefore, the present application does not need to redevelop and maintain a new software architecture, which reduces costs and improves user experience.

[0072] It is understandable that the present application does not limit the number of logical IPs to be merged. When N logical IPs are merged, it is only necessary to make the merged logical IP support the N-ear mechanism, that is, the N software drivers corresponding to the N logical IPs before the merger can be reused, and the N software drivers share the functions of the merged logical IP in time division multiplexing. Accordingly, when the merged logical IP needs to be split into N independent logical IPs, it is only necessary to restore the single-ear mechanism for each independent logical IP.

[0073] In some optional embodiments, the first operating system includes a first software driver, the second operating system includes a second software driver, and the first software driver is different from the second software driver.

[0074] Among them, since the first software driver can call the function of the third logical IP, the second software driver can also call the function of the third logical IP, it can be understood that two different software drivers located in different operating systems can share the function of the same logical IP. That is, when the present application merges different logical IPs, the logical IPs to be merged can be located in the same operating system or in different operating systems, and the present application does not limit this.

[0075] In some optional embodiments, the first operating system includes a first software driver, the second operating system includes a second software driver, and the first software driver is the same as the second software driver.

[0076] like Figure 6 As shown, when the chip in the communication device 300 is deployed as AMP, taking the dual system as an example, the first operating system includes a first software driver, the first software driver can call the function of the third logical IP, the second operating system includes a second software driver, the second software driver can call the function of the third logical IP, and the first software driver is the same as the second software driver. Since the first operating system and the second operating system both include the same software driver, and the same software driver shares the function of the same logical IP. Therefore, when the first operating system needs to call the function of the third logical IP, the first operating system does not need to call the function of the third logical IP by communicating with the second operating system core. The first operating system can directly call the function of the third logical IP through the first software driver, thereby reducing delays and work complexity, and effectively improving the work efficiency of the system. That is, when the services of multiple operating systems need to call the same logical IPE through software driver E, it is only necessary to allow the logical IPE to support the multi-ear mechanism, and deploy software driver E in the multiple operating systems, so that each operating system can call the logical IPE through the software driver E included in itself, without the need for inter-core communication.

[0077] In some optional embodiments, the first operating system includes a first software driver and a second software driver, and the second operating system includes a first software driver and a second software driver.

[0078] Among them, the first software driver and the second software driver can both call the function of the third logic IP, and the first operating system and the second operating system both include the first software driver and the second software driver. It can be understood that the third logic IP is a four-ear logic IP, that is, a multi-ear logic IP, and the first operating system and the second operating system can include multiple identical software drivers, thereby reducing latency and work complexity and effectively improving the work efficiency of the system.

[0079] It is understandable that the present application does not limit the number of operating systems. When the services of N operating systems require the functions of a certain logical IP, it is only necessary to make this logical IP support the N-ear mechanism, and then deploy software drivers with the same functions on the N operating systems, so that the N software drivers with the same functions can share the functions of the same logical IP in time-division multiplexing.

[0080] The N-ear mechanism of this application essentially virtualizes the number of logical IPs. From a software perspective, it can be seen as "N logical IPs", but from a hardware perspective, there is essentially only one logical IP. Therefore, the N-ear mechanism needs to solve the four core problems of "reset, clock control, task preemption and task cancellation". The following takes the communication device as communication device 300, and there is only one operating system in the communication device 300 as an example to introduce the process of handling four problems in a software-hardware interaction method for accessing logical IPs proposed in this application.

[0081] Problem 1: Reset

[0082] In some optional embodiments, the above step 410 includes controlling the first software driver to lock the first mutex register (mutex_reg), configuring at least one set of task registers in the multiple sets of task registers of the first group of task registers, and controlling the first software driver to unlock the first mutex register. The above step 420 includes controlling the second software driver to lock the second mutex register, configuring at least one set of task registers in the multiple sets of task registers of the second group of task registers, and controlling the second software driver to unlock the second mutex register.

[0083] Among them, the third logic IP3021 corresponds to the first group of task registers and the second group of task registers, and each group of task registers includes multiple sets of task registers. The mutex register is a system-side register located outside the logic IP. The first software driver corresponds to the first mutex register, and the second software driver corresponds to the second mutex register. It can be understood that each software driver corresponds to a mutex register. If the third logic IP3021 corresponds to N software drivers, there are N mutex registers corresponding to the N software drivers.

[0084] In the embodiment of the present application, under normal working conditions, when the software driver accesses the logic IP, the software driver needs to lock the corresponding mutex register first. When the value in the mutex register is 0, the software driver can configure the mutex register, that is, at this time, the software driver can write any non-zero value x into the mutex register, and the mutex register is written with any non-zero value x, which represents that the mutex register is locked. After the software driver locks the corresponding mutex register, the software driver configures at least one set of task registers in a group of task registers corresponding to the logic IP. After at least one set of task registers is configured, the software driver writes the same non-zero value x into the corresponding mutex register, so that the value in the mutex register returns to 0, which represents unlocking the mutex register. After the software driver completes the configuration of at least one set of task registers, the logic IP can start executing the at least one set of task registers.

[0085] For example, Figure 7 As shown, during normal operation, the first software driver 3011 corresponds to the first mutex register, and the second software driver 3012 corresponds to the second mutex register. The first software driver 3011 first configures a non-zero value x to the first mutex register to lock the first mutex register, and then configures at least one set of task registers in the third logic IP3021. After the configuration is completed, the first software driver 3011 configures a non-zero value x to the first mutex register to unlock the first mutex register, and then the third logic IP3021 executes the task configured in the task register. Correspondingly, the second software driver 3012 first configures a non-zero value y to the second mutex register to lock the second mutex register, and then configures at least one set of task registers in the third logic IP3021. After the configuration is completed, the second software driver 3012 configures a non-zero value y to the second mutex register to unlock the second mutex register, and then the third logic IP3021 executes the task configured in the task register.

[0086] It can be seen that during normal operation, the first software driver 3011 only configures the first mutex lock register, and the second software driver 3012 only configures the second mutex lock register. The two software drivers do not interfere with each other when configuring the mutex lock registers, and both can lock the corresponding mutex lock registers normally. Therefore, the two software drivers of the dual-ear logic IP can complete the normal function configuration in parallel.

[0087] In some optional embodiments, the method further includes: when the third logic IP is reset, controlling the first software driver to lock the first mutex register and the second mutex register, and after the third logic IP is reset, controlling the first software driver to unlock the first mutex register and the second mutex register. Or, controlling the second software driver to lock the first mutex register and the second mutex register, and after the third logic IP is reset, controlling the second software driver to unlock the first mutex register and the second mutex register.

[0088] Among them, when the logical IP is reset, the operation of the task register of the software driver to configure the logical IP is invalid, and the write configuration will be lost and the read status will be wrong. Therefore, in order to avoid this situation during the reset of the logical IP, it is necessary to ensure that no software driver can operate the logical IP when the logical IP is reset. Since the second software driver 3012 cannot know that the first software driver 3011 is performing a reset operation when the first software driver 3011 is performing a reset operation, in the embodiment of the present application, when the third logical IP is reset, the first software driver 3011 is controlled to lock the first mutex register and the second mutex register, that is, a non-zero value x is written to both the first mutex register and the second mutex register. At this time, the first software driver 3011 cannot operate the third logic IP due to the reset operation. Since the second software driver 3012 needs to lock the second mutex register first during normal operation, that is, write a non-zero value y, but the second mutex register has been locked in advance by the first software driver, the second software driver 3012 cannot perform the operation of writing the non-zero value y on the second mutex register. Therefore, the second software driver 3012 cannot operate the third logic IP, thereby achieving the technical effect of mutual exclusion between the first software driver 3011 and the second software driver 3012 during reset.

[0089] For example, Figure 8 As shown, when the third logic IP3021 is reset, the first software driver 3011 is controlled to lock the first mutex register and the second mutex register. After the third logic IP3021 is reset, the first software driver 3011 is controlled to unlock the first mutex register and the second mutex register, so that the first software driver 3011 and the second software driver 3012 can resume normal operation. Or, when the third logic IP3021 is reset, the second software driver 3012 is controlled to lock the first mutex register and the second mutex register. After the third logic IP3021 is reset, the second software driver 3012 is controlled to unlock the first mutex register and the second mutex register, so that the first software driver 3011 and the second software driver 3012 can resume normal operation.

[0090] It can be seen that each of the multiple software drivers corresponding to the logical IP can reset the logical IP, but it is necessary to ensure that the non-zero values ​​configured when the multiple software drivers corresponding to the logical IP lock the mutex register are different (for example, the above x is not equal to y), that is, to ensure that the mutex register locked by the first software driver 3011 will not be unlocked by the second software driver 3012, so that the two software drivers of the double-ear logical IP are mutually exclusive during the reset configuration.

[0091] In addition, since all task registers will be cleared after the logic IP is reset, the software driver needs to read the values ​​of the task registers that have been configured but not yet executed and save them to an external device, such as a double data rate synchronous dynamic random-access memory (DDR SDRAM) before resetting the logic IP. After the logic IP is reset, the software driver reads the values ​​of the task registers from the DDR again and reconfigures them into the task registers.

[0092] There are two ways for the software driver to configure registers (write only (WO) or read and read (WR) type registers). One is that the software driver directly writes the value to the register through the register interface. This type of register must be configured through the advanced peripheral bus (APB), and multiple sets of register interfaces need to be defined. The other is that the software driver writes the register value to the memory and configures the memory address to the APB register. The logic IP directly reads the register information from the memory. This type of register can be loaded from the DDR through the advanced extensible interface (AXI). This type of register does not need to define multiple sets of register interfaces. Similarly, there are two ways for the software driver to read the status of the register (read only (RO) register). One is to read the status through the APB register, and multiple sets of register interfaces need to be defined. The other is that the logic IP writes the register status to the DDR, and the software driver reads the status from the DDR. This type of register does not need to define multiple sets of register interfaces.

[0093] In order to simplify the recovery operation after reset and to reduce the chip area cost, the present application divides the register into two sections, one section is the register of APB attribute and the other section is the register of AXI attribute. According to whether it can be read and written, the register is divided into three categories: write-only (WO) register, read-write (WR) register and read-only (RO) register. Among them, the read-only register is the register of the return status of the logic IP. The software driver can only read information from the read-only register and cannot write the value to the read-only register. Therefore, this type of register does not require the software driver to configure. After the register is segmented, in normal operation, after the software driver locks the mutex register, it only needs to configure the registers classified as write-only and read-write types in the APB attribute. The number of these registers is relatively small compared to the total number of registers, so it can reduce the time for the software driver to configure the register, so that the mutex register can be unlocked quickly, which improves the chip working efficiency. As shown in Table 1 below, it shows an example of the system register mentioned in this application. As shown in Table 2 below, it shows an example of the register of the APB attribute in the logic IP of this application.

[0094] Table 1

[0095] Register Name property describe Remark XXX_RESET_CRG WO CRG reset register of XXX module XXX_CKEN0_CRG WR XXX module ear 0 clock switch XXX_CKEN1_CRG WR XXX module ear 1 clock switch XXX_MUTEX_REG0 WR Mutex lock register of XXX module XXX_MUTEX_REG1 WR Mutex lock register of XXX module

[0096] Table 2

[0097]

[0098]

[0099] Problem 2: Clock Control

[0100] In some optional embodiments, when both the first clock switch register and the second clock switch register are controlled to be closed, the logic clock of the third logic IP is closed. When the first clock switch register or the second clock switch register is controlled to be opened, the logic clock of the third logic IP is opened.

[0101] Among them, the clock switch register is a system register, that is, a system-side register located outside the logic IP. Before the logic IP works, the software driver needs to configure the clock switch register to turn on the logic clock of the logic IP. The logic clock can be understood as the power module of the logic IP. Only after the logic clock is turned on can the logic IP be powered on. Since the logic clock is strongly related to the power consumption of the chip, the logic clock is always on when the logic IP is not working, which will cause the chip to consume more power. Therefore, the software driver will turn off the logic clock when the logic IP is not working.

[0102] At present, a single-ear logic IP corresponds to one software driver, and the software driver exclusively uses one logic IP. When the software driver has no task assigned to the logic IP, the logic IP does not need to work. At this time, the software driver controls a corresponding clock switch register to be closed to turn off the logic clock of the logic IP. It can be understood that when the software driver is working, the software driver controls the corresponding clock switch register to be in an open state, and when the software driver is not working, the software driver controls the corresponding clock switch register to be in a closed state. After the dual-ear mechanism is introduced in the embodiment of the present application, if the logical clock is turned off when the first software driver is not working, the second software driver will also not work. Therefore, the clock control method of a single ear is not suitable for a dual-ear or multi-ear mechanism.

[0103] In this application, the dual-ear logic IP introduces dual clock switch registers, the first software driver corresponds to the first clock switch register, the second software driver corresponds to the second clock switch register, that is, the third logic IP corresponds to the first clock switch register and the second clock switch register, and the first clock switch register and the second clock switch register are used to control the logic clock of the third logic IP. When the first clock switch register and the second clock switch register are both closed, the logic clock of the third logic IP is closed, and when one of the first clock switch register or the second clock switch register is opened, the logic clock of the third logic IP is opened. That is, in the dual-ear mechanism, as long as one of the clock switch registers is opened, the logic clock of the logic IP is in the open state, and only when both clock switch registers are closed, the logic clock of the logic IP is in the closed state.

[0104] It can be understood that the logic IP of the N-ear mechanism needs to introduce N clock switch registers. Only when all N clock switch registers are closed, the logic clock of the logic IP is turned off. When any one or more clock switch registers are turned on, the logic clock of the logic IP is turned on.

[0105] Problem 3: Task preemption

[0106] In some optional embodiments, the third logic IP is controlled to execute each set of task registers according to the priority corresponding to each set of task registers.

[0107] Among them, the third logic IP3021 includes a first group of task registers and a second group of task registers, the first software driver 3011 can configure the first group of task registers of the third logic IP3021, and the second software driver 3012 can configure the second group of task registers of the third logic IP3021, each group of task registers includes multiple sets of task registers, each set of task registers includes a task priority register, and the task priority register is used to reflect the priority of a set of task registers. Taking the example that each group of task registers of the third logic IP3021 includes two sets of task registers, the third logic IP3021 includes 4 sets of task registers, wherein the first group of task registers includes task register 0 and task register 1, and the second group of task registers includes task register 2 and task register 3. Task register 0, task register 1, task register 2 and task register 3 all include task priority registers, and the task priority register located in task register 0 is used to reflect the priority of task register 0, and the task priority register located in task register 1 is used to reflect the priority of task register 1, and so on.

[0108] The third logic IP3021 executes each set of task registers according to the priority corresponding to each set of task registers. For example, if the first software driver configures task register 0 and task register 1, the priority of task register 0 is level 1, and the priority of task register 1 is level 2. The smaller the level of the agreed priority, the higher the priority level. Therefore, after the third logic IP3021 compares task register 0 and task register 1, it will execute task register 0 first and then task register 1.

[0109] In some optional embodiments, such as Fig. 9 As shown, controlling the third logic IP to execute each set of task registers according to the priority corresponding to each set of task registers specifically includes the following steps:

[0110] Step 1: Control the first software driver to traverse multiple sets of task registers of the first group of task registers and find the first set of task registers in an idle state.

[0111] For example, each group of task registers of the third logic IP3021 includes two sets of task registers. The third logic IP3021 includes four sets of task registers, namely, task register 0, task register 1, task register 2, and task register 3, wherein task register 0 and task register 1 belong to the first group of task registers, and task register 2 and task register 3 belong to the second group of task registers. The first software driver 3011 traverses task registers 0 and task register 1 of the first group of task registers, and finds a set of task registers in an idle state, that is, task registers that are not configured by the first software driver 3011, for example, the first set of task registers in an idle state is found to be task register 0.

[0112] Step 2: Control the first software driver to configure the first set of task registers, and the first set of task registers changes from an idle state to a waiting state.

[0113] After the first software driver 3011 finds the first set of task registers in the idle state, it will configure the first set of task registers, that is, write values ​​into the first set of task registers, so that the first set of task registers changes from the idle state to the wait state (wait), that is, changes to the state of waiting for the execution of the logic IP. For example, the first software driver 3011 configures task register 0, and task register 0 changes from the idle state to the wait state of waiting for the execution of the logic IP.

[0114] Step 3: Control the second software driver to traverse multiple sets of task registers of the second group of task registers and find the second set of task registers in the idle state.

[0115] The second software driver 3012 traverses task register 2 and task register 3 of the second group of task registers and finds a set of task registers in idle state, that is, task registers that are not configured by the second software driver 3012. For example, the second set of task registers found by the second software driver 3012 in idle state is task register 2.

[0116] Step 4: Control the second software driver to configure the second set of task registers, and the second set of task registers changes from an idle state to a waiting state.

[0117] After the second software driver 3012 finds the second set of task registers in the idle state, it will configure the second set of task registers, that is, write values ​​into the second set of task registers, so that the second set of task registers changes from the idle state to the waiting state, that is, changes to the state of waiting for the execution of the logic IP. For example, the second software driver 3012 configures task register 2, and task register 2 changes from the idle state to the waiting state of waiting for the execution of the logic IP.

[0118] Step 5: Control the third logic IP to traverse the first set of task registers and the second set of task registers in the waiting state, and compare the priority of the first set of task registers with the priority of the second set of task registers.

[0119] The third logic IP3021 traverses multiple sets of task registers in the waiting state. For example, the third logic IP3021 traverses task register 0 and task register 2 in the waiting state, and compares the priorities of task register 0 and task register 2 according to the priorities reflected by the task priority registers included in task register 0 and task register 2.

[0120] When the priority of the first set of task registers is higher than the priority of the second set of task registers, the third logic IP is controlled to execute the first set of task registers. When the third logic IP 3021 executes the first set of task registers, the first set of task registers changes from a waiting state to a busy state, indicating that the third logic IP 3021 is executing the first set of task registers. For example, when the priority of task register 0 is higher than the priority of task register 2, the third logic IP 3021 first executes task register 0, and task register 0 changes from a waiting state to a busy state.

[0121] Step 6: After the third logic IP completes executing the first set of task registers, the first set of task registers changes from a busy state to an idle state, and the third logic IP is controlled to report the interrupt status of task completion to the first software driver according to the first interrupt number.

[0122] After the third logic IP3021 executes the first set of task registers, the first set of task registers changes from a busy state to an idle state, that is, the first set of task registers changes to an idle state that can be found again by the first software driver 3011. At the same time, since the first software driver 3011 corresponds to the first interrupt number of the third logic IP3021, the third logic IP3021 reports the interrupt status of task completion to the first software driver 3011 according to the first interrupt number, indicating that the task of the first set of task registers has been completed. For example, after the third logic IP3021 executes task register 0, task register 0 changes from a busy state to an idle state, and at the same time, the third logic IP3021 reports the interrupt status of task completion to the first software driver 3011 according to the first interrupt number.

[0123] In some optional embodiments, when the priority of the first set of task registers is the same as the priority of the second set of task registers, the third logic IP is controlled to compare the configuration time of the first set of task registers and the configuration time of the second set of task registers, and when the configuration time of the second set of task registers is earlier than the configuration time of the first set of task registers, the third logic IP is controlled to execute the second set of task registers.

[0124] Wherein, when the third logic IP3021 traverses multiple sets of task registers in the waiting state, if multiple task registers with the highest priority are found, the configuration time of the multiple task registers with the highest priority is compared again, and the task register with the earlier configuration time is executed first. For example, when the third logic IP3021 traverses multiple sets of task registers in the waiting state, if task register 0 and task register 2 with the same priority are found, after comparing the configuration time of task register 0 and task register 2, if the configuration time of task register 2 is earlier than the configuration time of task register 0, the third logic IP3021 executes task register 2 first. In the above steps 1 to 6, the first half of step 1 and step 2 are steps executed by the first software driver 3011, the first half of step 3 and step 4 are steps executed by the second software driver 3012, and the remaining steps are steps executed by the logic IP. Wherein, step 1 and step 2 are executed serially in the first software driver 3011, and step 3 and step 4 are executed serially in the second software driver 3012. Step 1 and step 2 are executed in parallel with step 3 and step 4. Steps 5 and 6 are executed serially in the logic IP. After step 6 is completed, the logic IP will repeat from step 5 to execute the next round of tasks. Steps 1 to 4 and steps 5 and 6 are executed in parallel, which can be understood as the logic IP is in working state, that is, when executing tasks, multiple software drivers can still configure task registers.

[0125] like Fig.10As shown, the logic IP includes two groups of task registers, the first software driver corresponds to the first group of task registers, the second software driver corresponds to the second group of task registers, the first group of task registers includes task register 0 and task register 1, and the second group of task registers includes task register 2 and task register 3 as an example, showing the task preemption process diagram provided by the embodiment of the present application. Among them, the first software driver is controlled to traverse the first group of task registers, find the task register in the idle state and configure the task register, and the task register changes from the idle state to the waiting state, and the second software driver is controlled to traverse the second group of task registers, find the task register in the idle state and configure the task register, and the task register changes from the idle state to the waiting state. Therefore, the first software driver can configure task register 0 and task register 1, and the second software driver can configure task register 2 and task register 3. Taking the priority of task register 0 as priority 0, the priority of task register 1 as priority 1, the priority of task register 2 as priority 2, and the priority of task register 3 as priority 3 as an example, the smaller the number of agreed priorities, the higher the priority level. The control logic IP traverses the task registers in the waiting state, compares the priorities of the task registers in the waiting state, selects the task register with the highest priority, and if there are multiple task registers with the same priority, selects the task register with the earliest configuration time. The control logic IP starts to execute the selected task register, and the task register changes from the waiting state to the busy state. After the logic IP executes the task register, the task register changes from the busy state to the idle state. After that, the control logic IP reports the interrupt status of the task completion. It can be understood that if the executed task register is task register 0 or task register 1, the control logic IP reports the interrupt status of the task completion to the first software driver. If the executed task register is task register 2 or task register 3, the control logic IP reports the interrupt status of the task completion to the second software driver. After the control logic IP reports the interrupt status of the task completion, the control logic IP starts to execute the next round of tasks, that is, the control logic IP traverses the task registers in the waiting state, compares the priorities of the task registers in the waiting state, selects the task register with the highest priority, and continues to repeat the subsequent process.

[0126] Problem 4: Cancelling a task

[0127] In some optional embodiments, each group of task registers includes multiple sets of task registers, each set of task registers includes a task cancel register, and the task cancel register is used to instruct the third logic IP to cancel the execution of a set of task registers in the third logic IP.

[0128] Among them, the third logic IP3021 includes a first group of task registers and a second group of task registers, and each group of task registers includes multiple sets of task registers, so the third logic IP3021 includes multiple sets of task registers. In the double-ear multi-task mode, since the high-priority task register has the right to preempt the low-priority task register, in extreme cases, a low-priority task register may be preempted all the time and cannot be executed by the logic IP for a long time. And when the scene is switched, it is necessary to destroy the business of the existing scene and create the business of the new scene. When destroying the business, it is necessary to cancel the task registers that have been configured to the logic IP but have not been executed by the logic IP in time, which can be understood as canceling the task registers in the waiting state in time. Therefore, each set of task registers in the present application includes a task cancellation register, and the task cancellation register is used to instruct the third logic IP3021 to cancel the execution of a set of task registers in the third logic IP3021. Taking the example that each set of task registers of the third logic IP3021 includes two sets of task registers, the third logic IP3021 includes 4 sets of task registers, namely task register 0, task register 1, task register 2 and task register 3. Task register 0, task register 1, task register 2 and task register 3 all include task cancel registers. The task cancel register located in task register 0 is used to instruct the third logic IP3021 to cancel the execution of task register 0, and the task cancel register located in task register 1 is used to instruct the third logic IP3021 to cancel the execution of task register 1, and so on.

[0129] In some optional embodiments, the first software driver is controlled to configure a first task cancellation register, and the first task cancellation register is located in the first set of task registers. When the first set of task registers is in a busy state, the third logic IP is controlled to execute the first set of task registers, and report the interrupt status of task completion to the first software driver according to the first interrupt number. When the first set of task registers is in a waiting state, the third logic IP is controlled to cancel the execution of the first set of task registers, and report the interrupt status of task cancellation to the first software driver according to the first interrupt number.

[0130] Exemplarily, when a certain set of task registers needs to be canceled, for example, when the first set of task registers needs to be canceled, the first software driver configures the task cancel register in the first set of task registers, and instructs the third logic IP3021 to cancel the execution of the first set of task registers. When the first set of task registers is in a busy state, that is, the first set of task registers is being executed by the third logic IP3021, the third logic IP3021 is controlled to complete the execution of the first set of task registers. Since the first software driver 3011 corresponds to the first interrupt number of the third logic IP3021, the third logic IP3021 is controlled to report the interrupt status of the task completion to the first software driver according to the first interrupt number, which can be understood as the failure of the cancellation of the first set of task registers. When the first set of task registers is in a waiting state, that is, the first set of task registers has not been executed by the third logic IP3021, the third logic IP3021 is controlled to cancel the execution of the first set of task registers, and the interrupt status of the task cancellation is reported to the first software driver according to the first interrupt number, which can be understood as the success of the cancellation of the first set of task registers.

[0131] Therefore, a method for software-hardware interaction for accessing a logical IP provided by an embodiment of the present application can be applied to a communication device. When the logical IP is split, the software driver before the merger is reused, so that the software driver after the merger does not need to develop and maintain a new software architecture. Compared with the prior art that requires the reconstruction of the software driver to merge the logical IP, the new development and maintenance of the new software architecture leads to high costs and changes in user usage. The present application effectively reduces costs, and the reuse of software drivers will not cause changes in the API interface, thus improving the user experience. In addition, under the AMP deployment mode, when the services of multiple systems need to call the functions of the same logical IP, the present application supports the deployment of the same software driver on multiple systems. The software drivers in different systems can share the same underlying logical IP, avoiding the ability to obtain the software driver through inter-core communication, which leads to high CPU occupancy, large delays, and complex business interactions. Therefore, it can reduce delays and work complexity, and effectively improve the work efficiency of the system.

[0132] In some optional embodiments, the above four core issues of "reset, clock control, task preemption, and task cancellation" can also be implemented through other operation modes. For example, when resetting the logic IP, the mutex register is not used. In a single system, the mutual exclusion is realized by the software lock of the operating system, such as the spin lock spin_lock of the Linux system. In a dual system, the reset operation of the logic IP is uniformly performed by a software driver in one system through inter-core communication. The dual clock switch is not used during clock control. In a single system, the task working status of the software driver is queried and the task working status of the software driver is summarized to a software driver to uniformly judge whether the logic clock can be turned off. In a dual system, the task working status of the software driver is summarized to a system through inter-core communication to uniformly judge whether the logic clock can be turned off (this method is only suitable for module-level clock gating, not frame-level clock gating). When preempting a task, only the software driver can configure the priority, and the logic IP arbitrates the preemption, but the preemption algorithm can be customized. When canceling a task, only the software driver can configure the cancel command, and the logic IP responds to the cancel command, but the judgment of the cancel command can be set in multiple places. For example, when the software driver configures the cancel command, the logic IP immediately determines whether the task can be canceled, or when the software driver configures the cancel command, if the logic IP is working, it waits for the logic IP to complete the execution of the current task register, and determines whether the task can be canceled before the logic IP starts to enter the next round of tasks. Alternatively, you can also not cancel the command, and agree that a certain set of task registers will be forced to be canceled after being preempted a certain number of times or waiting for a period of time, so as to avoid the situation where low-priority task registers may not be executed.

[0133] It is understandable that, in order to realize the above functions, the above communication device includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0134] The embodiment of the present application can divide the functional modules of the above-mentioned communication device according to the above-mentioned method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0135] In the case of dividing each functional module into corresponding functional modules, Fig.11 A possible schematic diagram of the composition of the communication device 300 involved in the above embodiment is shown. Fig.11 As shown, the communication device 1100 may include: a first control unit 1101 , a second control unit 1102 and a third control unit 1103 .

[0136] The first control unit 1101 may be used to support the communication device 1100 in executing the above-mentioned step 410, step 1, step 2, etc., and / or other processes for the technology described herein.

[0137] The second control unit 1102 may be used to support the communication device 1100 to execute the above-mentioned step 420, step 3, step 4, etc., and / or other processes for the technology described herein.

[0138] The third control unit 1103 may be used to support the communication device 1100 to execute the above-mentioned steps 5, 6, etc., and / or other processes for the technology described herein.

[0139] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0140] The communication device 1100 provided in this embodiment is used to execute the software-hardware interaction method for accessing the logical IP, and thus can achieve the same effect as the above-mentioned implementation method.

[0141] In the case of integrated units, such as Fig.12As shown, the embodiment of the present application discloses a communication device 1200, which may be the communication device 300 in the above embodiment. The communication device 1200 may include a processing module, a storage module and a communication module. Among them, the processing module can be used to control and manage the actions of the communication device 1200, for example, it can be used to support the communication device 1200 to perform the above steps 410, 420, steps 1-6, etc. The storage module can be used to support the communication device 1200 to store program codes and data, etc. The communication module can be used to support the communication device 1200 to communicate with other devices.

[0142] Of course, the unit modules in the above-mentioned communication device 1200 include but are not limited to the above-mentioned processing module, storage module and communication module.

[0143] Among them, the processing module can be a processor or a controller. It can implement or execute various exemplary logic boxes, modules and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a neural network processor (neural network processing unit, NPU), a digital signal processing (digital signal processing, DSP) and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a device that interacts with other external devices.

[0144] For example, the processing module is the processor 1201, the storage module is the memory 1202, and the communication module is the communication interface 1203. The processor 1201, the memory 1202, the communication interface 1203, etc. may be connected together, for example, via a bus.

[0145] An embodiment of the present application also provides a computer-readable storage medium, which stores computer program code. When the computer instructions are executed on a computer or a processor, the computer or the processor executes the software-hardware interaction method for accessing the logic IP in the above embodiment.

[0146] An embodiment of the present application also provides a computer program product, which includes computer instructions. When the computer instructions are executed on a computer or a processor, the computer or the processor executes the above-mentioned related steps to implement the software-hardware interaction method for accessing the logical IP in the above-mentioned embodiment.

[0147] Among them, the communication device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0148] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0149] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0150] The units described as separate components may or may not be physically separated, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0151] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0152] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0153] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A software and hardware interaction method for accessing a logical IP, characterized in that: The first software driver is used to call the function of the first logic intellectual property IP, the second software driver is used to call the function of the second logic IP, the third logic IP is obtained by merging the first logic IP and the second logic IP, the third logic IP includes two interrupt numbers and two groups of task registers, the two groups of task registers are the first group of task registers and the second group of task registers, and the third logic IP includes all the functions of the first logic IP and the second logic IP; the method includes: When determining to call the same function as the first logic IP, controlling the first software driver to configure the first group of task registers of the third logic IP, wherein the first software driver corresponds to the first interrupt number of the third logic IP; When it is determined to call the same function as the second logic IP, the second software driver is controlled to configure the second group of task registers of the third logic IP, wherein the second software driver corresponds to the second interrupt number of the third logic IP.

2. The method according to claim 1, characterized in that The first operating system includes the first software driver, and the second operating system includes the second software driver. The first software driver is the same as or different from the second software driver.

3. The method according to claim 1 or 2, characterized in that: Each group of task registers includes multiple sets of task registers, the first software driver corresponds to a first mutex register, and the second software driver corresponds to a second mutex register; The first group of task registers for controlling the first software driver to configure the third logic IP includes: Control the first software driver to lock the first mutex register, configure at least one set of task registers among the multiple sets of task registers of the first group of task registers, and control the first software driver to unlock the first mutex register; The second group of task registers for controlling the second software driver to configure the third logic IP includes: The second software driver is controlled to lock the second mutex lock register, at least one set of task registers among the multiple sets of task registers of the second group of task registers is configured, and the second software driver is controlled to unlock the second mutex lock register.

4. The method according to claim 3, characterized in that The method further comprises: when the third logic IP is reset, Control the first software driver to lock the first mutex lock register and the second mutex lock register; After the third logic IP is reset, the first software driver is controlled to unlock the first mutex lock register and the second mutex lock register; or, Control the second software driver to lock the first mutex lock register and the second mutex lock register; After the third logic IP is reset, the second software driver is controlled to unlock the first mutex lock register and the second mutex lock register.

5. The method according to claim 1 or 2, characterized in that: The first software driver corresponds to a first clock switch register, the second software driver corresponds to a second clock switch register, and the first clock switch register and the second clock switch register are used to control the logic clock of the third logic IP; The method further comprises: When both the first clock switch register and the second clock switch register are controlled to be closed, the logic clock of the third logic IP is closed; When the first clock switch register or the second clock switch register is controlled to be turned on, the logic clock of the third logic IP is turned on.

6. The method according to claim 1 or 2, characterized in that: Each group of task registers includes multiple sets of task registers, each set of task registers includes a task priority register, and the task priority register is used to reflect the priority of a set of task registers; the method also includes: The third logic IP is controlled to execute each set of task registers according to the priority corresponding to each set of task registers.

7. The method according to claim 6, characterized in that The controlling the third logic IP to execute each set of task registers according to the priority corresponding to each set of task registers comprises: Control the first software driver to traverse multiple sets of task registers of the first group of task registers and find the first set of task registers in an idle state; Control the first software to drive and configure the first set of task registers, so that the first set of task registers changes from an idle state to a waiting state; Control the second software driver to traverse the plurality of sets of task registers of the second group of task registers and find the second set of task registers in an idle state; Control the second software to drive and configure the second set of task registers, so that the second set of task registers changes from an idle state to a waiting state; Control the third logic IP to traverse the first set of task registers and the second set of task registers in a waiting state, and compare the priority of the first set of task registers with the priority of the second set of task registers; When the priority of the first set of task registers is higher than the priority of the second set of task registers, controlling the third logic IP to execute the first set of task registers, and the first set of task registers changes from a waiting state to a busy state; After the third logic IP executes the first set of task registers, the first set of task registers changes from a busy state to an idle state, and controls the third logic IP to report the interrupt status of task completion to the first software driver according to the first interrupt number.

8. The method according to claim 7, characterized in that The method further comprises: When the priority of the first set of task registers is the same as the priority of the second set of task registers, the third logic IP is controlled to compare the configuration time of the first set of task registers and the configuration time of the second set of task registers; when the configuration time of the second set of task registers is earlier than the configuration time of the first set of task registers, the third logic IP is controlled to execute the second set of task registers.

9. The method according to claim 1 or 2, characterized in that: Each group of task registers includes multiple sets of task registers, and each set of task registers includes a task cancel register, which is used to instruct the third logic IP to cancel the execution of a set of task registers in the third logic IP.

10. The method according to claim 9, characterized in that The method further comprises: Control the first software to drive and configure a first task cancel register, wherein the first task cancel register is located in a first set of task registers; When the first set of task registers is in a busy state, controlling the third logic IP to complete executing the first set of task registers, and reporting the interrupt status of task completion to the first software driver according to the first interrupt number; When the first set of task registers is in a waiting state, the third logic IP is controlled to cancel the execution of the first set of task registers, and the interrupt status of the task cancellation is reported to the first software driver according to the first interrupt number.

11. A device for accessing a logical IP, characterized in that: The first software driver is used to call the function of the first logic intellectual property IP, the second software driver is used to call the function of the second logic IP, the third logic IP is obtained by merging the first logic IP and the second logic IP, the third logic IP includes two interrupt numbers and two groups of task registers, the two groups of task registers are the first group of task registers and the second group of task registers, and the third logic IP includes all the functions of the first logic IP and the second logic IP; the device includes a first control unit and a second control unit; When determining to call the same function as the first logic IP, the first control unit is used to control the first software driver to configure the first group of task registers of the third logic IP, wherein the first software driver corresponds to the first interrupt number of the third logic IP; When it is determined to call the same function as the second logical IP, the second control unit is used to control the second software driver to configure the second group of task registers of the third logical IP, wherein the second software driver corresponds to the second interrupt number of the third logical IP.

12. The device according to claim 11, characterized in that The first operating system includes the first software driver, and the second operating system includes the second software driver. The first software driver is the same as or different from the second software driver.

13. The device according to claim 11 or 12, characterized in that Each group of task registers includes multiple sets of task registers, the first software driver corresponds to a first mutex register, and the second software driver corresponds to a second mutex register; The first control unit is specifically configured to control the first software driver to lock the first mutex register, configure at least one set of task registers among the multiple sets of task registers of the first group of task registers, and control the first software driver to unlock the first mutex register; The second control unit is further specifically used to control the second software driver to lock the second mutex register, configure at least one set of task registers among the multiple sets of task registers of the second group of task registers, and control the second software driver to unlock the second mutex register.

14. The device according to claim 13, characterized in that When the third logic IP is reset, The first control unit is further used to control the first software driver to lock the first mutex lock register and the second mutex lock register; After the third logic IP is reset, the first control unit is further used to control the first software driver to unlock the first mutex lock register and the second mutex lock register; or, The second control unit is further used to control the second software driver to lock the first mutex lock register and the second mutex lock register; After the third logic IP is reset, the second control unit is further configured to control the second software driver to unlock the first mutex lock register and the second mutex lock register.

15. The device according to claim 11 or 12, characterized in that The first software driver corresponds to a first clock switch register, the second software driver corresponds to a second clock switch register, and the first clock switch register and the second clock switch register are used to control the logic clock of the third logic IP; When the first control unit controls the first clock switch register to be closed and the second control unit controls the second clock switch register to be closed, the logic clock of the third logic IP is closed; When the first control unit controls the first clock switch register to be turned on or the second control unit controls the second clock switch register to be turned on, the logic clock of the third logic IP is turned on.

16. The device according to claim 11 or 12, characterized in that Each group of task registers includes multiple sets of task registers, each set of task registers includes a task priority register, and the task priority register is used to reflect the priority of a set of task registers; the device also includes a third control unit, and the third control unit is used to: The third logic IP is controlled to execute each set of task registers according to the priority corresponding to each set of task registers.

17. The device according to claim 16, characterized in that The first control unit is specifically used to control the first software driver to traverse multiple sets of task registers of the first group of task registers and find the first set of task registers in an idle state; Control the first software to drive and configure the first set of task registers, so that the first set of task registers changes from an idle state to a waiting state; The second control unit is specifically used to control the second software driver to traverse multiple sets of task registers of the second group of task registers and find the second set of task registers in an idle state; Control the second software to drive and configure the second set of task registers, so that the second set of task registers changes from an idle state to a waiting state; The third control unit is specifically used to control the third logic IP to traverse the first set of task registers and the second set of task registers in a waiting state, and compare the priority of the first set of task registers with the priority of the second set of task registers; When the priority of the first set of task registers is higher than the priority of the second set of task registers, controlling the third logic IP to execute the first set of task registers, and the first set of task registers changes from a waiting state to a busy state; After the third logic IP executes the first set of task registers, the first set of task registers changes from a busy state to an idle state, and controls the third logic IP to report the interrupt status of task completion to the first software driver according to the first interrupt number.

18. The device according to claim 17, characterized in that The third control unit is further used for: When the priority of the first set of task registers is the same as the priority of the second set of task registers, the third logic IP is controlled to compare the configuration time of the first set of task registers and the configuration time of the second set of task registers; when the configuration time of the second set of task registers is earlier than the configuration time of the first set of task registers, the third logic IP is controlled to execute the second set of task registers.

19. The device according to claim 11 or 12, characterized in that Each group of task registers includes multiple sets of task registers, and each set of task registers includes a task cancel register, which is used to instruct the third logic IP to cancel the execution of a set of task registers in the third logic IP.

20. The device according to claim 19, characterized in that The first control unit is also used for: Control the first software to drive and configure a first task cancel register, wherein the first task cancel register is located in a first set of task registers; When the first set of task registers is in a busy state, the third control unit controls the third logic IP to complete the execution of the first set of task registers, and reports the interrupt status of task completion to the first software driver according to the first interrupt number; When the first set of task registers is in a waiting state, the third control unit controls the third logic IP to cancel the execution of the first set of task registers, and reports the interrupt status of the task cancellation to the first software driver according to the first interrupt number.

21. A computer-readable storage medium, characterized in that: Computer instructions are stored, and when the computer instructions are executed on the electronic device, the electronic device executes the method described in any one of claims 1 to 10.

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