Pipelined cache data buffering method and apparatus with variable delay and bit width
By generating micro-requests for pipelined access to each data array group during cache requests, the number of data array groups and the amount of RAM are determined, enabling variable bit-width and latency data caching. This solves the problem in existing technologies where fixed data size and latency cannot adapt to processor frequency modulation and bus bandwidth requirements, thus improving the flexibility and adaptability of the cache.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAT UNIV OF DEFENSE TECH
- Filing Date
- 2023-05-26
- Publication Date
- 2026-07-24
AI Technical Summary
In existing technologies, the data size of the cached data pipeline and the RAM multi-cycle latency are fixed, which cannot adapt to scenarios where the latency needs to be changed when the processor frequency is adjusted, as well as the bus bandwidth requirements of different processors.
When receiving cache requests, micro-requests are generated to access each data array group in a pipelined manner. The number of data array groups and the amount of RAM in each data array group are determined based on the pipeline width and the cache data block width, thereby realizing data caching with variable bit width and variable latency.
It enables flexible adaptation to the data width requirements of different processors in the cache data pipeline, and is suitable for scenarios where RAM multi-cycle latency changes due to processor frequency changes, thus improving the flexibility and adaptability of high-speed data cache.
Smart Images
Figure CN116701245B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of high-speed data caching technology, and in particular to a pipelined high-speed data caching method and apparatus with variable latency and bit width. Background Technology
[0002] To extend the battery life of portable devices (such as mobile phones, MP3 players, multimedia players, and laptops), it is essential to develop new energy-saving technologies. As a new energy-saving method, DVFS (Dynamic Voltage and Frequency Scaling) can effectively optimize processor power consumption based on the varying computing power requirements of the applications running on the chip. However, this also introduces various demands on RAM multi-cycle latency. Furthermore, different processors have different bus bandwidth requirements. For processors with high bus bandwidth requirements, the data width of the cache data pipeline should increase accordingly, and vice versa. Current technologies typically use cache data pipelines with fixed data sizes and fixed RAM multi-cycle latency, which cannot adapt to scenarios where latency needs to be changed during processor frequency scaling, nor can they meet the bus bandwidth requirements of different processors. Summary of the Invention
[0003] The technical problem to be solved by this invention is: In view of the technical problems existing in the prior art, this invention provides a pipelined high-speed cache data caching method and apparatus with variable latency and bit width that is simple to implement, low in cost, high in caching efficiency, and highly flexible and adaptable. It can realize a pipelined high-speed data cache with variable latency and variable bit width, and can be applied to scenarios where the latency needs to be changed when the processor frequency is adjusted, as well as meet the bus bandwidth requirements of different processors.
[0004] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:
[0005] A pipelined cache data caching method with variable latency and bit width, comprising the following steps:
[0006] S01. When a cache request is received, the request is pipelined into the cache corresponding to multiple data array groups. By changing the information in the request, pipelined read and write micro-requests for each data array group are spontaneously generated.
[0007] S02. Configure the pipeline width and cache data block width according to the currently required data bit width, and determine the number of data array groups and the number of RAMs used for caching data in each data array group according to the configured pipeline width and cache data block width, so as to realize variable bit width data caching;
[0008] S03. Access each data array group in a pipelined manner according to the request. When accessing each data array group, the request for each data array group is pipelined into the register and passed to the next station. Obtain the number of registers accessed by RAM multi-cycle in the current configuration, and select the request from the register that matches the current RAM multi-cycle delay number to realize variable delay data caching.
[0009] Furthermore, step S01 includes: when the pipeline is in a state where it can receive new requests, receiving cache requests through a handshake; after a successful handshake, requesting to cache each cache in turn, with the data ID value in the request corresponding to a data array group in turn; after caching the request, performing micro-operations on the request, increasing the ID number corresponding to the data array group in the request through control signals, so that the internal pipeline generates micro-requests for each data array group until they are cached in the cache of the last data array.
[0010] Furthermore, in step S02, the number of RAMs in a data array group is determined based on the pipeline data width, and the number of data array groups is determined based on the cache data block width. The expression for determining the cache data block width is: cache data block width = number of data array groups × 128 × number of RAMs in a data array group.
[0011] Furthermore, in step S02, the maximum value of the micro-operation ID number is determined based on the amount of RAM, so as to access different data array groups.
[0012] Furthermore, after step S01 and before step S02, each data array group receives a selection signal to enable seamless access to the data array group after a request enters the pipeline.
[0013] Furthermore, steps S02 and S03 are implemented using Python, wherein the pipeline width and cache data block width are configured by adjusting parameters in Python, and the number of registers accessed by RAM in multiple cycles is configured by adjusting parameters in Python.
[0014] A pipelined cache data caching device with variable latency and bit width includes multiple data array groups, each data array group including multiple RAMs for caching data, and further includes:
[0015] The request receiving module is used to receive cache requests. When a cache request is received, it will be pipelined into the cache corresponding to multiple data array groups and generate micro-requests for pipelined access to each data array group.
[0016] The bit width control module is used to configure the pipeline width and cache data block width according to the currently required data bit width, and to determine the number of data array groups and the number of RAMs used for caching data in each data array group according to the configured pipeline width and cache data block width, so as to realize variable bit width data caching.
[0017] The RAM latency control module is used to access each data array group in a pipelined manner according to the request. When accessing each data array group, the request for each data array group is pipelined into the register and passed to the next station. The number of registers accessed in the current RAM multi-cycle is obtained, and the request in the register that is consistent with the current RAM multi-cycle latency is selected to realize variable latency data caching.
[0018] Furthermore, it also includes a counter for controlling the pipeline state and requesting micro-operations. The counter calculates the lifecycle of a request from entering the pipeline to the completion of RAM access, and determines that the pipeline can receive new requests when the count is complete.
[0019] Furthermore, each of the data array groups receives a selection signal. The first selection signal selects the request information on the interface when the request just arrives; otherwise, it selects the request information in the corresponding first buffer. The other selection signals select the request information in the buffer corresponding to the current selection signal when the data ID is the corresponding ID value; otherwise, they select the request information in the next buffer.
[0020] Furthermore, the request information of each selection signal is used to access the corresponding data array group. During the sequential access of the data array group, when accessing the first data array group, the request enters the first register corresponding to the first data array group, and the current data ID is the first ID value; in the next clock cycle, the request with the first ID value enters the second register, and the request with the second ID value enters the first register; in the next clock cycle, the request with the third ID value enters the first register, the request with the second ID value enters the second register, the request with the first ID value enters the third register, and so on.
[0021] Compared with the prior art, the advantages of the present invention are as follows: When a cache request is received, the present invention pipelines the request into the cache corresponding to multiple data array groups, generating micro-requests for pipelined access to each data array group. Based on the pipeline width and the cache data block width, the number of data array groups and the amount of RAM in each data array group are determined, realizing the variability of cache data width. This allows for more flexible adaptation to the data width requirements of different processors in the high-speed cache data pipeline. At the same time, the requests pipeline to access each data array group, and the number of registers is determined based on the RAM multi-cycle latency, realizing the variability of latency. This allows for flexible application in various scenarios where changes in processor frequency lead to changes in the RAM multi-cycle latency, avoiding the design limitations caused by a fixed RAM multi-cycle latency, and greatly improving the flexibility and adaptability of high-speed data caching. Attached Figure Description
[0022] Figure 1 This is a schematic diagram illustrating the implementation process of the pipelined high-speed cache data caching method with variable latency and bit width in this embodiment.
[0023] Figure 2 This is a schematic diagram of the pipeline structure formed in a specific application embodiment (pipeline width is 256 bits, cache data width is 1024 bits). Detailed Implementation
[0024] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.
[0025] like Figure 1 As shown, the steps of the variable latency and bit width pipelined cache data caching method in this embodiment include:
[0026] S01. When a cache request is received, the request is pipelined into the cache corresponding to multiple data array groups. By changing the information in the request, pipelined read and write micro-requests for each data array group are spontaneously generated.
[0027] S02. Configure the pipeline width and cache data block width according to the currently required data bit width. Based on the configured pipeline width and cache data block width, determine the number of data array groups and the amount of RAM used for caching data in each data array group to achieve variable bit width data caching.
[0028] S03. Access each data array group in a pipelined manner according to the request. When accessing each data array group, the request for each data array group is pipelined into the register and passed to the next station. Obtain the number of registers accessed by RAM multi-cycle in the current configuration, and select the request from the register that matches the current RAM multi-cycle delay number to realize variable delay data caching.
[0029] This embodiment, upon receiving a cache request, pipelines the request into caches corresponding to multiple data array groups, generating micro-requests that pipeline access each data array group. Based on the pipeline width and cache data block width, the number of data array groups and the amount of RAM in each data array group are determined, achieving variability in cache data width. This allows for more flexible adaptation to the data width requirements of different processors in the cache data pipeline. Simultaneously, the pipelined access to each data array group and the determination of the number of registers based on the RAM multi-cycle latency clock cycles achieve variability in latency. This enables flexible application in various scenarios where changes in processor frequency lead to changes in the RAM multi-cycle latency clock cycles, avoiding design limitations caused by fixed RAM multi-cycle latency clock cycles, and greatly improving the flexibility and adaptability of high-speed data caching.
[0030] In this embodiment, the specific steps of step S01 include: when the pipeline is in a state that can receive new requests, a cache request is received through a handshake; after the handshake is successful, the request is cached in each cache in turn, and the value of the data ID in the request corresponds to a data array group in turn. After the request is cached, the request is micro-operated, and the ID number corresponding to the data array group in the request is increased by the control signal, so that the internal pipeline generates micro-requests for each data array group until they are cached in the cache of the last data array.
[0031] In a specific application embodiment, the pipeline state is controlled by a counter. For example, counter 1 is set to calculate the lifecycle of a request from entering the pipeline to completing RAM access. When the counter is complete, it means the pipeline can receive new requests, i.e., it is in the Ready state. When the pipeline is in the state of receiving new requests, it receives cached requests through a handshake. The value of the counter when it is complete can be automatically calculated in advance based on configuration parameters. Caching is implemented using registers, and caching behavior is controlled by the counter. Each data array group is configured with its own cache, and the data ID value in the request corresponds to a data array group in sequence. After a successful handshake, the request is cached in cache 0, at which time the data ID is 0; the next cache is cached in cache 1, at which time the data ID is 1, and so on, until it is cached in cache N of the last data array. The request in the cache will only change when the next request enters the pipeline. The number of caches can be automatically calculated in advance based on configuration parameters.
[0032] In step S02 of this embodiment, the number of RAMs in a data array group is determined based on the pipeline data width, and the number of data array groups is determined based on the cache data block width. During access, different data array groups are accessed pipelinedly according to the request. By modifying the parameters related to the pipeline width and cache data block, the required pipelined cache structure can be formed, making the bit width of the cached data variable.
[0033] Taking a RAM cache data width of 144 bits (128 bits of data and 16 bits of ECC encoding) as an example, the pipeline data width is an integer multiple of 128, which determines the number of RAMs in a data array group; the cache data block width determines the number of data array groups, and the cache data block width can be determined by the following formula:
[0034] Cache block width = number of data array groups × 128 × number of RAM in one data array group.
[0035] In step S02 of this embodiment, when the pipeline width and cache data block parameters are modified, different numbers of RAM bodies are automatically generated to form a data array group. The maximum value of the micro-operation ID number is determined according to the number of RAMs. That is, the maximum value of the micro-operation ID number will be automatically calculated and generated according to the number of RAMs, so as to access different data array groups.
[0036] In this embodiment, after step S01 and before step S02, each data array group receives a selection signal to ensure seamless access to the data array group after the request enters the pipeline. For example, each data array group corresponds to a selection signal. Selection signal 0 selects the request information on the interface when the request just enters; otherwise, it selects the request information in buffer 0. Selection signal 1 selects the request information in buffer 0 when the data ID is 1; otherwise, it selects the request information in buffer 1. Selection signal 2 selects the request information in buffer 1 when the data ID is 2; otherwise, it selects the request information in buffer 2, and so on.
[0037] In this embodiment, the RAM multi-cycle delay is configured as 1, 2, 3, 4 cycles. When accessing a data array group, the request for accessing each data array group is pipelined into the register and passed on. The selector selects the request in the register that corresponds to the number of RAM multi-cycle delay cycles. By modifying the parameters, the number of registers accessed by RAM multi-cycle can be configured, thereby changing the number of RAM multi-cycle access cycles.
[0038] In a specific application embodiment, steps S02 and S03 can be implemented using Python. By modifying parameters in Python to configure the pipeline width and cache data block width, as well as parameters to configure the number of registers accessed in RAM per cycle or the number of RAM per cycle accesses, Verilog code for different hardware configurations can be automatically generated. This allows for flexible application to different processors, meeting the different processor requirements for cache data pipeline width. The detailed steps for implementing the above high-speed data cache using Python are as follows:
[0039] Handshake request: When the pipeline is in a state where it can receive new requests, it receives requests through a handshake.
[0040] Request caching: Each data array group has its own cache, automatically generated based on parameters in Python, with no limit on the number. Upon receiving a request, it is pipelined and cached into the cache corresponding to each data array group. Control signals are used to increment the ID number of each data array group within the request, resulting in a pipelined flow of micro-requests to each data array group. This ensures that internally, micro-requests to each data array group are generated in a pipelined manner.
[0041] Request selection: Each data array group has its own corresponding selection signal to implement the bypass function, so that the request can access the data array group without gaps after entering the pipeline.
[0042] Data array group access: Python automatically generates Verilog entries. By modifying Python parameters (pipeline data width, cache data block width), different numbers of RAM blocks are generated to form data array groups, creating cache structures corresponding to cached data of different bit widths. The number of data array groups is determined by the different widths of the cached data, and the pipeline data width determines the amount of RAM in each data array group. During access, different data array groups are accessed pipelinedly according to the request. The maximum value of the micro-operation ID is automatically calculated based on the number of RAM blocks, generating corresponding Verilog code for accessing different data array groups.
[0043] RAM multi-cycle implementation: When accessing a data array group, requests for accessing each data array group are pipelined into registers and passed to the next station. A selector is used to select the request in a register that corresponds to the RAM multi-cycle latency. The number of registers depends on the RAM multi-cycle latency. In this embodiment, the RAM multi-cycle latency is configured as 1, 2, 3, and 4 cycles. Verilog is automatically generated using Python. By modifying the parameters in Python, the number of registers accessed in RAM multi-cycle is configured, thereby changing the RAM multi-cycle latency and generating cache structures with different RAM multi-cycle latency.
[0044] This embodiment of a variable latency and bit-width pipelined cache data caching device includes multiple data array groups, each data array group including multiple RAMs for caching data, and further includes:
[0045] The request receiving module is used to receive cache requests. When a cache request is received, it will be pipelined into the cache corresponding to multiple data array groups and generate micro-requests for pipelined access to each data array group.
[0046] The bit width control module is used to configure the pipeline width and cache data block width according to the currently required data bit width, and to determine the number of data array groups and the number of RAMs used for caching data in each data array group according to the configured pipeline width and cache data block width, so as to realize variable bit width data caching.
[0047] The RAM latency control module is used to access each data array group in a pipelined manner according to the request. When accessing each data array group, the request for each data array group is pipelined into the register and passed to the next station. The number of registers accessed in the current RAM multi-cycle is obtained, and the request in the register that is consistent with the current RAM multi-cycle latency is selected to realize variable latency data caching.
[0048] The device described in this embodiment can generate varying amounts of RAM based on different data bit widths, forming a high-speed cache data array pipeline with variable latency and bit width. It can adapt to scenarios where latency changes during processor frequency adjustment and to the bus bandwidth of different processors, exhibiting high flexibility and adaptability.
[0049] In this embodiment, a counter is also included for controlling the pipeline state and requesting micro-operations. The counter calculates the lifecycle of a request from entering the pipeline to the completion of RAM access. When the count is complete, it is determined that the pipeline can receive new requests.
[0050] This embodiment also includes several registers for implementing functions such as request micro-operations, pipeline design, and variable RAM multi-cycle delay.
[0051] In this embodiment, each data array group receives a selection signal. The first selection signal selects the request information on the interface when the request first arrives; otherwise, it selects the request information in the corresponding first buffer. Other selection signals select the request information in the buffer corresponding to the current selection signal when the data ID is the corresponding ID value; otherwise, they select the request information in the next buffer. For example, each data array group corresponds to one selection signal. Selection signal 0 selects the request information on the interface when the request first arrives; otherwise, it selects the request information in buffer 0. Selection signal 1 selects the request information in buffer 0 when the data ID is 1; otherwise, it selects the request information in buffer 1. Selection signal 2 selects the request information in buffer 1 when the data ID is 2; otherwise, it selects the request information in buffer 2, and so on.
[0052] In this embodiment, the request information of each selection signal is used to access the corresponding data array group. During the sequential access of the data array group, when accessing the first data array group, the request enters the first register corresponding to the first data array group, and the current data ID is the first ID value; in the next clock cycle, the request with the first ID value enters the second register, and the request with the second ID value enters the first register; in the next clock cycle, the request with the third ID value enters the first register, the request with the second ID value enters the second register, the request with the first ID value enters the third register, and so on.
[0053] Specifically, the request information of selection signal 0 is used to access data array group 0, and the request information of selection signal 1 is used to access data array group 1. The data array groups are accessed sequentially. When accessing data array group 0, a request is entered into register 0, at which time the data ID is 0; in the next clock cycle, the request for data ID 0 enters register 1, and the request for data ID 1 enters register 0; in the next clock cycle, the request for data ID 2 enters register 0, the request for data ID 1 enters register 1, the request for data ID 0 enters register 2, and so on.
[0054] In a specific application embodiment, the detailed process of implementing high-speed data caching using the above-mentioned device of the present invention is as follows:
[0055] Handshake request: The state of the pipeline is controlled by a counter. The counter is used to calculate the lifecycle of a request from entering the pipeline to the completion of RAM access. When the count is complete, it indicates that the pipeline can accept new requests, that is, it is in the Ready state. The value of the counter when it is complete is automatically calculated by Python based on the configuration parameters.
[0056] Request caching: Caching is implemented using registers, with a counter controlling caching behavior. Each data array group has its own cache, and the data ID value in the request corresponds sequentially to a data array group. After a successful handshake, the request is cached in cache 0, with the data ID at 0; in the next request, it is cached in cache 1, with the data ID at 1, and so on, until it is cached in cache N of the last data array. The requests in the cache only change when the next request enters the pipeline. The number of caches is automatically calculated by Python based on configuration parameters.
[0057] Request selection: Each data array group corresponds to a selection signal. Selection signal 0 selects the request information on the interface when the request first arrives; otherwise, it selects the request information in buffer 0. Selection signal 1 selects the request information in buffer 0 when the data ID is 1; otherwise, it selects the request information in buffer 1. Selection signal 2 selects the request information in buffer 1 when the data ID is 2; otherwise, it selects the request information in buffer 2. And so on.
[0058] RAM Access: Request information from select signal 0 is used to access data array group 0, and request information from select signal 1 is used to access data array group 1. Data array groups are accessed sequentially. When accessing data array group 0, a request enters register 0, at which point the data ID is 0. In the next clock cycle, a request for data ID 0 enters register 1, and a request for data ID 1 enters register 0. In the next clock cycle, a request for data ID 2 enters register 0, a request for data ID 1 enters register 1, a request for data ID 0 enters register 2, and so on. The number of data array groups and the number of RAM blocks in each data group are determined by the pipeline width and cache size in Python. Once determined, the corresponding Verilog code can be generated without limit.
[0059] The RAM multi-cycle delay implementation logic is as follows: When accessing a data array group, requests for accessing each data array group are pipelined into registers and passed to the next station. A selector is used to select the request in the register corresponding to the RAM multi-cycle delay count. For example, if configured for 2 clock cycles, the request in register 1 will be selected. The number of registers is determined by the parameter in Python regarding the RAM multi-cycle delay count; different parameter values will result in different numbers of registers generated in Verilog.
[0060] In a specific application embodiment, taking a configuration with a pipeline width of 256 bits and a cache data width of 1024 bits as an example, the pipeline structure constructed using this invention is as follows: Figure 2As shown, each data group has two RAM blocks, so the width of each pipelined read / write operation is 256 bits. There are four data groups in total, so the cached data width is 1024 bits. When a read / write request for the first data group is received from an external source, the request is cached in the corresponding buffer buffer0. Simultaneously, the selector mux bypasses the request to the next station one step ahead, and modifies the information in the request to spontaneously generate pipelined read / write requests for the remaining three data groups, caching them in their respective buffers. The selector mux also bypasses these requests to the next station one step ahead. There are four access cycles for each data group, namely stations h5, h50, h51, and h52 in the diagram. These four stations can be configured by adjusting Python parameters to generate only one or a few of them. After accessing a data group, the data read from each data group is pipelined out using the mux.
[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.
Claims
1. A pipelined high-speed cache data caching method with variable latency and bit width, characterized in that the steps include... include: S01. When a cache request is received, the request is pipelined into the cache corresponding to multiple data array groups. By changing the information in the request, pipelined read and write micro-requests for each data array group are spontaneously generated. S02. Configure the pipeline width and cache data block width according to the currently required data bit width, and determine the number of data array groups and the number of RAMs used for caching data in each data array group according to the configured pipeline width and cache data block width, so as to realize variable bit width data caching; S03. Access each data array group in a pipelined manner according to the request. When accessing each data array group, the request for each data array group is pipelined into the register and passed to the next station. Obtain the number of registers accessed by RAM multi-cycle in the current configuration, and select the request from the register that matches the current RAM multi-cycle delay number to realize variable delay data caching.
2. The pipelined high-speed cache data caching method with variable latency and bit width according to claim 1, characterized in that, Step S01 includes: when the pipeline is in a state where it can receive new requests, receiving cache requests through a handshake; after a successful handshake, requesting to cache each cache in turn, the value of the data ID in the request corresponds to a data array group in turn, after caching the request, performing micro-operations on the request, increasing the ID number corresponding to the data array group in the request through control signals, so that the internal pipeline generates micro-requests for each data array group until they are cached in the cache of the last data array.
3. The pipelined high-speed cache data caching method with variable latency and bit width according to claim 1, characterized in that, In step S02, the number of RAMs in a data array group is determined based on the pipeline data width, and the number of data array groups is determined based on the cache data block width. The expression for determining the cache data block width is: cache data block width = number of data array groups × 128 × number of RAMs in a data array group.
4. The pipelined high-speed cache data caching method with variable latency and bit width according to claim 1, characterized in that, In step S02, the maximum value of the micro-operation ID number is determined based on the amount of RAM, so as to access different data array groups.
5. The variable latency and bit width pipelined cache data caching method according to any one of claims 1 to 4, characterized in that, The process after step S01 and before step S02 includes each data array group receiving a selection signal to ensure seamless access to the data array group after a request enters the pipeline.
6. The variable latency and bit width pipelined cache data caching method according to any one of claims 1 to 4, characterized in that, Steps S02 and S03 are implemented using Python, wherein the pipeline width and cache data block width are configured by adjusting parameters in Python, and the number of registers accessed by RAM in multiple cycles is configured by adjusting parameters in Python.
7. A pipelined high-speed cache data caching device with variable latency and bit width, comprising multiple data array groups, each data array group including multiple RAMs for caching data, characterized in that, Also includes: The request receiving module is used to receive cache requests. When a cache request is received, it will be pipelined into the cache corresponding to multiple data array groups and generate micro-requests for pipelined access to each data array group. The bit width control module is used to configure the pipeline width and cache data block width according to the currently required data bit width, and to determine the number of data array groups and the number of RAMs used for caching data in each data array group according to the configured pipeline width and cache data block width, so as to realize variable bit width data caching. The RAM latency control module is used to access each data array group in a pipelined manner according to the request. When accessing each data array group, the request for each data array group is pipelined into the register and passed to the next station. The number of registers accessed in the current RAM multi-cycle is obtained, and the request in the register that is consistent with the current RAM multi-cycle latency is selected to realize variable latency data caching.
8. The variable latency and bit width pipelined cache data caching device according to claim 7, characterized in that, It also includes counters for controlling pipeline status and requesting micro-operations, which calculate the lifecycle of a request from entering the pipeline to the completion of RAM access, and determine when the count is complete that the pipeline can receive new requests.
9. The variable latency and bit width pipelined cache data caching device according to claim 7 or 8, characterized in that, Each of the data array groups receives a selection signal. The first selection signal selects the request information on the interface when the request just arrives; otherwise, it selects the request information in the corresponding first buffer. The other selection signals select the request information in the buffer corresponding to the current selection signal when the data ID is the corresponding ID value; otherwise, they select the request information in the next buffer.
10. The variable latency and bit width pipelined cache data caching device according to claim 9, characterized in that, The request information of each selection signal is used to access the corresponding data array group. During the process of accessing the data array group in sequence, when accessing the first data array group, the request enters the first register corresponding to the first data array group, and the current data ID is the first ID value; the request for the next data ID with the first ID value enters the second register, and the request for the data ID with the second ID value enters the first register. In the next iteration, a request with the third ID value enters the first register, a request with the second ID value enters the second register, a request with the first ID value enters the third register, and so on.