Dormancy control method and dormancy control circuit

Abstract

This disclosure relates to the field of semiconductor circuit design, and particularly to a sleep control method and sleep control circuit, comprising: a data transmission circuit including at least two data transmission structures; each data transmission structure including a storage transmission end, a bus transmission end, and an interactive transmission end, wherein the storage transmission end is used to connect to a storage area, the bus transmission end is used to connect to a data bus, and the interactive transmission end is used to connect to another data transmission structure; during the sleep phase, sleep data is transmitted to the data bus; the bus transmission end and the storage transmission end are turned on, the transmitting end of the interactive transmission end is turned on, and the receiving end of the interactive transmission end is turned off, so that data input from the bus transmission end is output through the storage transmission end and the interactive transmission end; thereby achieving sleep control of the data transmission structure while avoiding timing disorder of the input data of the data transmission structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a sleep control method and a sleep control circuit. Background Technology

[0002] Dynamic Random Access Memory (DRAM) has the characteristics of non-volatile data, low power consumption, small size, and no mechanical structure, making it suitable as a storage device for mobile devices.

[0003] With the advancement of technology, consumers have increasingly higher performance requirements for mobile devices, making the data transfer rate of storage devices a key parameter for judging the quality of storage devices. How to improve the data transfer efficiency of storage devices is a problem that technical personnel urgently need to solve. Summary of the Invention

[0004] This disclosure provides a sleep control method and a sleep control circuit, and provides a sleep control method for a data transmission circuit for improving the read and write data transmission efficiency of a memory.

[0005] This disclosure provides a sleep control method applied to a data transmission circuit, comprising: the data transmission circuit including at least two data transmission structures; each data transmission structure including a storage transmission end, a bus transmission end, and an interactive transmission end, wherein the storage transmission end is used to connect to a storage area, the bus transmission end is used to connect to a data bus, and the interactive transmission end is used to connect to another data transmission structure; during the sleep phase, sleep data is transmitted to the data bus; the bus transmission end and the storage transmission end are turned on, the transmitting end of the interactive transmission end is turned on, and the receiving end of the interactive transmission end is turned off, so that data input from the bus transmission end is output through the storage transmission end and the interactive transmission end.

[0006] By connecting the bus transmission end and the storage transmission end, the sleep data transmitted on the data bus is written to the storage area. By connecting the sending end of the interactive transmission end, the sleep data transmitted on the data bus can be transmitted to the interactive transmission end. Thus, the storage transmission end, the bus transmission end, and the interactive transmission end of the data transmission structure all transmit sleep data to achieve sleep mode. In addition, by disabling the receiving end of the interactive transmission end, that is, while the interactive transmission end is transmitting sleep data, the data transmission structure does not receive sleep data sent by another data transmission structure. This ensures that the writing of sleep data in the data transmission structure is only achieved through the bus transmission end, avoiding the timing disorder of the input data of the data transmission structure in sleep mode.

[0007] In addition, the sleep data transmitted to the data bus is high-level data.

[0008] In addition, the storage transmission end includes: a first transmission end and a second transmission end, the first transmission end and the second transmission end are connected to the same storage area, and the first transmission end is used to transmit low-order data, and the second transmission end is used to transmit high-order data; the bus transmission end includes: a fifth transmission end and a sixth transmission end, the fifth transmission end is used for data interaction transmission between its own data transmission structure and the data bus, and the sixth transmission end is used for unidirectional data transmission from its own data transmission structure to the data bus; the interactive transmission end includes: a seventh transmission end and an eighth transmission end, the seventh transmission end and the eighth transmission end are used for data interaction transmission between two data transmission structures; turning on the bus transmission end and the storage transmission end, turning on the transmitting end of the interactive transmission end, and turning off the receiving end of the interactive transmission end includes: turning on the receiving end of the fifth transmission end, turning on the transmitting end of the sixth transmission end; turning on the transmitting end of the first transmission end and the transmitting end of the second transmission end; turning on the transmitting end of the seventh transmission end and the transmitting end of the eighth transmission end, and turning off the receiving end of the seventh transmission end and the receiving end of the eighth transmission end.

[0009] In addition, the storage transmission end also includes: a third transmission end and a fourth transmission end, the third transmission end and the fourth transmission end are connected to the same storage area, the first transmission end and the third transmission end are connected to different storage areas, and the third transmission end is used to transmit low-order data and the fourth transmission end is used to transmit high-order data; the bus transmission end and the storage transmission end are connected, the transmitting end of the interactive transmission end is connected, and the receiving end of the interactive transmission end is simultaneously turned off, and the third transmission end and the fourth transmission end are connected.

[0010] In addition, during the working phase, the first and second transmission ends are used to interact with data buses connected to different data transmission structures; during the sleep phase, the first and second transmission ends are used to send sleep data input from the data buses connected to their respective data transmission structures; during the working phase, the first and third transmission ends alternately transmit data, the second and fourth transmission ends alternately transmit data, the first and second transmission ends transmit data simultaneously, and the third and fourth transmission ends transmit data simultaneously; during the sleep phase, the first, second, third, and fourth transmission ends transmit data simultaneously.

[0011] In addition, the data transmission structure includes: an input unit for receiving sleep data and a sleep input control signal, configured to input sleep data based on the sleep input control signal; an output unit for receiving sleep data and a sleep output control signal, configured to output sleep data based on the sleep output control signal; and a latch unit connected to the output unit for latching the sleep data output by the output unit.

[0012] Additionally, the input unit includes: multiple input controllers, each input controller corresponding to a bus transmission end or an interactive transmission end, and each input controller receiving sleep data; each input controller is used to receive a sleep input control signal from the corresponding bus transmission end or interactive transmission end; during the sleep phase, the input controller corresponding to the bus transmission end is turned on based on the sleep input control signal.

[0013] Additionally, the output unit includes: multiple output controllers, each output controller corresponding to a storage transmission end or an interactive transmission end, and each output controller receiving sleep data; each output controller is used to receive a sleep output control signal from the corresponding storage transmission end or interactive transmission end; during the sleep phase, based on the sleep output control signal, the output controller corresponding to the storage transmission end and the interactive transmission end is turned on.

[0014] In addition, the latch unit includes a first inverter and a second inverter connected end to end, and the input terminal of the first inverter and the output terminal of the second inverter are connected in parallel with the output terminal of the output unit.

[0015] In addition, the data transmission structure also includes: an input selection unit for receiving a sleep input control signal, configured to generate a gating pulse corresponding to the sleep input control signal, wherein the gating pulse corresponds to the effective port represented by the sleep input control signal, and there is a selection delay between the gating pulse and the sleep input control signal; and a trigger unit, whose clock terminal is connected to the input selection unit, whose input terminal is connected to the input unit, and whose output terminal is connected to the output unit, configured to output sleep data based on the gating pulse.

[0016] Additionally, the input selection unit includes: a trigger subunit for receiving a sleep input control signal and generating an indication signal if the sleep input control signal is received; a delay subunit connected to the trigger subunit for delaying the indication signal; and a conversion subunit connected to the delay subunit for converting the delayed indication signal into a strobe pulse.

[0017] In addition, the triggering unit is composed of D flip-flops.

[0018] Another embodiment of this disclosure provides a sleep control circuit applied to the above-described sleep control method, comprising: a data providing unit configured to send sleep data to a data bus during the sleep phase; a first data control unit configured to, during the sleep phase, connect a storage transmission end and a bus transmission end, control a data transmission circuit to receive sleep data transmitted by the data bus, and send sleep data to a storage area; and a second data control unit configured to, during the sleep phase, connect an interactive transmission end, control a data transmission structure to send sleep data to another data transmission structure, and refuse to receive sleep data sent by another data transmission structure.

[0019] In addition, the first data control unit includes: a first data receiving subunit for receiving a sleep input control signal and a sleep output control signal; and a first control unit connected to the first data receiving subunit for turning on the bus transmission end according to the sleep input control signal and turning on the storage transmission end according to the sleep output control signal.

[0020] Additionally, the second data control unit includes: a second data receiving subunit for receiving a sleep input control signal and a sleep output control signal; and a second control unit connected to the second data receiving subunit for turning on the transmitting end of the interactive transmission end according to the sleep output control signal and turning off the receiving end of the interactive transmission end according to the sleep input control signal. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of a refresh circuit provided in an embodiment of the present disclosure;

[0023] Figure 2 This is a schematic diagram of the structure of a preprocessing module provided in an embodiment of the present disclosure;

[0024] Figure 3 This is a schematic diagram of the structure of a counting unit provided in an embodiment of the present disclosure;

[0025] Figure 4 This is a schematic diagram of the structure of an address processing module provided in an embodiment of the present disclosure;

[0026] Figure 5 This is a schematic diagram of the structure of the storage judgment module and the processing output module provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic flowchart illustrating a sleep control method provided in an embodiment of this disclosure;

[0028] Figure 7 This is a schematic diagram of the circuit structure used in the sleep phase of a data transmission circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0029] With the advancement of technology, consumers have increasingly higher performance requirements for mobile devices, making the data transfer rate of storage devices a key parameter for judging the quality of storage devices. How to improve the data transfer efficiency of storage devices is a problem that technical personnel urgently need to solve.

[0030] In view of the above problems, this disclosure provides a data transmission circuit; in addition, one embodiment of this disclosure provides a sleep control method, which is a sleep control method for a data transmission circuit for improving the read and write data transmission efficiency of a memory.

[0031] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0032] Figure 1 This is a schematic diagram of the data transmission circuit provided in this embodiment. Figure 2 This is a schematic diagram of the specific structure of the control module provided in this embodiment. Figure 3 This is a schematic diagram illustrating a specific connection method of the data transmission structure provided in this embodiment. Figure 4 This is a schematic diagram illustrating the specific structure of the data transmission structure during data reading provided in this embodiment. Figure 5 This is a schematic diagram of the data transmission structure during data writing provided in this embodiment. Figure 6 This is a flowchart illustrating the hibernation control method provided in this embodiment. Figure 7 The diagram below shows the circuit structure of the data transmission circuit used in the sleep phase in this embodiment. The sleep control method provided in this embodiment will be further described in detail below with reference to the accompanying drawings:

[0033] refer to Figure 1 The data transmission circuit is applied to the memory, which includes a data bus 103 and multiple storage areas 102, and is used to improve the read and write data transmission efficiency of the memory. Specifically, it includes at least two data transmission structures 101.

[0034] Each data transmission structure includes a storage transmission end 111, a bus transmission end 112, and an interactive transmission end 113. The storage transmission end 111 is used to connect to the storage area 102, the bus transmission end 112 is used to connect to the data bus 103, and the interactive transmission end 113 is used to connect to another data transmission structure.

[0035] During the working phase, data input from the storage transmission terminal 111 is output through the bus transmission terminal 112 or through the interactive transmission terminal 113; data input from the bus transmission terminal 112 is output through the storage transmission terminal 111 or through the interactive transmission terminal 113; data input from the interactive transmission terminal 113 is output through the bus transmission terminal 112 or through the storage transmission terminal 111; and data input from the interactive transmission terminal 113 is the data input from the bus transmission terminal 112 or the storage transmission terminal 111 in another data transmission structure 101. The control module 104 is connected to the data transmission structure 101 and receives input control signals and adjustment control signals provided by its associated memory.

[0036] refer to Figure 6 During the hibernation phase, the hibernation control method includes step 10 (during the hibernation phase, controlling the data bus to transmit hibernation data) and step 20 (controlling the hibernation data to be written into the data transmission structure through the bus transmission end, and output through the storage transmission end and the interactive transmission end, and controlling the data transmission structure not to receive hibernation data input through the interactive transmission end).

[0037] Specifically, for step 10, during the sleep phase, sleep data is transmitted to the data bus 103 so that the data bus 103 transmits sleep data; for step 20, the bus transmission end 112 and the storage transmission end 111 are turned on, the sending end of the interactive transmission end 113 is turned on, and the receiving end of the interactive transmission end 113 is turned off so that the data input from the bus transmission end 112 is output through the storage transmission end 111 and the interactive transmission end 113.

[0038] By connecting the bus transmission terminal 112 and the storage transmission terminal 111, the sleep data transmitted on the data bus 103 is written to the storage transmission terminal 111. By connecting the sending end of the interactive transmission terminal 112, the sleep data transmitted on the data bus 103 can be transmitted to the interactive transmission terminal 112. Thus, the storage transmission terminal 111, the bus transmission terminal 112, and the interactive transmission terminal 113 of the data transmission structure 101 all transmit sleep data to achieve sleep mode. In addition, by closing the receiving end of the interactive transmission terminal 113, that is, while the interactive transmission terminal 113 is transmitting sleep data, the data transmission structure 101 does not receive sleep data sent by another data transmission structure 101. This ensures that the writing of sleep data in the data transmission structure 101 is only achieved through the bus transmission terminal 112, avoiding the timing disorder of the input data of the data transmission structure 101 in sleep mode.

[0039] In this embodiment, during the sleep phase, the sleep data transmitted to the data bus 103 is high-level data, that is, during the sleep phase, the storage transmission terminal 111, the bus transmission terminal 112, and the interaction transmission terminal 113 are set high; in other embodiments, during the sleep phase, the sleep data transmitted to the data bus 103 is low-level data, that is, during the sleep phase, the storage transmission terminal 111, the bus transmission terminal 112, and the interaction transmission terminal 113 are set low, so as to further reduce the power consumption during the sleep phase.

[0040] refer to Figure 1 and combined Figure 2 During the working phase, the control module 104 is configured to delay the output of the input control signal based on the adjustment control signal to generate an output control signal corresponding to the input control signal. The input control signal and the output control signal are used to indicate the data transmission path of the data transmission structure 101.

[0041] The adjustment control signal is generated based on the memory of the data transmission circuit and is used to control the delay between the corresponding input control signal and the output control signal.

[0042] The control module 104 controls the data transmission paths of the two data transmission structures 101, enabling different data transmission structures to transmit data simultaneously. For the same data transmission structure 101, data in different storage areas 102 can be transmitted alternately, making data transmission more compact and thus improving the data transmission efficiency of the memory.

[0043] It should be noted that in other embodiments, the number of data transmission structures can be any even number greater than 2, and the data transmission structures in pairs form the above-mentioned data transmission circuit, thereby further improving the efficiency of data transmission in the memory.

[0044] Specifically, the signal delay between the input control signal and the output control signal is controlled by the adjustment control signal, which helps to prevent the output terminal from opening too early or too late relative to the preset timing, and ensures that the data transmission structure accurately outputs the corresponding input data.

[0045] refer to Figure 1 and Figure 3In some embodiments, the storage transmission end 111 includes: a first transmission end A and a second transmission end B, the first transmission end A and the second transmission end B are connected to the same storage area, and the first transmission end A is used to transmit low-order data, and the second transmission end B is used to transmit high-order data; the bus transmission end 112 includes: a fifth transmission end E and a sixth transmission end F; the interactive transmission end 113 includes: a seventh transmission end G and an eighth transmission end H; wherein, the fifth transmission end E is used for data interactive transmission between its corresponding data transmission structure 101 and the data bus 103, the sixth transmission end F is used for unidirectional data transmission from its corresponding data transmission structure 101 to the data bus 103; the seventh transmission end G and the eighth transmission end H are used for data interactive transmission between two data transmission structures 101.

[0046] It should be noted that in this embodiment, both the seventh transmission terminal G and the eighth transmission terminal H can be used for data interaction and transmission between the two data transmission structures 101; in other embodiments, the data transmission from the left data transmission structure to the right data transmission structure is realized through the seventh transmission terminal, and the data transmission from the right data transmission structure to the left data transmission structure is realized through the eighth transmission terminal.

[0047] During the sleep phase, the bus transmission terminal 112 and the storage transmission terminal 111 are turned on, the transmitting end of the interactive transmission terminal 113 is turned on, and the receiving end of the interactive transmission terminal 113 is turned off, including: turning on the receiving end of the fifth transmission terminal E, turning on the transmitting end of the sixth transmission terminal F, turning on the transmitting end of the first transmission terminal A and the transmitting end of the second transmission terminal B, turning on the transmitting end of the seventh transmission terminal G and the transmitting end of the eighth transmission terminal H, and turning off the receiving end of the seventh transmission terminal G and the receiving end of the eighth transmission terminal H.

[0048] In other embodiments, if the data transmission from the left data transmission structure to the right data transmission structure is achieved through the seventh transmission end, and the data transmission from the right data transmission structure to the left data transmission structure is achieved through the eighth transmission end, then the switching on the sending end of the seventh transmission end and the sending end of the eighth transmission end, and the switching on the receiving end of the seventh transmission end and the receiving end of the eighth transmission end, need to be adjusted accordingly: for the left data transmission structure, the sending end of the seventh transmission end is turned on, and the receiving end of the eighth transmission end is turned off; for the right data transmission structure, the sending end of the eighth transmission end is turned on, and the receiving end of the seventh transmission end is turned off.

[0049] In some other embodiments, the storage transmission terminal 111 further includes a third transmission terminal C and a fourth transmission terminal D, the third transmission terminal C and the fourth transmission terminal D being connected to the same storage area, the first transmission terminal A and the third transmission terminal C being connected to different storage areas, and the third transmission terminal being used to transmit low-order data and the fourth transmission terminal being used to transmit high-order data.

[0050] At this time, during the sleep phase, the bus transmission terminal 112 and the storage transmission terminal 111 are turned on, the transmitting end of the interactive transmission terminal 113 is turned on, and the receiving end of the interactive transmission terminal 113 is turned off. It also includes turning on the transmitting end of the third transmission terminal C and the transmitting end of the fourth transmission terminal D.

[0051] It should be noted that the first transmission end A and the second transmission end B can be used to transmit the high-order and low-order data of the same data. For example, for the transmission of 16-bit data, the first transmission end A is used to transmit the low 8 bits of data, and the second transmission end B is used to transmit the high 8 bits of data. The first transmission end A and the second transmission end B can also be used to transmit different data. For example, for the transmission of 8-bit data, the first transmission end A and the second transmission end B are used to transmit different data.

[0052] It should be noted that during the working phase, the first transmission end A and the second transmission end B are used to interact with the data buses 103 connected to different data transmission structures 101; during the sleep phase, the first transmission end A and the second transmission end B are used to send sleep data input from the data buses 103 connected to their respective data transmission structures 101; during the working phase, the first transmission end A and the third transmission end C alternately transmit data, the second transmission end B and the fourth transmission end D alternately transmit data, the first transmission end A and the second transmission end B transmit data simultaneously, and the third transmission end C and the fourth transmission end D transmit data simultaneously; during the sleep phase, the first transmission end A, the second transmission end B, the third transmission end C and the fourth transmission end D transmit data simultaneously.

[0053] In some embodiments, reference Figure 2 And combined Figure 3 The input control signals include: Sel A, Sel B, Sel C, Sel D, Sel E, Sel F, Sel G and Sel H; the output control signals include: Drv A, Drv B, Drv C, Drv D, DrvE, Drv F, Drv G and Drv H.

[0054] Wherein, the input control signal corresponding to the first transmission terminal A is Sel A, and the output control signal is Drv A; the input control signal corresponding to the second transmission terminal B is Sel B, and the output control signal is Drv B; the input control signal corresponding to the third transmission terminal C is Sel C, and the output control signal is Drv C; the input control signal corresponding to the fourth transmission terminal D is Sel D, and the output control signal is Drv D; the input control signal corresponding to the fifth transmission terminal E is Sel E, and the output control signal is Drv E; the input control signal corresponding to the sixth transmission terminal F is Sel F, and the output control signal is Drv F; the input control signal corresponding to the seventh transmission terminal G is Sel G, and the output control signal is Drv G; and the input control signal corresponding to the eighth transmission terminal H is Sel H, and the output control signal is Drv H.

[0055] During the work phase, refer to Figure 4 and Figure 5 The data transmission structure 101 includes: an input unit 201, configured to receive at least one input data and an input control signal, and to output the input data corresponding to the input control signal based on the input control signal; an output unit 203, configured to receive the input data output by the input unit 201 and at least one output control signal, and to output the input data based on the valid port represented by the output control signal; and a latch unit 204, connected to the output unit 203, for latching the input data output by the output unit 203.

[0056] During the dormancy phase, refer to Figure 7 The data transmission structure 101 includes: an input unit 201 for receiving sleep data XM and a sleep input control signal KR, configured to input sleep data XM based on the sleep input control signal KR; an output unit 203 for receiving sleep data XM and a sleep output control signal KC, configured to output sleep data XM based on the sleep output control signal KC; and a latch unit 204 connected to the output unit 203 for latching the sleep data XM output by the output unit 203.

[0057] During the operation phase, the input unit 201 includes: a plurality of input controllers 211, each input controller 211 corresponding to the storage transmission terminal 111, the bus transmission terminal 112, or the interactive transmission terminal 113; each input controller 211 is used to receive input data and input control signals from the corresponding storage transmission terminal 111, the bus transmission terminal 112, or the interactive transmission terminal 113, and the input controller 211 is configured to turn on the corresponding port based on the input control signal to output the input data of the corresponding port.

[0058] Specifically, regarding data reading, refer to Figure 4Data can be read from the storage area connected to the data transmission structure 101 through the first transmission terminal A, the second transmission terminal B, the third transmission terminal C, or the fourth transmission terminal D. Alternatively, data from the storage area connected to another data transmission structure 101 can be read through the seventh transmission terminal G and the eighth transmission terminal H.

[0059] The first transmission terminal A's input data Data A is connected to an input controller 211, which is controlled by an input control signal Sel A. When the input control signal Sel A is received, the input data Data A of the first transmission terminal A is output. The second transmission terminal B's input data Data B is connected to an input controller 211, which is controlled by an input control signal Sel B. When the input control signal Sel B is received, the input data Data B of the second transmission terminal B is output. The third transmission terminal C's input data Data C is connected to an input controller 211, which is controlled by an input control signal Sel C. When the input control signal Sel C is received, the input data Data C of the third transmission terminal C is output. The fourth transmission terminal D's input data Data D is connected to an input controller 211, which is controlled by an input control signal Sel D. When the input control signal Sel D is received, the input data Data D of the fourth transmission terminal D is output. The seventh transmission terminal G's input data Data G is connected to an input controller 211, which is controlled by an input control signal Sel G. When the input control signal Sel G is received, the input data Data G of the seventh transmission terminal G is output. G; The input data Data H of the eighth transmission terminal H is connected to an input controller 211, which is controlled by the input control signal Sel H. When the input control signal Sel H is received, the input data Data H of the eighth transmission terminal H is output.

[0060] Specifically, regarding data writing, refer to Figure 5 Data can be written to the data transmission structure 101 through the fifth transmission terminal E, or it can be written to the data received by another data transmission structure 101 through the seventh transmission terminal G and the eighth transmission terminal H.

[0061] Specifically, the input data Data E of the fifth transmission terminal E is connected to an input controller 211, which is controlled by the input control signal Sel E. When the input control signal Sel E is received, the input data Data E of the fifth transmission terminal E is output. The input data Data G of the seventh transmission terminal G is connected to an input controller 211, which is controlled by the input control signal Sel G. When the input control signal Sel G is received, the input data Data G of the seventh transmission terminal G is output. The input data Data H of the eighth transmission terminal H is connected to an input controller 211, which is controlled by the input control signal Sel H. When the input control signal Sel H is received, the input data Data H of the eighth transmission terminal H is output.

[0062] In some embodiments, a masking unit 202 is further included, which is used to generate masking data DM based on the input data Data E of the fifth transmission terminal E. The masking data DM is input through the input controller 211 corresponding to the fifth transmission terminal E to realize the selective input of data on the data bus 103.

[0063] Specifically, the memory includes a data masking function and a data inversion function. When the data mask is valid, the corresponding 8 bits of data are not written. When 1s predominate in the 8 bits of data to be written, if it is more energy-efficient to transmit 0s through the transmission path, then the 8 bits of data to be written are inverted. When both data mask (DM) and data bus inversion (DBI) functions are enabled simultaneously, only one input can be selected because both the data mask signal and the data bus inversion signal need to utilize the same data port. This disclosure selects the data bus inversion signal as the input. That is, when writing data, the input data and the data bus inversion signal are transmitted to the data transmission structure together. When the data bus inversion signal is valid, the input data Data E representing synchronous input needs to be inverted. Since there is no need to invert if the input data Data E is not written, the validity of the data bus inversion signal also indicates that the input data Data E needs to be written. When the data bus inversion signal is invalid, if the input data is normal, then 0 should be the majority in the input data. That is, when the data bus inversion signal is invalid, it is necessary to check whether 0 accounts for half or more of the input data. If it accounts for half or more, then it is input normally without data inversion. If 0 accounts for a minority and 1 accounts for a majority, then it means that the input data represents the validity of the data mask signal, and the corresponding 8 bits of input data are masked and not stored in the storage array.

[0064] In other words, when the data inversion signal is valid, the fifth transmission terminal E receives the 8-bit original data to be written, and the inverting unit 207 receives the inverting control signal DBI. At this time, the inverting control signal DBI indicates that the data inversion signal is valid. For example, the inverting control signal DBI is 1, and the data input by the input unit 201 is inverted and output to the output unit 203. When the data inversion signal is invalid, the fifth transmission terminal E receives either the 8-bit original data to be written or the mask data DM according to the content of Data E. Specifically, when the data inversion signal is invalid, the input and output Data E are compiled by the masking unit 202 to determine whether the data mask signal is valid (assuming that valid is 1 and invalid is 0). If the data mask DM indicates that it is valid, it means that the 8-bit original data does not need to be written. At this time, the fifth transmission terminal E receives the mask data DM. If the data mask DM indicates that it is invalid, it means that the 8-bit original data needs to be written. At this time, the fifth transmission terminal E receives the input data Data E.

[0065] It should be noted that any data transmission structure only inverts the data input to the corresponding fifth transmission terminal E. That is, when writing data, the inversion control subunit 221 receives the inversion control signal DBI, which will only be the inversion control signal corresponding to the input data Data E, and not the inversion control signals corresponding to the input data Data G and Data H. This is because for the data input to the seventh input terminal Sel G and the eighth input terminal Sel H, that is, the data input by the data bus 103 through another data transmission structure, the input data has already completed the above-mentioned data inversion process in the inversion unit 207 of the other data transmission structure.

[0066] During the dormancy phase, refer to Figure 7 The input unit 201 includes: a plurality of input controllers 211, each input controller corresponding to a bus transmission terminal 112 or an interactive transmission terminal 113, and each input controller 211 receiving sleep data XM; each input controller 211 is used to receive a sleep input control signal KR from the corresponding bus transmission terminal 112 or interactive transmission terminal 113; during the sleep phase, the input controller 211 corresponding to the bus transmission terminal is turned on based on the sleep input control signal KR.

[0067] Specifically, the sleep input control signal KR is transmitted to the fifth transmission terminal E, the seventh transmission terminal G, and the eighth transmission terminal H to turn on the fifth transmission terminal E and turn off the seventh transmission terminal G and the eighth transmission terminal H. This allows the sleep data XM to be written from the data bus 103 to the data transmission structure 101 through the fifth transmission terminal E. Since the seventh transmission terminal G and the eighth transmission terminal H are turned off, that is, the receiving end of the interactive transmission terminal 113 is turned off, the sleep data XM cannot be written to the other data transmission structure 101 through the seventh transmission terminal G or the eighth transmission terminal H, thus avoiding data timing disorder.

[0068] During the working phase, the output unit 203 includes: a plurality of output controllers 212, each output controller 212 corresponding to the storage transmission terminal 111, the bus transmission terminal 112, or the interactive transmission terminal 113; each output controller 212 is used to receive input data and output control signals from the corresponding storage transmission terminal 111, the bus transmission terminal 112, or the interactive transmission terminal 113, and the output controller 212 is configured to output input data based on the output control signal being turned on.

[0069] Specifically, regarding data reading, refer to Figure 4 Data can be read out through the fifth transmission terminal E or the sixth transmission terminal F to the data bus 103, or through the seventh transmission terminal G and the eighth transmission terminal H to another data transmission structure 101, and finally through the fifth transmission terminal E or the sixth transmission terminal F corresponding to the other data transmission structure 101 to the corresponding other data bus 103.

[0070] Specifically, the output controller 212 connected to the fifth transmission terminal E is controlled by the output control signal Drv E. When the output control signal Drv E is received, the data is output through the fifth transmission terminal E. The output controller 212 connected to the seventh transmission terminal G is controlled by the output control signal Drv G. When the output control signal Drv G is received, the data is output through the seventh transmission terminal G. The output controller 212 connected to the eighth transmission terminal H is controlled by the output control signal Drv H. When the output control signal Drv H is received, the data is output through the eighth transmission terminal H.

[0071] Specifically, regarding data writing, refer to Figure 5 Data can be written to the storage area connected to the data transmission structure 101 through the first transmission end A, the second transmission end B, the third transmission end C, or the fourth transmission end D. Alternatively, it can be written to the storage area connected to another data transmission structure 101 through the seventh transmission end G and the eighth transmission end H.

[0072] Specifically, the output controller 212 connected to the first transmission terminal A is controlled by the output control signal Drv A. When it receives the output control signal Drv A, it outputs data through the first transmission terminal A. The output controller 212 connected to the second transmission terminal B is controlled by the output control signal Drv B. When it receives the output control signal Drv B, it outputs data through the second transmission terminal B. The output controller 212 connected to the third transmission terminal C is controlled by the output control signal Drv C. When it receives the output control signal Drv C, it outputs data through the third transmission terminal C. The output controller 212 connected to the fourth transmission terminal D is controlled by the output control signal Drv D. When it receives the output control signal Drv D, it outputs data through the fourth transmission terminal D. The output controller 212 connected to the seventh transmission terminal G is controlled by the output control signal Drv G. When it receives the output control signal Drv G, it outputs data through the seventh transmission terminal G. The output controller 212 connected to the eighth transmission terminal H is controlled by the output control signal Drv H. When it receives the output control signal Drv H, it outputs data through the eighth transmission terminal H.

[0073] During the sleep phase, the output unit 203 includes: a plurality of output controllers 212, each output controller 212 corresponding to the storage transmission terminal 111 or the interactive transmission terminal 113, and each output controller 212 receiving sleep data XM; each data controller is used to receive the sleep output control signal KC corresponding to the storage transmission terminal 111 or the interactive transmission terminal 113; during the sleep phase, based on the sleep output control signal KC, the output controllers 212 corresponding to the storage transmission terminal 111 and the interactive transmission terminal 113 are turned on.

[0074] Specifically, refer to Figure 7 The sleep output control signal KC is transmitted to the first transmission terminal A, the second transmission terminal B, the third transmission terminal C, the fourth transmission terminal D, the seventh transmission terminal G, and the eighth transmission terminal H to turn on the first transmission terminal A, the second transmission terminal B, the third transmission terminal C, the fourth transmission terminal D, the seventh transmission terminal G, and the eighth transmission terminal H. This allows the sleep data XM to be output through the first transmission terminal A, the second transmission terminal B, the third transmission terminal C, the fourth transmission terminal D, the seventh transmission terminal G, and the eighth transmission terminal H. Since the seventh transmission terminal G and the eighth transmission terminal H are turned on, the transmitting end of the interactive transmission terminal 113 is activated. The sleep data XM is transmitted to another data transmission terminal through the seventh transmission terminal G and the eighth transmission terminal H, thereby realizing the transmission of sleep data XM by the interactive transmission terminal 113.

[0075] In this embodiment, the latch unit 204 includes a first inverter 214 and a second inverter 213 connected end-to-end. The input terminal of the first inverter 214 and the output terminal of the second inverter 213 are connected in parallel with the output terminal of the output unit 203. By connecting the latch unit 204 in parallel with the output terminal of the output unit 203, the output data of the output unit 203 can be saved. It should be noted that in other embodiments, the latch unit includes a first inverter and a second inverter connected end-to-end. The input terminal of the first inverter and the output terminal of the second inverter are connected in series with the output port of the input unit. By connecting the latch unit in series with the output terminal of the output unit, the output data of the output unit can be latched in reverse. Subsequently, by connecting the inverters in series, the output data of the output unit can be saved.

[0076] In some embodiments, the accuracy of data during multiplexing is further ensured by delaying the input of data.

[0077] Specifically, during the working phase, the data transmission structure, reference Figure 4 and Figure 5 It also includes: an input selection unit 205 and a trigger unit 206.

[0078] The input selection unit 205 is configured to receive at least one input control signal and generate a gating pulse corresponding to the input control signal. The gating pulse corresponds to the effective port represented by the input control signal, and there is a selection delay between the gating pulse and the input control signal. The trigger unit 206 is connected to the input selection unit 205 at its clock end, connected to the input unit 201 at its input end, and connected to the output unit 203 at its output end. It is configured to transmit the input data received at the input end to the output end based on the gating pulse.

[0079] During the sleep phase, the data transmission structure is referenced. Figure 7 It also includes: an input selection unit 205 and a trigger unit 206.

[0080] The input selection unit 205 is used to receive the sleep input control signal KR, specifically, to receive the sleep input control signal KR_E corresponding to the fifth transmission terminal, the sleep input control signal KR_G corresponding to the seventh transmission terminal, and the sleep input control signal KR_H corresponding to the eighth transmission terminal. The input selection unit 205 is configured to generate a gating pulse corresponding to the sleep input control signal KR. The gating pulse corresponds to the effective port represented by the sleep input control signal KR, and there is a selection delay between the gating pulse and the sleep input control signal KR. The trigger unit 206, with its clock terminal connected to the input selection unit 205, its input terminal connected to the input unit 201, and its output terminal connected to the output unit 203, is configured to output sleep data XM based on the gating pulse.

[0081] During the working phase, the input selection unit 205 includes: a trigger subunit 215, used to receive at least one input control signal, and generate an indication signal if an input control signal is received; a delay subunit 216, connected to the trigger subunit 215, used to delay the indication signal; and a conversion subunit 217, connected to the delay subunit 216, used to convert the delayed indication signal into a strobe pulse.

[0082] The delay subunit 216 delays the indication signal to ensure that the data transmission structure accurately outputs the corresponding input data. The specific delay parameters of the delay subunit 216 are set based on the memory to which it belongs. In some embodiments, the specific delay parameters of the delay subunit 216 can be adjusted by the staff.

[0083] In this embodiment, the trigger subunit 215 is implemented through an OR gate. When data is read out, the reference... Figure 4 The input control signals Sel A, Sel B, Sel C, Sel D, Sel G, or Sel H are input to the trigger subunit 215. The trigger subunit 215 generates an indication signal based on the effective level of the input control signals Sel A, Sel B, Sel C, Sel D, Sel G, or Sel H. After being delayed by the delay subunit 216, the indication signal is converted into a strobe pulse by the conversion subunit 217 to drive the trigger unit 206. During data writing, the reference... Figure 5 The input control signal Sel E, Sel G or Sel H is input to the trigger subunit 215. The trigger subunit 215 generates an indication signal based on the effective level of the input control signal Sel E, Sel G or Sel H. After being delayed by the delay subunit 216, the indication signal is converted into a gating pulse by the conversion subunit 217 to drive the trigger unit 206.

[0084] During the sleep phase, the input selection unit 205 includes: a trigger subunit 215, used to receive at least one sleep input control signal KR, specifically, used to receive the sleep input control signal KR_E corresponding to the fifth transmission terminal, the sleep input control signal KR_G corresponding to the seventh transmission terminal, and the sleep input control signal KR_H corresponding to the eighth transmission terminal; if the trigger subunit 215 receives the sleep input control signal KR, it generates an indication signal; a delay subunit 216, connected to the trigger subunit 215, used to delay the indication signal; and a conversion subunit 217, connected to the delay subunit 216, used to convert the delayed indication signal into a strobe pulse.

[0085] The delay subunit 216 delays the indication signal to ensure that the data transmission structure accurately outputs the corresponding input data. The specific delay parameters of the delay subunit 216 are set based on the memory to which it belongs. In some embodiments, the specific delay parameters of the delay subunit 216 can be adjusted by the staff.

[0086] In some embodiments, the triggering unit is composed of a D flip-flop.

[0087] In some embodiments, the data transmission structure 101 further includes an inverting unit 207, disposed between the triggering unit 206 and the input unit 201, configured to output input data based on an inverting control signal, or to output the input data after inverting it.

[0088] By quantizing the data and outputting an inverting control signal, the data can be directly output or inverted via an inverting unit to reduce the data power consumption of the data transmission structure 101. Specifically, since low-level data consumes less power during data transmission, transmitting data via low-level signals can save energy. By quantizing the data, if there are more high-level data than low-level data, the data is inverted and transmitted via an inverting control signal; if there are fewer high-level data than low-level data, the data is transmitted directly via an inverting control signal.

[0089] refer to Figure 4 and Figure 5 The inverting unit 207 includes: a flip control subunit 221, used to receive an inverting control signal and generate a first control signal and a second control signal based on the inverting control signal; a first selection subunit 222 and a second selection subunit 223, connected in parallel, with their input terminals used to receive input data and their output terminals connected to the trigger unit 206; the first selection subunit 222 is configured to invert the input data and output it based on the first control signal being turned on; the second selection subunit 223 is configured to directly output the input data based on the second control signal being turned on.

[0090] It should be noted that the first control signal and the second control signal can be used as two signals to drive the first selection subunit 222 and the second selection subunit 223, or they can be used as the high and low levels of the same signal to drive the first selection subunit 222 and the second selection subunit 223.

[0091] refer to Figure 4 In some embodiments, the inverting unit 207 further includes a judgment subunit 224, which is used to receive input data and generate an inverting control signal based on the input data.

[0092] It should be noted that the signal driving method mentioned in this embodiment is described based on the presence or absence of a signal. In specific applications, driving can be based on the presence or absence of a signal, or it can be based on the high or low level of the signal. That is, if the signal is present, driving can be based on whether the signal level is an effective level.

[0093] By connecting the bus transmission end and the storage transmission end, the sleep data transmitted on the data bus is written to the storage area. By connecting the sending end of the interactive transmission end, the sleep data transmitted on the data bus can be transmitted to the interactive transmission end. Thus, the storage transmission end, the bus transmission end, and the interactive transmission end of the data transmission structure all transmit sleep data to achieve sleep mode. In addition, by disabling the receiving end of the interactive transmission end, that is, while the interactive transmission end is transmitting sleep data, the data transmission structure does not receive sleep data sent by another data transmission structure. This ensures that the writing of sleep data in the data transmission structure is only achieved through the bus transmission end, avoiding the timing disorder of the input data of the data transmission structure in sleep mode.

[0094] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0095] Another embodiment of this disclosure provides a sleep control circuit, applied to the above-described sleep control method embodiments, and provides a sleep control method for a data transmission circuit for improving the read and write data transmission efficiency of a memory.

[0096] The sleep control circuit provided in this embodiment will be described in detail below:

[0097] The sleep control circuit includes:

[0098] The data providing unit is configured to send sleep data to the data bus during the sleep phase.

[0099] The first data control unit is configured to, during the hibernation phase, turn on the storage transmission end and the bus transmission end, control the data transmission circuit to receive hibernation data transmitted by the data bus, and send hibernation data to the storage area.

[0100] The second data control unit is configured to, during the sleep phase, activate the interactive transmission end, control the data transmission structure to send sleep data to another data transmission structure, and refuse to receive sleep data sent by the other data transmission structure.

[0101] Specifically, the first data control unit includes:

[0102] The first data receiving subunit is used to receive sleep input control signals and sleep output control signals.

[0103] The first control unit is connected to the first data receiving subunit and is used to turn on the bus transmission end according to the sleep input control signal and turn on the storage transmission end according to the sleep output control signal.

[0104] Specifically, the second data control unit includes:

[0105] The second data receiving subunit is used to receive sleep input control signals and sleep output control signals.

[0106] The second control unit, connected to the second data receiving subunit, is used to turn on the transmitting end of the interactive transmission end according to the sleep output control signal, and to turn off the receiving end of the interactive transmission end according to the sleep input control signal.

[0107] By connecting the bus transmission end and the storage transmission end, the sleep data transmitted on the data bus is written to the storage area. By connecting the sending end of the interactive transmission end, the sleep data transmitted on the data bus can be transmitted to the interactive transmission end. Thus, the storage transmission end, the bus transmission end, and the interactive transmission end of the data transmission structure all transmit sleep data to achieve sleep mode. In addition, by disabling the receiving end of the interactive transmission end, that is, while the interactive transmission end is transmitting sleep data, the data transmission structure does not receive sleep data sent by another data transmission structure. This ensures that the writing of sleep data in the data transmission structure is only achieved through the bus transmission end, avoiding the timing disorder of the input data of the data transmission structure in sleep mode.

[0108] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A sleep control method applied to a data transmission circuit, characterized in that, include: The data transmission circuit includes at least two data transmission structures; Each of the data transmission structures includes a storage transmission end, a bus transmission end, and an interactive transmission end, wherein the storage transmission end is used to connect to a storage area, the bus transmission end is used to connect to a data bus, and the interactive transmission end is used to connect to another data transmission structure. During the sleep phase, sleep data is transmitted to the data bus; The bus transmission terminal and the storage transmission terminal are connected, the sending terminal of the interactive transmission terminal is connected, and the receiving terminal of the interactive transmission terminal is closed, so that the data input from the bus transmission terminal is output through the storage transmission terminal and the interactive transmission terminal.

2. The dormancy control method according to claim 1, wherein The sleep data transmitted to the data bus is high-level data.

3. The dormancy control method according to claim 1, wherein include: The storage transmission end includes: a first transmission end and a second transmission end, the first transmission end and the second transmission end are connected to the same storage area, and the first transmission end is used to transmit low-order data, and the second transmission end is used to transmit high-order data. The bus transmission end includes a fifth transmission end and a sixth transmission end. The fifth transmission end is used for data interaction transmission between the data transmission structure to which it belongs and the data bus. The sixth transmission end is used for unidirectional data transmission from the data transmission structure to the data bus. The interactive transmission end includes a seventh transmission end and an eighth transmission end, which are used for data interactive transmission between the two data transmission structures. The step of connecting the bus transmission end and the storage transmission end, connecting the sending end of the interactive transmission end, and disabling the receiving end of the interactive transmission end includes: Turn on the receiving end of the fifth transmission end and turn on the sending end of the sixth transmission end; Connect the transmitting end of the first transmission end and the transmitting end of the second transmission end; The transmitting end of the seventh transmission terminal and the transmitting end of the eighth transmission terminal are turned on, and the receiving end of the seventh transmission terminal and the receiving end of the eighth transmission terminal are turned off.

4. The dormancy control method according to claim 3, wherein include: The storage transmission end further includes: a third transmission end and a fourth transmission end, wherein the third transmission end and the fourth transmission end are connected to the same storage area, the first transmission end and the third transmission end are connected to different storage areas, and the third transmission end is used to transmit low-order data, and the fourth transmission end is used to transmit high-order data. The step of connecting the bus transmission end and the storage transmission end, connecting the sending end of the interactive transmission end, and simultaneously closing the receiving end of the interactive transmission end, further includes connecting the sending end of the third transmission end and the sending end of the fourth transmission end.

5. The dormancy control method according to claim 4, wherein include: During the working phase, the first transmission end and the second transmission end are respectively used to interact with the data buses connected to different data transmission structures; During the sleep phase, the first transmission terminal and the second transmission terminal are used to send the sleep data input from the data bus to which the data transmission structure is connected; During the working phase, the first transmission end and the third transmission end alternately transmit data, the second transmission end and the fourth transmission end alternately transmit data, the first transmission end and the second transmission end transmit data simultaneously, and the third transmission end and the fourth transmission end transmit data simultaneously. During the sleep phase, the first transmission terminal, the second transmission terminal, the third transmission terminal, and the fourth transmission terminal simultaneously transmit data.

6. The dormancy control method according to claim 1, wherein The data transmission structure includes: An input unit is configured to receive the sleep data and the sleep input control signal, and to input the sleep data based on the sleep input control signal. An output unit is configured to receive the sleep data and the sleep output control signal, and to output the sleep data based on the sleep output control signal. A latching unit, connected to the output unit, is used to latch the sleep data output by the output unit.

7. The dormancy control method according to claim 6, wherein The input unit includes: Multiple input controllers, each of which corresponds to the bus transmission terminal or the interactive transmission terminal, and each of which receives the sleep data; Each of the input controllers is used to receive the sleep input control signal corresponding to the bus transmission terminal or the interactive transmission terminal; During the sleep phase, the input controller corresponding to the bus transmission terminal is turned on based on the sleep input control signal.

8. The dormancy control method according to claim 6, wherein The output unit includes: Multiple output controllers, each output controller corresponding to the storage transmission end or the interaction transmission end, and each output controller receiving the sleep data; Each of the output controllers is used to receive the sleep output control signal corresponding to the storage transmission terminal or the interactive transmission terminal; During the hibernation phase, the output controller corresponding to the storage transmission terminal and the interactive transmission terminal is turned on based on the hibernation output control signal.

9. The dormancy control method according to claim 6, wherein The latching unit includes a first inverter and a second inverter connected end to end, and the input terminal of the first inverter and the output terminal of the second inverter are connected in parallel with the output terminal of the output unit.

10. The dormancy control method of claim 6, wherein The data transmission structure further includes: An input selection unit is configured to receive the sleep input control signal and generate a gating pulse corresponding to the sleep input control signal, wherein the gating pulse corresponds to the valid port represented by the sleep input control signal and there is a selection delay between the gating pulse and the sleep input control signal. The trigger unit, with its clock terminal connected to the input selection unit, its input terminal connected to the input unit, and its output terminal connected to the output unit, is configured to output the sleep data based on the strobe pulse.

11. The dormancy control method according to claim 10, wherein Input selection unit, including: The trigger subunit is used to receive the sleep input control signal and generate an indication signal if the sleep input control signal is received. A delay subunit, connected to the trigger subunit, is used to delay the indication signal; A conversion subunit, connected to the delay subunit, is used to convert the delayed indication signal into the strobe pulse.

12. The dormancy control method according to claim 10, wherein The triggering unit is composed of a D flip-flop.

13. A sleep control circuit applied to the sleep control method according to any one of claims 1 to 12, characterized by include: The data providing unit is configured to send sleep data to the data bus during the sleep phase; The first data control unit is configured to, during the hibernation phase, turn on the storage transmission terminal and the bus transmission terminal, control the data transmission circuit to receive the hibernation data transmitted by the data bus, and send the hibernation data to the storage area; The second data control unit is configured to, during the sleep phase, activate the interactive transmission terminal, control the data transmission structure to send the sleep data to another data transmission structure, and refuse to receive the sleep data sent by the other data transmission structure.

14. The sleep control circuit according to claim 13, characterized in that, The first data control unit includes: The first data receiving subunit is used to receive sleep input control signals and sleep output control signals; The first control unit, connected to the first data receiving subunit, is used to turn on the bus transmission terminal according to the sleep input control signal and to turn on the storage transmission terminal according to the sleep output control signal.

15. The dormancy control circuit of claim 13, wherein, The second data control unit includes: The second data receiving subunit is used to receive sleep input control signals and sleep output control signals; The second control unit, connected to the second data receiving subunit, is used to turn on the transmitting end of the interactive transmission end according to the sleep output control signal, and to turn off the receiving end of the interactive transmission end according to the sleep input control signal.

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