Storage device and storage device module
By setting heat dissipation components on the wiring board and forming heat dissipation paths with multiple wiring layers, the problem of memory element temperature rise caused by the heat generation of control components is solved, and the heat dissipation and performance of the storage device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MEIKO ELECTRONICS CO LTD
- Filing Date
- 2021-03-11
- Publication Date
- 2026-06-09
AI Technical Summary
As control components become more high-performance, they generate more heat, leading to increased memory component temperatures and affecting write and read speeds.
Heat dissipation components are set on the wiring board, and heat dissipation paths are formed through multiple wiring layers to conduct heat away from the control components and prevent heat from being transferred to the memory components.
It effectively reduces the temperature of the control components, prevents the memory components from overheating, maintains write and read speeds, and improves the heat dissipation of the storage device.
Smart Images
Figure CN116711068B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a storage device and a storage device module. Background Technology
[0002] An SSD (Solid State Drive) has a structure in which NAND flash memory elements and the control elements (controllers) that control these memory elements are actually mounted on a wiring board. In recent years, with the advancement of increased storage capacity and high-speed operation, the performance of control elements has improved, and heat generation has also increased accordingly. If the temperature of the memory elements also rises due to the heat from the control elements, there may be situations where it is necessary to reduce the operating speed (write speed and read speed) of the memory elements.
[0003] Patent documents
[0004] Patent Document 1: Japanese Patent No. 5767338
[0005] Patent Document 2: Japanese Patent No. 6584258 Summary of the Invention
[0006] The purpose of this invention is to provide a storage device and storage device module with improved heat dissipation of control components.
[0007] According to one embodiment of the present invention, a storage device includes: a wiring substrate having a first surface, a second surface opposite to the first surface, and a multilayer wiring layer; a control element embedded in the wiring substrate, having a first element surface with a plurality of electrode pads disposed on the multilayer wiring layer and a second element surface opposite to the first element surface; a first heat dissipation member disposed on the first surface of the wiring substrate in a region overlapping with the control element; a heat dissipation structure exposed from the second surface of the wiring substrate opposite to the second element surface of the control element; and at least one memory element disposed on the first surface of the wiring substrate in a region not overlapping with the control element, connected to the multilayer wiring layer. The multilayer wiring layer has: a signal pattern electrically connecting the control element and the memory element or an external connection terminal; and a heat dissipation conductor pattern forming a heat dissipation path between the control element and the first heat dissipation member. Attached Figure Description
[0008] Figure 1 This is a schematic cross-sectional view of the storage device according to the first embodiment.
[0009] Figure 2 This is a detailed schematic cross-sectional view of the portion of the storage device of the first embodiment that includes the control element and the first heat dissipation member.
[0010] Figure 3 This is a schematic plan view of the wiring layer of the wiring board in the storage device of the first embodiment.
[0011] Figure 4 This is a schematic plan view of the wiring layer of the wiring board in the storage device of the first embodiment.
[0012] Figure 5 This is a schematic plan view of the wiring layer of the wiring board in the storage device of the first embodiment.
[0013] Figure 6 This is a schematic plan view of the wiring layer of the wiring board in the storage device of the first embodiment.
[0014] Figure 7 This is a schematic plan view of the first element surface of the control element in the storage device of the first embodiment.
[0015] Figure 8 This is a schematic plan view of the second element surface of the control element in the storage device of the first embodiment.
[0016] Figure 9 This is a schematic plan view of the heat dissipation structure in the storage device of the first embodiment.
[0017] Figure 10 This is a schematic plan view of the heat dissipation structure in the storage device of the first embodiment.
[0018] Figure 11 This is a schematic plan view of the heat dissipation structure in the storage device of the first embodiment.
[0019] Figure 12 This is a schematic plan view of the first element surface of the control element in the storage device of the first embodiment.
[0020] Figure 13 This is a schematic plan view of the first element surface of the control element in the storage device of the first embodiment.
[0021] Figure 14 This is a schematic cross-sectional view of the storage device according to the second embodiment.
[0022] Figure 15 This is a schematic cross-sectional view of the storage device according to the third embodiment.
[0023] Figure 16 This is a schematic top view of the storage device module in the fourth embodiment.
[0024] Figure 17 This is a schematic cross-sectional view of the storage device according to the fifth embodiment.
[0025] Figure 18 This is a schematic top view of the storage device module in the sixth embodiment.
[0026] Symbol Explanation
[0027] 1-3, 5 - Storage device; 4, 6 - Storage device module; 10 - Wiring board; 11 - First surface; 12 - Second surface; 13 - Insulating layer; 20 - Control element; 21 - First element surface; 22 - Second element surface; 31 - First heat dissipation component; 32, 130 - Heat dissipation structure; 40 - Memory element; 50 - Multilayer wiring layer; 100 - Cooling component; 132 - Second heat dissipation component; 133 - Third heat dissipation component. Detailed Implementation
[0028] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Furthermore, in each drawing, the same symbols are used to label the same structures.
[0029] Implementation Method 1
[0030] Figure 1 This is a schematic cross-sectional view of the storage device 1 according to the first embodiment.
[0031] The storage device 1 includes a wiring board 10, a control element 20, at least one memory element 40, a first heat sink 31, and a heat dissipation structure 32. Although not shown, the wiring board 10 is equipped with a connector, a chip capacitor, etc. For example, the connector functions as an external connection terminal for electrical connection to an external circuit.
[0032] The wiring substrate 10 has a first surface 11, a second surface 12 opposite to the first surface 11, a multilayer wiring layer 50, and an insulating layer 13. The multilayer wiring layer 50 is a metal layer, for example, made of copper. An insulating layer 13 is disposed between the layers of the multilayer wiring layer 50. The insulating layer 13 is a resin layer, for example, made of epoxy resin.
[0033] The control element 20 is embedded within the wiring substrate 10. The control element 20 is, for example, a non-resin-molded silicon semiconductor device, having a first element surface 21 with hundreds of electrode pads and a second element surface 22 opposite to the first element surface 21. The first element surface 21 faces the first surface 11 of the wiring substrate 10, and the second element surface 22 faces the second surface 12 of the wiring substrate 10. The sides of the control element 20 are covered by the insulating layer 13 of the wiring substrate 10.
[0034] Figure 7 It is a patterned plan view of the first element surface 21 of the control element 20.
[0035] An integrated circuit for controlling the read / write operations of the memory element 40 is formed on the control element 20. Multiple electrode pads 54a, 54b, and 54c electrically connected to the integrated circuit are formed on the first element surface 21. The electrode pads 54a, 54b, and 54c are electrically connected to the multilayer wiring layer 50 of the wiring substrate 10.
[0036] The electrode pads of control element 20 include Figure 7 Multiple power pads 54a and marked "PW" Figure 7 Multiple grounding pads 54b marked "GND" are included. Power supply pads 54a are assigned a power potential, and grounding pads 54b are assigned a ground potential. The electrode pads also include multiple signal pads 54c. Various signal exchanges occur between the control element 20 and the memory element 40, and / or between the control element 20 and external connection terminals where input signals from the outside are input, via the signal pads 54c.
[0037] like Figure 1 As shown, a first heat dissipation member 31 is disposed in the area on the first surface 11 of the wiring board 10 that overlaps with the control element 20. For example, the first heat dissipation member 31 is a metal member having multiple heat sinks. The top surface 31a and the sides 31b and 31c of the first heat dissipation member 31 are exposed on the first surface 11 from the wiring board 10. The bottom surface of the first heat dissipation member 31 is opposite to the first element surface 21 of the control element 20 by means of multiple wiring layers 50. The height of the first heat dissipation member 31 is greater than the height of the memory element 40.
[0038] A heat dissipation structure 32 is disposed opposite to the second element surface 22 of the control element 20. The side of the heat dissipation structure 32 opposite to the side of the second element surface 22 is exposed from the second surface 12 of the wiring board 10.
[0039] A plurality of memory elements 40 are disposed in an area on the first surface 11 of the wiring board 10 that does not overlap with the control element 20. A first direction from the first heat sink 31 toward the memory elements 40 is orthogonal to a second direction from the control element 20 toward the first heat sink 31. Furthermore, a third direction from the control element 20 toward the memory elements 40 is inclined relative to the first and second directions.
[0040] The memory element 40 has a package structure in which multiple memory chips 41 are encapsulated and laminated on a substrate 42 with resin 44. The memory chips 41 are, for example, NAND flash memory. Metal wires 45 electrically connect the memory chips 41 to a wiring layer formed on the substrate 42. The resin 44 covers the multiple memory chips 41 and the metal wires 45. On the back side of the substrate 42, multiple terminals (e.g., solder balls) 43 are disposed, electrically connected to the wiring layer of the substrate 42. The terminals 43 are electrically connected to the multilayer wiring layer 50 of the wiring substrate 10. When the temperature exceeds approximately 80°C, the memory element 40 reduces its write / read speed. In order to maintain operating quality, it can operate at high temperatures while reducing performance.
[0041] Figure 2 It is a detailed schematic cross-sectional view of the part of the storage device 1 in which the control element 20 and the first heat dissipation member 31 are arranged.
[0042] Between the first element surface 21 of the control element 20 and the first heat dissipation member 31, a wiring layer (conductor patterns L1a-b, L2a-c, L3a-c) is provided, for example, three layers. Each wiring layer is connected between the layers by a plurality of vias. Furthermore, the number of wiring layers between the control element 20 and the first heat dissipation member 31 is not limited to this, but can also be two layers or four or more layers.
[0043] The multilayer wiring layer 50 has: signal patterns L2c and L3c that electrically connect the control element 20 and the memory element 40; and heat dissipation conductor patterns L1a, L1b, L2a, L2b, L3a, and L3b that thermally connect the control element 20 and the first heat dissipation member 31. The heat dissipation conductor patterns L1a, L1b, L2a, L2b, L3a, and L3b form a heat dissipation path between the control element 20 and the first heat dissipation member 31.
[0044] Figure 3 This is a schematic plan view of the uppermost wiring layer on the first surface 11 of the wiring substrate 10. The uppermost wiring layer includes a first power pattern L1a and a first ground pattern L1b. The first power pattern L1a serves as both a power pattern with a power potential and a heat dissipation conductor pattern thermally connected to the first heat dissipation member 31. The first ground pattern L1b serves as both a ground pattern with a ground potential and a heat dissipation conductor pattern thermally connected to the first heat dissipation member 31.
[0045] The width of the first power pattern L1a and the width of the first ground pattern L1b are greater than the width of the signal pattern. The first power pattern L1a and the first ground pattern L1b are formed in a plate shape.
[0046] like Figure 2As shown, a first heat dissipation member 31 is provided on the first power supply pattern L1a and the first grounding pattern L1b. A thermally conductive insulating member 14 is provided between the first power supply pattern L1a and the first heat dissipation member 31 and between the first grounding pattern L1b and the first heat dissipation member 31.
[0047] The outermost signal pattern is covered by an insulating protective film (solder resist) 15.
[0048] Figure 4 yes Figure 3 The diagram shows a schematic plan view of the wiring layer below the wiring layer. Figure 4 The layer shown includes a second power supply pattern L2a, a second grounding pattern L2b, and a second signal pattern L2c.
[0049] The second signal pattern L2c is formed in the form of multiple lines. The second signal pattern L2c is electrically connected to the signal pad 54c of the control element 20 and the memory element 40 and / or the external connection terminal where input signals from the outside are input.
[0050] The second power pattern L2a is formed in a plate shape with a width greater than that of the second signal pattern L2c, and extends to the area where the memory element 40 is disposed. The second power pattern L2a is electrically connected to the first power pattern L1a via a plurality of vias 51a. The second power pattern L2a serves as both a power pattern and a heat dissipation conductor pattern.
[0051] The second grounding pattern L2b is formed in the shape of multiple islands. Each second grounding pattern L2b is electrically connected to the first grounding pattern L1b via via 51b. The second grounding pattern L2b serves as both a grounding pattern and a heat dissipation conductor pattern.
[0052] Figure 5 and Figure 6 yes Figure 4 The diagram shows a schematic plan view of the wiring layer below the wiring layer. Figure 5 and Figure 6 The layer shown includes a third power supply pattern L3a, a third grounding pattern L3b, and a third signal pattern L3c.
[0053] The third signal pattern L3c is formed in the form of multiple lines. The third signal pattern L3c is electrically connected to the signal pad 54c of the control element 20 and the memory element 40 and / or the external connection terminal where input signals from the outside are input.
[0054] The third power pattern L3a is formed as a plate with a width greater than that of the third signal pattern L3c. The third power pattern L3a is electrically connected to the second power pattern L2a via multiple vias 52a. The third power pattern L3a serves as both a power pattern and a heat dissipation conductor pattern.
[0055] The third ground pattern L3b is formed as a plate with a width greater than that of the third signal pattern L3c. The third ground pattern L3b is electrically connected to the second ground pattern L2b via a via 52b. The third ground pattern L3b serves as both a ground pattern and a heat dissipation conductor pattern. A portion of the third ground pattern L3b is formed as a line and extends to the area where the memory element 40 is disposed.
[0056] Figure 7 The first element surface 21 of the control element 20 shown is located below the layer where the third power supply pattern L3a, the third ground pattern L3b, and the third signal pattern L3c are provided. The third power supply pattern L3a, the third ground pattern L3b, and the third signal pattern L3c are respectively... Figure 6 Vias 53a, 53b, and 53c, indicated by dashed lines, are connected to the electrode pads of the control element 20.
[0057] The third power pattern L3a is electrically connected to the power pad 54a of the control element 20 via via 53a. The third ground pattern L3b is electrically connected to the ground pad 54b of the control element 20 via via 53b. The third signal pattern L3c is electrically connected to the signal pad 54c of the control element 20 via via 53c. Signal patterns on different layers are electrically connected vias.
[0058] Heat emitted by the control element 20 is transferred to the first heat dissipation member 31 via power supply patterns L3a, L2a, L1a and grounding patterns L3b, L2b, L1b and vias 53a, 52a, 51a, 53b, 52b, 51b and thermally conductive insulating member 14, and then dissipated from the first heat dissipation member 31 to the outside of the storage device 1.
[0059] Furthermore, the control element 20 and the first heat sink 31 can be connected thermally via a power supply pattern alone. Alternatively, the control element 20 and the first heat sink 31 can be connected thermally via a ground pattern alone. In this case, the ground pattern can be connected to the first heat sink 31 without the aid of an insulating member.
[0060] On the other hand, such as Figure 2 As shown, a heat dissipation structure 32 is formed on the second element surface 22 of the control element 20. The heat dissipation structure 32 includes, for example, multiple metal layers 60, L4, L5, L6 and multiple thermally conductive vias 61, 62, 63 connecting these metal layers. The metal layers and thermally conductive vias are made of the same material (e.g., copper) as the multilayer wiring layer 50.
[0061] Figure 8 It is a patterned plan view of the second element surface 22 of the control element 20.
[0062] Instead of electrode pads, the second element surface 22 of the control element 20 is covered by, for example, silicon. A first metal layer 60 is disposed on the second element surface 22. The first metal layer 60 is not electrically connected to the integrated circuit of the control element 20. The first metal layer 60 covers the entire surface of the second element surface 22.
[0063] A plurality of first thermally conductive vias 61 are connected to the first metal layer 60. The number of the plurality of first thermally conductive vias 61 is greater than the number of electrode pads disposed on the first element surface 21 of the control element 20. The first thermally conductive vias 61 function as heat dissipation paths. The first thermally conductive vias 61 can be configured without considering electrical connection with the integrated circuit of the control element 20. Therefore, by having a greater number of first thermally conductive vias 61 than the number of electrode pads disposed on the first element surface 21, heat dissipation from the second element surface 22 side can be improved.
[0064] Figure 9 This is a schematic plan view of the second metal layer L4 beneath the first metal layer 60. Within the insulating layer 13 of the wiring substrate 10, the second metal layer L4 is laid out with a larger area compared to the second element surface 22 of the control element 20. The second metal layer L4 is connected to the first metal layer 60 via the aforementioned plurality of first thermally conductive vias 61.
[0065] Additionally, on the opposite side of the surface of the second metal layer L4 to which the first metal layer 60 is connected, a plurality of second thermally conductive vias 62 are connected.
[0066] Figure 10 This is a schematic plan view of the third metal layer L5 beneath the second metal layer L4. Within the insulating layer 13 of the wiring substrate 10, the third metal layer L5 is laid out with a larger area compared to the second element surface 22 of the control element 20. The third metal layer L5 is connected to the second metal layer L4 via the aforementioned plurality of second thermally conductive vias 62.
[0067] Since the areas of the second metal layer L4 and the third metal layer L5 are larger than the second element surface 22 of the control element 20, the number of second thermally conductive vias 62 connecting them can be greater than the number of first thermally conductive vias 61 connected to the second element surface 22 of the control element 20. This increases the heat dissipation pathways and improves heat dissipation.
[0068] Figure 11 This is a schematic plan view of the fourth metal layer L6 beneath the third metal layer L5. Within the insulating layer 13 of the wiring substrate 10, the fourth metal layer L6 is laid out with a larger area compared to the second element surface 22 of the control element 20. The fourth metal layer L6 is connected to the third metal layer L5 via a plurality of third thermally conductive vias 63.
[0069] Because the areas of the third metal layer L5 and the fourth metal layer L6 are larger than the second element surface 22 of the control element 20, the number of third thermally conductive vias 63 connecting them can be greater than the number of first thermally conductive vias 61 connected to the second element surface 22 of the control element 20. This increases the heat dissipation pathways and improves heat dissipation performance.
[0070] like Figure 2 As shown, an insulating protective film (solder resist film) 16 is formed on the second surface 12 side of the wiring substrate 10, and the surface of the fourth metal layer L6 is exposed from the protective film 16.
[0071] Heat generated by the control element 20 is dissipated to the outside of the storage device 1 via metal layers 60, L4, L5, L6 and thermal vias 61-63. Furthermore, the number of metal layers included in the heat dissipation structure 32 is not limited to [specific number missing]. Figure 2 The number of layers shown.
[0072] According to an embodiment of the present invention, by embedding the control element 20 within the wiring board 10, both sides (the first element surface 21 and the second element surface 22) of the control element 20 can be connected to the first heat dissipation member 31 and the heat dissipation structure 32 respectively, forming heat dissipation paths to both sides of the wiring board 10. Thus, heat generated by the control element 20 can be efficiently dissipated from both sides through the first heat dissipation member 31 and the heat dissipation structure 32. Furthermore, the memory element 40 is not located on the heat dissipation path from the control element 20 to the first heat dissipation member 31 and the heat dissipation structure 32. According to this embodiment, heat transfer from the control element 20 to the memory element 40 can be suppressed. Therefore, the temperature of the memory element 40 can be prevented from rising to a temperature (e.g., above 80°C) that could lead to a decrease in write or read speed.
[0073] according to Figure 12 and Figure 13 In the example shown, the circuit, electrode pad and signal pattern of the control element 20 are not connected to the first element surface 21 of the control element 20. Instead, metal patterns 71 and 72 are formed on the first heat dissipation member 31 by means of the heat dissipation conductor pattern of the wiring board 10.
[0074] exist Figure 12 In the example shown, a heat dissipation ring 71 is formed that surrounds a region on the first element surface 21 of the control element 20, where multiple electrode pads 54a, 54b, and 54c are arranged. The heat dissipation ring 71 is formed, for example, of copper.
[0075] exist Figure 13In the example shown, a heat sink 72 is formed in the area of the first element surface 21 of the control element 20, excluding the plurality of electrode pads 54a, 54b, and 54c. The heat sink 72 has a plurality of openings, in which the electrode pads 54a, 54b, and 54c are located. The heat sink 72 is, for example, made of copper.
[0076] By forming metal patterns 71 and 72 other than electrode pads 54a, 54b, and 54c on the first element surface 21 of the control element 20, and connecting the metal patterns 71 and 72 to the first heat dissipation member 31 via the heat dissipation conductor pattern of the wiring board 10, the heat dissipation performance of the first element surface 21 side of the control element 20 can be further improved.
[0077] Implementation Method 2
[0078] Figure 14 This is a schematic cross-sectional view of the storage device 2 in the second embodiment.
[0079] The storage device 2 of the second embodiment includes a second heat dissipation member 132 connected to the second element surface 22 as a heat dissipation structure for the control element 20. The second heat dissipation member 132 is bonded to the second element surface 22, for example, by solder paste 134. The second heat dissipation member 132 is, for example, a metal body formed of copper. The second heat dissipation member 132 is embedded in the insulating layer 13 of the wiring board 10, with one side contacting the second element surface 22 of the control element 20 and the other side exposed from the second surface 12 of the wiring board 10. The second heat dissipation member 132 may also be a coin-shaped copper component.
[0080] Third implementation method
[0081] Figure 15 This is a schematic cross-sectional view of the storage device 3 according to the third embodiment.
[0082] In the storage device 3 of the third embodiment, a plurality of memory chips 41 of memory elements 140 are directly stacked on the first surface 11 of the wiring substrate 10 without the aid of a substrate or the like. Furthermore, a resin member 150 covering the plurality of memory chips 41 and metal wires 45 is provided on the first surface 11 of the wiring substrate 10.
[0083] The resin component 150 covers the sides 31b and 31c of the first heat dissipation component 31. The surface 31a of the first heat dissipation component 31 (the side opposite to the surface opposite to the first surface 11 of the wiring substrate 10) is exposed from the resin component 150. Alternatively, the sides 31b and 31c of the first heat dissipation component 31 may also be exposed from the resin component 150.
[0084] Implementation Method 4
[0085] Figure 16This is a schematic top view of the storage device module 4 in the fourth embodiment.
[0086] The storage device module 4 includes a plurality of storage devices 1 and a cooling member 100 as described in the first embodiment. Furthermore, the plurality of storage devices included in the storage device module 4 may also be the structure of the second or third embodiment.
[0087] Multiple storage devices 1 in Figure 16 The components are arranged horizontally, for example, to form a high-capacity memory storage system for data centers that incorporates multiple SSDs. Between adjacent wiring boards 10, the first surface 11 of one wiring board 10 faces the second surface 12 of another wiring board 10.
[0088] Figure 16 In this configuration, a module substrate is provided with its paper facing inwards. Each wiring board 10 has a plug provided with its paper facing inwards, and the plug is inserted into a socket on the module substrate.
[0089] On the surface 32a of the heat dissipation structure 32 of one of the adjacent storage devices 1 exposed from the wiring board 10, the surface 31a of the first heat dissipation member 31 of another storage device 1 is connected, thereby arranging a plurality of storage devices 1.
[0090] The cooling member 100 extends along the direction in which the plurality of storage devices 1 are arranged and is connected to the side 31c of the first heat dissipation member 31 of each storage device 1 (the side opposite to the side inserted into the module substrate). The cooling member 100 includes, for example, a metal member such as a heat sink, an air cooling device such as a fan, a water cooling device, an air cooling device, or a combination thereof.
[0091] According to this embodiment, the heat dissipation members 31 and heat dissipation structures 32 on both sides of each storage device 1 are continuously connected and in contact with the heat dissipation members 31 and heat dissipation structures 32 of another storage device 1, thereby forming a larger metal body, and the cooling member 100 is connected in such a way that it covers the entire metal body, so that very high heat dissipation can be obtained in the module as a whole.
[0092] In the embodiments described above, the memory elements 40 and 140 are not actually mounted on the second surface 12 of the wiring board 10, but are actually mounted on the first surface 11, which is the same as the actual mounting surface of the first heat dissipation member 31, thereby reducing the overall thickness of the storage device and the storage device module.
[0093] In the area on the second surface 12 of the wiring board 10 that overlaps with the memory element 40, other components or more memory elements can also be actually mounted. Additionally, as... Figure 1 , Figure 14 , Figure 15As shown, on the second surface 12 side of the wiring substrate 10, a multilayer wiring layer 150 can also be formed in the region that overlaps with the memory element 40. The multilayer wiring layer 150 is electrically connected to the multilayer wiring layer 50 on the first surface 11 side, for example, via an interstitial via hole (IVH).
[0094] Fifth Implementation
[0095] Figure 17 This is a schematic cross-sectional view of the storage device 5 according to the fifth embodiment.
[0096] In the storage device 5 of the fifth embodiment, with Figure 14 Similarly, in the second embodiment shown, the heat dissipation structure 130 on the second element surface 22 side of the control element 20 includes a second heat dissipation member 132 connected to the second element surface 22. Furthermore, the heat dissipation structure 130 includes a third heat dissipation member 133 connected to the surface 132a of the second heat dissipation member 132 that is exposed from the second surface 12 of the wiring substrate 10. The third heat dissipation member 133 is exposed to the outside of the wiring substrate 10 on the second surface 12 side of the wiring substrate 10, and can be made thicker than the second heat dissipation member 132 embedded in the wiring substrate 10. The third heat dissipation member 133 is, for example, a metal member having multiple heat sinks.
[0097] Furthermore, the storage device 5 in the fifth embodiment has a two-sided mounting configuration. In the area on the second side 12 of the wiring board 10 that overlaps with the memory element 40, another memory element 240 is actually mounted. The memory element 240 includes, for example, a DRAM chip 241.
[0098] Additionally, in the area on the second surface 12 of the wiring board 10 that overlaps with the memory element 40, passive components 250 such as resistors or capacitors, or memory elements 40 identical to those actually mounted on the first surface 11, may be actually installed. The height of the third heat dissipation member 133 protruding from the second surface 12 of the wiring board 10 is higher than the height of the memory element 40, the height of the memory element 240, and the height of the passive component 250.
[0099] A multilayer wiring layer 150 electrically connected to the control element 20 is formed on the second surface 12 side of the wiring substrate 10. Furthermore, the multilayer wiring layer 150 is electrically connected to the multilayer wiring layer 50 on the first surface 11 side, for example, via IVH. The memory element 240, passive element 250, and memory element 40, which are actually mounted on the second surface 12, are electrically connected to the multilayer wiring layer 150.
[0100] Implementation Method 6
[0101] Figure 18 This is a schematic top view of the storage device module 6 in the sixth embodiment.
[0102] The storage device module 6 includes a plurality of storage devices 5 and a cooling component 100 as described in the fifth embodiment above.
[0103] Multiple storage devices 5 Figure 18 The components are arranged horizontally, for example, to form a high-capacity memory storage system for data centers that incorporates multiple SSDs. Between adjacent wiring boards 10, the first surface 11 of one wiring board 10 faces the second surface 12 of another wiring board 10.
[0104] Figure 18 In this configuration, a module substrate is provided with its paper facing inwards. Each wiring board 10 has a plug provided with its paper facing inwards, and the plug is inserted into a socket on the module substrate.
[0105] On the third heat dissipation member 133 of one of the adjacent storage devices 5, the first heat dissipation member 31 of another storage device 5 is connected, thereby arranging multiple storage devices 5.
[0106] The cooling component 100 extends along the direction in which the plurality of storage devices 5 are arranged, and is connected to the side 31c of the first heat dissipation component 31 and the side 133c of the third heat dissipation component 133 of each storage device 5. The cooling component 100 includes, for example, a metal component such as a heat sink, an air cooling device such as a fan, a water cooling device, an air cooling device, or a combination thereof.
[0107] According to this embodiment, the heat dissipation members 31, 133 on both sides of each storage device 5 are made to continuously contact the heat dissipation members 31, 133 of another storage device 5, thereby forming a larger metal body, and the cooling member 100 is connected in such a way that it covers the entire metal body, so that very high heat dissipation can be obtained in the module as a whole.
[0108] While several embodiments of the present invention have been described, these embodiments are provided by way of example and do not limit the scope of the invention. These new embodiments can be implemented in various other ways, with various omissions, substitutions, and modifications made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope and equivalents of the invention as described in the claims.
Claims
1. A storage device, characterized in that, It comprises: a wiring substrate having a first surface, a second surface opposite to the first surface, and a multilayer wiring layer; The control element, while being embedded in the wiring substrate, has a first element surface with a plurality of electrode pads connected to the multilayer wiring layer and a second element surface opposite to the first element surface. The first heat dissipation component is disposed on the first surface of the wiring substrate in the region that overlaps with the control element; A heat dissipation structure is exposed from the second surface of the wiring board, opposite to the second element surface of the control element; and at least one memory element, disposed on the first surface of the wiring substrate in a region that does not overlap with the control element, and connected to the multilayer wiring layer. The multilayer wiring layer has: a signal pattern that electrically connects the control element to the memory element or an external connection terminal; and a heat dissipation conductor pattern that forms a heat dissipation path between the control element and the first heat dissipation component.
2. The storage device according to claim 1, characterized in that, At least one memory element connected to the multilayer wiring layer is also disposed in a region on the second surface of the wiring substrate that does not overlap with the control element.
3. The storage device according to claim 2, characterized in that, The heat dissipation structure includes a third heat dissipation member protruding from the second surface of the wiring substrate.
4. The storage device according to claim 1 or 2, characterized in that, The electrode pads of the control element include a power pad and a ground pad. The heat dissipation conductor pattern includes at least one of a power pattern and a ground pattern, wherein the power pattern is connected to the power pad and has a width greater than the signal pattern, and the ground pattern is connected to the ground pad and has a width greater than the signal pattern.
5. The storage device according to claim 1 or 2, characterized in that, A metal pattern is provided on the first element surface of the control element, which is not connected to the electrode pad of the control element and the signal pattern of the wiring board, but is connected to the heat dissipation conductor pattern.
6. The storage device according to claim 1 or 2, characterized in that, The heat dissipation structure includes: a metal layer disposed on the second element surface of the control element; And multiple thermally conductive vias, connected to the metal layer, and in greater number than the electrode pads.
7. The storage device according to claim 1 or 2, characterized in that, The heat dissipation structure includes a second heat dissipation component embedded in the wiring substrate.
8. A storage device module, Its characteristics are, It includes the plurality of storage devices and cooling components as described in claim 1. On the surface of the wiring board exposed from the heat dissipation structure of one of the adjacent storage devices, the first heat dissipation member of another storage device is connected, and the plurality of storage devices are arranged. The cooling component extends along the direction in which the plurality of storage devices are arranged and is connected to the side of the first heat dissipation component.
9. A storage device module, characterized in that, It includes the plurality of storage devices and cooling components described in claim 3. The plurality of storage devices are arranged such that the first heat dissipation member of another storage device is connected to the third heat dissipation member exposed on the wiring board of the heat dissipation structure of one of the adjacent storage devices. The cooling component extends along the direction in which the plurality of storage devices are arranged and is connected to the side of the first heat dissipation component and the side of the third heat dissipation component.