Two-phase buffer operation supporting write commands

Abstract

This application relates to a two-stage buffered operation supporting write commands. If data is written to a memory device starting with a non-zero multiplane page offset, read performance for that data can be significantly degraded due to die misalignment. To avoid die misalignment, the memory system can support two buffers for writing data: a refresh buffer and a temporary buffer. The memory system can determine whether to add received data to the refresh buffer, the temporary buffer, or a combination thereof based on the data transfer size and a threshold size. If the data in the temporary buffer satisfies a copy condition, then the data in the temporary buffer is copied to the refresh buffer. If the data in the refresh buffer satisfies a refresh condition, then the data in the refresh buffer is written to the memory device starting with a zero multiplane page offset.

Description

[0001] Cross-reference

[0002] This patent application is the national phase application of International Patent Application No. PCT / CN2021 / 078387, filed by TAN et al. on March 1, 2021, entitled “TWO-STAGE BUFFER OPERATIONS SUPPORTING WRITE COMMANDS”, which has been assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves two-stage buffering operations that support write commands. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR and NAND memory devices, and others. Memory devices can be volatile or non-volatile. Volatile memory cells (such as DRAM cells) lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (such as NAND memory cells) can retain their programmed state for a long time, even without external power. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory device; and a controller coupled to the memory device and configured such that the apparatus: receives a command to write data to the memory device, the data having a data transfer size; determines, at least in part based on the data transfer size and the threshold size, whether to add the data to a first buffer, a second buffer, or a combination thereof; adds the data to the first buffer, the second buffer, or a combination thereof, at least in part based on the determination, the first buffer storing a first set of data and the second buffer storing a second set of data; and clears the first set of data to the memory device, at least in part based on the first set of data satisfying a clear condition of the first buffer, wherein after clearing the first set of data to the memory device at least in part based on the clear condition of the first buffer, the controller is configured such that the apparatus maintains the second set of data in the second buffer.

[0007] A non-transitory computer-readable medium storing code is described. The code may contain instructions, when executed by a processor of an electronic device, causing the electronic device to: receive a command to write data to a memory device, the data having a data transfer size; determine, at least in part based on the data transfer size and the threshold size, whether to add the data to a first buffer, a second buffer, or a combination thereof; add the data to the first buffer, the second buffer, or a combination thereof, at least in part based on the determination, the first buffer storing a first set of data and the second buffer storing a second set of data; and clear the first set of data to the memory device, at least in part based on the first set of data satisfying a clear condition of the first buffer, wherein after the first set of data is cleared to the memory device at least in part based on the clear condition of the first buffer, the instructions, when executed by the processor of the electronic device, cause the electronic device to maintain the second set of data in the second buffer.

[0008] A method performed by a memory system is described. The method may include: receiving a command to write data to a memory device of the memory system, the data having a data transfer size; determining, at least in part based on the data transfer size and the threshold size, whether to add the data to a first buffer, a second buffer, or a combination thereof; adding the data to the first buffer, the second buffer, or a combination thereof, at least in part based on the determination, wherein the first buffer stores a first set of data and the second buffer stores a second set of data; and clearing the first set of data to the memory device, at least in part based on the first set of data satisfying a clearing condition of the first buffer, wherein after the first set of data is cleared to the memory device at least in part based on the clearing condition of the first buffer, the second set of data is maintained in the second buffer. Attached Figure Description

[0009] Figure 1 and 2 This document describes an example of a system that supports two-stage buffering operations for write commands, based on the examples disclosed herein.

[0010] Figure 3 and 4 This document describes an instance of a data stream that supports two-stage buffering operations for write commands, based on the examples disclosed herein.

[0011] Figure 5 This document describes an example of a process flow that supports two-stage buffering operations for write commands, based on the examples disclosed herein.

[0012] Figure 6 A block diagram illustrating a memory system that supports two-stage buffering operations for write commands, based on the examples disclosed herein.

[0013] Figure 7 The flowchart illustrates one or more methods that support two-stage buffering operations for write commands, based on the examples disclosed herein. Detailed Implementation

[0014] Some memory devices (such as NAND flash memory devices, solid-state drives (SSDs), or other memory devices) can use multi-plane pages to store data. For example, a memory die may contain a number of planes (e.g., two or four planes), and the memory system can perform access operations, such as read and write operations, in parallel across one or more planes of a physical page. The same physical page spanning a set of multiple planes can be called a multi-plane page. A multi-plane page can support multiple offsets, and data can be written at these offsets based on or in response to the multi-plane page size or a minimum threshold size for reading or writing data, or both. For example, if the minimum threshold size for reading or writing data (or both) is 4 kilobytes (kB) and the multi-plane page size is 64 kB (e.g., for a 16 kB physical page spanning four planes), then the multi-plane page size can support 16 offsets for reading and writing data within the multi-plane page.

[0015] A memory system can efficiently read data written to a memory device starting at a zero multiplane page offset. If data is written to the memory die using the starting logical block address (LBA) at a zero multiplane page offset, this configuration can be called "die-aligned" or "die-in alignment." In this configuration, the memory system can perform a single read operation to read data starting at zero offset (e.g., reading data from a multiplane page) and can further improve read performance using cache read operations. However, if data is written to the memory die using the starting LBA at a non-zero multiplane page offset, this configuration can be called "die-unaligned" or "die-in alignment." In this configuration, the memory system can perform two read operations to read data from the corrected LBA of the multiplane page (e.g., one read operation to read the multiplane page and one read operation to read corrected data from the multiplane page starting at a non-zero offset) and may not support cache read operations. Therefore, compared to a die-aligned configuration, a die-unaligned configuration can result in inefficient read operations and other disadvantages due to increased read latency and processing overhead. Furthermore, due to the relatively large number of read operations performed when reading relatively large data files across multiple multi-plane pages, the negative effects of disk misalignment can be particularly pronounced for read operations performed on relatively large data files (e.g., data files spanning multiple multi-plane pages).

[0016] To support mitigation of die misalignment, a memory system may implement a two-stage buffering operation for write commands. The two-stage buffering operation may implement a first buffer (which may be called a clear buffer in some cases) and a second buffer (which may be called a temporary buffer in some cases). If the memory system receives a command to write data to the memory device, the memory system may determine whether to add data to the first buffer, the second buffer, or a combination thereof (e.g., adding a portion of the data to the first buffer and adding a portion of the data to the second buffer) based on or in response to the data transfer size or a threshold size, or both. For example, if the data transfer size is less than the threshold size, the memory system may add data smaller than the threshold size to the second buffer. If the data transfer size is greater than or equal to the threshold size, the memory system may add one or more portions of the threshold size of data to the first buffer and one or more other portions of the data (e.g., any remaining data (e.g., less than the threshold size)) to the second buffer. If the data stored in the second buffer satisfies a copy threshold (which may be equal to the threshold size in some instances), then the data may be copied to the first buffer. Therefore, data may be added to the first buffer in blocks equal to the threshold size (or multiples of the threshold size). If the data stored in the first buffer meets the clear threshold, the memory system can write the data from the first buffer to the memory device. By setting the threshold size to be equal to the multiplane page size of the memory device, the memory system can ensure that the data written from the first buffer to the memory device starts with a zero multiplane page offset, thereby avoiding die misalignment and supporting improved read performance (e.g., compared to die misaligned data).

[0017] Firstly, in reference Figure 1 and 2 The features of this disclosure are described in the context of the systems and apparatus described. Additionally, in reference to... Figures 3 to 5 The features of this disclosure are described within the context of the described data flow and process flow. (See references...) Figure 6 and 7 The device diagrams and flowcharts described in connection with the two-stage buffering operation that supports write commands further illustrate and describe these and other features of this disclosure, and are also referred to in the device diagrams and flowcharts.

[0018] Figure 1 This document describes an example of a system 100 that supports two-stage buffering operations for write commands, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be contained in a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or any other computing device containing memory and processing devices.

[0021] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface with host system controller 106, which may be an instance of a control component configured to cause host system 105 to perform various operations according to the examples described herein. Host system 105 may include one or more devices, and in some cases may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to and read data from memory system 110. Although Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include (but are not limited to) SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, DIMM interfaces (e.g., DIMM slot interfaces supporting DDR), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be included in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, then the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0025] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling, discard item collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or any combination thereof. The hardware may include a circuit system having dedicated (e.g., hard-coded) logic that performs the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuit system.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed to the memory system controller 115 herein.

[0028] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0029] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115 or perform one or more functions attributed herein to memory system controller 115. For example, such as Figure 1 As described above, memory device 130-a may include local controller 135-a and memory device 130-b may include local controller 135-b.

[0030] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0031] In some instances, memory device 130 may operate using or based on virtual blocks and virtual pages. A virtual block may correspond to a block 170 for each plane 165 and each NAND die 160. Each virtual block may contain multiple virtual pages. In some cases, multiple virtual pages may correspond to physical pages 175 (e.g., four virtual pages per physical page 175). In some instances, a virtual block may contain tens of thousands of virtual pages (e.g., depending on the size of memory device 130). Memory device 130 may perform read and write operations based on virtual blocks and virtual pages. In some instances, one or more virtual pages, virtual blocks, pages 175, blocks 170, or memory device 130 may be referred to as a “partition” or “subset” of memory system 110.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLC) when configured to store two bits of information, as three-level cells (TLC) when configured to store three bits of information, as four-level cells (QLC) when configured to store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases, may involve narrower read or write margins or greater complexity to support the circuitry.

[0033] In some cases, plane 165 may refer to several groups of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, as long as different blocks 170 are in different planes 165, concurrent operations can be performed on memory cells within different blocks 170. In some cases, performing concurrent operations in different planes 165 is subject to one or more restrictions, such as performing the same operation on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared between planes 165).

[0034] For example, host system 105 can read data from and write data to pages 175 spanning multiple planes 165 across memory die 160. A page 175 spanning multiple planes 165 (which may be referred to as a multi-plane page) may contain multiple offsets to which data can be written and read. Each offset may correspond to a minimum data unit supported by memory device 130. For example, host system 105 may support minimum data sizes for reading and writing data (e.g., 4 kB for Universal Flash Storage (UFS), 512 bytes (B) for an embedded multimedia card (eMMC)). The multi-plane pages of memory device 130 may be divided into multiple offsets of the minimum data size, such that data can be written to a multi-plane page starting from any offset and, correspondingly, read from a multi-plane page starting from any offset.

[0035] In some instances, memory device 130 (e.g., a NAND flash device) may contain a physical page size of 16 kB. Memory device 130 may support parallel read and write operations across different planes 165 (e.g., two or four planes) of memory die 160. Therefore, the multi-plane page size of memory device 130 may be 32 kB for a two-plane NAND die 160 or 64 kB for a four-plane NAND die 160. However, other page sizes and numbers of planes may be supported by system 100. If the minimum data read and write size is 4 kB and the multi-plane physical page size is 64 kB, then the multi-plane page may contain 16 cells for reading and writing the minimum size of data (e.g., each cell is a 16 kB user data size). Therefore, the multi-plane page may support 16 possible offsets. If host system 105 writes data to a multi-plane page of memory die 160 starting at zero offset, the write operation may result in die alignment. However, if the host system 105 writes data to a multiplane page of the memory die 160 that begins at a non-zero offset (e.g., 1 to 15), the write operation can result in die misalignment. System 100 may support one or more techniques to avoid die misalignment. For example, system 100 may support two-stage buffering operations for write commands to ensure that data is written to the multiplane page of the memory die 160 starting at a zero offset.

[0036] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled to a common word line), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled to a common digital line).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level) but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., partially concurrently programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., partially concurrently erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, an older page 175 may not be updated until the entire block 170 containing page 175 is erased in some cases.

[0038] System 100 may include any number of non-transitory computer-readable media that support two-stage buffered operations supporting write commands. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media containing instructions (e.g., firmware) for performing the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0039] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include one or more memory arrays and associated circuitry, for example, in combination with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0040] Although features of this disclosure are described herein with reference to NAND memory device 130, it should be understood that features of this disclosure may be implemented in other memory devices 130 or memory systems 110. For example, one or more features of this disclosure described herein may be implemented in non-volatile memory or other memory devices 130, such as SSD memory devices.

[0041] Figure 2 This document describes an instance of system 200 that supports two-stage buffering operations for write commands, based on the examples disclosed herein. System 200 may be used as a reference. Figure 1 The system 100 or an example of its aspects is described. System 200 may include a memory system 210 configured to store data received from host system 205 and to send data to host system 205 when requested by host system 205 using access commands (e.g., read commands or write commands). System 200 may implement references Figure 1 The described aspects of system 100. For example, memory system 210 and host system 205 may be instances of memory system 110 and host system 105, respectively.

[0042] Memory system 210 may include memory device 240 to store data transferred between memory system 210 and host system 205, for example, in response to receiving an access command from host system 205, as described herein. Memory device 240 may include references Figure 1The memory device 240 may include NAND memory, PCM, self-select memory, 3D cross-connect, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, OxRAM, or SSD.

[0043] Memory system 210 may include a memory controller 230 for controlling the direct transfer of data to and from memory device 240, such as for storing data, retrieving data, and determining memory locations where data is stored and retrieved. The memory controller 230 may communicate with memory device 240 directly or via a bus (not shown) using protocols specific to each type of memory device 240. In some cases, a single memory controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, memory system 210 may include multiple memory controllers 230, such as different memory controllers 230 for each type of memory device 240. In some cases, the memory controller 230 may implement a reference... Figure 1 Aspects of the local controller 135 described.

[0044] The memory system 210 may additionally include an interface 220 for communicating with the host system 205 and a buffer 225 for temporarily storing data transferred between the host system 205 and the memory device 240. In some instances, the interface 220, buffer 225, and memory controller 230 may be used to translate data between the host system 205 and the memory device 240 (e.g., as shown by data path 250) and may be collectively referred to as data path components. In some systems (e.g., for managed NAND), buffer 225-a may be a component of the memory system controller 215. In some other systems (e.g., for SSDs), buffer 225-b may be separate from the memory system controller 215.

[0045] Using buffer 225 to temporarily store data during transmission allows data to be buffered while commands are being processed, thereby reducing latency between commands and allowing for arbitrary data sizes associated with commands. This also allows for handling command bursts, and once the burst stops, buffered data can be stored or transmitted (or both). Buffer 225 may include relatively fast memory (such as some type of volatile memory, such as SRAM or DRAM) or hardware accelerators or both to allow for fast storage of data into and retrieval of data from buffer 225. Buffer 225 may include data path switching components for bidirectional data transfer between buffer 225 and other components.

[0046] In some cases, temporarily storing data in buffer 225 can refer to storing data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be stored in buffer 225 (e.g., it can be overwritten with data from an additional access command). Additionally, buffer 225 can be a non-cached buffer. That is, data may not be read directly from buffer 225 by the host system 205. For example, a read command can be added to a queue without requiring an operation to match the address with an address already in buffer 225 (e.g., no cached address matching or lookup operation is required).

[0047] Memory system 210 may include memory system controller 215 for executing commands received from host system 205 and controlling data path components during data movement. Memory system controller 215 may be a reference... Figure 1 An example of a memory system controller 115 is described. Bus 235 can be used for communication between system components.

[0048] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) can be used to control the processing of access commands and the movement of corresponding data. This can be advantageous, for example, if more than one access command from host system 205 is processed concurrently by memory system 210. As an example of a possible implementation, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and memory controller 230, respectively. However, the queues can be located anywhere within memory system 210 during use.

[0049] Data transferred between host system 205 and memory device 240 may use a different path within memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 via data path components instead of bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0050] If host system 205 transmits an access command to memory system 210, the command can be received by interface 220, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). Therefore, interface 220 can be considered the front end of memory system 210. After receiving each access command, interface 220 can transmit the command to memory system controller 215, for example, via bus 235. In some cases, each command can be added to command queue 260 via interface 220 to transmit the command to memory system controller 215.

[0051] The memory system controller 215 can determine that an access command has been received in response to communication from interface 220. In some cases, the memory system controller 215 can determine that an access command has been received by retrieving the command from command queue 260. The command can be removed from command queue 260 after it has been retrieved, for example, by the memory system controller 215. In some cases, the memory system controller 215 can cause interface 220 to remove the command from command queue 260, for example, via bus 235.

[0052] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transferring the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0053] In either case, the memory system controller 215 may use buffer 225 to temporarily store data received from or sent to the host system 205, etc. Buffer 225-a or buffer 225-b can be considered as an intermediate step in the memory system 210. In some cases, buffer address management (e.g., pointers to address locations in buffer 225) may be performed by hardware (e.g., dedicated circuitry) in interface 220, buffer 225, or memory controller 230.

[0054] In order to process a write command received from host system 205, memory system controller 215 may first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the write command, for example via firmware (e.g., controller firmware).

[0055] In some cases, buffer queue 265 can be used to control the flow of commands associated with data stored in buffer 225, including write commands. Buffer queue 265 may contain access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 may be moved to buffer queue 265 by memory system controller 215 and may remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating the location in buffer 225 where the data associated with each command is stored may be maintained. Using buffer queue 265, multiple access commands can be received sequentially from host system 205 and at least a portion of the access commands can be processed concurrently.

[0056] If buffer 225 has sufficient space to store the write data, then memory system controller 215 may cause interface 220 to transmit an availability indication (e.g., a "transfer ready" indication) to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). When interface 220 subsequently receives data associated with the write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of the stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, for example, via bus 235 whether the data transfer to buffer 225 has been completed.

[0057] Once written data is stored in buffer 225 via interface 220, the data can be transferred out of buffer 225 and stored in memory device 240. This can be accomplished using memory controller 230. For example, memory system controller 215 can cause memory controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Memory controller 230 can be considered as the back-end of memory system 210. Memory controller 230 can, for example, indicate to memory system controller 215 via bus 235 that the transfer of data to memory device 240 has been completed.

[0058] In some cases, memory queue 270 can be used to assist in write data transfers. For example, memory system controller 215 can push write commands from buffer queue 265 (e.g., via bus 235) to memory queue 270 for processing. Memory queue 270 may contain entries for each access command. In some instances, memory queue 270 may additionally include: a buffer pointer (e.g., an address) indicating the location in buffer 225 where the data associated with the command is stored; and a memory pointer (e.g., an address) indicating the location in memory device 240 associated with the data. In some cases, memory controller 230 can obtain the location within buffer 225 from which data is obtained, either from buffer 225, buffer queue 265, or memory queue 270. Memory controller 230 can manage the location within memory device 240 for storing data (e.g., performing wear leveling, discarded item collection, and the like). Entries can be added to memory queue 270, for example, by memory system controller 215. The entry can be removed from the storage queue 270 after the data transfer is complete, for example by the storage controller 230 or the memory system controller 215.

[0059] To support access commands (e.g., write commands), system 200 may implement a two-stage buffering operation. For example, instead of using a single buffer 225 to store data for a command (e.g., a write command), system 200 may implement two buffers: a clear buffer 275 and a temporary buffer 280. The clear buffer 275 and temporary buffer 280 may be subsets of the same buffer 225 (e.g., the same buffer 225 may be used to form a multi-stage buffering process) or may be separate buffers in memory. In some instances, the multi-stage buffering process may contain two stages, while in other instances, it may contain more stages. In some instances, buffer 225-a may contain clear buffer 275-a and temporary buffer 280-a, or buffer 225-b may contain clear buffer 275-b and temporary buffer 280-b. The clear buffer 275 and temporary buffer 280 may correspond to two stages of a multi-stage buffering operation. As an example, host data may be written to an mNAND device (e.g., memory system 210). Data can be sent to a write buffer (e.g., buffer 225-a) of the mNAND controller (e.g., memory system controller 215) and later cleared from the write buffer into the NAND flash (e.g., memory device 240). The write buffer can be divided into two buffers (clear buffer 275-a and temporary buffer 280-a) to support multi-stage buffering operations.

[0060] System 200 may receive a command (e.g., a write command) to write data to memory device 240. In some cases, the command may be received from host system 205. The write command may be associated with a specific data transfer size. Based on or in response to the data transfer size and a threshold size, memory system controller 215, buffer queue 265, or a combination thereof may determine whether to add data to clear buffer 275, temporary buffer 280, or a combination thereof (e.g., adding a first portion of the data to clear buffer 275 and adding a second dissimilar portion of the data to temporary buffer 280). For example, the threshold size may be a reference... Figure 1 The memory device 240 is described as having a multi-plane page size. The memory system controller 215, buffer queue 265, or a combination thereof can add data to a clear buffer 275 in blocks according to a threshold size (e.g., the multi-plane page size of the memory device 240) and can add other data (e.g., data smaller than the threshold size) to a temporary buffer 280. If the data stored in the temporary buffer 280 meets a copy threshold (e.g., the data meets or exceeds the multi-plane page size), then the threshold-sized data can be copied from the temporary buffer 280 to the clear buffer 275 and removed from or overwritten in the temporary buffer 280. Therefore, data added to the clear buffer 275 is added in blocks according to the threshold size.

[0061] The clear buffer 275 can clear data into (e.g., out of) the memory device 240 (e.g., using the memory controller 230, the memory queue 270, or both). Clearing data may involve writing data to one or more partitions of the memory device 240 and removing the corresponding data from the clear buffer 275. If the threshold size of the data block in the clear buffer 275 is equal to the multiplane page size of the memory device 240, then the multistage buffering operation ensures that data written from the clear buffer 275 to the memory device 240 can be written starting with zero offset and can fill one or more complete multiplane pages (so that subsequent write operations from the clear buffer 275 also start with zero offset). Thus, by implementing a first buffer (e.g., the clear buffer 275) and a second buffer (e.g., a temporary buffer 280) to handle operations (e.g., write operations), the memory system 210 can avoid die misalignment in one or more memory devices 240 and other advantages. In some instances, the multistage buffering process may contain two stages, while in other instances, the multistage buffering process may contain more stages.

[0062] In order to process a read command received from host system 205, memory system controller 215 may again first determine whether buffer 225 has sufficient available space to store the data associated with the command. For example, memory system controller 215 may determine the amount of space within buffer 225 available for storing the data associated with the read command, for example via firmware (e.g., controller firmware).

[0063] In some cases, buffer queue 265 can be used to assist in buffering the data associated with a read command in a manner similar to that described above regarding write commands. For example, if buffer 225 has sufficient space to store the read data, then memory system controller 215 can cause memory controller 230 to retrieve the data associated with the read command from memory device 240 and store the data in buffer 225 for temporary storage using data path 250. Once the data transfer to buffer 225 is complete, memory controller 230 can, for example, indicate this to memory system controller 215 via bus 235.

[0064] In some cases, the storage queue 270 can be used to assist in data transfer. For example, the memory system controller 215 can push a read command to the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location of the data retrieved from the buffer 225 or the storage queue 270 within the memory device 240. In some cases, the storage controller 230 can obtain the location of the data stored in the buffer 225 from the buffer queue 265. In some cases, the storage controller 230 can obtain the location of the data stored in the buffer 225 from the storage queue 270. In some cases, the memory system controller 215 can move a command processed by the storage queue 270 back to the command queue 260.

[0065] Once data is stored in buffer 225 by storage controller 230, the data can be transferred out of buffer 225 and sent to host system 205. For example, storage system controller 215 can cause interface 220 to retrieve data from buffer 225 using data path 250 and transfer the data to host system 205, for example, according to a protocol (e.g., UFS protocol or eMMC protocol). For example, interface 220 can process commands from command queue 260 and can indicate to storage system controller 215, for example, via bus 235, that the data transfer to host system 205 has been completed.

[0066] The memory system controller 215 can execute received commands according to a sequence (e.g., first-in-first-out order, or according to the order of command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to be moved into and out of buffer 225, as described above. When data is moved into and stored in buffer 225, the command may remain in buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred out of buffer 225), then the command may be removed from buffer queue 265, for example, by the memory system controller 215. If the command is removed from buffer queue 265, then the address where the data previously associated with the command was stored can be used to store the data associated with the new command.

[0067] The memory system controller 215 may be additionally configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling, discard item collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may recognize one or more physical block addresses indicated by the LBAs. Based on or in response to a two-stage buffer operation, the starting LBA of each write operation may be distributed with zero offset across physical multiplane pages to support die alignment. In some cases, one or more consecutive LBAs may correspond to non-consecutive physical block addresses. In some cases, the memory controller 230 may be configured to perform one or more of the above operations in conjunction with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the memory controller 230, and the memory controller 230 may be omitted.

[0068] Figure 3 This describes an instance of data stream 300 that supports two-stage buffering operations for write commands, based on the examples disclosed herein. Data stream 300 can be found in the reference... Figure 1 and 2 The system 100 (or one or more components thereof) or system 200 (or one or more components thereof) described are implemented. For example, host device 305 may be an instance or component of host system 105 or host system 205, first buffer 315 may be an instance of clear buffer 275, second buffer 320 may be an instance of temporary buffer 280, and memory device 335 may be a reference. Figure 1 and 2Examples of memory devices 130 or 240 described. Data stream 300 may use first buffer 315 and second buffer 320 to avoid die misalignment in memory device 335, thereby improving read performance for data files stored in memory device 335 (e.g., compared to read operations for die misaligned data).

[0069] The multi-plane page of memory device 335 may include a set of planes 340 and multiple offsets 345. For example, as shown in the reference... Figure 1 The multi-plane page may contain four planes 340 (e.g., plane 0, plane 1, plane 2, and plane 3) and 16 offsets 345 (e.g., 0 to 15). If the memory system receives a read command on the memory device 335, the read command may instruct a starting LBA for reading data from the memory device 335. The starting LBA may correspond to an offset 345 in the multi-plane page (e.g., based on a logical-to-physical (L2P) mapping).

[0070] If the starting LBA is mapped to offset 0 (e.g., corresponding to die alignment), the memory system can efficiently read data from memory device 335. For example, due to die alignment, the memory system can perform a single read operation (e.g., a system-level sequential read operation) to read data from memory device 335 and can further improve read performance by utilizing cache read operations. Based on or in response to reading data starting from offset 0, memory device 335 can support sequential and random read performance of approximately 2000 megabytes per second (MBps) with relatively large block sizes (e.g., 512 kB). Alternatively, if the starting LBA is mapped to a non-zero offset (e.g., any offset from 1 to 15), then device-level (e.g., memory device 335 level) and system-level (e.g., memory system level) read performance will be degraded compared to reading data starting from zero offset. For example, due to die misalignment, the memory system can perform two read operations to read data from memory device 335 starting from the corrected offset and cannot support cache read operations (e.g., based on or in response to performing two read operations to read data from a multi-plane page). Reading data when the die is misaligned can significantly increase processing overhead and latency compared to reading data when the die is aligned, as it involves executing two read commands and not utilizing cached read operations. For die misalignment, the memory device 335 can support read performance of approximately 1000 MBps. This performance degradation associated with die misalignment can be particularly significant when reading relatively large files (e.g., files larger than a threshold size) due to the large file size originating from multiple multi-plane pages.

[0071] Host device 305 may support optimal transfer lengths for relatively large file operations based on the characteristics of host device 305, the memory system, or a combination thereof. In some instances, host device 305 may support write optimal transfer lengths L for relatively large file operations of 512kB or 1024kB. Host device 305 may encapsulate user data for write operations using the optimal transfer length. Additionally, host device 305 may support metadata and small file operations with variable transfer lengths. For example, host device 305 may write small files or metadata to memory device 335, wherein the small files or metadata may have a transfer length dynamically determined based on the small file size or metadata size. The transfer length of small files or metadata may be less than the optimal transfer length for relatively large files. In some cases, host device 305 may support a minimum threshold size (e.g., 4kB) for reading and writing metadata and small files to memory device 335.

[0072] In some cases, die misalignment can occur in response to the memory system mixing relatively large files with small files or metadata in the same multiplane page. For example, host device 305 may begin writing user data of a relatively large file to memory device 335, update the metadata of the relatively large file, or insert a small file into memory device 335, and then write the relatively large file. This process can occur due to multiple threads running in parallel at host device 305, one thread writing the relatively large file to memory device 335 while another thread concurrently updates the metadata or writes the small file to memory device 335. Mixing user data of a relatively large file with metadata, small file data, or both in the write buffer can result in a die misalignment configuration in memory device 335 (e.g., in a NAND flash). For example, the write buffer may clear metadata or small file data to a subset of cells in the multiplane page (e.g., starting at offset 0, metadata or small file data may be stored in the first two cells of the multiplane page). In response to this metadata update or small file creation, the write buffer can flush the user data of a relatively large file into the remaining cells of the multiplane page. Due to the metadata or small file data, the user data of a relatively large file may start at a non-zero offset of 345 (e.g., starting at offset 2 and spanning the remaining cells of the multiplane page). Therefore, if a metadata update, small file creation, or both are performed, using a single write buffer can result in a bare misalignment of the relatively large file, where mixing the relatively large file with small files or metadata in the same multiplane page negatively impacts the read performance of the relatively large file data.

[0073] Some systems can implement dummy data padding to avoid die misalignment for relatively large files of user data. For example, a system can inspect host write operations to determine the data block size of the write operation. If the system detects a write operation with a small data block size (e.g., smaller than the multiplane page size) inserted within a write operation of a relatively large data block size (e.g., the optimal transfer length or another similar length), the system can pad the small data block size with dummy data from the write buffer, making the small data block with the additional dummy data equal to the multiplane page size. Therefore, writing a small data block with additional dummy data to memory device 335 does not cause die misalignment because the small data block with additional dummy data pads the multiplane page. However, storing dummy data shortens the lifetime of memory device 335 by using a portion of the total bytes written (TBW) for memory device 335. Additionally, if data is relocated within memory device 335 (e.g., for discarded item collection, folding), the dummy data (which may be an instance of invalid data) can be removed during the relocation process. Therefore, the dummy data filling effect that avoids misalignment of the die can be lost after data repositioning.

[0074] Some other systems may implement different open blocks to avoid misalignment of relatively large file user data. For example, a system may implement a block size threshold for writing data, where the block size threshold is equal to the multiplane page size (e.g., 64 kB). If the data block size for a write operation is lower than the block size threshold, the system may write the data to a first open block (e.g., a temporary SLC open block). Otherwise, if the data block size for a write operation is equal to or higher than the block size threshold, the system may write the data to a second open block (e.g., a main TLC open block). This process avoids mixing the storage of relatively large file data with the storage of small file data or metadata. However, the block size cannot be an accurate indicator of the data type. In some cases, the metadata write block size may be greater than the block size threshold or the relatively large file write block size may be less than the block size threshold. For example, to write a relatively large file of 32788 kB, the host device 305 may send multiple write commands with an optimal transfer length, resulting in a final write command of 20 kB (e.g., less than the multiplane page size). This final write command can create a raw misalignment for subsequent files stored in the same block. Furthermore, maintaining multiple open blocks for host device 305 increases resource overhead at the memory system level. For example, the memory system must perform independent Redundant Array of Independent Disks (RAID) protection and data erasure switching between different open blocks, thereby increasing the processing overhead associated with the system performing write operations on different open blocks.

[0075] In contrast, the memory system implementing data flow 300 can support two-stage buffering operations (e.g., using a first buffer 315 and a second buffer 320) to avoid die misalignment. Two-stage buffering can support more efficient use of memory resources of memory device 335 than system-implemented dummy data padding, for example, by storing dummy data without using resources. Furthermore, two-stage buffering can prevent die misalignment even if data is repositioned. In addition, two-stage buffering can support more efficient use of processing resources to avoid die misalignment than system-implemented different open blocks, for example, by managing fewer open blocks for handling host-written data.

[0076] Data stream 300 may use multiple buffers instead of a single write buffer. For example, the write buffer of the memory system may be separated into or may include two buffers (a clear buffer (e.g., the first buffer 315) and a temporary buffer (e.g., the second buffer 320)) to avoid mixing small file data and metadata with relatively large file data. If the host device 305 performs a write operation 310, the data of the write operation 310 may be added to the first buffer 315, the second buffer 320, or a combination thereof based on or in response to the data transfer size and a threshold size (e.g., equal to the multiplane page size). Thus, data may be added to the first buffer 315 in chunks equal to the multiplane page size, while data may be added to the second buffer 320 in chunks smaller than the multiplane page size. If the data stored in the second buffer 320 reaches the threshold size, the memory system may perform a copy operation 325 to copy the threshold size of data (e.g., comprising multiple data chunks corresponding to metadata, small data files, or both, together equal to the multiplane page size) from the second buffer 320 to the first buffer 315. If the clearing condition is met by the first buffer 315, then the first buffer 315 can perform a clearing operation 330 to write data from the first buffer 315 instead of from the second buffer 320 to the multiplane page of the memory device 335. By using the first buffer 315 and the second buffer 320 to ensure that data is added to the first buffer 315 in blocks equal to the size of the multiplane page, the memory system can avoid mixing relatively large file data with metadata or small file data in the same multiplane page of the same block. Therefore, the two-stage buffering operation of the write command reduces die misalignment in the memory device 335 and correspondingly improves the read performance of the memory system.

[0077] Figure 4 This describes an instance of a data stream 400 that supports two-stage buffering operations for write commands, based on the examples disclosed herein. Data stream 400 can be found in the reference... Figure 1 and 2The system 100 (or one or more components thereof) or system 200 (or one or more components thereof) described are implemented. For example, data flow 400 may be referenced. Figure 3 An example of the described write operation 310. The first buffer 405 may be an instance of clear buffer 275, first buffer 315, or both, and the second buffer 410 may be an instance of temporary buffer 280, second buffer 320, or both, as referenced. Figure 2 and 3 Description. The first buffer 405 and the second buffer 410 may be components of a write buffer or may be separate buffers. The memory system may implement the first buffer 405 and the second buffer 410 to mitigate die misalignment during write operations.

[0078] In some instances, a device (e.g., a memory system) may include a first buffer 405 and a second buffer 410. The first buffer 405 may be configured to support storing data of a first data size (e.g., a threshold size 425), while the second buffer 410 may be configured to support storing data smaller than the first data size (e.g., the threshold size 425). Furthermore, the second buffer 410 may be configured to trigger a copy operation after a copy condition is met. The copy condition may be storing a total amount of data equal to or greater than the threshold size 425 in the second buffer 410. After triggering the copy operation, the second buffer 410 may be configured to copy data of the threshold size 425 from the second buffer 410 to the first buffer 405. The copied data may be deleted from the second buffer 410 or may be retained and overwritten during subsequent write operations. The first buffer 405 may be configured to trigger a buffer clearing operation after a clear condition is met. In some instances, the clearing condition may be storing a total amount of data equal to or greater than a clearing threshold (e.g., the size of the first buffer 405) in the first buffer 405. After a buffer clearing operation is triggered, the first buffer 405 may be configured to write data to one or more memory devices. The second buffer 410 may directly respond to the triggered buffer clearing operation to avoid writing data to the memory devices, and may instead retain data in the second buffer 410 (e.g., retain a portion of the data in the write buffer despite the buffer clearing operation). The first buffer 405 may be configured to write data of threshold size 425 in blocks to each multiplane page of the memory device to avoid die misalignment, wherein the multiplane page size may be equal to the threshold size 425.

[0079] As an example, the memory system may support writing data to one or more memory devices with a multiplane page size of 64 kB. In some cases, the write buffer may support a storage capacity of 832 kB. Depending on the multiplane page size, the write buffer may be divided into a first buffer 405 (e.g., a clear buffer) of 768 kB and a second buffer 410 (e.g., a temporary buffer) of 64 kB. For example, relatively large file data may be added to the first buffer 405 in blocks of 64 kB each (e.g., the threshold size 425 may be 64 kB), while data such as small file data, metadata, or remaining relatively large file data may be added to the second buffer 410 in blocks of less than 64 kB. If the second buffer 410 is full, then the second buffer 410 may copy 64 kB of data to the first buffer 405. In some instances, the second buffer 410 may contain additional storage capacity exceeding the threshold size 425.

[0080] Alternatively, the memory system may include multiple temporary buffers such that if the first temporary buffer is full, the memory system may add data to another temporary buffer until the data from the first temporary buffer is successfully copied to the clear buffer. If the first buffer 405 is full or otherwise meets the clearing condition, the first buffer 405 may, in some instances, trigger an automatic buffer clearing mechanism to write data from the first buffer 405, rather than the second buffer 410, to one or more memory devices (e.g., NAND flash, SSD, or other memory devices).

[0081] If the memory system receives a command to write data to the memory device, the memory system can determine whether to add data to the first buffer 405, the second buffer 410, or a combination thereof based on or in response to the data transfer size 420 and the threshold size 425. For example, if the data transfer size 420 is greater than or equal to the threshold size 425, the memory system can identify one or more portions of data having the threshold size 425 and can determine to add one or more portions of the data to the first buffer 405. For example, for data 415-a having a data transfer size 420-a, the memory system can determine to add both portions of the threshold size 425 to the first buffer 405. Because the data transfer size 420-a is a multiple of the threshold size 425, the memory system can determine to add data 415-a to the first buffer 405 instead of the second buffer 410.

[0082] In some instances, if the data transfer size 420 is not a multiple of the threshold size 425, then the data 415 may consist of one or more portions of the threshold size 425 and an additional portion smaller than the threshold size 425 (e.g., remaining relatively large file data). In some such instances, the memory system may determine to add one or more portions of the data having the threshold size 425 to the first buffer 405 and to add the additional portion having a size smaller than the threshold size 425 to the second buffer 410. For example, for data 415-b having a data transfer size 420-b, the memory system may determine to add a portion of the threshold size 425 to the first buffer 405 and to add the additional portion smaller than the threshold size 425 to the second buffer 410. Because the data transfer size 420-b is greater than the threshold size 425 but not a multiple of the threshold size 425, the memory system may determine to add data 415-b to a combination of the first buffer 405 and the second buffer 410 (e.g., adding different discrete portions of data 415-b to the first buffer 405 and the second buffer 410).

[0083] If the data transfer size 420 is less than the threshold size 425, then the memory system may add data 415 to the second buffer 410. For example, for data 415-c with a data transfer size 420-c, the memory system may determine to add data 415-c to the second buffer 410 instead of the first buffer 405 because the data transfer size 420-c is less than the threshold size 425. Using this technique, the memory system may load any data received for a write command into the first buffer 405, the second buffer 410, or a combination thereof, where the buffers determine how the data is written to one or more memory devices.

[0084] Figure 5 This document describes an example of a process flow 500 that supports two-stage buffering operations for write commands, based on the examples disclosed herein. Process flow 500 can be found in the references. Figure 1 and 2 The described system 100 (or one or more components thereof) or system 200 (or one or more components thereof) is implemented and can be implemented with reference to this. Figure 3 and 4The data flow described is 300 or 400. For example, process flow 500 can be implemented by a device (e.g., a memory system) comprising one or more memory devices and controllers coupled to the memory devices. The memory devices of the memory system may include a physical page size M and a number of planes (N), such that each multi-plane page size is equal to M*N. The memory system can implement process flow 500 to write data to the multi-plane pages with zero offset to avoid die misalignment and support improved read performance. In some cases, alternative instances can be implemented, some of which may be performed in a different order than described or not at all. Additionally or alternatively, operations may include additional features not mentioned below, or additional processes may be added.

[0085] At 505, a write command is received. For example, the memory system may receive a write command (e.g., a host write operation) from the host system. The write command may be received at the controller of the memory system. The write command may indicate the data to be written to memory (e.g., one or more memory devices, such as NAND flash, SSD, or other memory devices). The data transfer size 510 of the data to be written to memory may be represented as (A*M*N+B) kB. For example, the data may consist of a certain number of portions A multiplied by a data size equal to the multiplane page size M*N plus an additional data portion B smaller than the multiplane page size. For relatively large data files, portion B may be referred to as the remaining relatively large file data (e.g., the data remaining after dividing the relatively large data file into A portions of size M*N).

[0086] At 515, the memory system determines whether to add data to a first buffer, a second buffer, or a combination thereof. The first buffer may be an instance of a clear buffer, and the second buffer may be an instance of a temporary buffer. If A ≠ 0, then at 520, at least a portion of the data is added to the first buffer. Specifically, the memory system may determine to add A*M*N data 525 (e.g., A portions of data of size M*N) to the first buffer. If B ≠ 0, then at 530, at least a portion of the data is added to the second buffer. Specifically, the memory system may determine to add B data 535 (e.g., a portion of data of size B) to the second buffer.

[0087] For example, if the data transfer size 510 is less than the multiplane page size (e.g., less than M*N, such that A=0), then the data can be added to the temporary buffer at 530. For example, if the data transfer size 510 is the "optimal" transfer length (e.g., the data transfer size 510 is a multiple of the multiplane page size M*N, such that B=0), then the data can be added directly to the clear buffer at 520. If the data transfer size 510 is greater than the multiplane page size but not a multiple of it such that A≠0 and B≠0, then the data can be added to a combination of the clear buffer and the temporary buffer at both 520 and 530. For example, A*M*N data 525 can be added to the clear buffer at 520 and B data 535 can be added to the temporary buffer at 530.

[0088] At 540, the memory system determines whether the second buffer (e.g., a temporary buffer) meets the copy threshold. If the second buffer stores a amount of data equal to or greater than the threshold size (e.g., a multiplane page size M*N), then the second buffer meets the copy threshold (e.g., a copy condition). If the copy threshold is met, then at 545, the memory system can copy at least a portion of the data stored in the second buffer into the first buffer.

[0089] For example, a memory system can copy data 550 of a threshold size (e.g., a multi-plane page size M*N) from a temporary buffer to a clear buffer. If the size of the temporary buffer is M*N, then the copying condition for the temporary buffer can be that the temporary buffer is full. If the temporary buffer is full, then the memory system can move (e.g., copy or relocate) the data from the temporary buffer to the clear buffer. In some instances, the temporary buffer can invalidate the copied data stored in the temporary buffer in response to copying data to the clear buffer, so that invalid data can be overwritten in the temporary buffer. If the copying threshold is not met, then the memory system can continue to store data in the temporary buffer.

[0090] At 555, the memory system determines whether the first buffer (e.g., a clear buffer) meets a clear threshold. If the first buffer stores an amount of data equal to or greater than the clear threshold size (e.g., based on the size of the first buffer), then the first buffer meets the clear threshold (e.g., a clear condition). If the clear threshold is met, then at 560, the memory system can clear the data from the first buffer to a memory device (e.g., a NAND flash or another memory device).

[0091] For example, a memory system can write data 565 of size k*M*N to one or more memory devices that support multi-plane pages of size M*N. That is, because data is added to a first buffer in blocks of size M*N, the data to be cleared from the first buffer is a multiple of M*N, k. Therefore, writing k*M*N to the multi-plane pages of the memory device begins with zero offset and ends with completion of the multi-plane page, ensuring that the next write operation also begins with zero offset and avoiding die misalignment. A second buffer can directly respond to the first buffer meeting a clear threshold by avoiding clearing data to the memory device (e.g., avoiding die misalignment). If the clear threshold is not met, the memory system can continue to store data in the clear buffer.

[0092] At 570, the memory system determines whether a buffer clearing command has been received. A buffer clearing command can be an instance of a synchronous cache operation or any other forced buffer clearing operation. The buffer clearing command can be received from the host system or can be triggered within the memory system. If a buffer clearing command is received, data can be cleared from both buffers (e.g., a first buffer and a second buffer) into the memory device at 575. For example, the memory system can clear data from the clearing buffer into the memory device as if a clearing threshold had been met. For temporary buffers, the memory system can clear data from the temporary buffer into a temporary block in the memory device. By clearing data from the temporary buffer into a temporary block different from the block into which data from the clearing buffer was written, the memory system avoids die misalignment. In some instances, the memory system can determine the amount of data written to the temporary block and can write additional data to the temporary block, such that the data fills one or more complete multiplane pages. If the size of the data written to the temporary block is a multiple of the multiplane page size M*N, then the memory system or memory device can reposition the data from the temporary block to another block without causing die misalignment.

[0093] The memory system can repeat this process for each write operation to avoid die misalignment and improve read performance, for example, for relatively large data files (e.g., data files spanning multiple multi-plane pages).

[0094] Aspects of process flow 500 may be implemented by controllers and other components in a system (e.g., system 100 or system 200). Alternatively, aspects of process flow 500 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory system). For example, when executed by a controller (e.g., a memory system controller), the instructions may cause the controller to perform operations of process flow 500.

[0095] Figure 6A block diagram 600 illustrates a memory system 620 supporting two-stage buffering operations for write commands, based on an example disclosed herein. The memory system 620 may be used as a reference. Figures 1 to 5 Examples of aspects of the described memory system. Memory system 620 or its various components may be examples of constructs for performing various aspects of a two-stage buffered operation supporting write commands, as described herein. For example, memory system 620 may include a write command component 625, a data transfer size determination component 630, a buffer manager 635, a buffer clearing component 640, a buffer copying component 645, a data invalidation component 650, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses, data paths, or both). Memory system 620 may be an example of a device comprising a memory device and a controller coupled to the memory device and configured such that the device performs one or more of the functions described herein.

[0096] Write command component 625 may be configured or otherwise supported to support means for receiving commands to write data to a memory device, the data having a data transfer size. Data transfer size determination component 630 may be configured or otherwise supported to support means for determining whether to add data to a first buffer, a second buffer, or a combination thereof based at least in part on the data transfer size and a threshold size. Buffer manager 635 may be configured or otherwise supported to support means for adding data to a first buffer, a second buffer, or a combination thereof (e.g., adding a first portion of data to a first buffer and adding a second portion of data different from the first portion of data to a second buffer, the data containing both the first and second portions) based at least in part on the addition, wherein the first buffer stores a first set of data and the second buffer stores a second set of data based at least in part on the addition. Buffer clearing component 640 may be configured or otherwise supported to clear a first set of data to a memory device based at least in part on the first set of data satisfying a clearing condition of the first buffer, wherein after the first set of data is cleared to the memory device at least in part on the clearing condition of the first buffer, the second set of data remains in the second buffer. For example, clearing the first set of data from the first buffer to the memory device does not cause the second set of data to be cleared from the second buffer to the memory device. Instead, the memory system may avoid clearing the second set of data to the memory device. In some instances, the first buffer may be called a clear buffer and the second buffer may be called a temporary buffer.

[0097] In some instances, the data transfer size determination component 630 may be configured or otherwise supported to determine, at least in part, whether to add data to the second buffer based on the data transfer size being less than a threshold size. In some such instances, the buffer manager 635 may be configured or otherwise supported to add data to the second buffer based at least in part on the determination that data should be added to the second buffer.

[0098] In some instances, the data transfer size determination component 630 may be configured or otherwise supported to include means for identifying one or more portions of data based at least in part on a data transfer size greater than or equal to a threshold size, each of the one or more portions having a threshold size, and the data transfer size determination component 630 may be configured or otherwise supported to include means for determining, at least in part on the threshold size of each of the one or more portions, to add one or more portions of data to a first buffer. In some such instances, the buffer manager 635 may be configured or otherwise supported to include means for adding one or more portions of data to a first buffer based at least in part on the determination that one or more portions of data should be added to the first buffer.

[0099] In some instances, the data consists of one or more portions plus an additional portion, the additional portion having a size smaller than a threshold size. In some such instances, the data transfer size determination component 630 may be configured or otherwise supported to determine, at least in part, whether to add the additional portion of data to the second buffer based on the additional portion size being smaller than the threshold size. In some such instances, the buffer manager 635 may be configured or otherwise supported to add the additional portion of data to the second buffer based at least in part on the determination that the additional portion of data should be added to the second buffer.

[0100] In some instances, the buffer copy component 645 may be configured or otherwise supported to copy at least a portion of the second set of data stored in the second buffer to the first buffer based at least partially on the second set of data satisfying the copy conditions of the second buffer. In some instances, the second set of data satisfies the copy conditions of the second buffer based at least partially on the second set of data having a second data size greater than or equal to a threshold size. In some instances, a portion of the second set of data has a third data size equal to the threshold size. In some instances, the data invalidation component 650 may be configured or otherwise supported to invalidate a portion of the second set of data stored in the second buffer based at least partially on copying at least a portion of the second set of data to the first buffer.

[0101] In some instances, to support the clearing of the first set of data into the memory device, the buffer clearing component 640 may be configured or otherwise supported to support the writing of the first set of data into the memory device with a zero multiplane page offset.

[0102] In some instances, the buffer clearing component 640 may be configured or otherwise supported to support means for receiving buffer clearing commands. In some instances, the buffer clearing component 640 may be configured or otherwise supported to support means for clearing a second set of data into a temporary block of the memory device, at least in part based on a buffer clearing command.

[0103] In some instances, the threshold size is the product of the physical page size of the memory device and the number of planes of the memory device.

[0104] In some instances, the buffer manager 635 may be configured or otherwise support means for storing data in a single buffer comprising a first buffer and a second buffer. In some other instances, the buffer manager 635 may be configured or otherwise support means for storing a first portion of data in the first buffer. In some instances, the buffer manager 635 may be configured or otherwise support means for storing a second portion of data in a second buffer separate from the first buffer. In some instances, the controller includes both the first and second buffers. In some instances, the memory device includes a NAND memory device.

[0105] Figure 7 The flowchart illustrates a method 700 that supports a two-stage buffering operation for write commands, based on examples disclosed herein. The operation of method 700 can be implemented by the memory system or its components described herein. For example, the operation of method 700 can be implemented by [reference needed]. Figures 1 to 6 The memory system described herein performs the functions described. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the functions described. Alternatively, the memory system may use dedicated hardware to perform aspects of the functions described. In some instances, the memory system may be an instance of a device comprising a memory device and a controller coupled to the memory device, and configured such that the device performs one or more of the functions described herein.

[0106] At 705, the method may include receiving a command to write data to a memory device, the data having a data transfer size. Operation 705 may be performed according to the examples disclosed herein. In some instances, aspects of operation 705 may be derived from references. Figure 6 The write command component 625 described is executed.

[0107] At 710, the method may include determining, at least in part, whether to add data to a first buffer, a second buffer, or a combination thereof, based on the data transfer size and a threshold size. Operation 710 may be performed according to the examples disclosed herein. In some instances, aspects of operation 710 may be derived from references... Figure 6 The data transfer size is determined by component 630.

[0108] At 715, the method may include adding data to a first buffer, a second buffer, or a combination thereof, at least in part based on the determination, wherein the first buffer stores a first set of data and the second buffer stores a second set of data, at least in part based on the addition. Operation 715 may be performed according to the examples disclosed herein. In some instances, aspects of operation 715 may be derived from references... Figure 6 The buffer manager 635 described is executed.

[0109] At 720, the method may include clearing a first set of data into a memory device based at least in part on the first set of data satisfying a clearing condition of a first buffer. The method may further include maintaining a second set of data in a second buffer after clearing the first set of data into the memory device based at least in part on the clearing condition of the first buffer. Operation 720 may be performed according to the examples disclosed herein. In some instances, aspects of operation 720 may be derived from references... Figure 6 The described buffer clearing component 640 is executed.

[0110] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing code containing instructions executable by a processor of an electronic device) for: receiving a command to write data to a memory device, the data having a data transfer size; determining, at least in part based on the data transfer size and a threshold size, whether to add data to a first buffer, a second buffer, or a combination thereof; adding data to the first buffer, the second buffer, or a combination thereof, at least in part based on the determination, wherein, at least in part based on the addition, the first buffer stores a first set of data and the second buffer stores a second set of data; and clearing the first set of data to the memory device, at least in part based on the first set of data satisfying a clearing condition of the first buffer, wherein, after the first set of data is cleared to the memory device at least in part based on the clearing condition of the first buffer, the second set of data remains in the second buffer.

[0111] In some instances of the method 700 and apparatus described herein, determining whether to add data to a first buffer, a second buffer, or a combination thereof may include operations, features, circuitry, logic, components, or instructions for determining whether to add data to a second buffer based at least in part on a data transfer size being less than a threshold size, and adding data to a first buffer, a second buffer, or a combination thereof may include operations, features, circuitry, logic, components, or instructions for adding data to a second buffer based at least in part on the determination to add data to a second buffer.

[0112] In some instances of the method 700 and apparatus described herein, determining whether to add data to a first buffer, a second buffer, or a combination thereof may include operations, features, circuitry, logic, components, or instructions for: identifying one or more portions of data, each of the one or more portions having a threshold size, at least in part based on the data transfer size being greater than or equal to a threshold size; and determining whether to add one or more portions of data to the first buffer, at least in part based on the threshold size of each of the one or more portions, and adding data to the first buffer, the second buffer, or a combination thereof may include operations, features, circuitry, logic, components, or instructions for adding one or more portions of data to the first buffer, at least in part based on the determination that one or more portions of data should be added to the first buffer.

[0113] In some instances of the method 700 and apparatus described herein, the data consists of one or more portions and additional portions having an additional portion size smaller than a threshold size. Determining whether to add data to a first buffer, a second buffer, or a combination thereof may include operations, features, circuitry, logic, components, or instructions for determining whether to add the additional portion of data to a second buffer, at least in part based on the additional portion size being smaller than the threshold size. Adding data to a first buffer, a second buffer, or a combination thereof may also include operations, features, circuitry, logic, components, or instructions for adding the additional portion of data to a second buffer, at least in part based on the determination that the additional portion of data should be added to the second buffer.

[0114] Some examples of the method 700 and apparatus described herein may further include operations, features, circuitry, logic, components, or instructions for copying at least a portion of the second set of data stored in the second buffer to the first buffer based at least in part on the second set of data satisfying a copy condition of the second buffer.

[0115] In some instances of the method 700 and apparatus described herein, the second set of data satisfies the replication condition of the second buffer at least in part based on the second set of data having a second data size greater than or equal to a threshold size.

[0116] In some instances of the method 700 and device described herein, a portion of the second set of data may have a third data size equal to the threshold size.

[0117] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for invalidating portions of the second set of data stored in the second buffer by at least partially copying at least a portion of the second set of data to the first buffer.

[0118] In some instances of the method 700 and apparatus described herein, clearing the first set of data into a memory device may include operations, features, circuitry, logic, components, or instructions for writing the first set of data into the memory device with a zero multiplane page offset.

[0119] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for: receiving a buffer clear command; and clearing a second set of data into a temporary block of the memory device, at least in part based on the buffer clear command.

[0120] In some instances of the method 700 and device described herein, the threshold size may be the product of the physical page size of the memory device and the number of planes of the memory device.

[0121] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for storing data in a single buffer that includes a first buffer and a second buffer.

[0122] Some examples of the method 700 and apparatus described herein may further include operations, features, circuit systems, logic, components, or instructions for storing a first portion of data in a first buffer; and storing a second portion of data in a second buffer separate from the first buffer.

[0123] In some instances of the method 700 and device described herein, the controller includes a first buffer and a second buffer.

[0124] In some instances of the method 700 and apparatus described herein, the memory device includes a NAND memory device.

[0125] It should be noted that the above methods describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0126] The information and signals described herein can be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal can represent a signal bus, where the bus can have various bit widths.

[0127] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that support the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connection, or coupling) if there is any conductive path between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connection, or coupling) can be open or closed, depending on the operation of the device containing the connected component. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the flow of signals between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0128] The term "coupling" refers to the condition that changes from an open-circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components via conductive paths). If, for example, a component of a controller couples other components together, then the component triggers a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0129] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, if a switch positioned between two components is turned on, then the components separated by the switch are isolated from each other. If a controller isolates two components, then the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0130] As used herein, the term “substantially” means that the modified characteristic (e.g., a verb or adjective modified by the term “substantially”) does not need to be absolute but is close enough to realize the advantage of the characteristic.

[0131] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe the connection between conditional actions, conditional procedures, or parts of a procedure.

[0132] The term "in response to" can refer to a condition or action that occurs at least partially (if not entirely) as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least partially as a result of the preceding condition or action (whether directly following or following one or more other intermediate conditions or actions that occur after the first condition or action).

[0133] Additionally, the terms "directly in response to" or "directly responding to" may refer to a condition or action occurring directly as a result of a preceding condition or action. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of a preceding condition or action, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of a preceding condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly responding to" this other condition or action.

[0134] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0135] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, then the transistor may be "off" or "deactivated."

[0136] The descriptions presented herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other instances." The detailed descriptions include specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described instances.

[0137] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a concatenated character following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the description, then the description applies to any similar components having the same first reference numeral, regardless of the second reference numeral.

[0138] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the above functions can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0139] For example, the various specification boxes and components described in connection with this disclosure may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0140] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the disclosure herein, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0141] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, DSL, or technology (such as infrared, radio, and microwave) is included in the media definition. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically copy data magnetically, while optical discs copy data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0142] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure will be made, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: Memory devices; and A controller, coupled to and configured to cause the memory system to: Receive a command to write data to the memory device, the data having a data transfer size; Whether to add the data to the first buffer, the second buffer, or a combination thereof is determined at least in part based on the data transfer size and the threshold size. The data is added to the first buffer, the second buffer, or a combination thereof, at least in part based on the determination, wherein the first buffer stores a first set of data and the second buffer stores a second set of data; and The first set of data is cleared into the memory device at least in part based on the first set of data satisfying the clearing condition of the first buffer, wherein after the first set of data is cleared into the memory device at least in part based on the clearing condition of the first buffer, the controller is configured such that the memory system maintains the second set of data in the second buffer.

2. The memory system according to claim 1, wherein: The controller, configured to cause the memory system to determine whether to add the data to the first buffer, the second buffer, or a combination thereof, is configured to cause the memory system to: The decision to add the data to the second buffer is based at least in part on the data transfer size being less than the threshold size; and The controller, configured to cause the memory system to add the data to the first buffer, the second buffer, or a combination thereof, is configured to cause the memory system to: The data is added to the second buffer at least in part based on the determination to add the data to the second buffer.

3. The memory system according to claim 1, wherein: The controller, configured to cause the memory system to determine whether to add the data to the first buffer, the second buffer, or a combination thereof, is configured to cause the memory system to: At least in part, one or more portions of the data are identified based on the data transmission size being greater than or equal to the threshold size, each of the one or more portions having the threshold size; and The decision to add one or more portions of the data to the first buffer is based at least in part on the fact that each of the one or more portions has the threshold size. and The controller, configured to cause the memory system to add the data to the first buffer, the second buffer, or a combination thereof, is configured to cause the memory system to: The data is added to the first buffer at least in part based on the determination to add one or more portions of the data to the first buffer.

4. The memory system according to claim 3, wherein: The data consists of one or more portions and an additional portion, wherein the additional portion has an additional portion size smaller than the threshold size; The controller, configured to cause the memory system to determine whether to add the data to the first buffer, the second buffer, or a combination thereof, is further configured to cause the memory system to: The decision to add the extra portion of the data to the second buffer is based at least in part on the fact that the size of the extra portion is less than the threshold size; and The controller, configured to cause the memory system to add the data to the first buffer, the second buffer, or a combination thereof, is further configured to cause the memory system to: The additional portion of the data is added to the second buffer, at least in part based on the determination to add the additional portion of the data to the second buffer.

5. The memory system of claim 1, wherein the controller is further configured such that the memory system: At least a portion of the second set of data stored in the second buffer is copied to the first buffer, based at least in part on the second set of data satisfying the copy condition of the second buffer.

6. The memory system of claim 5, wherein the second set of data satisfies the copy condition of the second buffer at least in part based on the second set of data having a second data size greater than or equal to the threshold size.

7. The memory system of claim 6, wherein the portion of the second set of data has a third data size equal to the threshold size.

8. The memory system of claim 5, wherein the controller is further configured such that the memory system: At least in part, the second set of data is invalidated by copying at least a portion of the second set of data to the first buffer.

9. The memory system of claim 1, wherein the controller configured to cause the memory system to clear the first set of data into the memory device is configured to cause the memory system to: The first set of data is written to the memory device with zero multi-plane page offset.

10. The memory system of claim 1, wherein the controller is further configured such that the memory system: Receive buffer clear command; and The second set of data is cleared into a temporary block of the memory device, at least in part, based on the buffer clear command.

11. The memory system of claim 1, wherein the threshold size is the product of the physical page size of the memory device and the number of planes of the memory device.

12. The memory system of claim 1, wherein the controller is further configured such that the memory system: The data is stored in a single buffer that includes the first buffer and the second buffer.

13. The memory system of claim 1, wherein the controller is further configured such that the memory system: The first portion of the data is stored in the first buffer; and The second portion of the data is stored in a second buffer that is separate from the first buffer.

14. The memory system of claim 1, wherein the controller includes the first buffer and the second buffer.

15. The memory system of claim 1, wherein the memory device includes a non-memory device.

16. A non-transitory computer-readable medium storing code, said code including instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: Receive a command to write data to a memory device, the data having a data transfer size; Whether to add the data to the first buffer, the second buffer, or a combination thereof is determined at least in part based on the data transfer size and the threshold size. The data is added to the first buffer, the second buffer, or a combination thereof, at least in part based on the determination, wherein the first buffer stores a first set of data and the second buffer stores a second set of data; and The first set of data is cleared into the memory device at least in part based on the first set of data satisfying the clear condition of the first buffer, wherein after the first set of data is cleared into the memory device at least in part based on the clear condition of the first buffer, the instruction, when executed by the processor of the electronic device, causes the electronic device to maintain the second set of data in the second buffer.

17. The non-transitory computer-readable medium of claim 16, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: At least a portion of the second set of data stored in the second buffer is copied to the first buffer, based at least in part on the second set of data satisfying the copy condition of the second buffer.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: At least in part, the second set of data is invalidated by copying at least a portion of the second set of data to the first buffer.

19. The non-transitory computer-readable medium of claim 16, wherein the instruction for clearing the first set of data into the memory device causes the electronic device to: The first set of data is written to the memory device with zero multi-plane page offset.

20. A method executed by a memory system, comprising: Receive a command to write data to a memory device of the memory system, the data having a data transfer size; Whether to add the data to the first buffer, the second buffer, or a combination thereof is determined at least in part based on the data transfer size and the threshold size. The data is added to the first buffer, the second buffer, or a combination thereof, at least in part based on the determination, wherein the first buffer stores a first set of data and the second buffer stores a second set of data; and The first set of data is cleared into the memory device at least in part based on the first set of data satisfying the clearing condition of the first buffer, wherein after the first set of data is cleared into the memory device at least in part based on the clearing condition of the first buffer, the second set of data is maintained in the second buffer.

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