Data transfer / testing circuit, method and storage device

Abstract

This disclosure relates to a data transmission / testing circuit, method, and storage device. A word line data readout module, when word lines in each memory bank are activated, reads data from multiple activated word lines in response to a read command, and then compresses the read data into parallel data of a first preset bit length according to a preset compression method. A clock control module generates a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal based on a preset clock signal, a read command, a compression mode enable signal, and a compression mode control signal. A data selection module compresses the parallel data into serial data of a second preset bit length according to the first-level clock control signal, compresses the second preset bit length serial data into serial data of a third preset bit length according to the second-level clock control signal, and compresses the third preset bit length serial data into serial data of a fourth preset bit length according to the third-level clock control signal, thereby reducing the size of the data transmission circuit and lowering data transmission power consumption.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and in particular to a data transmission / testing circuit, method, and memory. Background Technology

[0002] With the rapid development of semiconductor storage technology, the market has placed higher demands on the performance and reliability of semiconductor storage products, which means that semiconductor storage products need to minimize size and improve performance while ensuring low power consumption.

[0003] However, after traditional semiconductor storage products leave the factory, users generally find it difficult to efficiently read stored data from the semiconductor storage products and verify their performance.

[0004] Therefore, how to increase the functionality and improve the performance of semiconductor memory products while ensuring their small size and low power consumption has become an important research and development direction. Summary of the Invention

[0005] Therefore, it is necessary to provide a data transmission / test circuit, method, and memory to address the technical problems mentioned above in the background art.

[0006] A first aspect of this disclosure provides a data transmission circuit, including a word line data readout module, a clock control module, and a data selection module. The word line data readout module is connected to multiple memory banks in a memory, and is used to respond to a read command when word lines in each of the memory banks are activated, read data from multiple activated word lines, compress the read data into parallel data of a first preset number of bits according to a preset compression method, and then output it. The clock control module is used to generate a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal according to a preset clock signal, the read command, a compression mode enable signal, and a compression mode control signal. The data selection module is connected to both the clock control module and the word line data readout module, and is used to compress the parallel data into serial data of a second preset number of bits according to the first-level clock control signal, compress the second preset number of bits of serial data into serial data of a third preset number of bits according to the second-level clock control signal, and compress the third preset number of bits of serial data into serial data of a fourth preset number of bits according to the third-level clock control signal.

[0007] In the data transmission circuit of the above embodiments, the data reading efficiency is effectively improved by using the word line data read module to read parallel data of a first preset number of bits from the memory in parallel. Then, the clock control module generates a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal based on a preset clock signal, a read command, a compression mode enable signal, and a compression mode control signal. This causes the low-power data selection module to respond to the first-level clock control signal to compress the first preset number of bits of parallel data into a second preset number of bits of serial data, respond to the second-level clock control signal to compress the second preset number of bits of serial data into a third preset number of bits of serial data, and respond to the third-level clock control signal to compress the third preset number of bits of serial data into a fourth preset number of bits of serial data before outputting it. This reduces the size of the data transmission circuit, reduces the occupation of the data transmission ports of the memory, and lowers data transmission power consumption. By comparing the read data with the preset write data, abnormal storage bits in the memory can be determined based on the comparison result, improving the efficiency of performance testing of semiconductor memory devices. This increases the functionality and improves the performance of semiconductor memory products while ensuring their small size and low power consumption.

[0008] A second aspect of this disclosure provides a test circuit, including a data transmission circuit and a judgment unit as described in any of the embodiments of this disclosure. The data transmission circuit is used to convert data read from a memory pre-written with preset data into serial data of a fourth preset number of bits and then output it. The judgment unit is connected to the data transmission circuit and is used to compare the serial data of the fourth preset number of bits with the preset data, and to determine whether the memory has defects based on the comparison result. This improves the efficiency of performance testing of semiconductor memory devices, and increases the functionality of semiconductor memory products while ensuring that the semiconductor memory products are small in size and have low power consumption, thereby improving the performance of semiconductor memory products.

[0009] A third aspect of this disclosure provides a storage device including the test circuit described in any of the embodiments of this disclosure, which increases the functionality of the semiconductor storage product and improves its performance while ensuring that the semiconductor storage product has a small size and low power consumption.

[0010] A fourth aspect of this disclosure provides a data transmission method, comprising: when word lines in multiple memory banks are activated in a memory, controlling a word line data readout module to respond to a read command, reading data from multiple activated word lines, compressing the read data into parallel data of a first preset bit length according to a preset compression method, and then outputting the compressed data; controlling a clock control module to generate a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal according to a preset clock signal, the read command, a compression mode enable signal, and a compression mode control signal; controlling a data selection module to compress the parallel data into serial data of a second preset bit length according to the first-level clock control signal, compress the second preset bit length serial data into serial data of a third preset bit length according to the second-level clock control signal, and compress the third preset bit length serial data into serial data of a fourth preset bit length according to the third-level clock control signal. This embodiment reduces the size of the data transmission circuit, reduces the occupation of the data transmission ports of the memory, and reduces data transmission power consumption. By comparing the read data with the preset write data, abnormal storage bits in the memory can be determined based on the comparison results, thereby improving the efficiency of performance testing of semiconductor storage devices. This also increases the functionality and performance of semiconductor storage products while ensuring that they are small in size and have low power consumption.

[0011] A fifth aspect of this disclosure provides a testing method, comprising: pre-writing preset data into a memory; when word lines in multiple memory banks are activated in the memory, controlling a word line data readout module to respond to a read command, reading data from multiple activated word lines, and then compressing the read data into parallel data of a first preset bit length according to a preset compression method before outputting it; controlling a clock control module to generate a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal according to a preset clock signal, the read command, a compression mode enable signal, and a compression mode control signal; controlling a data selection module to compress the parallel data into serial data of a second preset bit length according to the first-level clock control signal, compress the second preset bit length serial data into serial data of a third preset bit length according to the second-level clock control signal, and compress the third preset bit length serial data into serial data of a fourth preset bit length according to the third-level clock control signal; comparing the fourth preset bit length serial data with the preset data, and determining whether the memory has a defect based on the comparison result. This embodiment improves the efficiency of performance testing of semiconductor memory devices, and can increase the functionality and improve the performance of semiconductor memory products while ensuring that the semiconductor memory products are small in size and have low power consumption. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figures 1-2 The diagram shows the circuit principle of the data transmission circuit provided in different embodiments of this disclosure.

[0014] Figure 3a This is a circuit diagram of the clock control unit in a data transmission circuit provided in one embodiment of the present disclosure;

[0015] Figure 3b for Figure 3a The diagram shows the timing sequence of the clock control unit.

[0016] Figure 4a This is a circuit diagram of a decoding unit in a data transmission circuit provided in one embodiment of the present disclosure;

[0017] Figure 4b for Figure 4a The diagram shows the timing sequence of the decoding unit.

[0018] Figure 5 This is a circuit diagram of a data transmission circuit provided in one embodiment of the present disclosure;

[0019] Figure 6a for Figure 5 A circuit diagram of the middle section of the multiplexer circuit;

[0020] Figure 6b for Figure 5 A circuit diagram of the middle part of the second-stage sub-selector and part of the third-stage sub-selector;

[0021] Figure 7 for Figure 5 A partial timing diagram of the data selection circuit;

[0022] Figure 8 This is a flowchart illustrating a data transmission method provided in one embodiment of the present disclosure;

[0023] Figure 9 This is a flowchart illustrating a testing method provided in one embodiment of the present disclosure.

[0024] Explanation of reference numerals in the attached figures:

[0025] 100. Data transmission circuit; 10. Word line data readout module; 20. Clock control module; 30. Data selection module; 31. First-level data selection sub-circuit; 32. Second-level data selection sub-circuit; 33. Third-level data selection sub-circuit; 21. Clock control unit; 22. Decoding unit; 211. Signal receiving circuit; 212. First delay unit; 213. Second delay unit; 214. Third delay unit; 215. Fourth delay unit; 216. Fifth delay unit; 217. Feedback unit; 221. 2-to-4 decoder; 222. Sixth delay unit; 223. Seventh delay unit; 311. First multiplexer circuit; 312. Second multiplexer circuit; 3111. First buffer unit; 3121. Second buffer unit. Detailed Implementation

[0026] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the specification of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. Additionally, certain terms used throughout the specification and following claims refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to elements. This document does not intend to distinguish between elements with different names but the same function. In the following description and embodiments, the terms “comprising” and “including” are used in an open-ended manner and should therefore be interpreted as “comprising, but not limited to…”. Similarly, the term “connection” is intended to express an indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection may be accomplished through a direct electrical connection or through an indirect electrical connection with other devices and connectors.

[0028] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0029] Please refer to Figure 1In one embodiment of this disclosure, a data transmission circuit 100 is provided, including a word line data readout module 10, a clock control module 20, and a data selection module 30. The word line data readout module 10 is connected to multiple memory banks in the memory. When a word line in each memory bank is activated, it responds to the read command RD CMD, reads data from multiple activated word lines, compresses the read data into parallel data Input_data of a first preset number of bits according to a preset compression method, and then outputs it. The clock control module 20 is used to select the data according to the preset clock signal CLK and the read command RD. The CMD, compression mode enable signal TPARA, and compression mode control signal SET generate a first-level clock control signal CLKST1, a second-level clock control signal CLKST2, and a third-level clock control signal CLKST3. The data selection module 30 is connected to the clock control module 20 and the word line data readout module 10. It is used to compress parallel data Input_data into serial data of a second preset bit length according to the first-level clock control signal CLKST1, compress the second preset bit length serial data into serial data of a third preset bit length according to the second-level clock control signal CLKST2, and compress the third preset bit length serial data into serial data DATA_PARAB of a fourth preset bit length according to the third-level clock control signal CLKST3. It can be understood that the fourth preset bit length is less than the third preset bit length, the third preset bit length is less than the second preset bit length, and the second preset bit length is less than the first preset bit length.

[0030] As an example, please continue to refer to Figure 1If the word line data readout module 10 is connected to all 16 memory banks (memory bank 0, memory bank 1, ..., memory bank 15), before executing the read command RD CMD, it first activates two word lines in each of the 16 memory banks, for a total of 32 word lines. Then, it controls the word line data readout module 10 to respond to the read command RD CMD, reading the data from each activated word line. The read data is then compressed into a first preset number of bits, such as 64 bits, of parallel data Input_data according to a preset compression method before being output. Each activated word line outputs 64 bits of data, and the 32 activated word lines output a total of 2048 bits of data. The word line data readout module 10 responds to the read command RD CMD. After CMD reads the data from each activated word line, it compresses the 2048 bits of read data into a first preset number of bits, such as 64 bits, of parallel data Input_data according to a preset compression method, and then outputs it. Because the word line data read module 10 reads the first preset number of bits of parallel data Input_data from the memory in parallel, the data read efficiency is effectively improved. Then, the clock control module 20 uses the preset clock signal CLK and the read command RD... The CMD, compression mode enable signal TPARA, and compression mode control signal SET generate a first-level clock control signal CLKST1, a second-level clock control signal CLKST2, and a third-level clock control signal CLKST3. This causes the low-power data selection module 30 to respond to the first-level clock control signal CLKST1 by compressing the first preset number of parallel data Input_data into a second preset number of serial data (e.g., 16 bits), respond to the second-level clock control signal CLKST2 by compressing the second preset number of serial data into a third preset number of serial data (e.g., 8 bits), and respond to the third-level clock control signal CLKST3 by compressing the third preset number of serial data into a fourth preset number of serial data DATA_PARAB before outputting it. This reduces the size of the data transmission circuit 100, reduces the occupancy of the memory's data transmission ports, and lowers data transmission power consumption. By comparing the serial data DATA_PARAB of the fourth preset bit with the preset data, abnormal storage bits in the memory can be determined based on the comparison result, thereby improving the efficiency of performance testing of semiconductor memory devices. This increases the functionality of semiconductor memory products and improves their performance while ensuring that the semiconductor memory products are small in size and have low power consumption.

[0031] As an example, please continue to refer to Figure 1The word line data reading module 10 includes a compression unit and multiple word line data reading units. Each word line data reading unit is configured such that its input end is connected to two memory banks and its output end is connected to the compression unit. When a word line in each memory bank is activated, it responds to the read command RD CMD, reads the data on the four activated word lines connected to it, and provides it to the compression unit. The compression unit is connected to each word line data reading unit and is used to compress the data provided by each word line data reading unit into parallel data Input_data of a first preset number of bits according to a preset compression method, and then outputs it to the data selection module 30. For example, the word line data readout module 10 may include eight word line data readout units. Each word line data readout unit is connected to two memory banks and a compression unit. After all 32 word lines connected to the eight word line data readout units are activated, the eight word line data readout units respond to the read command RD CMD, read the data on each activated word line, and provide it to the compression unit. The compression unit compresses the read data, such as 2048 bits, into a first preset number of bits, such as 64 bits, of parallel data Input_data according to a preset compression method and outputs it. Then, the low-power data selection module 30 compresses the 64 bits of parallel data Input_data into 4 bits of serial data DATA_PARAB and outputs it, thereby reducing the size of the data transmission circuit 100, reducing the occupation of the data transmission ports of the memory, and reducing the energy consumption of data transmission.

[0032] For example, please refer to Figure 2The data selection module 30 includes a primary data selection sub-circuit 31, a secondary data selection sub-circuit 32, and a tertiary data selection sub-circuit 33. The primary data selection sub-circuit 31 is connected to both the clock control module 20 and the word line data readout module 10. It is used to sample parallel data Input_data during the first state of the primary clock control signal CLKST1 and to intercept parallel data Input_data during the second state of the primary clock control signal CLKST1 to generate and output serial data Output1 with a second preset number of bits. The secondary data selection sub-circuit 32 is connected to both the clock control module 20 and the primary data selection sub-circuit 31. It is used to sample the data provided by the primary data selection sub-circuit 31 according to the secondary clock control signal CLKST2 to generate and output serial data Output2 with a third preset number of bits. The tertiary data selection sub-circuit 33 is connected to both the clock control module 20 and the secondary data selection sub-circuit 32. It is used to sample the data provided by the secondary data selection sub-circuit 32 according to the tertiary clock control signal CLKST3 to generate and output serial data DATA_PARAB with a fourth preset number of bits. In this embodiment, the data selection module 30 compresses the parallel data Input_data into serial data DATA_PARAB of the fourth preset bit length before outputting it, thereby reducing the size of the data transmission circuit, reducing the occupation of the data transmission port of the memory, and reducing the energy consumption of data transmission.

[0033] As an example, please continue to refer to Figure 2 The clock control module 20 includes a clock control unit 21 and a decoding unit 22. The clock control unit 21 is used to determine the clock signal CLK and the read command RD according to the preset clock signal CLK and the read command RD. The initial clock control signal CLKS is generated by CMD, the compression mode enable signal TPARA, and the compression mode control signal SET. The decoding unit 22 is connected to the clock control unit 21 and is used to generate a first-level clock control signal CLKST1, a second-level clock control signal CLKST2, and a third-level clock control signal CLKST3 according to the initial clock control signal CLKS. This controls the low-power data selection module 30 to compress the first preset number of parallel data Input_data into a second preset number of serial data Output1 in response to the first-level clock control signal CLKST1. The data selection module 30 compresses the second preset number of serial data Output1 into a third preset number of serial data Output2 in response to the second-level clock control signal CLKST2. The data selection module 30 compresses the third preset number of serial data Output2 into a fourth preset number of serial data DATA_PARAB in response to the third-level clock control signal CLKST3. This reduces the size of the data transmission circuit 100, reduces the occupation of the data transmission port of the memory, and reduces the energy consumption of data transmission.

[0034] For example, please refer to Figure 3aThe initial clock control signal CLKS includes the first sub-initial clock control signal CLKS. <0> Second Sub-Initial Clock Control Signal CLKS <1> Third Sub-Initial Clock Control Signal CLKS <2> and the fourth sub-initial clock control signal CLKS <3> The clock control unit 21 includes a signal receiving circuit 211, a first delay unit 212, a second delay unit 213, a third delay unit 214, a first NAND gate (Nand1), a second NAND gate (Nand2), a fourth delay unit 215, a fifth delay unit 216, and a feedback unit 217. The signal receiving circuit 211 is used to generate a data control signal C1 and a first sub-clock control signal clkc1 based on the received preset clock signal CLK, read command RD CMD, compression mode enable signal TPARA, and target feedback signal C8. The data control signal C1 includes a second preset number of continuously changing sub-data control signals. The first delay unit 212 is connected to the signal receiving circuit 211 and is used to generate a first intermediate clock control signal C3 based on the compression mode control signal SET, the sub-data control signal, and the first sub-clock control signal clkc1. The second delay unit 213 is connected to both the signal receiving circuit 211 and the first delay unit 212 and is used to generate a first intermediate clock control signal C3 based on the compression mode control signal SET, the second sub-data control signal, and the first sub-clock control signal clkc1. A sub-clock control signal clkc1 and a first intermediate clock control signal C3 generate a second intermediate clock control signal C4; a third delay unit 214 is connected to both the signal receiving circuit 211 and the second delay unit 213, and is used to generate a third intermediate clock control signal C5 based on the compression mode control signal SET, the first sub-clock control signal clkc1, and the second intermediate clock control signal C4; a first NAND gate Nand1 is configured such that its first input is connected to the first intermediate clock control signal C3, its second input is connected to the third intermediate clock control signal C5, and its output outputs the first sub-initial clock control signal CLKS. <0> The second NAND gate, Nand2, is configured such that its first input is connected to the third intermediate clock control signal C5, its second input is connected to the second intermediate clock control signal C4, and its output is the second sub-initial clock control signal CLKS. <1> The fourth delay unit 215 is connected to both the signal receiving circuit 211 and the third delay unit 214, and is used to generate the second sub-clock control signal clkc2 and the third sub-initial clock control signal CLKS based on the compression mode control signal SET, the first sub-clock control signal clkc1, and the third intermediate clock control signal C5. <2> The fifth delay unit 216 is connected to both the signal receiving circuit 211 and the fourth delay unit 215, and is used to generate the fourth sub-initial clock control signal CLKS based on the compression mode control signal SET and the second sub-clock control signal clkc2. <3> ;Feedback unit 217 is connected to signal receiving circuit 211, third delay unit 214, fourth delay unit 215 and fifth delay unit 216, and is used to control the signal according to the third intermediate clock control signal C5 and the third sub-initial clock control signal CLKS. <2> and the fourth sub-initial clock control signal CLKS <3> Generate the target feedback signal C8.

[0035] As an example, please continue to refer to Figure 3a The feedback unit 217 includes a first AND gate And1 and a first NOR gate Nor1. The first AND gate And1 is configured such that its first input is connected to the third sub-initial clock control signal CLKS. <2> The second input terminal is connected to the fourth sub-initial clock control signal CLKS. <3> The output terminal outputs the first initial feedback signal C7; the first NOR gate Nor1 is configured such that the first input terminal is connected to the first initial feedback signal C7, the second input terminal is connected to the third intermediate clock control signal C5, and the output terminal outputs the target feedback signal C8; the first initial feedback signal C7 and the third intermediate clock control signal C5 are processed by the first NOR gate Nor1 to generate the target feedback signal C8, so that the target feedback signal C8 is pulled low from the rising edge of the 13th cycle T0. Then the target feedback signal C8 and the read command RD CMD signal are processed by the second NOR gate Nor2 to generate the data control signal C1 and the first sub-clock control signal clkc1. The data control signal C1 includes a second preset number of continuously changing sub-data control signals. The signal receiving circuit 211 includes a second AND gate And2, a third AND gate And3, and a second NOR gate Nor2. The second AND gate And2 is configured to receive the read command RD CMD at its first input and the compression mode enable signal TPARA at its second input. The third AND gate And3 is configured to receive the compression mode enable signal TPARA at its first input, the preset clock signal CLK at its second input, and output the first sub-clock control signal clkc1 at its output. The second NOR gate Nor2 is configured to connect its first input to the output of the second AND gate And2, receive the target feedback signal C8 at its second input, and output the data control signal C1 at its output.

[0036] As an example, please continue to refer to Figure 3aThe first delay unit 212 includes a first flip-flop DFF0 and a second flip-flop DFF1. The first flip-flop DFF0 is configured to receive a data control signal C1 at its signal input terminal, receive a first sub-clock control signal clkc1 at its clock input terminal, and receive a compression mode control signal SET at its reset terminal, and is used to output a zeroth intermediate clock control signal C2. The second flip-flop DFF1 is configured to connect its signal input terminal to the signal output terminal of the first flip-flop DFF0, receive the first sub-clock control signal clkc1 at its clock input terminal, output a first intermediate clock control signal C3 at its signal output terminal, and receive the compression mode control signal SET at its reset terminal. The first intermediate clock control signal C3 is a delayed signal of the zeroth intermediate clock control signal C2. During the first state when the compression mode control signal SET is in the compression mode control signal SET, both the first flip-flop DFF0 and the second flip-flop DFF1 are set to 1. During the second state when the compression mode control signal SET is in the compression mode control signal SET, both the first flip-flop DFF0 and the second flip-flop DFF1 remain in their original states.

[0037] As an example, please continue to refer to Figure 3aThe second delay unit 213 includes a third flip-flop DFF2, which is configured such that its signal input is connected to the signal output of the second flip-flop DFF1, its clock input receives the first sub-clock control signal clkc1, its signal output outputs the second intermediate clock control signal C4, and its reset terminal receives the compression mode control signal SET. The third delay unit 214 can be configured to include a fourth flip-flop DFF3, which is configured such that its signal input is connected to the signal output of the third flip-flop DFF2, its clock input receives the first sub-clock control signal clkc1, its signal output outputs the third intermediate clock control signal C5, and its reset terminal receives the compression mode control signal SET. During the first state of the compression mode control signal SET, both the third flip-flop DFF2 and the fourth flip-flop DFF3 are set to 1; during the second state of the compression mode control signal SET, both the third flip-flop DFF2 and the fourth flip-flop DFF3 remain in their original states. The fourth delay unit 215 can be configured to include a fifth flip-flop DFF4, a first inverter Inv1, and a sixth flip-flop DFF5. The fifth flip-flop DFF4 is configured such that its signal input is connected to the signal output of the fourth flip-flop DFF3, its clock input receives the first sub-clock control signal clkc1, and its reset receives the compression mode control signal SET. The first inverter Inv1 is configured such that its input is connected to the signal output of the fifth flip-flop DFF4. The sixth flip-flop DFF5 is configured such that its signal input is connected to the second signal output of the sixth flip-flop DFF5, its clock input is connected to the output of the first inverter Inv1, its reset receives the compression mode control signal SET, and its first signal output outputs the third sub-initial clock control signal CLKS. <2> The second signal output terminal outputs the second sub-clock control signal clkc2; wherein, during the first state of the compression mode control signal SET, the fifth flip-flop DFF4 is set to 1, and the sixth flip-flop DFF5 remains in its original state; during the second state of the compression mode control signal SET, both the fifth flip-flop DFF4 and the sixth flip-flop DFF5 remain in their original states. The fifth delay unit 216 can be configured to include a seventh flip-flop DFF6, which is configured such that: its signal input terminal is connected to the second signal output terminal of the seventh flip-flop DFF6, its clock input terminal is connected to the second signal output terminal of the sixth flip-flop DFF5, its reset terminal receives the compression mode control signal SET, and its first signal output terminal outputs the fourth sub-initial clock control signal CLKS. <3> During the compression mode control signal SET in the first and second states, the seventh flip-flop DFF6 remains in its original state.

[0038] For example, please refer to Figure 3bIn step ①: The preset clock signal CLK has one cycle T0. After a delay of 4 cycles T0, the read command RDCMD signal is delayed. The third intermediate clock control signal C5, output by the fourth flip-flop DFF3, is transmitted to the first NOR gate Nor1, and then outputs the target feedback signal C8 via Nor1. In steps ② and ③: After a delay of 5 cycles T0, the read command RD CMD signal is transmitted to the fifth flip-flop DFF4. The fifth flip-flop DFF4 outputs the fourth intermediate clock control signal C6. The fourth intermediate clock control signal C6 is inverted by the first inverter Inv1 and transmitted to the sixth flip-flop DFF5. After being divided by two by the sixth flip-flop DFF5, the fifth intermediate clock control signal TSEL is generated. <0> The second sub-clock control signal clkc2 is divided by two by the seventh flip-flop DFF6 to generate the sixth intermediate clock control signal TSEL. <1> In step ④: the fifth intermediate clock control signal TSEL <0> and the sixth intermediate clock control signal TSEL <1> Under the action of the first AND gate And1, a first initial feedback signal C7 is generated. The first initial feedback signal C7 and the third intermediate clock control signal C5 are then processed by the first NOR gate Nor1 to generate a target feedback signal C8. This target feedback signal C8 is pulled low from the rising edge of the 13th cycle T0. Subsequently, the target feedback signal C8 and the read command RDCMD signal are processed by the second NOR gate Nor2 to generate a data control signal C1 and a first sub-clock control signal clkc1. The data control signal C1 includes a second preset number of continuously changing sub-data control signals. In steps ⑤ and ⑥, the fourth sub-initial clock control signal CLKS... <3> The sixth intermediate clock control signal TSEL from the output of the seventh flip-flop DFF6 <1> The third sub-initial clock control signal CLKS <2> The fifth intermediate clock control signal TSEL from the output of the sixth flip-flop DFF5 <0> In step ⑦, the second sub-initial clock control signal CLKS <1> The third intermediate clock control signal C5 and the second intermediate clock control signal C4 are generated through the second NAND gate Nand2. In step ⑧, the first sub-initial clock control signal CLKS... <0> The first intermediate clock control signal C3 and the third intermediate clock control signal C5 are generated by the first NAND gate Nand1.

[0039] For example, please refer to Figure 4aThe decoding unit 22 includes a 2-to-4 decoder 221, a sixth delay unit 222, and a seventh delay unit 223. The 2-to-4 decoder 221 is configured to receive the third sub-initial clock control signal CLKS at its first input. <2> The second input terminal receives the fourth sub-initial clock control signal CLKS. <3> The output terminal outputs the first-level clock control signal CLKST1<3:0>; the sixth delay unit 222 is configured to receive the first sub-initial clock control signal CLKS at its input terminal. <0> The output terminal outputs the secondary clock control signal CLKST2; the seventh delay unit 223 is configured to receive the second sub-initial clock control signal CLKS at its input terminal. <1> The output terminal outputs a three-level clock control signal CLKST3. This utilizes the low-power data selection module to respond to the first-level clock control signal CLKST1 to compress a first preset number of bits (e.g., 64-bit parallel data Input_data) into a second preset number of bits (e.g., 16-bit serial data Output1). Then, in response to the second-level clock control signal CLKST2, it compresses the second preset number of bits (e.g., 16-bit serial data Output1) into a third preset number of bits (e.g., 8-bit serial data Output2). Finally, in response to the third-level clock control signal CLKST3, it compresses the third preset number of bits (e.g., 8-bit serial data Output2) into a fourth preset number of bits (e.g., 4-bit serial data DATA_PARAB) before outputting it. This reduces the size of the data transmission circuit, reduces the occupancy of the memory's data transmission ports, and lowers data transmission power consumption.

[0040] For example, please refer to Figure 4bThe initial clock control signal CLKS includes the first sub-initial clock control signal CLKS. <0> Second Sub-Initial Clock Control Signal CLKS <1> Third Sub-Initial Clock Control Signal CLKS <2> and the fourth sub-initial clock control signal CLKS <3> The third-level clock control signal CLKST3 is the first sub-initial clock control signal CLKS. <0> The in-phase delayed signal; the second sub-initial clock control signal CLKS <1> It can be the first sub-initial clock control signal CLKS <0> The frequency divider signal, the third sub-initial clock control signal CLKS <2> It can be the second sub-initial clock control signal CLKS <1> The frequency divider signal, the fourth sub-initial clock control signal CLKS <3> It can be the third sub-initial clock control signal CLKS <2> The frequency divider signal; the primary clock control signal CLKST1 includes the primary sub-clock control signal CLKST1. <0> Level 1 sub-clock control signal CLKST1 <1> Level 1 sub-clock control signal CLKST1 <2> and the first-level sub-clock control signal CLKST1 <3> Level 1 sub-clock control signal CLKST1 <3> It can be the first-level sub-clock control signal CLKST1 <2> The delayed signal, the first-level sub-clock control signal CLKST1 <2> It can be the first-level sub-clock control signal CLKST1 <1> The delayed signal.

[0041] For example, please refer to Figure 5The primary data selection sub-circuit 31 includes N1 multiplexer circuits. Each multiplexer circuit is configured such that: its data input terminal is connected to N2 bits of parallel data Input_data; its clock input terminal is connected to the primary clock control signal CLKST1; and its output terminal outputs the corresponding bit of the primary selection data Output1. N2 = L1 / N1; L1 is the first preset number of bits, i.e., the total number of bits of parallel data Input_data; and N1, N2, and L1 are all positive integers. For example, the first preset number of bits is 64 bytes, and the second preset number of bits is 16 bytes. The primary data selection sub-circuit 31 includes a first multiplexer circuit, a second multiplexer circuit, ..., and an eighth multiplexer circuit, totaling eight multiplexer circuits. The first multiplexer circuit is configured such that: its data input terminal is connected to the first to eighth bits of parallel data Input_data, i.e., parallel data Input_data<7:0>; and its output terminal outputs the first bit of the primary selection data Output1. <0> and the 3rd data Output1 <2> The second multiplexer circuit is configured such that: the data input terminal connects to the 9th to 16th bits of the parallel data Input_data, i.e., the parallel data Input_data<15:8>; and the output terminal outputs the 9th bit of the first-level selection data Output1. <8> and the 11th bit of data Output1 <10> Similarly, the eighth multiplexer circuit is configured such that: the data input terminal connects to bits 57 to 64 of the parallel data Input_data, i.e., parallel data Input_data<63:56>, and the output terminal outputs bit 14 of the first-stage selection data Output1. <13> and the 16th bit of data Output1 <15> The clock input terminals of the eight multiplexer circuits all receive the first-level clock control signal CLKST1<3:0>. The eight multiplexer circuits compress the 8 bytes of data in the received parallel data into 2 bytes of first-level sub-serial data according to the first-level clock control signal CLKST1<3:0> and output them. Each first-level sub-serial data constitutes the second preset number of serial data Output1<15:0>.

[0042] As an example, please continue to refer to Figure 5The secondary data selection sub-circuit 32 includes a second-level sub-selector corresponding to each multiplexer circuit. The second-level sub-selector is configured such that its data input is connected to the data output of the corresponding multiplexer circuit, and its clock input is connected to a secondary clock control signal CLKST2. In response to the secondary clock control signal CLKST2, it compresses two bits at different positions in the second preset number of serial data into one byte of second-level sub-data and outputs it. Each second-level sub-data constitutes a third preset number of serial data bits. For example, the secondary data selection sub-circuit 32 includes eight second-level sub-selectors: mux321, mux322, ..., and mux328. The data input of the second-level sub-selector mux321 is connected to the output of the corresponding first multiplexer circuit, and the output of the second-level sub-selector mux321 outputs the first bit of the third preset number of secondary selection data (Output2). <0> The data input of the second-stage sub-selector mux322 is connected to the output of the fourth multiplexer circuit, and the output of the second-stage sub-selector mux322 outputs the second bit of the secondary selection data (Output2). <1> The data input of the second-stage sub-selector mux323 is connected to the output of the corresponding third multiplexer circuit, and the output of the second-stage sub-selector mux323 outputs the third bit of the secondary selection data (Output2). <2> The data input of the second-stage sub-selector mux324 is connected to the output of the corresponding seventh multiplexer circuit, and the output of the second-stage sub-selector mux324 outputs the fourth bit of the second-stage selection data (Output2). <3> The data input of the second-stage sub-selector mux325 is connected to the output of the corresponding second multiplexer circuit, and the output of the second-stage sub-selector mux325 outputs the 5th bit of the second-stage selection data (Output2). <4> The data input of the second-stage sub-selector mux326 is connected to the output of the corresponding sixth multiplexer circuit, and the output of the second-stage sub-selector mux326 outputs the 6th bit of the second-stage selection data (Output2). <5> The data input of the second-stage sub-selector mux327 is connected to the output of the corresponding fifth multiplexer circuit, and the output of the second-stage sub-selector mux327 outputs the 7th bit of the second-stage selection data (Output2). <6> The data input of the second-stage sub-selector mux328 is connected to the output of the corresponding eighth multiplexer circuit, and the output of the second-stage sub-selector mux328 outputs the 8th bit of the secondary selection data (Output2). <7> The clock inputs of all eight second-stage sub-selectors are connected to the second-stage clock control signal CLKST2.Taking the second-level sub-selector mux321 as an example, the specific working principle of each second-level sub-selector is illustrated. When the second-level clock control signal CLKST2 is in the first state, the second-level sub-selector mux321 samples and outputs the input signal of its first input terminal, and when the second-level clock control signal CLKST2 is in the second state, it samples and outputs the input signal of its second input terminal.

[0043] For example, please refer to Figure 6a , Figure 5 The first multiplexer circuit 311 may include eight first buffer units 3111. The non-inverting clock inputs of all eight first buffer units 3111 are connected to a first-level clock control signal CLKST1<3:0>, and the inverting clock inputs of all eight first buffer units 3111 are connected to the inverted signal of the first-level clock control signal CLKST1<3:0>. The data inputs of the eight first buffer units 3111 are sequentially connected to the corresponding bits of the parallel data Input_data. The outputs of the first four first buffer units 3111 are connected to a second-level sub-selector and output the first bit of the first-level selection data Output1, TDABK0, to the connected second-level sub-selector. The outputs of the last four first buffer units 3111 are connected to a second-level sub-selector and output the third bit of the first-level selection data Output1, TDABK2, to the connected second-level sub-selector. Similarly, Figure 5 The second multiplexer circuit 312 includes eight second buffer units 3121. The outputs of the first four second buffer units 3121 are connected and output the 9th bit of the first-level selection data Output1, TDABK8, to the connected second-level sub-selector. The outputs of the last four second buffer units 3121 are connected and output the 11th bit of the first-level selection data Output1, TDABK10, to the connected second-level sub-selector.

[0044] For example, please refer to Figure 6b , Figure 5 The second-level sub-selector mux321 is configured such that: the first input receives the first bit of the first-level selection data Output1, TDABK0; the second input is connected to the third bit of the first-level selection data Output1, TDABK2; and the output is connected to the first input of the corresponding third-level sub-selector mux331. Figure 5 The second-level sub-selector mux322 is configured such that: the first input receives the third bit of the first-level selection data Output1, TDABK2; the second input receives the eleventh bit of the first-level selection data Output1, TDABK10; and the output is connected to the second input of the corresponding third-level sub-selector mux331, which outputs the third bit of the fourth preset number of serial data, DATA_PARAB2. Figure 5 For details on the specific circuit connections and data flow of the other six second-level sub-selectors, please refer to the second-level sub-selector mux321 or the second-level sub-selector mux322. The specific details will not be repeated here.

[0045] As an example, please continue to refer to Figure 5 and Figure 6b If the fourth preset bit length is 4 bytes, the three-level data selection sub-circuit can include four third-level sub-selectors: mux331, mux332, mux333, and mux334. Each third-level sub-selector compresses two bits of data at different positions in the serial data of the third preset bit length into 1 byte of third-level sub-data according to the three-level clock control signal CLKST3 and outputs it. Each third-level sub-data constitutes the serial data DATA_PARAB<0:3> of the fourth preset bit length. For example, the second-level sub-selector mux321 outputs the first bit of the second-level selected data Output2, net0; the second-level sub-selector mux322 outputs the second bit of the second-level selected data Output2, net2; and the third-level sub-selector mux331, in response to the third-level clock control signal CLKST3, compresses the received data into one bit of serial data of the fourth preset number of bits. The bits of data output by the four third-level sub-selectors constitute the fourth preset number of bits of serial data DATA_PARAB<0:3>.

[0046] For example, please refer to Figure 7 ,by Figure 7The specific implementation principle of this disclosure embodiment is illustrated by taking the working timing diagram as an example, with the first-level sub-clock control signal CLKST1. <3> It can be the first-level sub-clock control signal CLKST1 <2> The delayed signal, the first-level sub-clock control signal CLKST1 <2> It can be the first-level sub-clock control signal CLKST1 <1> The delay signal. The second-level clock control signal CLKST2 can be a divided-by-two signal of the third-level clock control signal CLKST3. Each bit of the 16-bit first-level selection data Output1 includes 4 bits of parallel data Input_data. For example, the first bit of the primary selection data Output1, TDABK0, contains DATA0 (bit 1), DATA1 (bit 2), DATA2 (bit 3), and DATA3 (bit 4) from the parallel data Input_data; the second bit of the primary selection data Output1, TDABK1, contains DATA4 (bit 5), DATA5 (bit 6), DATA6 (bit 7), and DATA7 (bit 8) from the parallel data Input_data; the third bit of the primary selection data Output1, TDABK2, contains DATA8 (bit 9), DATA9 (bit 10), DATA10 (bit 11), and DATA11 (bit 12) from the parallel data Input_data; and the fourth bit of the primary selection data Output1, TDABK3, contains DATA12 (bit 13), DATA13 (bit 14), DATA14 (bit 15), and DATA15 (bit 16) from the parallel data Input_data. Each bit in the 8-bit secondary selection data Output2 contains 8 bits of parallel data Input_data. For example, the first bit, net0, in the 8-bit secondary selection data Output2 contains 8 bits of parallel data Input_data: DATA0 (bit 1), DATA8 (bit 9), DATA1 (bit 2), DATA9 (bit 10), DATA2 (bit 3), DATA10 (bit 11), DATA3 (bit 4), and DATA11 (bit 12). The second bit, net2, in the 8-bit secondary selection data Output2 contains 8 bits of parallel data Input_data: DATA4 (bit 5), DATA12 (bit 13), DATA5 (bit 6), DATA13 (bit 14), DATA6 (bit 7), DATA14 (bit 15), DATA7 (bit 8), and DATA15 (bit 16).The third bit DATA_PARAB2 in the fourth preset bit serial data DATA_PARAB contains DATA0 (bit 1), DATA4 (bit 5), DATA8 (bit 9), DATA12 (bit 13), DATA1 (bit 2), DATA5 (bit 6), DATA9 (bit 10), DATA13 (bit 14), DATA2 (bit 3), DATA6 (bit 7), DATA10 (bit 11), DATA14 (bit 15), DATA3 (bit 4), DATA7 (bit 8), DATA11 (bit 12), and DATA15 (bit 16) from the parallel data Input_data. Figure 5 The system includes four third-level sub-selectors, each corresponding to one bit of the output serial data DATA_PARAB<3:0>, and each bit of the serial data DATA_PARAB<3:0> corresponds to 16 bits of parallel data Input_data. Therefore, this embodiment converts 64 bits of parallel data Input_data<63:0> into 4 bits of serial data DATA_PARAB<3:0> for output.

[0047] This disclosure provides a test circuit, including a data transmission circuit and a judgment unit as described in any of the embodiments of this disclosure. The data transmission circuit is used to compress data read from a memory pre-written with preset data into serial data of a fourth preset number of bits and then output it. The judgment unit is connected to the data transmission circuit and is used to compare the serial data of the fourth preset number of bits with the preset data, and to determine whether there is a defect in the memory based on the comparison result. This improves the efficiency of performance testing of semiconductor memory devices, increases the functionality of semiconductor memory products while ensuring that the semiconductor memory products are small in size and have low power consumption, and improves the performance of semiconductor memory products. Furthermore, if faulty bits in semiconductor memory can be detected in time during the semiconductor memory design process or before the mass production of semiconductor memory, and faulty bits can be accurately repaired, the design efficiency, production yield, and reliability of semiconductor memory can be effectively improved.

[0048] As an example, you can set all bits of the preset data to be the same to reduce the complexity of designing the preset data. You can also detect abnormal data to determine whether there are faulty bits in the semiconductor memory, thereby improving the efficiency of the test and reducing the complexity of the test algorithm.

[0049] This disclosure provides a memory, including the test circuit in any of the embodiments of this disclosure, which increases the functionality and improves the performance of the semiconductor memory product while ensuring that the semiconductor memory product is small in size and low in power consumption; and can promptly detect faulty bits in the semiconductor memory during the semiconductor memory design process or before the semiconductor memory is mass-produced, so as to accurately repair the faulty bits and effectively improve the design efficiency, production yield and reliability of the semiconductor memory.

[0050] Please refer to Figure 8 This disclosure provides a data transmission method 200, including:

[0051] Step 202: When multiple word lines in the memory are activated, control the word line data reading module to respond to the read command, read the data on multiple activated word lines, compress the read data into parallel data of a first preset number of bits according to the preset compression method, and then output it.

[0052] Step 204: The clock control module generates a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal based on the preset clock signal, the read command, the compression mode enable signal, and the compression mode control signal.

[0053] Step 206: The control data selection module compresses parallel data into serial data of a second preset number of bits according to the first-level clock control signal, compresses the serial data of the second preset number of bits into serial data of a third preset number of bits according to the second-level clock control signal, and compresses the serial data of the third preset number of bits into serial data of a fourth preset number of bits according to the third-level clock control signal.

[0054] For details, please continue to refer to Figure 8When word lines in each memory bank are activated, the control word line data read module responds to the read command, reads data from multiple activated word lines (e.g., 2048 bits), and compresses the read data into a first preset number of bits (e.g., 64 bits) of parallel data according to a preset compression method before outputting it. Then, the control low-power data selection module responds to the first-level clock control signal CLKST1 to compress the first preset number of bits (e.g., 64 bits of parallel data Input_data) into a second preset number of bits (e.g., 16 bits of serial data Output1). Then, responding to the second-level clock control signal CLKST2, the second preset number of bits (e.g., 16 bits of serial data Output1) is compressed into a third preset number of bits (e.g., 8 bits of serial data Output2). Finally, responding to the third-level clock control signal CLKST3, the third preset number of bits (e.g., 8 bits of serial data Output2) is compressed into a fourth preset number of bits (e.g., 4 bits of serial data DATA_PARAB) before outputting it. This reduces the size of the data transmission circuit, reduces the occupation of the memory's data transmission ports, and lowers data transmission power consumption.

[0055] Please refer to Figure 9 This disclosure provides a testing method 300, including:

[0056] Step 302: Pre-written preset data into the memory;

[0057] Step 304: When multiple word lines in the memory are activated, control the word line data reading module to respond to the read command, read the data on multiple activated word lines, compress the read data into parallel data of a first preset number of bits according to the preset compression method, and then output it.

[0058] Step 306: The clock control module generates a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal based on the preset clock signal, the read command, the compression mode enable signal, and the compression mode control signal.

[0059] Step 308: The control data selection module compresses parallel data into serial data of a second preset number of bits according to the first-level clock control signal, compresses the serial data of the second preset number of bits into serial data of a third preset number of bits according to the second-level clock control signal, and compresses the serial data of the third preset number of bits into serial data of a fourth preset number of bits according to the third-level clock control signal.

[0060] Step 3010: Compare the serial data of the fourth preset bit with the preset data, and determine whether there is a defect in the memory based on the comparison result.

[0061] For details, please continue to refer to Figure 9When word lines are activated in each memory bank, the control word line data read module responds to the read command, reads data from multiple activated word lines (e.g., 2048 bits), and compresses the read data into a first preset number of bits (e.g., 64 bits) of parallel data according to a preset compression method before outputting it. Then, the control low-power data selection module responds to the first-level clock control signal CLKST1 to compress the first preset number of bits (e.g., 64 bits of parallel data Input_data) into a second preset number of bits (e.g., 16 bits of serial data Output1). Finally, responding to the second-level clock control signal CLKST2, the second preset number of bits (e.g., 16 bits of serial data Output1) is compressed into a third preset number of bits (e.g., 8 bits). The serial data Output2, in response to the third-level clock control signal CLKST3, compresses the third preset number of bits, such as 8 bits, of the serial data Output2 into a fourth preset number of bits, such as 4 bits, of the serial data DATA_PARAB before outputting it. This reduces the size of the data transmission circuit, reduces the occupation of the data transmission port of the memory, and reduces the energy consumption of data transmission. By comparing the content of the read data with the preset write data, the abnormal storage bits in the memory are determined based on the comparison result, which improves the efficiency of performance testing of semiconductor memory devices. While ensuring that the semiconductor memory product is small in size and low in energy consumption, the functionality of the semiconductor memory product is increased and the performance of the semiconductor memory product is improved.

[0062] It should be understood that, although Figure 8 , Figure 9 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 8 , Figure 9 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0063] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this disclosure can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0064] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.

[0065] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0066] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A data transmission circuit, characterized by include: The word line data reading module is connected to multiple storage banks in the memory. When a word line in each of the storage banks is activated, it responds to a read command, reads data from multiple activated word lines, compresses the read data into parallel data of a first preset number of bits according to a preset compression method, and then outputs it. The clock control module is used to generate a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal based on a preset clock signal, the read command, the compression mode enable signal, and the compression mode control signal. The data selection module is connected to both the clock control module and the word line data readout module. It is used to compress the parallel data into serial data of a second preset number of bits according to the first-level clock control signal, compress the serial data of the second preset number of bits into serial data of a third preset number of bits according to the second-level clock control signal, and compress the serial data of the third preset number of bits into serial data of a fourth preset number of bits according to the third-level clock control signal.

2. The data transmission circuit of claim 1, wherein, The data selection module includes: The primary data selection sub-circuit is connected to both the clock control module and the word line data readout module. It is used to sample the parallel data during the first state of the primary clock control signal and to intercept the parallel data during the second state of the primary clock control signal to generate and output serial data of the second preset number of bits. The secondary data selection sub-circuit is connected to both the clock control module and the primary data selection sub-circuit, and is used to sample the data provided by the primary data selection sub-circuit according to the secondary clock control signal, so as to generate and output the third preset number of serial data. The third-level data selection sub-circuit is connected to both the clock control module and the second-level data selection sub-circuit, and is used to sample the data provided by the second-level data selection sub-circuit according to the third-level clock control signal, so as to generate and output the fourth preset number of serial data.

3. The data transmission circuit of claim 2, wherein, The first preset bit length is 64 bytes; the second preset bit length is 16 bytes; the first-level data selection sub-circuit includes 8 multiplexer circuits; Each of the multiplexer circuits is used to compress 8 bytes of data in the parallel data into 2 bytes of first-level sub-serial data according to the first-level clock control signal and then output them. Each of the first-level sub-serial data constitutes the second preset number of serial data.

4. The data transmission circuit of claim 3, wherein, The third preset bit length is 8 bytes; the secondary data selection sub-circuit includes 8 secondary sub-selectors; Each second-level sub-selector is used to compress two bits of data at different positions in the second preset number of bits of serial data into 1 byte of second-level sub-data according to the second-level clock control signal and then output the second-level sub-data. Each second-level sub-data constitutes the third preset number of bits of serial data.

5. The data transmission circuit of claim 4, wherein, The fourth preset bit length is 4 bytes; the three-level data selection sub-circuit includes 4 third-level sub-selectors; The third-level sub-selector is used to compress two bits of data at different positions in the third preset number of bits of serial data into 1 byte of third-level sub-data according to the third-level clock control signal, and then outputs the third-level sub-data. Each of the third-level sub-data constitutes the fourth preset number of bits of serial data.

6. The data transmission circuit according to any one of claims 1 to 5, characterized in that, The clock control module includes: A clock control unit is used to generate an initial clock control signal based on the preset clock signal, the read command, the compression mode enable signal, and the compression mode control signal. The decoding unit, connected to the clock control unit, is used to generate the first-level clock control signal, the second-level clock control signal, and the third-level clock control signal based on the initial clock control signal.

7. The data transmission circuit of claim 6, wherein, The initial clock control signal includes a first sub-initial clock control signal, a second sub-initial clock control signal, a third sub-initial clock control signal, and a fourth sub-initial clock control signal; The clock control unit includes: A signal receiving circuit is used to generate a data control signal and a first sub-clock control signal based on the received preset clock signal, the read command, the compression mode enable signal and the target feedback signal. The data control signal includes a second preset number of continuously changing sub-data control signals. The first delay unit is connected to the signal receiving circuit and is used to generate a first intermediate clock control signal according to the compression mode control signal, the sub-data control signal and the first sub-clock control signal. The second delay unit is connected to both the signal receiving circuit and the first delay unit, and is used to generate a second intermediate clock control signal according to the compression mode control signal, the first sub-clock control signal and the first intermediate clock control signal. The third delay unit is connected to both the signal receiving circuit and the second delay unit, and is used to generate a third intermediate clock control signal according to the compression mode control signal, the first sub-clock control signal and the second intermediate clock control signal. The first NAND gate is configured such that: the first input terminal is connected to the first intermediate clock control signal, the second input terminal is connected to the third intermediate clock control signal, and the first sub-initial clock control signal is output at the output terminal. The second NAND gate is configured such that: the first input terminal is connected to the third intermediate clock control signal, the second input terminal is connected to the second intermediate clock control signal, and the output terminal outputs the second sub-initial clock control signal; The fourth delay unit is connected to both the signal receiving circuit and the third delay unit, and is used to generate the second sub-clock control signal and the third sub-initial clock control signal according to the compression mode control signal, the first sub-clock control signal and the third intermediate clock control signal. The fifth delay unit is connected to both the signal receiving circuit and the fourth delay unit, and is used to generate the fourth sub-initial clock control signal according to the compression mode control signal and the second sub-clock control signal. The feedback unit is connected to the signal receiving circuit, the third delay unit, the fourth delay unit, and the fifth delay unit, and is used to generate the target feedback signal based on the third intermediate clock control signal, the third sub-initial clock control signal, and the fourth sub-initial clock control signal.

8. The data transmission circuit of claim 7, wherein, The feedback unit includes: The first AND gate is configured such that: the first input terminal is connected to the third sub-initial clock control signal, the second input terminal is connected to the fourth sub-initial clock control signal, and the output terminal outputs the first initial feedback signal; The first NOR gate is configured such that: the first input is connected to the first initial feedback signal, the second input is connected to the third intermediate clock control signal, and the output outputs the target feedback signal.

9. The data transmission circuit of claim 7, wherein, The signal receiving circuit includes: The second AND gate is configured such that its first input is connected to the read command and its second input is connected to the compression mode enable signal. The third AND gate is configured such that: the first input terminal is connected to the compression mode enable signal, the second input terminal is connected to the preset clock signal, and the output terminal outputs the first sub-clock control signal; The second NOR gate is configured such that: the first input is connected to the output of the second AND gate, the second input is connected to the target feedback signal, and the output outputs the data control signal.

10. The data transmission circuit of claim 7, wherein, The first delay unit includes: The first trigger is configured such that: its signal input terminal is connected to the data control signal, its clock input terminal is connected to the first sub-clock control signal, and its reset terminal is connected to the compression mode control signal; The second flip-flop is configured such that: its signal input terminal is connected to the signal output terminal of the first flip-flop, its clock input terminal is connected to the first sub-clock control signal, its signal output terminal outputs the first intermediate clock control signal, and its reset terminal is connected to the compression mode control signal; During the first state of the compression mode control signal, both the first and second triggers are set to 1; during the second state of the compression mode control signal, both the first and second triggers remain in their original states.

11. The data transmission circuit of claim 10, wherein, The second delay unit includes: The third flip-flop is configured such that: its signal input terminal is connected to the signal output terminal of the second flip-flop; its clock input terminal is connected to the first sub-clock control signal; its signal output terminal outputs the second intermediate clock control signal; and its reset terminal is connected to the compression mode control signal. The third delay unit includes: The fourth flip-flop is configured such that: its signal input terminal is connected to the signal output terminal of the third flip-flop; its clock input terminal is connected to the first sub-clock control signal; its signal output terminal outputs the third intermediate clock control signal; and its reset terminal is connected to the compression mode control signal. During the first state of the compression mode control signal, both the third and fourth flip-flops are set to 1; during the second state of the compression mode control signal, both the third and fourth flip-flops remain in their original states.

12. The data transmission circuit of claim 11, wherein, The fourth delay unit includes: The fifth flip-flop is configured such that its signal input terminal is connected to the signal output terminal of the fourth flip-flop, its clock input terminal is connected to the first sub-clock control signal, and its reset terminal is connected to the compression mode control signal. The first inverter is configured such that its input is connected to the signal output of the fifth flip-flop; The sixth flip-flop is configured such that: its signal input terminal is connected to its second signal output terminal, its clock input terminal is connected to the output terminal of the first inverter, its reset terminal is connected to the compression mode control signal, its first signal output terminal outputs the third sub-initial clock control signal, and its second signal output terminal outputs the second sub-clock control signal. During the first state of the compression mode control signal, the fifth trigger is set to 1 and the sixth trigger remains in its original state. During the second state of the compression mode control signal, both the fifth and sixth triggers remain in their original states.

13. The data transmission circuit of claim 12, wherein, The fifth delay unit includes: The seventh flip-flop is configured such that its signal input terminal is connected to its second signal output terminal, its clock input terminal is connected to the second signal output terminal of the sixth flip-flop, its reset terminal is connected to the compression mode control signal, and its first signal output terminal outputs the fourth sub-initial clock control signal. During the first and second states of the compression mode control signal, the seventh trigger remains in its original state.

14. The data transmission circuit of claim 7, wherein, The decoding unit includes: The 2-4 decoder is configured such that: the first input terminal is connected to the third sub-initial clock control signal, the second input terminal is connected to the fourth sub-initial clock control signal, and the output terminal outputs the first-level clock control signal; The sixth delay unit is configured such that its input is connected to the first sub-initial clock control signal and its output is the second-level clock control signal. The seventh delay unit is configured such that its input is connected to the second sub-initial clock control signal and its output is the third-level clock control signal.

15. The data transmission circuit according to any one of claims 1 to 5, characterized in that, The word line data reading module includes a compression unit and multiple word line data reading units; The word line data reading unit is configured such that its input end is connected to two storage banks and its output end is connected to the compression unit. When a word line is activated in each of the storage banks, it responds to a read command, reads the data on the four activated word lines connected to it, and provides it to the compression unit. The compression unit is connected to each of the word line data readout units and is used to compress the data provided by each of the word line data readout units into parallel data of a first preset number of bits according to a preset compression method and then output it to the data selector.

16. A test circuit, characterized by include: The data transmission circuit according to any one of claims 1-15 is used to convert data read from a memory pre-written with preset data into serial data of a fourth preset number of bits and then output it. as well as The judgment unit, connected to the data transmission circuit, is used to compare the serial data of the fourth preset number of bits with the preset data, and to determine whether the memory has a defect based on the comparison result.

17. The test circuit of claim 16, wherein, All bits of the preset data are identical.

18. A memory device, comprising: include: The test circuit as described in claim 16 or 17.

19. A data transmission control method, characterized in that, include: When multiple word lines in the memory are activated, the control word line data reading module responds to the read command, reads the data from multiple activated word lines, and then compresses the read data into parallel data of a first preset number of bits according to a preset compression method before outputting it. The clock control module generates a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal based on a preset clock signal, the read command, the compression mode enable signal, and the compression mode control signal. The control data selection module compresses the parallel data into serial data of a second preset number of bits according to the first-level clock control signal, compresses the serial data of the second preset number of bits into serial data of a third preset number of bits according to the second-level clock control signal, and compresses the serial data of the third preset number of bits into serial data of a fourth preset number of bits according to the third-level clock control signal.

20. A testing method, characterized in that, include: Pre-written data is written into the memory; When multiple word lines in the memory are activated, the control word line data reading module responds to the read command, reads the data from multiple activated word lines, and then compresses the read data into parallel data of a first preset number of bits according to a preset compression method before outputting it. The clock control module generates a first-level clock control signal, a second-level clock control signal, and a third-level clock control signal based on a preset clock signal, the read command, the compression mode enable signal, and the compression mode control signal. The control data selection module compresses the parallel data into serial data of a second preset number of bits according to the first-level clock control signal, compresses the serial data of the second preset number of bits into serial data of a third preset number of bits according to the second-level clock control signal, and compresses the serial data of the third preset number of bits into serial data of a fourth preset number of bits according to the third-level clock control signal. The serial data of the fourth preset bit number is compared with the preset data, and the memory is determined to have a defect based on the comparison result.

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