A memory SEU accurate detection, data dynamic compression method and device

Abstract

The embodiment of the application relates to the field of semiconductor memory testing, and discloses a memory SEU accurate detection and data dynamic compression method and device, wherein the detection method comprises the following steps: setting test parameters and a fixed value, reading current data of basic storage units corresponding to each physical address, binding the current data, the physical address and an irradiation time stamp to obtain a current data group of each basic storage unit; comparing the current data of each basic storage unit with the fixed value bit by bit to obtain current flip data of each basic storage unit, including a positive flip bit number, a negative flip bit number and a total flip bit number, and respectively performing statistics according to a hierarchical structure of the memory to obtain hierarchical statistical data. The detection method and the data dynamic compression method disclosed by the application solve the problems of low detection precision and large data volume, improve the precision of detection data, and reduce the data volume.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory testing technology, and in particular to a method and apparatus for accurate detection of memory SEUs and dynamic data compression. Background Technology

[0002] In specialized fields such as aerospace and high-energy physics, memory, as a core storage component, is constantly exposed to single-event radiation environments, making it prone to single-event upsets (SETs). These SETs can cause data anomalies and directly threaten the operational stability of electronic devices. Therefore, the detection and analysis of single-event upsets in memory under simulated ground-based radiation environments is a crucial step in evaluating the radiation resistance of memory.

[0003] In single-event upset (SEU) detection, traditional methods only count the total number of flipped bits, lacking precise binding with the 24-bit physical address. Furthermore, they cannot distinguish between positive flips (0→1) and negative flips (1→0), making it difficult to trace the root cause of errors, locate weak units, or deeply analyze flip patterns, resulting in insufficient detection accuracy and dimensionality. In data transmission, data transmission and storage solutions face significant bottlenecks. Current mainstream technologies lack targeted dynamic compression algorithms, only able to simply count the total number of flips or upload scattered address data. Limited by transmission interface bandwidth, existing solutions can only achieve data transmission in low-rate testing scenarios, unable to match the massive flip data generated by reading and writing all physical addresses at full rates (e.g., 2400MT / s). To retain complete data to ensure evaluation accuracy, local storage using large-capacity hard drives is necessary, leading to high hardware procurement and maintenance costs, cumbersome data export, and low analysis efficiency. This severely restricts the efficient conduct of ground-based simulated irradiation tests and fails to meet the actual needs of engineering-level preliminary testing.

[0004] Therefore, improving the accuracy of single-event flip detection and accelerating data transmission are urgent problems to be solved in single-event flip detection. Summary of the Invention

[0005] The purpose of this invention is to provide at least one method and apparatus for accurate detection of memory SEU and dynamic data compression, which can at least solve the technical problems of low detection accuracy and low data transmission efficiency, and at least achieve high-accuracy detection effect, reduce data volume and improve data transmission efficiency.

[0006] To address the aforementioned technical problems, at least one embodiment of this application provides a method for accurate detection of SEU in a memory, comprising: setting test parameters and fixed values; reading the current data of the basic memory cell corresponding to each physical address; binding the current data, physical address, and irradiation timestamp to obtain the current data group of each basic memory cell; comparing the current data of each basic memory cell with the fixed value bit by bit to obtain the current flip data of each basic memory cell, including the number of positive flips, the number of negative flips, and the total number of flips; and performing statistics according to the hierarchical structure of the memory to obtain hierarchical statistical data.

[0007] At least one embodiment of this application also provides a dynamic compression method for memory SEU data, comprising: setting a compression unit level and a flip-over ratio threshold; dividing all physical addresses according to the set compression unit level; calculating the flip-over ratio of each compression unit based on the flip-over data corresponding to each compression unit; comparing the flip-over ratio with the flip-over ratio threshold; obtaining a simplified compression frame based on the comparison result; for the flip-over data frame that needs to be compressed, using a differential address encoding compression method to obtain differential address encoded data; for the flip-over state number corresponding to the differentially encoded address, using a flip-over state number adaptive combination compression method to obtain a combined compressed data unit; and combining the simplified compressed frame or differential address encoded data and the combined compressed data unit according to a set format to obtain compressed data.

[0008] At least one embodiment of this application also provides a memory SEU precise detection device, including a host computer and a test module. The test module is equipped with a slave program. The host computer is used to set detection parameters and perform human-computer interaction. The slave program is used to provide software support for the operation of the detection method and compression algorithm. The test module is used to parse parameters, coordinate the operation of each circuit within the module, store historical read data, provide a reference for dual-path comparison, and communicate with the host computer. It includes a main control circuit, a memory circuit, a DRAM buffer circuit, a USB communication circuit, and a power conversion circuit. The power conversion circuit is connected to the main control circuit, the memory circuit, the DRAM buffer circuit, and the USB communication circuit respectively, and is used to provide power to each circuit. The main control circuit is connected to the memory circuit, the DRAM buffer circuit, and the USB communication circuit respectively. The main control circuit acts as the core control center, coordinating the collaborative operation of each circuit, parsing parameters, and configuring the working status of each module. The memory circuit carries the memory device under test. The DRAM buffer circuit is used to reserve a storage area with the same capacity as the memory under test, store historical read data, and provide a reference for dual-path comparison. The USB communication circuit uses communication to provide a high-speed transmission channel.

[0009] At least one embodiment of this application also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the above-described method for accurate detection of memory SEU and / or the above-described method for dynamic compression of memory SEU data.

[0010] At least one embodiment of this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for accurate detection of memory SEU and / or a method for dynamic compression of memory SEU data.

[0011] The embodiments of this application provide a method and apparatus for accurate detection of single-event flips (SEUs) and dynamic data compression in memory. By employing dual-path comparison and address binding, combined with hierarchical statistical detection data, the method achieves accurate detection of single-event flip (SEU) numbers, thereby improving detection accuracy. The method also simplifies the data volume by employing a combination compression method of domain statistical optimization, differential address encoding, and flip state number adaptation, and enables real-time capture, accurate quantization, and efficient uploading of single-event flip data.

[0012] In some optional embodiments, the memory SEU accurate detection method further includes: comparing the current data of each basic memory cell with its previous data bit by bit to obtain the newly added flip data of each basic memory cell, including the newly added positive flip bits, the newly added negative flip bits, and the newly added total flip bits, and storing the current data as the previous data; binding the physical address, flip data, and irradiation timestamp; and performing statistics according to the hierarchical structure of the memory to obtain hierarchical statistical data; wherein the flip data includes the current flip data and the newly added flip data.

[0013] By comparing with historical data, newly added flipping data can be obtained, enabling the dynamic changes in flipping status. Hierarchical statistical quantification of flipping distribution characteristics is employed to capture both the cumulative flipping trend over irradiation time and the differences in flipping status, providing multidimensional data support for radiation resistance performance analysis.

[0014] In some optional embodiments, binding the physical address, flipped data, and irradiation timestamp includes: taking the time it takes for the basic storage unit corresponding to all physical addresses to complete one full read as a single time base unit; during the irradiation test, performing continuous integer counting for each cyclic read operation of all physical addresses; marking the irradiation timestamp M after each read of all physical addresses; and binding each irradiation timestamp as the core identifier of the irradiation time with the physical address and flipped data, wherein M is a positive integer greater than or equal to 1.

[0015] Binding irradiation time to physical address and flipped data ensures the correspondence between address traceability, compressed data, and irradiation time, while improving the effectiveness of radiation resistance assessment.

[0016] In some optional embodiments, comparing the flipping ratio with a flipping ratio threshold and obtaining a simplified compressed frame based on the comparison result includes: when the flipping ratio of the compression unit is greater than or equal to the flipping ratio threshold, determining that the radiation resistance of the compression unit does not meet the application requirements and that detailed flipping data does not need to be transmitted, and forming a simplified compressed frame using the comparison result marker bit, start address, end address, and cumulative flipping bits of the compression unit; when the flipping ratio of the compression unit is less than the flipping ratio threshold, determining that the detailed flipping data of the compression unit is the flipping data that needs to be compressed.

[0017] Setting a threshold for the percentage of flipped data allows for the differentiation of flipped data based on radiation resistance, thereby reducing the amount of flipped data.

[0018] In some optional embodiments, the differential address encoding compression method includes: arranging all physical addresses corresponding to each compression unit in ascending or descending order, calculating the address difference between adjacent physical addresses, and when the address difference is greater than or equal to 1, representing it as a continuous address or an interleaved address, using a continuous marker, a starting address, and a total difference as differential address encoding data; when the address difference is equal to 0, representing it as a non-contiguous address, using a non-contiguous marker bit and a complete physical address as differential address encoding data.

[0019] By distinguishing whether the physical addresses are consecutive, the amount of data that needs to be compressed is further reduced.

[0020] In some optional embodiments, the adaptive combination compression method for the number of flip states includes: compressing the number of flip states corresponding to each compression unit; determining the data density based on whether the number of flip bits exceeds a bit threshold; using the positive or negative sign of the number of flip bits as the flip type; simplifying the number of flip bits data according to the flip type to obtain a simplified flip number; grouping two compression units together, using the type and density markers of the two compression units as the first byte, the positive simplified flip number of the two compression units as the second byte, and the negative simplified flip number of the two compression units as the third byte, with the first byte, second byte, and third byte forming a 3-byte standardized combination compression data unit.

[0021] The flipped data corresponding to the encoded address is marked according to the flip state and density. The positive flipped data in the two sets of compression units is compressed using the marked bytes and flip simplified number of the two sets of compression units. The flip state of the two original data is represented by 3 bytes in a standardized manner, which is fully compatible with the 8-bit integer multiple transmission standard. While accurately preserving the flip information, the 64-bit original data transmission is abandoned, which greatly reduces the amount of data.

[0022] In some optional embodiments, the flipped reduction number includes: using half the number of bits of data in a single compressed unit as a bit threshold, when the number of flipped bits is less than or equal to the bit threshold, it is judged as low density, and the flipped reduction number is the flipped bit value in the case of low density; when the number of flipped bits is greater than the bit threshold, it is judged as high density, and the flipped reduction number is the difference between the number of bits of data in the basic storage unit and the flipped bit value in the case of high density.

[0023] By using density labeling, the flipped data is reduced from high-bit to low-bit, which greatly reduces the amount of data.

[0024] In some optional embodiments, the first byte includes: a positive flip type marker of the first compressed unit data, a negative flip type marker of the first compressed unit data, a positive flip density marker of the first compressed unit data, a negative flip density marker of the first compressed unit data, a positive flip type marker of the second compressed unit data, a negative flip type marker of the second compressed unit data, a positive flip density marker of the second compressed unit data, and a negative flip density marker of the second compressed unit data, totaling 8 bits.

[0025] Using one byte to mark the flag bits of two compression units reduces the number of flag bits required for each compression unit to be marked separately, thus reducing the amount of data.

[0026] In some optional embodiments, the second byte includes: the positive flip simplified number and the negative flip simplified number of the first compression unit data, set in order from low bit to high bit; the third byte includes: the positive flip simplified number and the negative flip simplified number of the second compression unit data, set in order from low bit to high bit.

[0027] Compression of the inverted data of two compression units using two bytes reduces the amount of data.

[0028] In some optional embodiments, the host computer includes: a human-computer interaction interface, a parameter configuration module, a data receiving and decompression module, and a storage and analysis module. The parameter configuration module is used to set parameters, including fixed values, compression unit levels, and flipping ratio thresholds. The data receiving and decompression module is used to receive the parameter settings and decompress the received values. The storage and analysis module is used to analyze the received test data. The human-computer interaction interface is used for visualization.

[0029] The host computer is used to communicate with the test module, and the human-machine interface provides functions such as parameter setting, which can support user-defined parameters and expand the application scope.

[0030] In some optional embodiments, the lower-level program includes: a memory interface module, a single-event upset detection module, a dynamic compression module, a data buffer module, a high-efficiency upload module, and a control module. The high-efficiency upload module is connected to the control module, the data buffer module, and the host computer, respectively. The single-event upset detection module is connected to the memory interface module, the dynamic compression module, and the control module, respectively. The memory interface module is also connected to the control module and the data buffer module. The data buffer module is connected to the memory interface module, the control module, the dynamic compression module, and the high-efficiency upload module, respectively. The memory interface module is used to follow the memory communication protocol and perform all physical address read and write operations according to the configuration parameters. In each loop, it first completes the reading of all physical address data, reads the data and transmits it to the single-event upset detection module in real time, and simultaneously collects the physical address and irradiation timestamp corresponding to the currently read data to provide basic data for binding the number of upset states with the address and time.

[0031] Installing a lower-level machine program in the test module enables the acquisition of test data and the compression of the data, thereby reducing testing costs and improving efficiency. Attached Figure Description

[0032] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, and these illustrative descriptions do not constitute a limitation on the embodiments.

[0033] Figure 1 This is a schematic diagram of a precision detection device provided in one embodiment of this application; Figure 2 This is a schematic diagram of the lower-level machine structure provided in one embodiment of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this application to help readers better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the various embodiments below is for the convenience of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0035] To facilitate understanding of the embodiments of this application, relevant information about the memory will be introduced first.

[0036] Taking DRAM memory as an example, it employs a three-dimensional hierarchical storage structure of Bank-Row-Column, which achieves precise field mapping with 24-bit physical addresses. The memory contains several independent storage banks, forming the top-level storage cell domain. Each bank is a complete independent storage array, internally composed of numerous intersecting storage rows and columns, with each intersection representing a basic storage cell (composed of 32 bits). The 24-bit physical address corresponds to the selection of the memory's Bank, the location of the Row address, and the location of the Column address, enabling unique addressing of all storage cells within the memory using a 24-bit address. A single 24-bit physical address corresponds to one basic storage cell, and one basic storage unit is 32 bits of data; that is, one 32-bit data can be written to or read from the memory at a time.

[0037] A full physical address refers to a single physical address that is 2 to the power of 24, which includes 16,777,216 single physical addresses.

[0038] To address the aforementioned technical problems of low accuracy, large data volume, and low data transmission efficiency in single-particle flip detection, this invention proposes a method and apparatus for accurate detection of memory SEUs and dynamic data compression. The implementation details of the accurate detection method for memory SEUs in this embodiment are described below. The following implementation details are provided for ease of understanding and are not essential for implementing this solution.

[0039] Example 1: This embodiment provides a method for accurate detection of the Memory Utility (SEU), which can be applied to electronic devices with communication, computing, and data storage capabilities, and includes: Set test parameters and fixed values, read the current data of the basic storage unit corresponding to each physical address, bind the current data, physical address, and irradiation timestamp to obtain the current data group of each basic storage unit; compare the current data of each basic storage unit with the fixed value bit by bit to obtain the current flip data of each basic storage unit, including the number of positive flips, the number of negative flips, and the total number of flips, which is used to analyze the cumulative flip trend of the total number of flips with irradiation time; compare the current data of each basic storage unit with its previous data bit by bit to obtain the newly added flip data of each basic storage unit, including the number of newly added positive flips, the number of newly added negative flips, and the number of newly added total flips, which is used to analyze the dynamic changes of the flip state, and store the current data as the previous data; the flip data of the basic storage unit corresponding to each physical address includes the current flip data and the newly added flip data.

[0040] The flipped data of all basic storage units forms the raw flipped data. Based on the raw flipped data, the flipped data of all basic storage units, the flipped data of each cell domain, and the flipped data of each basic storage unit are statistically analyzed to form a hierarchical statistical data report.

[0041] Positive flip bits refer to the number of bits in a data frame that change from logic low to logic high, while negative flip bits refer to the number of bits in a data frame that change from logic high to logic low. The total number of flip bits is equal to the sum of the positive and negative flip bits.

[0042] The current data of each basic storage unit is compared bit by bit with its previous data. This includes: in the first loop, reading the data frame of each basic storage unit and storing the read data frame in the reserved storage area as historical reference data for the next loop; in the subsequent second loop, after reading the data frame of each basic storage unit, comparing the second read data frame of each basic storage unit with the first read data frame of that basic storage unit, counting the newly added positive flip bits, newly added negative flip bits, and newly added total flip bits of each basic storage unit, and storing the second data frame in the reserved storage area, overwriting the first stored data frame, as the reference value for the third read data frame, and repeating this loop until the loop number is reached.

[0043] The flipped data in the statistical report includes the cumulative number of flipped bits, the cumulative number of forward flipped bits, the cumulative number of forward flipped bits, the cumulative number of newly added flipped bits, the cumulative number of newly added forward flipped bits, and the cumulative number of newly added forward flipped bits.

[0044] For each address's flipped data, the core flipped state number is extracted and combined with the irradiation timestamp to form a standardized raw flipped data frame, which is used to remove the raw data and retain the key indicators required for compression.

[0045] The standardized raw flipped data frame format is as follows: physical address field, cumulative positive flip bits, cumulative negative flip bits, and irradiation timestamp.

[0046] Among them, the cumulative positive flip bits and negative flip bits each account for one-quarter of the physical address bits, which are used to fully characterize the range of values ​​for the number of bits of data in the basic storage unit.

[0047] Binding the flipped data, physical address, and irradiation timestamp includes: using the time taken for all physical addresses to complete one full read as a single time base unit, continuously counting integers for each cyclic read operation of all basic storage units during the irradiation test, marking the irradiation timestamp M after each read of all basic storage units, and binding each irradiation timestamp as the core identifier of the irradiation time with the physical address and flipped data, where M is a positive integer greater than or equal to 1.

[0048] Specifically, the irradiation timestamps are incremented sequentially starting from 1. The first time all basic storage units are read is recorded as irradiation timestamp 1, the second time as irradiation timestamp 2, and so on. This irradiation timestamp is used as the core identifier of the irradiation time and is synchronously bound to the physical address, the cumulative positive flip bits, and the cumulative negative flip bits.

[0049] After each reading of all basic storage units, the flip data of each basic storage unit within the current physical address range is counted. At the same time, the corresponding incremented irradiation timestamp is embedded into the original flip data frame to achieve precise correlation and synchronous capture and upload of physical address, flip state number, and irradiation time. This is used to clearly trace the flip evolution law of each physical address unit of the memory under different irradiation durations, and to provide accurate time dimension data support for analyzing the cumulative change trend of single-particle flip with irradiation time and determining the radiation resistance time-dependent characteristics of the memory.

[0050] This embodiment employs a dual-path comparison mechanism of fixed value comparison and historical data comparison to accurately capture three-dimensional data of the number of flips, positive flips, and negative flips, and binds them to addresses. Combined with hierarchical statistics, it enables the traceability and quantification of flip data, solving the problems of single detection dimension and low accuracy of traditional methods.

[0051] Example 2: This embodiment of the memory SEU data dynamic compression method can be applied to electronic devices with communication, computing, and data storage capabilities, including: The compression unit hierarchy, flip-flop ratio threshold, and bit depth threshold are set. All physical addresses are divided according to the set compression unit hierarchy. For the original flip-flop data to be compressed, the flip-flop ratio of each compression unit is calculated. The flip-flop ratio is compared with the flip-flop ratio threshold, and a simplified compressed frame for each compression unit is obtained based on the comparison result. For the flip-flop data to be compressed, a differential address encoding compression method is used. Based on whether the physical addresses of the compression units are continuous, the differential address encoded data of the compression units is obtained. For the number of flip-flop states corresponding to the differentially encoded addresses, an adaptive combination compression method based on the number of flip-flop states is used to obtain a combined compressed data unit. The simplified compressed frame or differential address encoded data and combined compressed data unit of each compression unit are combined according to the set format to obtain the compressed data frame of each compression unit for transmission.

[0052] The compression unit level can be set, including: based on the physical address, you can choose Bank level, Row level, Column level or a combination of levels as the compression unit level, among which Bank level is the largest compression unit.

[0053] The flipping ratio refers to the ratio of the cumulative flipped bits within a compression unit to the sum of the bits of all physical addresses within the compression unit. The expression is as follows: (cumulative flipped bits within the compression unit / (number of physical addresses within the compression unit * number of bits per physical address)) * 100%.

[0054] The flipping ratio of each compression unit is compared with a flipping ratio threshold, and a simplified compressed frame is obtained based on the comparison result, including: When the flipping ratio of a compression unit is greater than or equal to the flipping ratio threshold, it is determined that the radiation resistance of the compression unit does not meet the application requirements, and there is no need to transmit detailed flipping data, thus forming a simplified compression frame; when the flipping ratio of a compression unit is less than the flipping ratio threshold, it is determined that the detailed flipping data of the compression unit is the flipping data frame that needs to be compressed.

[0055] For flipped data frames that need to be compressed, differential address encoding compression is used for address compression. Based on whether the physical addresses of the compression units are continuous, differential address encoded data is obtained, including: arranging all physical addresses of the compression unit in ascending or descending order, calculating the address difference between adjacent physical addresses, and when the address difference is greater than or equal to 1, it is represented as a continuous address or an interleaved address, with the starting address and the total difference used as differential address encoded data; when the address difference is equal to 0, it is represented as a non-contiguous address, and complete address data needs to be transmitted, i.e., complete address data is not compressed.

[0056] For the number of flip states corresponding to the address after differential encoding, an adaptive combined compression method based on the number of flip states is adopted to obtain a combined compressed data unit. This includes comparing the positive or negative flip number of the compressed unit with a bit threshold, and determining the density of the positive or negative flip number based on the comparison result. When the number of flip states is less than or equal to the bit threshold, it is considered low density, and the simplified flip number is the original flip value. When the number of flip states is greater than the bit threshold, it is considered high density, and the simplified flip number is the difference between the number of bits in the compressed unit and the original flip value. After simplification, the flipped data is compressed.

[0057] Grouping the flip state counts corresponding to two compression units into a single group, extract the density and flip simplification number of each compression unit. Then, based on the flip type and density of each compression unit, integrate the marker bits of this group of data in a fixed order from low to high bits. The marker bit is the first byte, and the rule is as follows: Positive flip type marker of the first compression unit → Negative flip type marker of the first compression unit → Positive flip density marker of the first compression unit → Negative flip density marker of the first compression unit → Positive flip type marker of the second compression unit → Negative flip type marker of the second compression unit → Positive flip density marker of the second compression unit → Negative flip density marker of the second compression unit.

[0058] The inverted simplified numbers of each compression unit within the group are integrated in a fixed order from the least significant bit to the most significant bit, resulting in 1 byte for each compression unit and a total of 2 bytes.

[0059] Specifically, the second byte is the flipped and simplified number of the first compression unit: The positive flip reduction number of the first compression unit + the negative flip reduction number of the first compression unit.

[0060] The third byte is the flipped and simplified number of the second compression unit: The positive flip reduction number of the second compression unit + the negative flip reduction number of the second compression unit.

[0061] The data is integrated according to the order of the first byte flag bit, the second byte, and the third byte to obtain a standardized combined compressed data of 3 bytes. The standardized combined compressed data can completely represent the positive and negative flip information of the two compression units, and it is in an 8-bit integer multiple format, which can be directly connected to the transmission process for data transmission.

[0062] Simplified compressed frames or differential address encoded data and standardized combined compressed data are encapsulated in a unified format to obtain compressed inverted data.

[0063] The compressed flip data and irradiation timestamps are combined into a data frame to obtain all the detection data of single-particle flip.

[0064] This embodiment processes data using a three-level hybrid compression strategy, compressing each set of inverted data into a non-redundant transmission format. Combined with domain statistical optimization and differential address encoding, it overcomes the bottleneck of full-rate test data transmission. This significantly reduces the transmission volume and avoids the high-cost solution of local storage on large-capacity hard drives.

[0065] While adhering to the 8-bit integer multiple transmission standard, each set of flipped data is compressed into a non-redundant transmission format. By combining domain statistical optimization and differential address encoding, the bottleneck of full-rate test data transmission is broken through, the compression ratio is significantly improved, and it is compatible with industry standards.

[0066] The compressed test data significantly reduces the amount of data transmitted.

[0067] Example 3: Another embodiment of this application relates to a memory SEU precise detection device. The implementation details of this memory SEU precise detection device are described below. The following implementation details are provided for ease of understanding and are not essential for implementing this solution. A schematic diagram of this memory SEU precise detection device can be seen as follows: Figure 1 As shown, it includes: a host computer and a test module.

[0068] The test module includes: a main control circuit, a memory circuit, a DRAM buffer circuit, a USB communication circuit, and a power conversion circuit. The power conversion circuit is connected to the main control circuit, memory circuit, DRAM buffer circuit, and USB communication circuit to provide power to each circuit. The main control circuit is connected to the memory circuit, DRAM buffer circuit, and USB communication circuit. As the core control center, the main control circuit coordinates the collaborative work of each circuit, analyzes parameters, and configures the working status of each module. The memory circuit carries the memory device under test. The DRAM buffer circuit is used to reserve a storage area with the same capacity as the memory device under test to store historical read data and provide a reference for dual-path comparison. The USB communication circuit uses communication to provide a high-speed transmission channel.

[0069] After the test module is powered on, the main control circuit loads the lower-level machine program to complete the self-test of each circuit and parameter initialization to adapt to the 24-bit address and 32-bit data width.

[0070] Specifically, in one embodiment of this application, the memory device is adapted to a 24-bit address width and a 32-bit data width, and adopts the USB 3.0 protocol.

[0071] The host computer includes: a human-computer interaction interface, a parameter configuration module, a data receiving and decompression module, and a storage and analysis module. The parameter configuration module is used to set parameters, including fixed values, cell domain levels, and flipping percentage thresholds. The data receiving and decompression module is used to receive the parameter settings and decompress the received values. The storage and analysis module is used to analyze the received test data. The human-computer interaction interface is used for visualization.

[0072] After the device is powered on, the host computer is used to configure the detection parameters and compression parameters. The detection parameters include: 32-bit fixed comparison value, 24-bit address range, read and write rate, etc. The compression parameters include: cell domain level, flip ratio threshold, etc., and the test parameters are sent to the test module.

[0073] like Figure 2 As shown, the lower-level program includes: a memory interface module, a single-particle flip detection module, a dynamic compression module, a data buffer module, a high-efficiency upload module, and a control module, providing software support for the operation of the detection method and compression algorithm.

[0074] The high-efficiency upload module is connected to the control module, the data buffer module, and the host computer.

[0075] The single-particle flip detection module is connected to the memory interface module, the dynamic compression module, and the control module, respectively.

[0076] The memory interface module is also connected to the control module and the data buffer module.

[0077] The data buffer module is connected to the memory interface module, control module, dynamic compression module, and high-efficiency upload module, respectively.

[0078] The memory interface module is used to follow the memory communication protocol and perform all physical address read and write operations according to the configuration parameters. In each loop, it first completes the reading of 32-bit data of all physical addresses, reads the data and transmits it to the single particle flip detection module in real time. At the same time, it synchronously collects the 24-bit physical address and irradiation timestamp corresponding to the currently read data, providing basic data for binding the flip state number with address and time. The physical address is mapped to the 24-bit address field of Bank / Row / Column, and the irradiation timestamp is calculated by the system clock count.

[0079] The single-particle flip detection module is used to initiate dual-path synchronous comparison and accurately capture three-dimensional flip data.

[0080] The dynamic compression module adopts a three-level hybrid compression strategy of "simplified compression frame or differential address encoding + standardized combined compression data". It designs a combined compression scheme for the number of flip states with a data width that is an integer multiple of 8 bits, adapts to the industry's 8-bit integer multiple transmission standard, and generates simplified compression frames, differential address encoded data, and combined compression data units to maximize the compression ratio while ensuring the effectiveness of radiation resistance assessment.

[0081] It is worth mentioning that all modules involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0082] Example 4: Another embodiment of this application is a detailed description of a method for accurate detection of a memory SEU and a method for dynamic data compression.

[0083] In this embodiment, the memory has a 24-bit physical address and the basic storage unit has a 32-bit data width. The basic storage unit is used as a compression unit for illustration. The other structures are similar and will not be described in detail.

[0084] In the precise detection method, a dual-path approach is adopted, which compares the data read from the memory with fixed values ​​and with historical data respectively. This simultaneously achieves precise binding between the 24-bit physical address and the number of flip states. A hierarchical statistical approach is used to quantify the flip distribution characteristics, which not only captures the cumulative flip trend over irradiation time, but also distinguishes the differences in flip states, providing multi-dimensional data support for radiation resistance performance analysis.

[0085] The number of flip states includes positive flip bits and negative positive flip bits.

[0086] Comparison of data read from memory with a fixed value: Users can customize the 32-bit fixed value, address bit width, and data bit width through the host computer. The 32-bit fixed value, such as 0x55555555, 0xAAAAAAAA, 0xFFFFFFFF, 0x00000000, etc., serves as a reference benchmark for long-term cumulative flip-over trends. During memory irradiation, the main control circuit reads the memory data in real time and compares it with this fixed value to calculate the number of flip-over bits. Therefore, it is a reference benchmark value for comparison.

[0087] When the address width is 24 bits, the covered address range is 0x000000-0xFFFFFF. A 32-bit data width means that a single address can store 32 bits of data.

[0088] Flip state definition: Positive flip bit (from 0 to 1) - the number of bits in 32-bit data that change from logic low to logic high; Negative flip bit (from 1 to 0) - the number of bits in 32-bit data that change from logic high to logic low; Total flip bit = positive flip bit + negative flip bit, and the maximum value of the total flip bit is 32.

[0089] Hierarchical statistical dimensions: First level: Number of flip states for all addresses, including: total number of flip bits for all addresses / total number of positive flip bits for all addresses / total number of negative flip bits for all addresses.

[0090] The first layer counts the number of flips in all basic memory cells across the entire memory, distinguishing between positive and negative flips; the total number of physical address flips (total number of memory flips) = positive flips + negative flips. The second layer is the number of flip states of the cell field, which is based on the 24-bit address. The cell field refers to the bank and / or row and / or column, including: the number of flips of the cell field / the number of positive flips of the cell field / the number of negative flips of the cell field.

[0091] Statistical analysis at the cell domain level provides a detailed count of the number of flips in different banks. For example, if a memory has four banks, the total number of flips in banks 0 / 1 / 2 / 3, as well as the number of positive and negative flips in banks 0 / 1 / 2 / 3, can be calculated. It can also precisely count the total number of flips, the number of positive flips, and the number of negative flips in a bank's rows or columns. Cell domain-level statistics enable precise analysis of the irradiation sensitivity of each cell domain.

[0092] The third layer consists of the number of flip states of a basic storage unit, i.e., a single physical address, including: the number of flips of a single physical address / the number of positive flips of a single physical address / the number of negative flips of a single physical address.

[0093] From the perspective of basic storage units, the basic storage unit corresponding to a single physical address consists of 32 bits, which can accurately count the total number of flips, positive flips, and negative flips of the smallest storage unit of the memory.

[0094] This application allows users to configure the above three levels of statistics themselves.

[0095] Specifically, the detection method includes the following steps: S1. Initialize and configure parameters; S2, Read memory data and corresponding physical address; S3. Use a dual-path comparison method to obtain the number of flipped states; S4. Bind the toggle state number to a 24-bit address; S5. Perform hierarchical statistics on the flipped data to generate hierarchical statistical reports.

[0096] In step S1, after the system is powered on, the host computer sends out test parameters, including a 32-bit fixed value (such as 0x55555555), a 24-bit memory address range (0x000000-0xFFFFFF), read / write rate, and number of loop reads. The FPGA main control module parses the parameters and configures the working status of each module. The DRAM buffer circuit is initialized, adapted to the 32-bit data width, and a storage area consistent with the capacity of the memory under test is reserved for caching historical read data.

[0097] In step S2, the memory interface module follows the memory communication protocol and performs all physical address read / write operations according to the configuration parameters: Each loop first completes the reading of all 32-bit physical address data, and the read data is transmitted to the single-particle flip detection module in real time; simultaneously, it synchronously acquires the 24-bit physical address and irradiation timestamp (converted from system clock count) corresponding to the currently read data, providing basic data for binding the flip state number with address and time. The 24-bit physical address maps Bank / Row / Column to a 24-bit address field, and the irradiation timestamp is calculated based on the system clock count.

[0098] In step S3, the single-particle flip detection module initiates a dual-path synchronous comparison, the dual paths including: Path 1, Comparison with fixed values: Compare the 32-bit data in the basic storage unit corresponding to all physical addresses read this time with the preset 32-bit fixed values ​​bit by bit, count the number of positive flips (0→1) and negative flips (1→0) in each basic storage unit, and calculate the total number of flips to analyze the cumulative flip trend with irradiation time. Path Two: Comparison with Historical Data in the Reserved Area: First, after the first loop of data reading, all 32 bits of data from each basic storage unit are directly stored in the reserved area of ​​the DRAM buffer circuit as historical reference data for the next loop. After the second loop of data reading, the 32 bits of data read in the second loop are compared bit by bit with the 32 bits of data from the previous loop cached in the DRAM buffer circuit. The number of newly added positive flip bits and the number of newly added negative flip bits for each basic storage unit are counted, and the total number of newly added flip bits is calculated to analyze the dynamic changes in the flip state. At the same time, the 32 bits of data read from the basic storage unit in the second loop are stored in the reserved area of ​​the DRAM buffer circuit, overwriting the original data, and used as the reference value for the third loop of 32 bits of data for comparison. This process is repeated in sequence.

[0099] In step S4, all flipped data detected by dual-path comparison is bound and encapsulated in units of "single physical address": each basic storage unit data corresponds to a flip record, which includes a 24-bit physical address field, cumulative positive flip bit length (6 bits, maximum value 32), cumulative negative flip bit length (6 bits, maximum value 32), newly added positive flip bit length (6 bits), newly added negative flip bit length (6 bits), and a 24-bit irradiation timestamp, forming a standardized raw flipped data frame. The format of the standardized raw flipped data frame is: 24-bit address field + 6-bit cumulative positive flip bit length + 6-bit cumulative negative flip bit length + 6-bit newly added positive flip bit length + 6-bit newly added negative flip bit length + 24-bit irradiation timestamp.

[0100] In step S5, statistics are performed based on the original flipped data frame according to a preset hierarchy: 1. Total cumulative number of flips / positive flips / negative flips in all basic storage units; Total newly added number of flips / positive flips / negative flips in all basic storage units; 2. Cumulative number of flipped bits / positive number of flipped bits / negative number of flipped bits for each cell field (Bank / Row / Column); newly added number of flipped bits / positive number of flipped bits / negative number of flipped bits; 3. Maximum cumulative number of flips / positive flips / negative flips in a single basic storage unit.

[0101] A hierarchical statistical report is generated to provide a basis for judgment in subsequent dynamic compression algorithms.

[0102] The detection method adopted in this application has high accuracy and comprehensive dimensions: it is optimized for 24-bit address and 32-bit data bit width, and the dual-path comparison mechanism accurately captures three-dimensional data of the number of flips, positive flips, and negative flips. 24-bit address binding, 24-bit irradiation timestamp binding, and hierarchical statistics enable the traceability and quantification of flip data, solving the problems of single detection dimensions and low accuracy of traditional methods.

[0103] Flipped data dynamic compression method: A three-level hybrid compression strategy of "simplified compressed frame or differential address encoding + standardized combined compressed data" is adopted. A combined compression scheme is designed for the number of flip states (6 bits each for positive and negative flip states) of 32-bit data width, which is compatible with the industry's 8-bit integer multiple transmission standard, maximizing the compression ratio while ensuring the effectiveness of radiation resistance assessment.

[0104] First, the percentage of single-particle flips is counted according to the preset storage basic units divided by 24-bit addresses to determine whether the threshold has been reached. If the threshold has not been reached, fine-grained compression is performed, including differential address encoding and flip state number combination compression to retain detailed flip information. If the threshold has been reached, the transmission is simplified, including address range and total number of errors, to remove redundant data. Finally, the data is uploaded efficiently through the USB 3.0 channel, achieving a triple balance of "precise transmission, standard adaptation, and efficiency improvement".

[0105] Compression unit level: Supports user customization based on 24-bit address, and can select Bank level (largest compression unit), Row level (medium compression unit), Column level (smallest compression unit), basic storage unit level (smallest compression unit) or combined level (such as Bank+Row level). Flipping percentage threshold: 50% by default, can be configured by the user via host computer, ranging from 10% to 90%, and the flipping percentage is defined as "cumulative flipping bits in basic storage unit / (number of compressed unit addresses × 32 bits) × 100%"; Simplified data transmission: 24-bit start address + 24-bit end address + 32-bit cumulative flip bits; Flip state number compression parameters: positive flip bit number / negative flip bit number each occupy 6 bits, of which 4 bits are data bits, 1 bit is flip type flag, 1 bit is density flag, the maximum value corresponding to 6 bits is 32, half of 32 bits is used as density threshold, and density flag occupies 1 bit.

[0106] When the number of flip states is ≤16, it is low density and marked with 0. The flip reduction number is the original flip value. When 16 < number of flip states ≤32, it is high density. The flip reduction number is the difference between the number of bits of the compressed unit and the original flip value.

[0107] Specifically, it includes the following steps: A1. Divide the compression unit into basic storage units and count the number of flip states of each basic storage unit; A2. Based on the flipping ratio and the flipping ratio threshold, determine whether the flipped data in the basic storage unit needs to be compressed; A3. For the flipped data that needs to be compressed, determine the density based on the flipping threshold and the number of flipped bits, and simplify the number of flipped bits based on the density to obtain the flipped simplified number. A4. Compress using differential address encoding to obtain differential address encoded data; A5. Combine and compress the number of flipped states to obtain standardized combined compressed data; A6. Encapsulate simplified compressed frames or differential address encoded data and standardized combined compressed data in a unified format to obtain compressed inverted data; A7. Combine the compressed flip data and irradiation timestamp into a data frame to obtain all detection data of single-particle flip, and upload all detection data to the host computer.

[0108] In step A1, the dynamic compression module receives the original flipped data frame and the hierarchical statistical report, and divides all 24-bit physical address ranges into compression units based on the user-preset basic storage units; for each compression unit, the flipping percentage R is calculated as R = ((cumulative flipped bits in the compression unit) / (number of addresses in the compression unit × 32)) × 100%.

[0109] In step A2, determine whether the data in each basic storage unit needs to be compressed: When R ≥ preset threshold (default 50%): It is determined that the radiation resistance of the basic storage unit does not meet the application requirements, and there is no need to transmit detailed flip data. Only the 24-bit start address, 24-bit end address, and 32-bit cumulative flip number of the basic storage unit are stored, and the "simplified transmission flag" is set to 1, occupying 1 bit, to form a simplified compressed frame.

[0110] The simplified compressed frame format is: 1 bit flag + 24 bits start address + 24 bits end address + 32 bits cumulative flip bits.

[0111] When R < preset threshold: it is determined that the basic storage unit needs to retain detailed flipped data, and the detailed flipped data that needs to be retained enters the compression process.

[0112] In step A3, the original flipped data to be compressed is compressed. The positive flip bit / negative flip bit of the 32-bit data in a single basic storage unit ranges from 0 to 32, with the midpoint 16 as the threshold. When the flip bit is ≤16, it is judged as low density, the density is marked as 0, occupying 1 bit, and the flip reduction number is the original flip number. When 17 < flip bit ≤32, it is judged as high density, the density is marked as 1, occupying 1 bit, and the flip reduction number is the difference between the basic storage unit bit 32 and the original flip number. Under both densities, the flip reduction number ranges from 0 to 16.

[0113] In step A4, the original flipped data frames to be compressed are sorted in ascending order by 24-bit address using bubble sort within the FPGA, with a delay of ≤8 clock cycles. The difference between adjacent addresses ΔAddr is calculated: ΔAddr = current address - previous address. When ΔAddr≥1, it indicates a continuous address or a spaced address: only the starting address and the total difference are transmitted. The total difference = the last continuous address - the starting address. The differential address encoding data format is "1-bit continuous tag (1) + 24-bit starting address + 24-bit total difference", replacing N independent 24-bit address fields. When ΔAddr=0, it indicates a non-contiguous address: transmit the complete 24-bit address, and the differential address encoding data format is "1-bit non-contiguous flag (0) + 24-bit address".

[0114] In step A5, for the number of flip states corresponding to the encoded address, the flip type flag and density flag of each basic storage unit are calculated in pairs. Following a fixed order from low to high bits, the flag bits of the group data are integrated as the first byte, including: The first and second 32-bit data in each group are processed independently. The cumulative positive flip bits and cumulative negative flip bits of the cell are extracted sequentially, and preprocessing is performed according to the following rules: Take the middle value of 16 out of 32 bits as the bit threshold.

[0115] If the number of flipped bits ∈ [0,16], it is a low density: the density flag is set to 0, and the simplified flipped number is directly taken as the original flipped bit value; If the number of flips is ∈ [17,32], it is a high density: set the density flag to 1, simplify the number of flips calculation to 32 - the original number of flips, and convert the result to the 0-16 range.

[0116] After preprocessing, the simplified flipped number has a value of 0-16, which can be fully represented by 4 bits, and two 4 bits make up one byte.

[0117] Extract the type flag and density flag (a total of 8 1-bit signals) from the 32-bit data of the two basic storage units, and combine them into one byte in a fixed order from the least significant bit to the most significant bit, as shown below: Positive flip type marker of the first basic memory cell → Negative flip type marker of the first basic memory cell → Positive flip density marker of the first basic memory cell → Negative flip density marker of the first basic memory cell → Positive flip type marker of the second basic memory cell → Negative flip type marker of the second basic memory cell → Positive flip density marker of the second basic memory cell → Negative flip density marker of the second basic memory cell.

[0118] In one specific embodiment of this application, the positive flip bit is set to 0, and the negative flip bit is set to 1.

[0119] The reversed and simplified numbers of the two basic storage units in step A3 are combined in a fixed order from the least significant bit to the most significant bit to obtain two bytes of reversed data, which are as follows: The second byte: the forward flipped simplified number of the first basic storage unit data → the negative flipped simplified number of the first basic storage unit data, each occupying 4 bits, forming 8 bits.

[0120] The third byte: the positive flip simplified number of the second basic storage unit data → the negative flip simplified number of the second basic storage unit data, each occupying 4 bits, forming 8 bits.

[0121] The first byte (mark bit integration) + the second byte (simplified flip number of the first unit) + the third byte (simplified flip number of the second unit) are integrated in sequence to form a 24-bit (3-byte) standardized combined compressed data.

[0122] Standardized combined compressed data can fully represent the core information of the positive / negative flip bits of two basic storage units (64-bit original data), and is in an 8-bit integer multiple format, which can be directly connected to the subsequent transmission process. The host computer can reverse the original flip bits through the marker bits, and there is no information loss.

[0123] Simplified compressed frames or differential address encoded data and combined compression units are encapsulated in a unified format to form a compressed inverted data frame consisting of an 8-bit frame header, all detection data, a 32-bit checksum, and an 8-bit frame tail.

[0124] After compression, the data follows the 8-bit integer multiple transmission standard, compressing each set of flipped data into a non-redundant transmission format. Combined with domain statistical optimization and differential address encoding, it breaks through the bottleneck of full-rate test data transmission.

[0125] The compressed data significantly reduces the amount of data transmitted. It eliminates the need to transmit 32 bits of raw data, transmitting only 12 bits of toggle state numbers. The toggle state numbers are compressed without redundancy. Compared to traditional transmission schemes, the data volume is reduced by more than 62%. It is compatible with USB 3.05Gbps bandwidth and operates without blocking at full speed (2400MT / s).

[0126] It supports user-defined levels and thresholds, is compatible with general-purpose memory with 24-bit address width and 32-bit data width, and allows for adjustment of test strategies without hardware modification, adapting to different radiation resistance evaluation standards.

[0127] It reduces testing costs and improves efficiency: The high flip-over area simplifies the transmission design, avoids the high-cost solution of local storage on large-capacity hard drives, improves data upload and analysis efficiency by more than 3 times, and reduces hardware costs by more than 60%, meeting the engineering testing requirements of ground-based simulated irradiation.

[0128] Example 5: Another embodiment of this application relates to an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a memory SEU precise detection method and a data dynamic compression method according to the above embodiments.

[0129] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0130] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0131] The compressed data has a significantly improved compression ratio, conforms to industry standards, and greatly reduces the amount of data transmitted. It is highly adaptable and flexible, reduces testing costs, and improves efficiency.

[0132] Specifically, it eliminates the need to transmit 32-bit raw data, transmitting only 10-bit flip state numbers. After compression, there is no redundancy, reducing data volume by over 75% compared to traditional transmission schemes. It is compatible with USB 3.05Gbps bandwidth and operates without blocking at full rate (2400MT / s) during testing. The 32-bit fixed contrast value, cell domain level, and flip percentage threshold are all user-defined, adaptable to general-purpose memory with 24-bit address width and 32-bit data width. Test strategies can be adjusted without hardware modifications, adapting to different radiation resistance evaluation standards. The high flip percentage area simplifies the transmission design, avoiding the high-cost solution of large-capacity hard drive local storage. Data upload and analysis efficiency is improved by more than 3 times, and hardware costs are reduced by more than 60%, meeting the requirements of ground-based simulated irradiation engineering testing.

[0133] Example 6: Another embodiment of this application relates to a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the method embodiments described above.

[0134] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0135] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A method for accurate detection of a memory SEU, characterized in that, include: Set test parameters and fixed values, read the current data of the basic storage unit corresponding to each physical address, bind the current data, physical address, and irradiation timestamp to obtain the current data group of each basic storage unit; compare the current data of each basic storage unit with the fixed value bit by bit to obtain the current flip data of each basic storage unit, including the number of positive flips, the number of negative flips, and the total number of flips, and perform statistics according to the hierarchical structure of the memory to obtain hierarchical statistical data.

2. The method for accurate detection of SEU in a memory according to claim 1, characterized in that, Also includes: The current data of each basic storage unit is compared bit by bit with its previous data to obtain the newly added flipped data of each basic storage unit, including the newly added positive flipped bits, the newly added negative flipped bits, and the newly added total flipped bits, and the current data is stored as the previous data; the physical address, flipped data, and irradiation timestamp are bound together; Statistical analysis was performed according to the hierarchical structure of the memory to obtain hierarchical statistical data. The flipped data includes the currently flipped data and the newly added flipped data.

3. The method for accurate detection of SEU in a memory according to claim 2, characterized in that, The binding of physical address, flipped data, and irradiation timestamp includes: taking the time it takes for the basic storage unit corresponding to all physical addresses to complete one full read as a single time base unit; during the irradiation test, performing continuous integer counting for each cyclic read operation of all physical addresses; marking the irradiation timestamp M after each read of all physical addresses; and binding each irradiation timestamp as the core identifier of the irradiation time with the physical address and flipped data, where M is a positive integer greater than or equal to 1.

4. A method for dynamic compression of SEU data in a memory, characterized in that, include: Set the compression unit level and the flip ratio threshold, divide all physical addresses according to the set compression unit level, calculate the flip ratio of each compression unit based on the flip data corresponding to each compression unit, compare the flip ratio with the flip ratio threshold, and obtain the simplified compressed frame based on the comparison result. For the flipped data frames that need to be compressed, a differential address encoding compression method is used to obtain differential address encoded data. For the flipped state number corresponding to the address after differential encoding, an adaptive combination compression method for flipped state number is used to obtain a combined compressed data unit. The simplified compressed frame or differential address encoded data and the combined compressed data unit are combined according to a set format to obtain compressed data.

5. The method for dynamic compression of SEU data in a memory according to claim 4, characterized in that, The step of comparing the flipping ratio with the flipping ratio threshold and obtaining a simplified compressed frame based on the comparison result includes: when the flipping ratio of the compression unit is greater than or equal to the flipping ratio threshold, it is determined that the radiation resistance of the compression unit does not meet the application requirements and there is no need to transmit detailed flipping data; a simplified compressed frame is formed using the comparison result marker bit, start address, end address, and cumulative flipping bits of the compression unit; when the flipping ratio of the compression unit is less than the flipping ratio threshold, it is determined that the detailed flipping data of the compression unit is the flipping data that needs to be compressed.

6. The method for dynamic compression of SEU data in a memory according to claim 4, characterized in that, The differential address encoding compression method includes: arranging all physical addresses corresponding to each compression unit in ascending or descending order, calculating the address difference between adjacent physical addresses, and when the address difference is greater than or equal to 1, representing it as a continuous address or an intermittent address, using a continuous marker, a starting address, and a total difference as differential address encoding data; when the address difference is equal to 0, representing it as a non-contiguous address, using a non-contiguous marker bit and a complete physical address as differential address encoding data.

7. The method for dynamic compression of SEU data in a memory according to claim 4, characterized in that, The adaptive combination compression method for the number of flipped states includes: compressing the number of flipped states corresponding to each compression unit; determining the data density based on whether the number of flipped bits exceeds a bit threshold; using the positive or negative sign of the number of flipped bits as the flipping type; simplifying the number of flipped bits data according to the flipping type to obtain the flipped simplified number; grouping two compression units together, using the type and density markers of the two compression units as the first byte, the positive flipped simplified number of the two compression units as the second byte, and the negative flipped simplified number of the two compression units as the third byte; the first byte, the second byte, and the third byte together form a 3-byte standardized combination compression data unit.

8. The method for dynamic compression of SEU data in a memory according to claim 7, characterized in that, The flipped reduction number includes: using half the number of bits of data in a single compressed unit as a bit threshold, when the number of flipped bits is less than or equal to the bit threshold, it is judged as low density, and the flipped reduction number is the flipped number in low density; when the number of flipped bits is greater than the bit threshold, it is judged as high density, and the flipped reduction number is the difference between the number of bits of data in the basic storage unit and the flipped number in high density.

9. The method for dynamic compression of SEU data in a memory according to claim 7, characterized in that, The first byte includes: a positive flip type marker for the first compressed unit data, a negative flip type marker for the first compressed unit data, a positive flip density marker for the first compressed unit data, a negative flip density marker for the first compressed unit data, a positive flip type marker for the second compressed unit data, a negative flip type marker for the second compressed unit data, a positive flip density marker for the second compressed unit data, and a negative flip density marker for the second compressed unit data, totaling 8 bits.

10. The method for dynamic compression of SEU data in a memory according to claim 7, characterized in that, The second byte includes: the positive flip simplified number and the negative flip simplified number of the first compressed unit data, set in order from low bit to high bit; the third byte includes: the positive flip simplified number and the negative flip simplified number of the second compressed unit data, set in order from low bit to high bit.

11. A device for precise detection of SEU in a memory, characterized in that, include: The host computer and the test module are configured with the slave computer program. The host computer is used to set detection parameters and perform human-computer interaction. The lower-level program provides software support for the operation of the detection method and compression algorithm; The test module is used to analyze parameters, coordinate the operation of various circuits within the module, store historical read data, provide a reference for dual-path comparison, and communicate with the host computer. It includes a main control circuit, a memory circuit, a DRAM buffer circuit, a USB communication circuit, and a power conversion circuit. The power conversion circuit is connected to the main control circuit, memory circuit, DRAM buffer circuit, and USB communication circuit respectively, providing power to each circuit. The main control circuit is connected to the memory circuit, DRAM buffer circuit, and USB communication circuit respectively. As the core control center, the main control circuit coordinates the collaborative work of each circuit, analyzes parameters, and configures the operating status of each module. The memory circuit carries the memory device under test, and the DRAM buffer circuit reserves a storage area with the same capacity as the memory device under test to store historical read data, providing a reference for dual-path comparison. The USB communication circuitry uses communication technology to provide a high-speed transmission channel.

12. The memory SEU precise detection device according to claim 11, characterized in that, The host computer includes: a human-computer interaction interface, a parameter configuration module, a data receiving and decompression module, and a storage and analysis module. The parameter configuration module is used to set parameters, including fixed values, compression unit levels, and flipping ratio thresholds. The data receiving and decompression module is used to receive the parameter settings and decompress the received values. The storage and analysis module is used to analyze the received test data. The human-computer interaction interface is used for visualization.

13. The memory SEU precise detection device according to claim 11, characterized in that, The lower-level program includes: a memory interface module, a single-event upset detection module, a dynamic compression module, a data buffer module, a high-efficiency upload module, and a control module. The high-efficiency upload module is connected to the control module, the data buffer module, and the upper-level computer. The single-event upset detection module is connected to the memory interface module, the dynamic compression module, and the control module. The memory interface module is also connected to the control module and the data buffer module. The data buffer module is connected to the memory interface module, the control module, the dynamic compression module, and the high-efficiency upload module. The memory interface module is used to follow the memory communication protocol and perform all physical address read and write operations according to the configuration parameters. In each loop, it first completes the reading of all physical address data, reads the data and transmits it to the single-event upset detection module in real time, and simultaneously collects the physical address and irradiation timestamp corresponding to the currently read data to provide basic data for binding the number of upset states with the address and time.

14. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which enable the at least one processor to perform a memory SEU precise detection method as described in any one of claims 1 to 3, and / or a memory SEU data dynamic compression method as described in any one of claims 4 to 10.

15. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements a memory SEU accurate detection method as described in any one of claims 1 to 3, and / or a memory SEU data dynamic compression method as described in any one of claims 4 to 10.

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