A memory computing device, counter, shift accumulator, and memory- in product-sum architecture
By using a skyrmion-based spintronic system and in-memory computing devices with magnetic orbital layers and magnetic recording layers, the memory wall and power wall problems of the von Neumann architecture are solved, achieving high-precision, low-power neural network computing with the characteristics of high speed and high storage density.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CETHIK GRP
- Filing Date
- 2022-03-21
- Publication Date
- 2026-06-26
AI Technical Summary
Existing von Neumann architecture computing systems are struggling to meet rapidly growing computing demands due to memory and power wall issues, and the conversion between analog and digital signals affects computing accuracy and energy efficiency.
It employs a pure spintronic system based on skyrmions, and uses a storage and computing device composed of a magnetic orbital layer and a magnetic recording layer to realize storage and computing by utilizing the physical properties of skyrmions, avoiding the conversion between digital signals and analog signals, and integrating a counter, a shift accumulator and an in-memory multiply-accumulate structure.
It achieves high-precision, low-power neural network computation, features high speed and high storage density, has a small physical size, and can directly perform matrix multiplication, accumulation, and shift operations, meeting the needs of efficient computation.
Smart Images
Figure CN116820390B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a memory computing device, a counter, a shift accumulator, and an in-memory multiply-accumulate structure. Background Technology
[0002] Modern computer systems are primarily based on the von Neumann architecture, characterized by the separation of storage and computation units. In recent years, with the rapid development of artificial intelligence, the amount of data that computing systems need to process has been continuously increasing. Due to issues such as the memory wall and power wall, the von Neumann architecture is increasingly unable to meet the ever-growing computational demands, becoming a major bottleneck in computational intelligence. In-memory computing technology is an important direction for solving the von Neumann bottleneck. By enabling storage units to simultaneously perform storage and computation functions, the memory wall and power wall problems can be effectively alleviated. In current in-memory computing architectures, matrix multiplication and accumulation calculations can be achieved in a single operation using cross-arranged non-volatile memory arrays. However, this computation is mainly based on the analog characteristics of circuits, and the calculation results inevitably contain noise, affecting the overall computational accuracy. Furthermore, the computation process requires continuous conversion between digital and analog signals, and the energy efficiency still needs improvement. Summary of the Invention
[0003] This invention provides a memory computing device, a counter, a shift accumulator, and an in-memory multiply-accumulate structure. The calculation process is based entirely on the physical properties of skyrmions, without the need for conversion between digital and analog signals, which can meet the requirements of high-precision, low-power neural network computing. At the same time, the physical size is small, which can achieve high storage and computing density.
[0004] In a first aspect, the present invention provides a memory computing device comprising a magnetic orbital layer and a magnetic recording layer. The magnetic orbital layer is used for inputting and outputting skyrmions, and also for stabilizing and allowing the skyrmions within it to move. The magnetic recording layer includes a barrier layer stacked on the surface of the magnetic orbital layer and a reference layer stacked on the barrier layer. The magnetic orbital layer and the magnetic recording layer form a magnetic tunnel junction, and the region in the magnetic orbital layer that overlaps with the barrier layer is the magnetic recording layer region. The magnetization directions of the magnetic orbital layer and the reference layer are opposite; when there are no skyrmions in the magnetic recording layer region, the resistance state of the magnetic tunnel junction is a high-resistivity state; when skyrmions input to the magnetic orbital layer move into the magnetic recording layer region, they are pinned within the magnetic recording layer region, thereby changing the resistance state of the magnetic tunnel junction from a high-resistivity state to a low-resistivity state.
[0005] In the above-described scheme, a memory device comprising a magnetic orbital layer and a magnetic recording layer is used. Storage is achieved by utilizing the difference in resistance states of the magnetic tunnel junction formed by the magnetic orbital layer and the magnetic recording layer due to the presence or absence of skyrmions in the magnetic recording layer region. Compared to existing technologies that rely on flipping the magnetization direction of a free layer, the memory device disclosed in this application, based on a pure spintronic system with magnetic skyrmions, possesses the high speed and low power consumption characteristics of spintronic devices. Furthermore, the memory device has a small physical size, enabling higher storage density.
[0006] In one specific embodiment, the in-memory computing device further includes an erasure region located on the side of the magnetic track layer, used to erase skyrmions entering therein. The magnetic track layer has skyrmion input ports and skyrmion output ports. When fixed skyrmions exist in the magnetic recording layer region, moving skyrmions input through the skyrmion input ports can collide the fixed skyrmions with the erasure region, and the moving skyrmions themselves can be output from the skyrmion output ports. By adding an erasure region on the side of the magnetic track layer, for continuously input skyrmions, one skyrmion is output for every two skyrmions input, and the resistance state of the magnetic tunnel junction is reset, exhibiting a binary addition rule of carry-over every two, which can directly realize in-memory accumulation operations. The calculation process is entirely based on the physical characteristics of skyrmions, without the need for digital signal to analog signal conversion, which can meet the requirements of high-precision, low-power neural network computing, and can also achieve high computational density.
[0007] In one specific embodiment, the erasure region is provided with an energized port. When current flows into the energized port of the erasure region, skyrmions in the magnetic recording layer region can be output from the skyrmion output port; when current flows out of the energized port of the erasure region, skyrmions in the magnetic recording layer region can be erased. This facilitates the output or erasure of skyrmions within the memory unit.
[0008] In one specific embodiment, the magnetic orbital layer comprises stacked heavy metal layers and magnetic layers, with a barrier layer stacked on the surface of the magnetic layers. The interface coupling between the heavy metal layer and the magnetic layer generates a DMI effect, enabling the stable existence of skyrmions within the magnetic orbital layer; the spin-orbit moment effect between the heavy metal layer and the magnetic layer drives the motion of the skyrmions within the magnetic orbital layer. This facilitates the stable existence and motion of skyrmions within the magnetic orbital layer.
[0009] In one specific embodiment, the magnetic track layer has a T-shaped cross-section. Each end of the straight track in the T-shaped magnetic track layer has an energized port; the skyrmion input port and skyrmion output port coincide with the two energized ports of the magnetic track layer, respectively. An erasing region is distributed at the remaining third end of the T-shaped magnetic track layer to optimize the structure of the magnetic track layer and optimize the skyrmion's orbital path.
[0010] In one specific implementation, the magnetic anisotropy of both the magnetic orbital layer and the reference layer is perpendicular magnetic anisotropy, which facilitates pinning skyrmions that have moved to the magnetic recording layer region.
[0011] Secondly, the present invention also provides a counter comprising: a plurality of memory devices, each of the aforementioned types, having an erasure region, arranged sequentially. Between any two adjacent memory devices, a skyrmion input port of one memory device is connected to a skyrmion output port of the other memory device, so that skyrmions in one memory device can move into the other memory device.
[0012] In the above scheme, a memory device consisting of a magnetic orbital layer and a magnetic recording layer is used. Storage is achieved by utilizing the difference in resistance states of the magnetic tunnel junction formed by the magnetic orbital layer and the magnetic recording layer due to the presence or absence of skyrmions in the magnetic recording layer region. An eraser region is added to the side of the magnetic orbital layer. For continuously input skyrmions, one skyrmion is output for every two input skyrmions, and the resistance state of the magnetic tunnel junction is reset, exhibiting a binary addition rule of carry-over every two inputs. This allows for direct in-memory accumulation operations. The calculation process is entirely based on the physical properties of skyrmions, eliminating the need for digital-to-analog signal conversion, and meeting the requirements of high-precision, low-power neural network computation. This scheme is entirely based on a pure spintronic system of magnetic skyrmions, possessing the high speed and low power consumption characteristics of spintronic devices, while also having a small physical size, enabling high storage and computational density.
[0013] Thirdly, the present invention also provides a shift accumulator, which includes the aforementioned counter and at least one additional input port. Each additional input port is connected to a magnetic track layer of a memory device, and at most one additional input port is connected to a magnetic track layer of a memory device. Each additional input port is used to input skyrmions to the magnetic track layer to which it is connected.
[0014] In the above scheme, a memory device consisting of a magnetic orbital layer and a magnetic recording layer is used. Storage is achieved by utilizing the difference in resistance states of the magnetic tunnel junction formed by the magnetic orbital layer and the magnetic recording layer due to the presence or absence of skyrmions in the magnetic recording layer region. An eraser region is added to the side of the magnetic orbital layer. For continuously input skyrmions, one skyrmion is output for every two input skyrmions, and the resistance state of the magnetic tunnel junction is reset, exhibiting a binary addition rule of carry-over every two inputs. This allows for direct in-memory accumulation operations. The calculation process is entirely based on the physical properties of skyrmions, eliminating the need for digital-to-analog signal conversion, and meeting the requirements of high-precision, low-power neural network computation. This scheme is entirely based on a pure spintronic system of magnetic skyrmions, possessing the high speed and low power consumption characteristics of spintronic devices, while also having a small physical size, enabling high storage and computational density.
[0015] In one specific implementation, for each memory device connected to an additional input port, the additional input port and the erase area are located on opposite sides of the magnetic track layer, optimizing the placement of the additional input port and the erase area.
[0016] In one specific implementation, each memory device is provided with a shunt port at the top or bottom of the magnetic track layer to keep the current in the magnetic track layer constant at a set current value, so that the current in the magnetic track layer at the central position remains unchanged during reset, shift, and accumulation operations, thus ensuring normal operation of the device.
[0017] Fourthly, the present invention also provides an in-memory multiply-accumulate structure, comprising: any of the aforementioned shift accumulators, and a plurality of arrayed cells, each memory cell being any of the aforementioned in-memory computing devices. Between any two adjacent in-memory computing devices in the same column, the skyrmion input port of one in-memory computing device is sequentially connected to the skyrmion output port of the other in-memory computing device, so that skyrmions in one in-memory computing device can move into the other in-memory computing device; and the skyrmion output port of the end-positioned in-memory computing device is connected to an additional input port of the shift accumulator. All cells in the same row are interconnected via the same wire to apply the same voltage to all cells in the same row. Each cell can determine whether to generate skyrmions based on the magnitude of the applied voltage and the resistance state of its internal magnetic tunnel junction, and after generating skyrmions, the generated skyrmions flow into the additional input port connected to that cell.
[0018] In the above scheme, by integrating the shift accumulator and multiple in-memory computing units, binary multiplication, accumulation, and shift operations can be performed, meeting the computational requirements of vector-matrix multiplication. Furthermore, the binary multiplication, accumulation, and shift operations are all directly implemented in-memory multiplication and addition operations. The computation process is entirely based on the physical properties of skyrmions, eliminating the need for digital-to-analog signal conversion, thus meeting the requirements of high-precision, low-power neural network computation. This scheme is entirely based on a pure spintronic system of magnetic skyrmions, possessing the high speed and low power consumption characteristics of spintronic devices, while also having a small physical size, enabling high storage and computational density.
[0019] In one specific implementation, each cell can determine whether to generate skyrmions based on the applied voltage and its resistance state. Specifically: when the magnetic tunnel junction within the cell is in a high-resistivity state, no skyrmions are generated in its magnetic orbitals regardless of whether a high or low voltage is applied; when the magnetic tunnel junction within the cell is in a low-resistivity state, no skyrmions are generated in its magnetic orbitals if a low voltage is applied, but skyrmions can be generated in its magnetic orbitals if a high voltage is applied. This facilitates the implementation of multiplication operations for each cell. Attached Figure Description
[0020] Figure 1 A three-dimensional structural schematic diagram of a memory computing device provided in an embodiment of the present invention;
[0021] Figure 2 for Figure 1 A top view of the memory computing device is shown;
[0022] Figure 3 A schematic diagram of the motion of a skyrmion;
[0023] Figure 4 A schematic diagram of the motion of another type of skyrmion;
[0024] Figure 5 A structural cross-sectional view of a memory computing device provided in an embodiment of the present invention;
[0025] Figure 6 A counter provided in an embodiment of the present invention;
[0026] Figure 7 for Figure 6 A top view of the provided counter;
[0027] Figure 8 This is a top view of a shift accumulator provided in an embodiment of the present invention;
[0028] Figure 9 A side view of a shift accumulator provided in an embodiment of the present invention;
[0029] Figure 10 A three-dimensional structural diagram of an in-memory multiplication-addition structure is provided in an embodiment of the present invention;
[0030] Figure 11 This invention provides a binary multiplication truth table for array cells in an in-memory multiply-add structure.
[0031] Figure label:
[0032] 10-Memory computing device; 11-Magnetic track layer; 111-Heavy metal layer
[0033] 112-Magnetic layer 12-Barrier layer 13-Reference layer
[0034] 14 - Erasure area; 15 - Magnetic recording layer area; 20 - Counter
[0035] 30 - Shift accumulator 31 - Shunt port
[0036] 32 - Additional Input Port 40 - Wire Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0038] To facilitate understanding of the in-memory computing device provided in the embodiments of the present invention, the application scenarios of the in-memory computing device provided in the embodiments of the present invention will be described first. This in-memory computing device is applied in the storage and computing processes in the computer field. The in-memory computing device will be described in detail below with reference to the accompanying drawings.
[0039] refer to Figure 1 , Figure 2 and Figure 3The in-memory computing device provided in this embodiment of the invention includes a magnetic orbital layer 11 and a magnetic recording layer. The magnetic orbital layer 11 is used for inputting and outputting skyrmions, and also for stabilizing and allowing the skyrmions within it to move. The magnetic recording layer includes a barrier layer 12 stacked on the surface of the magnetic orbital layer 11 and a reference layer 13 stacked on the barrier layer 12. The magnetic orbital layer 11 and the magnetic recording layer form a magnetic tunnel junction, and the region in the magnetic orbital layer 11 that overlaps with the barrier layer 12 is the magnetic recording layer region 15. The magnetization directions of the magnetic orbital layer 11 and the reference layer 13 are opposite; when there are no skyrmions in the magnetic recording layer region 15, the resistance state of the magnetic tunnel junction is a high-resistance state; when skyrmions input to the magnetic orbital layer 11 move to the magnetic recording layer region 15, they are pinned within the magnetic recording layer region 15, thereby changing the resistance state of the magnetic tunnel junction from a high-resistance state to a low-resistance state.
[0040] In the above scheme, a memory device consisting of a magnetic orbital layer 11 and a magnetic recording layer is used. Storage is achieved by utilizing the difference in resistance states between the magnetic tunnel junction formed by the magnetic orbital layer 11 and the magnetic recording layer due to the presence or absence of skyrmions in the magnetic recording layer region 15. Compared to the prior art method of flipping the magnetization direction of a free layer, the memory device disclosed in this application, based on a pure spintronic system with magnetic skyrmions, possesses the characteristics of high speed and low power consumption of spintronic devices. Furthermore, the physical size of the memory device is small, enabling higher storage density. The following detailed description of the configuration of each structure is provided in conjunction with the accompanying drawings.
[0041] like Figure 1 , Figure 2 and Figure 3 As shown, the magnetic orbital layer 11 is used for inputting and outputting skyrmions, and also for stabilizing and allowing the skyrmions within it to move. In configuration, the magnetic orbital layer 11 may include skyrmion input ports and skyrmion output ports. When it is necessary to input skyrmions into the magnetic orbital layer 11, they can be input through the skyrmion input ports.
[0042] In a specific implementation where the skymint within the input is stably maintained, refer to Figure 5The magnetic orbital layer 11 may include a stacked heavy metal layer 111 and a magnetic layer 112, with a barrier layer 12 stacked on the surface of the magnetic layer 112. The interface coupling between the heavy metal layer 111 and the magnetic layer 112 generates a DMI effect, enabling the skyrmions within the magnetic orbital layer 11 to exist stably. The spin-orbit moment effect of the heavy metal layer 111 and the magnetic layer 112 drives the movement of the skyrmions within the magnetic orbital layer 11, facilitating their stable existence and movement. Two energized ports can be provided on the magnetic orbital layer 11, allowing current to flow into the magnetic orbital layer 11, thereby driving the skyrmions to move within the magnetic orbital layer 11. Specifically, the skyrmion input port and skyrmion output port can be aligned with the two energized ports on the magnetic orbital layer 11, optimizing the structure of the magnetic orbital layer 11 and the orbital path of the skyrmions. Figure 1 and Figure 2 The magnetic track layer 11 shown has a T-shaped cross-section. A power-conducting port is located at each end of the straight track of the T-shaped magnetic track layer 11, such that the skyrmion input port and skyrmion output port coincide with the two power-conducting ports of the magnetic track layer 11, respectively. Specifically, as shown... Figure 2 The magnetic track layer 11 shown has a power-on port at ports A and B, used to supply current to the magnetic track layer 11. Additionally, port A has a skyrmion output port, and port B has a skyrmion input port. When current is supplied to ports A and B, skyrmions can be driven to move from port A to port B. It should be understood that the configuration of the magnetic track layer 11 is not limited to the configuration shown above; other configurations can also be used. For example, a magnetic track layer 11 with a rectangular cross-sectional shape can also be used.
[0043] Continue to refer to Figure 1 In setting the magnetic recording layer, the magnetic recording layer includes a barrier layer 12 stacked on the surface of the magnetic orbital layer 11 and a reference layer 13 stacked on the barrier layer 12, wherein the magnetic orbital layer 11 and the magnetic recording layer form a magnetic tunnel junction. Furthermore, the magnetization directions of the magnetic orbital layer 11 and the reference layer 13 are opposite, so that when a skyrmion moves to a region overlapping with the barrier layer 12, the magnetic orbital layer 11 can pin the skyrmion to that region. This region is defined as the magnetic recording layer region 15, which is located in the magnetic orbital layer 11 and overlaps with the barrier layer 12. Specifically, when the magnetization directions of the reference layer 13 and the magnetic orbital layer 11 are opposite, the reference layer 13... Figure 5The magnetic anisotropy of both the magnetic orbital layer 11 and the reference layer 13 can be perpendicular to the magnetic anisotropy, facilitating the pinning of skyrmions that move to the magnetic recording layer region 15. For example, the magnetization direction in the magnetic orbital layer 11 can be perpendicular to the downward direction, while the magnetization direction in the reference layer 13 can be perpendicular to the upward direction, thus setting the perpendicular magnetization directions of the magnetic orbital layer 11 and the reference layer 13 opposite to each other. Of course, the magnetization direction in the magnetic orbital layer 11 can also be perpendicular to the upward direction, while the magnetization direction in the reference layer 13 can be perpendicular to the downward direction, thus setting the perpendicular magnetization directions of the magnetic orbital layer 11 and the reference layer 13 opposite to each other.
[0044] refer to Figure 3 When skyrmions are absent in magnetic recording layer region 15, the magnetic tunnel junction exhibits a high-resistivity state, manifested by the antiparallel magnetization directions of the reference layer 13 and the magnetic orbital layer 11. However, when skyrmions input to the magnetic orbital layer 11 move into magnetic recording layer region 15, they are pinned within it, thus changing the high-resistivity state of the magnetic tunnel junction to a low-resistivity state. This can be seen from... Figure 2 A skyrmion is input at port B. When the skyrmion moves to magnetic recording layer region 15, it remains in region 15, causing the resistance of the magnetic tunnel junction to change from a high-resistance state to a low-resistance state. In other words, the presence or absence of a skyrmion in magnetic recording layer region 15 affects the resistance across the magnetic tunnel junction. When no skyrmion is present in region 15, the magnetic tunnel junction exhibits a high-resistance state; conversely, when a skyrmion is present, the resistance is low. The resistance state of the magnetic tunnel junction can be read through the top port of the magnetic recording layer and any port of the magnetic orbital layer 11. Storage is achieved by utilizing the characteristic that the presence or absence of a skyrmion in magnetic recording layer region 15 results in a different resistance state of the magnetic tunnel junction formed by the magnetic orbital layer 11 and the magnetic recording layer. Compared to existing technologies that rely on flipping the magnetization direction of the free layer, the memory computing device disclosed in this application, based on a pure spintronic system of magnetic skyrmions, possesses the characteristics of high speed and low power consumption of spintronic devices. At the same time, the physical size of the memory computing device is small, enabling the achievement of high storage density.
[0045] In addition, such as Figure 1 and Figure 2 As shown, the memory device may also include an erasure region 14 located on the side of the magnetic track layer 11. The erasure region 14 is used to erase skyrmions that enter therein, thereby integrating a counting function into the memory device. Specifically, refer to... Figure 4When fixed skyrmions exist in the magnetic recording layer region 15, if moving skyrmions continue to be introduced into the magnetic orbital layer 11 through the skyrmions on the magnetic orbital layer 11, the moving skyrmions can collide with the fixed skyrmions originally present in the magnetic recording layer region 15, causing the fixed skyrmions originally present in the magnetic recording layer region 15 to enter the erase region 14. Furthermore, the moving skyrmions themselves will be output from the skyrmion output port, thus eliminating the presence of skyrmions in the magnetic recording layer region 15, thereby changing the low-resistivity state of the magnetic tunnel junction to a high-resistivity state. For example, refer to... Figure 4 When a skyrmion is input from port B, and skyrmions already exist in the magnetic recording layer region 15, the moving skyrmion will collide with the skyrmions pinned to the magnetic recording layer region 15, pushing the existing skyrmions into the erase region 14. The skyrmions themselves will then be output from port A, changing the magnetic tunnel junction from a low-resistance state to a high-resistance state. In other words, by adding an erase region 14 to the side of the magnetic orbital layer 11, for every two continuously input skyrmions, one skyrmion will be output, and the resistance state of the magnetic tunnel junction will be reset. This manifests as a binary addition rule of carrying over every two skyrmions, enabling direct in-memory accumulation. The calculation process is entirely based on the physical properties of skyrmions, requiring no conversion between digital and analog signals. This meets the requirements of high-precision, low-power neural network computation and achieves high computational density.
[0046] refer to Figure 1 and Figure 2 When the cross-sectional shape of the magnetic tunnel layer is T-shaped, the remaining third end of the T-shaped magnetic track layer 11, in addition to the two ends of the straight track mentioned above, can be distributed with erasure regions 14 to optimize the structure of the magnetic track layer 11 and optimize the orbital path of the skyrmion.
[0047] Furthermore, an energizing port can be provided in the erasure region 14. When current flows into the energizing port of the erasure region 14, the skyrmions of the magnetic recording layer region 15 can be output from the skyrmion output port. That is, by inputting current into the energizing port of the erasure region 14, the fixed skyrmions present in the magnetic recording layer region 15 can be output from the skyrmion output port for shifting operation. When current flows out of the energizing port of the erasure region 14, the skyrmions of the magnetic recording layer region 15 can be erased, directly resetting the skyrmions of the magnetic recording layer region 15. (Reference) Figure 2The power-on port can be located at port C of the magnetic track layer 11. When current flows into port C, skyrmions in the magnetic recording layer region 15 can be output from the skyrmion output port of the magnetic track layer 11. When current flows out of port C, skyrmions in the magnetic recording layer region 15 can be erased. By providing a power-on port in the erasure region 14, it is possible to output or erase skyrmions within the memory unit.
[0048] In addition, embodiments of the present invention also provide a counter, see reference. Figure 1 , Figure 2 , Figure 6 and Figure 7 The counter includes multiple memory devices 10 arranged sequentially, each containing an erase region 14. Between any two adjacent memory devices 10, the skyrmion input port of one memory device 10 is connected to the skyrmion output port of the other memory device 10, allowing skyrmions in one memory device 10 to move into the other. By employing a memory device 10 comprising a magnetic track layer 11 and a magnetic recording layer, storage is achieved by utilizing the characteristic that the presence or absence of skyrmions in the magnetic recording layer region 15 results in different resistance states in the magnetic tunnel junction formed by the magnetic track layer 11 and the magnetic recording layer. An eraser region 14 is added to the side of the magnetic orbital layer 11. For continuously input skyrmions, one skyrmion is output for every two input skyrmions, and the resistance state of the magnetic tunnel junction is reset, exhibiting a binary addition rule of carrying over every two inputs. This enables direct in-memory computation, and the computation process is entirely based on the physical properties of skyrmions, requiring no conversion between digital and analog signals. This meets the requirements of high-precision, low-power neural network computation. The above scheme is entirely based on a pure spintronic system of magnetic skyrmions, possessing the characteristics of high speed and low power consumption of spintronic devices. Furthermore, its small physical size allows for high storage and computational density.
[0049] like Figure 6 and Figure 7As shown, multiple memory-based computing devices 10 are arranged sequentially, and the skyrmion input and output ports of two adjacent memory-based computing devices 10 are connected. Skyrmions can be input from one memory-based computing device 10 to another without conversion. The ends of the counter each contain two power-on ports A and B. Port B is also a skyrmion input port, and port A is a skyrmion output port. Applying current to ports A and B allows skyrmions to move from port B to port A. Because the memory-based computing devices 10, which include an erase region 14, have a carry-over characteristic (carry-over every two), the counter can count the number of input skyrmions. The counting result is represented by the resistance state of the magnetic tunnel junction (MTJ) in different positions of the memory-based computing devices 10; a low resistance state represents a binary 1, and a high resistance state represents a binary 0. The resistance states of the magnetic tunnel junctions at different positions represent different bits of the binary number. Figure 7 As shown, from end B to end A, the resistance states of the magnetic tunnel junction are represented sequentially as follows: 2 0 ,2 1 ,…,2 n-1 Bit.
[0050] Furthermore, embodiments of the present invention also provide a shift accumulator, see reference. Figure 1 , Figure 2 , Figure 6 , Figure 7 and Figure 8 The shift accumulator includes the aforementioned counter 20 and at least one additional input port 32. Each additional input port 32 is connected to the magnetic track layer 11 of a memory device 10, and at most one additional input port 32 is connected to the magnetic track layer 11 of a memory device 10. Each additional input port 32 is used to input skyrmions into the magnetic track layer 11 to which it is connected. By employing a memory device 10 consisting of a magnetic track layer 11 and a magnetic recording layer, storage is achieved by utilizing the characteristic that the presence or absence of skyrmions in the magnetic recording layer region 15 results in different resistance states of the magnetic tunnel junction formed by the magnetic track layer 11 and the magnetic recording layer. An eraser region 14 is added to the side of the magnetic orbital layer 11. For continuously input skyrmions, one skyrmion is output for every two input skyrmions, and the resistance state of the magnetic tunnel junction is reset, exhibiting a binary addition rule of carry-over every two inputs. This enables direct in-memory accumulation operations. The calculation process is entirely based on the physical properties of skyrmions, requiring no conversion between digital and analog signals, thus meeting the requirements of high-precision, low-power neural network computation. The above scheme is entirely based on a pure spintronic system of magnetic skyrmions, possessing the characteristics of high speed and low power consumption of spintronic devices. Furthermore, its small physical size allows for high storage and computational density.
[0051] When setting the additional input port 32, for each memory device 10 connected to the additional input port 32, the additional input port 32 and the erase area 14 can be arranged on two opposite sides of the magnetic track layer 11, optimizing the setting position of the additional input port 32 and the erase area 14.
[0052] like Figure 9 The diagram shows a shift accumulator, which includes the counter 20 described above. Furthermore, n additional input ports 32 are provided on the side of the counter 20 opposite to the magnetic track layer 11 and the erase region 14. These n additional input ports 32 are numbered D0-D10. n-1 The shift accumulator has two energized ports, A and B, at its two ends. Port B is also the skyrmion input port, and port A is the skyrmion output port. Applying current to ports A and B causes the skyrmion to move from port B to port A. Ports D0-D n-1 This is the additional input port 32 for the skyrmion. Current input through this additional input port 32 allows the skyrmion to enter the magnetic track at the intermediate position. Additional input port 32D0-D n-1 The inputs correspond to different weights, representing 2 from end B to end A respectively. 0 ,2 1 ,…, 2 n-1 Bits. The accumulation result is represented by the resistance state of the magnetic tunnel junction in different storage units. A low-resistance state can represent a binary 1, and a high-resistance state can represent a binary 0. The resistance states of the magnetic tunnel junction at different locations represent different bits of the binary number. For example... Figure 9 As shown, from end B to end A, the resistance states of the magnetic tunnel junction are represented sequentially as follows: 2 0 ,2 1 ,…,2 n-1 Bit.
[0053] refer to Figure 9 Power ports C0-C are sequentially provided in the erasure area 14. n-1 When current flows out of the power-on port of erasure region 14, the skyrmion in the magnetic tunnel junction of the corresponding memory device 10 can be erased. When current flows into the power-on port of erasure region 14, the skyrmion in the magnetic tunnel junction of the corresponding memory device 10 can be output to the next bit. When C0-C n-1 When current flows out simultaneously, skyrmions within the magnetic tunnel junctions of all memory devices 10 are erased, which can be considered a reset operation. When C0-C n-1 When current flows in simultaneously, skyrmions in the magnetic tunnel junctions of all memory devices 10 will be shifted one bit to the left, which can be regarded as a shift operation.
[0054] refer to Figure 9Furthermore, a shunt port 31 can be provided at the top or bottom of the magnetic track layer 11 of each memory device 10 to keep the current in the magnetic track layer 11 constant at a set current value, so that the current in the magnetic track layer 11 at the central position remains unchanged during reset, shift, and accumulation operations, ensuring normal operation of the device.
[0055] Furthermore, embodiments of the present invention also provide an in-memory multiply-accumulate structure, see reference. Figure 1 , Figure 2 , Figure 6 , Figure 7 , Figure 8 and Figure 10 The in-memory multiply-accumulate structure includes: any of the aforementioned shift accumulators 30, and multiple arrayed cells, each memory cell being any of the aforementioned in-memory computing devices 10. Between any two adjacent in-memory computing devices 10 in the same column, the skyrmion input port of one in-memory computing device 10 is sequentially connected to the skyrmion output port of the other in-memory computing device 10, so that skyrmions in one in-memory computing device 10 can move into the other in-memory computing device 10; and the skyrmion output port of the end-positioned in-memory computing device 10 is connected to an additional input port 32 of the shift accumulator 30. All cells in the same row are interconnected via the same wire 40 to apply the same voltage to all cells in the same row. Each cell can determine whether to generate skyrmions based on the magnitude of the applied voltage and the resistance state of its internal magnetic tunnel junction, and after generating skyrmions, the generated skyrmions flow into the additional input port 32 connected to that cell. By integrating the aforementioned shift accumulator 30 and multiple in-memory units, binary multiplication, accumulation, and shift operations can be performed, meeting the computational requirements of vector-matrix multiplication. Furthermore, these binary multiplication, accumulation, and shift operations are all directly implemented in-memory multiplication and addition operations. The computation process is entirely based on the physical properties of skyrmions, eliminating the need for digital-to-analog signal conversion, thus meeting the requirements of high-precision, low-power neural network computation. This scheme is entirely based on a pure spintronic system of magnetic skyrmions, possessing the high speed and low power consumption characteristics of spintronic devices, while also having a small physical size, enabling high storage and computational density.
[0056] like Figure 10 The diagram illustrates an in-memory multiply-accumulate structure. The in-memory multiply-accumulate result includes a shift accumulator 30 as shown above, and also comprises multiple cells arranged in an array with rows and columns. Each cell includes the in-memory computing device 10 shown above. (Reference) Figure 10 The memory computing device 10 may not be like Figure 1The T-shaped magnetic track layer 11 shown can be rectangular. Between memory devices 10 in the same column, the skyrmion input ports and skyrmion output ports of adjacent memory devices 10 are connected sequentially, and the skyrmion output port near the end of the shift accumulator 30 is connected to an additional input port 32 of the shift accumulator 30. Cells in the same row are interconnected via the same wire 40, allowing the same voltage to be applied to all cells in the same row. Each cell can store weight information by changing the magnetization direction of the reference layer 13. Each cell can determine whether to generate skyrmions on its magnetic track layer 11 based on the applied voltage and the weight information. If the applied voltage and the resistance state of the magnetic tunnel junction in the memory device 10 are considered as two inputs, this operation can be viewed as a binary multiplication of the voltage applied to the wire 40 and the resistance value of the magnetic tunnel junction in the memory cell. The skyrmions generated by binary multiplication operations can be fed into shift-accumulator 30 to perform shift and accumulation operations, thus enabling the in-memory multiply-accumulate structure to perform binary multiplication, accumulation, and shift operations, meeting the computational requirements of vector-matrix multiplication. Additionally, refer to... Figure 10 This allows the number of memory devices 10 included in the shift accumulator 30 to be greater than the number of additional input ports 32, thereby preventing errors in the calculation due to data bit overflow during the accumulation process.
[0057] When each unit decides whether to generate skyrmions based on the applied voltage and its resistive state, it can use methods such as... Figure 11 The truth table shown illustrates this. Specifically, when the magnetic tunnel junction within a cell is in a high-resistivity state, no skyrmions are generated in its magnetic orbital layer 11 regardless of whether a high or low voltage is applied. When the magnetic tunnel junction within a cell is in a low-resistivity state, no skyrmions are generated in its magnetic orbital layer 11 if a low voltage is applied, but skyrmions can be generated in its magnetic orbital layer 11 if a high voltage is applied. This facilitates multiplication operations within each cell. It should be understood that the specific method by which each cell determines whether to generate skyrmions based on the applied voltage and its resistance state is not limited to the method shown above; other methods may also be used.
[0058] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A memory computing device, characterized in that, include: Magnetic orbital layers are used for inputting and outputting skyrmions, and also for stabilizing and allowing the skyrmions within them to move. The magnetic recording layer includes a barrier layer stacked on the surface of the magnetic orbital layer and a reference layer stacked on the barrier layer; the magnetic orbital layer and the magnetic recording layer form a magnetic tunnel junction, and the region of the magnetic orbital layer that overlaps with the barrier layer is the magnetic recording layer region; The magnetic orbital layer has the opposite magnetization direction to the reference layer; when there are no skyrmions in the magnetic recording layer region, the magnetic tunnel junction is in a high-resistance state; when skyrmions input to the magnetic orbital layer move into the magnetic recording layer region, they are pinned to the magnetic recording layer region by the magnetic recording layer, thereby changing the resistance state of the magnetic tunnel junction from the high-resistance state to the low-resistance state. The memory device further includes an erasure region located on the side of the magnetic track layer for erasing skyrmions that have entered therein; The magnetic orbital layer has skyrmion input ports and skyrmion output ports; When there are fixed skyrmions in the magnetic recording layer region, moving skyrmions input through the skyrmion input port can collide the fixed skyrmions with the erasure region, and the moving skyrmions themselves can be output from the skyrmion output port.
2. The memory computing device as described in claim 1, characterized in that, The erasure area is equipped with a power port; When current flows into the power port of the erasure region, skyrmions of the magnetic recording layer region can be output from the skyrmion output port; When current flows out of the energized port of the erasure region, the skyrmions of the magnetic recording layer region can be erased.
3. The memory computing device as described in claim 1, characterized in that, The magnetic orbital layer comprises a stacked heavy metal layer and a magnetic layer, and the barrier layer is stacked on the surface of the magnetic layer; The interface coupling between the heavy metal layer and the magnetic layer generates the DMI effect, which enables skyrmions in the magnetic orbital layer to exist stably. The spin-orbit moment effect of the heavy metal layer and the magnetic layer drives the movement of skyrmions within the magnetic orbital layer.
4. The memory computing device as described in claim 1, characterized in that, The cross-sectional shape of the magnetic track layer is T-shaped; A power-on port is provided at both ends of the straight track of the T-shaped magnetic track layer; the skyrmion input port and skyrmion output port coincide with the two power-on ports of the magnetic track layer, respectively. The erasure area is distributed at the remaining third end of the T-shaped magnetic track layer.
5. The memory computing device as described in claim 1, characterized in that, The magnetic anisotropy of both the magnetic orbital layer and the reference layer is perpendicular magnetic anisotropy.
6. A counter, characterized in that, include: Multiple memory computing devices arranged in sequence as described in any one of claims 1 to 5; Between any two adjacent memory devices, the skyrmion input port of one memory device is connected to the skyrmion output port of the other memory device, so that the skyrmion in the one memory device can move into the other memory device.
7. A shift accumulator, characterized in that, include: The counter as described in claim 6; At least one additional input port, each additional input port being connected to a magnetic orbital layer of a memory device, and at most one additional input port being connected to a magnetic orbital layer of a memory device, each additional input port being used to input skyrmions to the magnetic orbital layer to which it is connected.
8. The shift accumulator as described in claim 7, characterized in that, For each memory device connected to the additional input port, the additional input port and the erasure area are located on two opposite sides of the magnetic track layer.
9. The shift accumulator as described in claim 8, characterized in that, Each memory device also has a shunt port at the top or bottom of its magnetic track layer to keep the current in the magnetic track layer constant at a set value.
10. An in-memory multiply-add structure, characterized in that, include: The shift accumulator as described in any one of claims 7 to 9; Multiple units distributed in an array, wherein each storage unit is a storage computing device as described in any one of claims 1 to 5; In this configuration, between any two adjacent memory devices in the same column, the skyrmion input port of one memory device is sequentially connected to the skyrmion output port of the other memory device, so that the skyrmion in the one memory device moves into the other memory device; and the skyrmion output port of the memory device located at the end position is connected to an additional input port of the shift accumulator. All cells in the same row are interconnected by the same wire so that the same voltage is applied to all cells in the same row; Each cell can determine whether to generate skyrmions based on the magnitude of the applied voltage and the resistance state of its internal magnetic tunnel junction, and after generating skyrmions, it can flow the generated skyrmions into an additional input port connected to the cell.
11. The in-memory multiply-accumulate structure as described in claim 10, characterized in that, Each unit can determine whether to generate skyrmions based on the applied voltage and its resistive state. Specifically: When the magnetic tunnel junction within the unit is in a high-resistivity state, no skyrmions are generated in its magnetic orbital layer regardless of whether a high or low voltage is applied. When the magnetic tunnel junction within the unit is in a low-resistance state, no skyrmions are generated in its magnetic orbital layers if a low voltage is applied; however, if a high voltage is applied, skyrmions can be generated in its magnetic orbital layers.